1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 * 5 * Read out the current hardware modeset state, and sanitize it to the current 6 * state. 7 */ 8 9 #include <drm/drm_atomic_uapi.h> 10 #include <drm/drm_atomic_state_helper.h> 11 12 #include "i915_drv.h" 13 #include "intel_atomic.h" 14 #include "intel_bw.h" 15 #include "intel_color.h" 16 #include "intel_crtc.h" 17 #include "intel_crtc_state_dump.h" 18 #include "intel_ddi.h" 19 #include "intel_de.h" 20 #include "intel_display.h" 21 #include "intel_display_power.h" 22 #include "intel_display_types.h" 23 #include "intel_modeset_setup.h" 24 #include "intel_pch_display.h" 25 #include "intel_pm.h" 26 27 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 28 struct drm_modeset_acquire_ctx *ctx) 29 { 30 struct intel_encoder *encoder; 31 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 32 struct intel_bw_state *bw_state = 33 to_intel_bw_state(i915->bw_obj.state); 34 struct intel_cdclk_state *cdclk_state = 35 to_intel_cdclk_state(i915->cdclk.obj.state); 36 struct intel_dbuf_state *dbuf_state = 37 to_intel_dbuf_state(i915->dbuf.obj.state); 38 struct intel_crtc_state *crtc_state = 39 to_intel_crtc_state(crtc->base.state); 40 struct intel_plane *plane; 41 struct drm_atomic_state *state; 42 struct intel_crtc_state *temp_crtc_state; 43 enum pipe pipe = crtc->pipe; 44 int ret; 45 46 if (!crtc_state->hw.active) 47 return; 48 49 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 50 const struct intel_plane_state *plane_state = 51 to_intel_plane_state(plane->base.state); 52 53 if (plane_state->uapi.visible) 54 intel_plane_disable_noatomic(crtc, plane); 55 } 56 57 state = drm_atomic_state_alloc(&i915->drm); 58 if (!state) { 59 drm_dbg_kms(&i915->drm, 60 "failed to disable [CRTC:%d:%s], out of memory", 61 crtc->base.base.id, crtc->base.name); 62 return; 63 } 64 65 state->acquire_ctx = ctx; 66 67 /* Everything's already locked, -EDEADLK can't happen. */ 68 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 69 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 70 71 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret); 72 73 i915->display->crtc_disable(to_intel_atomic_state(state), crtc); 74 75 drm_atomic_state_put(state); 76 77 drm_dbg_kms(&i915->drm, 78 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 79 crtc->base.base.id, crtc->base.name); 80 81 crtc->active = false; 82 crtc->base.enabled = false; 83 84 drm_WARN_ON(&i915->drm, 85 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 86 crtc_state->uapi.active = false; 87 crtc_state->uapi.connector_mask = 0; 88 crtc_state->uapi.encoder_mask = 0; 89 intel_crtc_free_hw_state(crtc_state); 90 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 91 92 for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) 93 encoder->base.crtc = NULL; 94 95 intel_fbc_disable(crtc); 96 intel_update_watermarks(i915); 97 intel_disable_shared_dpll(crtc_state); 98 99 intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains); 100 101 cdclk_state->min_cdclk[pipe] = 0; 102 cdclk_state->min_voltage_level[pipe] = 0; 103 cdclk_state->active_pipes &= ~BIT(pipe); 104 105 dbuf_state->active_pipes &= ~BIT(pipe); 106 107 bw_state->data_rate[pipe] = 0; 108 bw_state->num_active_planes[pipe] = 0; 109 } 110 111 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915) 112 { 113 struct intel_connector *connector; 114 struct drm_connector_list_iter conn_iter; 115 116 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 117 for_each_intel_connector_iter(connector, &conn_iter) { 118 struct drm_connector_state *conn_state = connector->base.state; 119 struct intel_encoder *encoder = 120 to_intel_encoder(connector->base.encoder); 121 122 if (conn_state->crtc) 123 drm_connector_put(&connector->base); 124 125 if (encoder) { 126 struct intel_crtc *crtc = 127 to_intel_crtc(encoder->base.crtc); 128 const struct intel_crtc_state *crtc_state = 129 to_intel_crtc_state(crtc->base.state); 130 131 conn_state->best_encoder = &encoder->base; 132 conn_state->crtc = &crtc->base; 133 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 134 135 drm_connector_get(&connector->base); 136 } else { 137 conn_state->best_encoder = NULL; 138 conn_state->crtc = NULL; 139 } 140 } 141 drm_connector_list_iter_end(&conn_iter); 142 } 143 144 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 145 { 146 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 147 return; 148 149 crtc_state->uapi.enable = crtc_state->hw.enable; 150 crtc_state->uapi.active = crtc_state->hw.active; 151 drm_WARN_ON(crtc_state->uapi.crtc->dev, 152 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 153 154 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 155 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 156 157 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 158 crtc_state->hw.degamma_lut); 159 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 160 crtc_state->hw.gamma_lut); 161 drm_property_replace_blob(&crtc_state->uapi.ctm, 162 crtc_state->hw.ctm); 163 } 164 165 static void 166 intel_sanitize_plane_mapping(struct drm_i915_private *i915) 167 { 168 struct intel_crtc *crtc; 169 170 if (DISPLAY_VER(i915) >= 4) 171 return; 172 173 for_each_intel_crtc(&i915->drm, crtc) { 174 struct intel_plane *plane = 175 to_intel_plane(crtc->base.primary); 176 struct intel_crtc *plane_crtc; 177 enum pipe pipe; 178 179 if (!plane->get_hw_state(plane, &pipe)) 180 continue; 181 182 if (pipe == crtc->pipe) 183 continue; 184 185 drm_dbg_kms(&i915->drm, 186 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 187 plane->base.base.id, plane->base.name); 188 189 plane_crtc = intel_crtc_for_pipe(i915, pipe); 190 intel_plane_disable_noatomic(plane_crtc, plane); 191 } 192 } 193 194 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 195 { 196 struct drm_device *dev = crtc->base.dev; 197 struct intel_encoder *encoder; 198 199 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 200 return true; 201 202 return false; 203 } 204 205 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 206 { 207 struct drm_device *dev = encoder->base.dev; 208 struct intel_connector *connector; 209 210 for_each_connector_on_encoder(dev, &encoder->base, connector) 211 return connector; 212 213 return NULL; 214 } 215 216 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state) 217 { 218 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 219 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 220 221 if (!crtc_state->hw.active && !HAS_GMCH(i915)) 222 return; 223 224 /* 225 * We start out with underrun reporting disabled to avoid races. 226 * For correct bookkeeping mark this on active crtcs. 227 * 228 * Also on gmch platforms we dont have any hardware bits to 229 * disable the underrun reporting. Which means we need to start 230 * out with underrun reporting disabled also on inactive pipes, 231 * since otherwise we'll complain about the garbage we read when 232 * e.g. coming up after runtime pm. 233 * 234 * No protection against concurrent access is required - at 235 * worst a fifo underrun happens which also sets this to false. 236 */ 237 crtc->cpu_fifo_underrun_disabled = true; 238 239 /* 240 * We track the PCH trancoder underrun reporting state 241 * within the crtc. With crtc for pipe A housing the underrun 242 * reporting state for PCH transcoder A, crtc for pipe B housing 243 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 244 * and marking underrun reporting as disabled for the non-existing 245 * PCH transcoders B and C would prevent enabling the south 246 * error interrupt (see cpt_can_enable_serr_int()). 247 */ 248 if (intel_has_pch_trancoder(i915, crtc->pipe)) 249 crtc->pch_fifo_underrun_disabled = true; 250 } 251 252 static void intel_sanitize_crtc(struct intel_crtc *crtc, 253 struct drm_modeset_acquire_ctx *ctx) 254 { 255 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 256 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 257 258 if (crtc_state->hw.active) { 259 struct intel_plane *plane; 260 261 /* Disable everything but the primary plane */ 262 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 263 const struct intel_plane_state *plane_state = 264 to_intel_plane_state(plane->base.state); 265 266 if (plane_state->uapi.visible && 267 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 268 intel_plane_disable_noatomic(crtc, plane); 269 } 270 271 /* Disable any background color/etc. set by the BIOS */ 272 intel_color_commit_noarm(crtc_state); 273 intel_color_commit_arm(crtc_state); 274 } 275 276 /* 277 * Adjust the state of the output pipe according to whether we have 278 * active connectors/encoders. 279 */ 280 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 281 !intel_crtc_is_bigjoiner_slave(crtc_state)) 282 intel_crtc_disable_noatomic(crtc, ctx); 283 } 284 285 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 286 { 287 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 288 289 /* 290 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 291 * the hardware when a high res displays plugged in. DPLL P 292 * divider is zero, and the pipe timings are bonkers. We'll 293 * try to disable everything in that case. 294 * 295 * FIXME would be nice to be able to sanitize this state 296 * without several WARNs, but for now let's take the easy 297 * road. 298 */ 299 return IS_SANDYBRIDGE(i915) && 300 crtc_state->hw.active && 301 crtc_state->shared_dpll && 302 crtc_state->port_clock == 0; 303 } 304 305 static void intel_sanitize_encoder(struct intel_encoder *encoder) 306 { 307 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 308 struct intel_connector *connector; 309 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 310 struct intel_crtc_state *crtc_state = crtc ? 311 to_intel_crtc_state(crtc->base.state) : NULL; 312 313 /* 314 * We need to check both for a crtc link (meaning that the encoder is 315 * active and trying to read from a pipe) and the pipe itself being 316 * active. 317 */ 318 bool has_active_crtc = crtc_state && 319 crtc_state->hw.active; 320 321 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 322 drm_dbg_kms(&i915->drm, 323 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 324 pipe_name(crtc->pipe)); 325 has_active_crtc = false; 326 } 327 328 connector = intel_encoder_find_connector(encoder); 329 if (connector && !has_active_crtc) { 330 drm_dbg_kms(&i915->drm, 331 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 332 encoder->base.base.id, 333 encoder->base.name); 334 335 /* 336 * Connector is active, but has no active pipe. This is fallout 337 * from our resume register restoring. Disable the encoder 338 * manually again. 339 */ 340 if (crtc_state) { 341 struct drm_encoder *best_encoder; 342 343 drm_dbg_kms(&i915->drm, 344 "[ENCODER:%d:%s] manually disabled\n", 345 encoder->base.base.id, 346 encoder->base.name); 347 348 /* avoid oopsing in case the hooks consult best_encoder */ 349 best_encoder = connector->base.state->best_encoder; 350 connector->base.state->best_encoder = &encoder->base; 351 352 /* FIXME NULL atomic state passed! */ 353 if (encoder->disable) 354 encoder->disable(NULL, encoder, crtc_state, 355 connector->base.state); 356 if (encoder->post_disable) 357 encoder->post_disable(NULL, encoder, crtc_state, 358 connector->base.state); 359 360 connector->base.state->best_encoder = best_encoder; 361 } 362 encoder->base.crtc = NULL; 363 364 /* 365 * Inconsistent output/port/pipe state happens presumably due to 366 * a bug in one of the get_hw_state functions. Or someplace else 367 * in our code, like the register restore mess on resume. Clamp 368 * things to off as a safer default. 369 */ 370 connector->base.dpms = DRM_MODE_DPMS_OFF; 371 connector->base.encoder = NULL; 372 } 373 374 /* notify opregion of the sanitized encoder state */ 375 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 376 377 if (HAS_DDI(i915)) 378 intel_ddi_sanitize_encoder_pll_mapping(encoder); 379 } 380 381 /* FIXME read out full plane state for all planes */ 382 static void readout_plane_state(struct drm_i915_private *i915) 383 { 384 struct intel_plane *plane; 385 struct intel_crtc *crtc; 386 387 for_each_intel_plane(&i915->drm, plane) { 388 struct intel_plane_state *plane_state = 389 to_intel_plane_state(plane->base.state); 390 struct intel_crtc_state *crtc_state; 391 enum pipe pipe = PIPE_A; 392 bool visible; 393 394 visible = plane->get_hw_state(plane, &pipe); 395 396 crtc = intel_crtc_for_pipe(i915, pipe); 397 crtc_state = to_intel_crtc_state(crtc->base.state); 398 399 intel_set_plane_visible(crtc_state, plane_state, visible); 400 401 drm_dbg_kms(&i915->drm, 402 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 403 plane->base.base.id, plane->base.name, 404 str_enabled_disabled(visible), pipe_name(pipe)); 405 } 406 407 for_each_intel_crtc(&i915->drm, crtc) { 408 struct intel_crtc_state *crtc_state = 409 to_intel_crtc_state(crtc->base.state); 410 411 intel_plane_fixup_bitmasks(crtc_state); 412 } 413 } 414 415 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) 416 { 417 struct intel_cdclk_state *cdclk_state = 418 to_intel_cdclk_state(i915->cdclk.obj.state); 419 struct intel_dbuf_state *dbuf_state = 420 to_intel_dbuf_state(i915->dbuf.obj.state); 421 enum pipe pipe; 422 struct intel_crtc *crtc; 423 struct intel_encoder *encoder; 424 struct intel_connector *connector; 425 struct drm_connector_list_iter conn_iter; 426 u8 active_pipes = 0; 427 428 for_each_intel_crtc(&i915->drm, crtc) { 429 struct intel_crtc_state *crtc_state = 430 to_intel_crtc_state(crtc->base.state); 431 432 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 433 intel_crtc_free_hw_state(crtc_state); 434 intel_crtc_state_reset(crtc_state, crtc); 435 436 intel_crtc_get_pipe_config(crtc_state); 437 438 crtc_state->hw.enable = crtc_state->hw.active; 439 440 crtc->base.enabled = crtc_state->hw.enable; 441 crtc->active = crtc_state->hw.active; 442 443 if (crtc_state->hw.active) 444 active_pipes |= BIT(crtc->pipe); 445 446 drm_dbg_kms(&i915->drm, 447 "[CRTC:%d:%s] hw state readout: %s\n", 448 crtc->base.base.id, crtc->base.name, 449 str_enabled_disabled(crtc_state->hw.active)); 450 } 451 452 cdclk_state->active_pipes = active_pipes; 453 dbuf_state->active_pipes = active_pipes; 454 455 readout_plane_state(i915); 456 457 for_each_intel_encoder(&i915->drm, encoder) { 458 struct intel_crtc_state *crtc_state = NULL; 459 460 pipe = 0; 461 462 if (encoder->get_hw_state(encoder, &pipe)) { 463 crtc = intel_crtc_for_pipe(i915, pipe); 464 crtc_state = to_intel_crtc_state(crtc->base.state); 465 466 encoder->base.crtc = &crtc->base; 467 intel_encoder_get_config(encoder, crtc_state); 468 469 /* read out to slave crtc as well for bigjoiner */ 470 if (crtc_state->bigjoiner_pipes) { 471 struct intel_crtc *slave_crtc; 472 473 /* encoder should read be linked to bigjoiner master */ 474 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 475 476 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 477 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 478 struct intel_crtc_state *slave_crtc_state; 479 480 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 481 intel_encoder_get_config(encoder, slave_crtc_state); 482 } 483 } 484 } else { 485 encoder->base.crtc = NULL; 486 } 487 488 if (encoder->sync_state) 489 encoder->sync_state(encoder, crtc_state); 490 491 drm_dbg_kms(&i915->drm, 492 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 493 encoder->base.base.id, encoder->base.name, 494 str_enabled_disabled(encoder->base.crtc), 495 pipe_name(pipe)); 496 } 497 498 intel_dpll_readout_hw_state(i915); 499 500 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 501 for_each_intel_connector_iter(connector, &conn_iter) { 502 if (connector->get_hw_state(connector)) { 503 struct intel_crtc_state *crtc_state; 504 struct intel_crtc *crtc; 505 506 connector->base.dpms = DRM_MODE_DPMS_ON; 507 508 encoder = intel_attached_encoder(connector); 509 connector->base.encoder = &encoder->base; 510 511 crtc = to_intel_crtc(encoder->base.crtc); 512 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 513 514 if (crtc_state && crtc_state->hw.active) { 515 /* 516 * This has to be done during hardware readout 517 * because anything calling .crtc_disable may 518 * rely on the connector_mask being accurate. 519 */ 520 crtc_state->uapi.connector_mask |= 521 drm_connector_mask(&connector->base); 522 crtc_state->uapi.encoder_mask |= 523 drm_encoder_mask(&encoder->base); 524 } 525 } else { 526 connector->base.dpms = DRM_MODE_DPMS_OFF; 527 connector->base.encoder = NULL; 528 } 529 drm_dbg_kms(&i915->drm, 530 "[CONNECTOR:%d:%s] hw state readout: %s\n", 531 connector->base.base.id, connector->base.name, 532 str_enabled_disabled(connector->base.encoder)); 533 } 534 drm_connector_list_iter_end(&conn_iter); 535 536 for_each_intel_crtc(&i915->drm, crtc) { 537 struct intel_bw_state *bw_state = 538 to_intel_bw_state(i915->bw_obj.state); 539 struct intel_crtc_state *crtc_state = 540 to_intel_crtc_state(crtc->base.state); 541 struct intel_plane *plane; 542 int min_cdclk = 0; 543 544 if (crtc_state->hw.active) { 545 /* 546 * The initial mode needs to be set in order to keep 547 * the atomic core happy. It wants a valid mode if the 548 * crtc's enabled, so we do the above call. 549 * 550 * But we don't set all the derived state fully, hence 551 * set a flag to indicate that a full recalculation is 552 * needed on the next commit. 553 */ 554 crtc_state->inherited = true; 555 556 intel_crtc_update_active_timings(crtc_state); 557 558 intel_crtc_copy_hw_to_uapi_state(crtc_state); 559 } 560 561 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 562 const struct intel_plane_state *plane_state = 563 to_intel_plane_state(plane->base.state); 564 565 /* 566 * FIXME don't have the fb yet, so can't 567 * use intel_plane_data_rate() :( 568 */ 569 if (plane_state->uapi.visible) 570 crtc_state->data_rate[plane->id] = 571 4 * crtc_state->pixel_rate; 572 /* 573 * FIXME don't have the fb yet, so can't 574 * use plane->min_cdclk() :( 575 */ 576 if (plane_state->uapi.visible && plane->min_cdclk) { 577 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10) 578 crtc_state->min_cdclk[plane->id] = 579 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 580 else 581 crtc_state->min_cdclk[plane->id] = 582 crtc_state->pixel_rate; 583 } 584 drm_dbg_kms(&i915->drm, 585 "[PLANE:%d:%s] min_cdclk %d kHz\n", 586 plane->base.base.id, plane->base.name, 587 crtc_state->min_cdclk[plane->id]); 588 } 589 590 if (crtc_state->hw.active) { 591 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 592 if (drm_WARN_ON(&i915->drm, min_cdclk < 0)) 593 min_cdclk = 0; 594 } 595 596 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 597 cdclk_state->min_voltage_level[crtc->pipe] = 598 crtc_state->min_voltage_level; 599 600 intel_bw_crtc_update(bw_state, crtc_state); 601 } 602 } 603 604 static void 605 get_encoder_power_domains(struct drm_i915_private *i915) 606 { 607 struct intel_encoder *encoder; 608 609 for_each_intel_encoder(&i915->drm, encoder) { 610 struct intel_crtc_state *crtc_state; 611 612 if (!encoder->get_power_domains) 613 continue; 614 615 /* 616 * MST-primary and inactive encoders don't have a crtc state 617 * and neither of these require any power domain references. 618 */ 619 if (!encoder->base.crtc) 620 continue; 621 622 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 623 encoder->get_power_domains(encoder, crtc_state); 624 } 625 } 626 627 static void intel_early_display_was(struct drm_i915_private *i915) 628 { 629 /* 630 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 631 * Also known as Wa_14010480278. 632 */ 633 if (IS_DISPLAY_VER(i915, 10, 12)) 634 intel_de_write(i915, GEN9_CLKGATE_DIS_0, 635 intel_de_read(i915, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 636 637 if (IS_HASWELL(i915)) { 638 /* 639 * WaRsPkgCStateDisplayPMReq:hsw 640 * System hang if this isn't done before disabling all planes! 641 */ 642 intel_de_write(i915, CHICKEN_PAR1_1, 643 intel_de_read(i915, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 644 } 645 646 if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) { 647 /* Display WA #1142:kbl,cfl,cml */ 648 intel_de_rmw(i915, CHICKEN_PAR1_1, 649 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 650 intel_de_rmw(i915, CHICKEN_MISC_2, 651 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 652 KBL_ARB_FILL_SPARE_14); 653 } 654 } 655 656 void intel_modeset_setup_hw_state(struct drm_i915_private *i915, 657 struct drm_modeset_acquire_ctx *ctx) 658 { 659 struct intel_encoder *encoder; 660 struct intel_crtc *crtc; 661 intel_wakeref_t wakeref; 662 663 wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 664 665 intel_early_display_was(i915); 666 intel_modeset_readout_hw_state(i915); 667 668 /* HW state is read out, now we need to sanitize this mess. */ 669 get_encoder_power_domains(i915); 670 671 intel_pch_sanitize(i915); 672 673 /* 674 * intel_sanitize_plane_mapping() may need to do vblank 675 * waits, so we need vblank interrupts restored beforehand. 676 */ 677 for_each_intel_crtc(&i915->drm, crtc) { 678 struct intel_crtc_state *crtc_state = 679 to_intel_crtc_state(crtc->base.state); 680 681 intel_sanitize_fifo_underrun_reporting(crtc_state); 682 683 drm_crtc_vblank_reset(&crtc->base); 684 685 if (crtc_state->hw.active) 686 intel_crtc_vblank_on(crtc_state); 687 } 688 689 intel_fbc_sanitize(i915); 690 691 intel_sanitize_plane_mapping(i915); 692 693 for_each_intel_encoder(&i915->drm, encoder) 694 intel_sanitize_encoder(encoder); 695 696 for_each_intel_crtc(&i915->drm, crtc) { 697 struct intel_crtc_state *crtc_state = 698 to_intel_crtc_state(crtc->base.state); 699 700 intel_sanitize_crtc(crtc, ctx); 701 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state"); 702 } 703 704 intel_modeset_update_connector_atomic_state(i915); 705 706 intel_dpll_sanitize_state(i915); 707 708 if (IS_G4X(i915)) { 709 g4x_wm_get_hw_state(i915); 710 g4x_wm_sanitize(i915); 711 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 712 vlv_wm_get_hw_state(i915); 713 vlv_wm_sanitize(i915); 714 } else if (DISPLAY_VER(i915) >= 9) { 715 skl_wm_get_hw_state(i915); 716 skl_wm_sanitize(i915); 717 } else if (HAS_PCH_SPLIT(i915)) { 718 ilk_wm_get_hw_state(i915); 719 } 720 721 for_each_intel_crtc(&i915->drm, crtc) { 722 struct intel_crtc_state *crtc_state = 723 to_intel_crtc_state(crtc->base.state); 724 struct intel_power_domain_mask put_domains; 725 726 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains); 727 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 728 intel_modeset_put_crtc_power_domains(crtc, &put_domains); 729 } 730 731 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 732 733 intel_power_domains_sanitize_state(i915); 734 } 735