1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 * 5 * Read out the current hardware modeset state, and sanitize it to the current 6 * state. 7 */ 8 9 #include <drm/drm_atomic_uapi.h> 10 #include <drm/drm_atomic_state_helper.h> 11 12 #include "i915_drv.h" 13 #include "intel_atomic.h" 14 #include "intel_bw.h" 15 #include "intel_color.h" 16 #include "intel_crtc.h" 17 #include "intel_crtc_state_dump.h" 18 #include "intel_ddi.h" 19 #include "intel_de.h" 20 #include "intel_display.h" 21 #include "intel_display_power.h" 22 #include "intel_display_types.h" 23 #include "intel_modeset_setup.h" 24 #include "intel_pch_display.h" 25 #include "intel_pm.h" 26 #include "skl_watermark.h" 27 28 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 29 struct drm_modeset_acquire_ctx *ctx) 30 { 31 struct intel_encoder *encoder; 32 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 33 struct intel_bw_state *bw_state = 34 to_intel_bw_state(i915->display.bw.obj.state); 35 struct intel_cdclk_state *cdclk_state = 36 to_intel_cdclk_state(i915->display.cdclk.obj.state); 37 struct intel_dbuf_state *dbuf_state = 38 to_intel_dbuf_state(i915->display.dbuf.obj.state); 39 struct intel_crtc_state *crtc_state = 40 to_intel_crtc_state(crtc->base.state); 41 struct intel_plane *plane; 42 struct drm_atomic_state *state; 43 struct intel_crtc_state *temp_crtc_state; 44 enum pipe pipe = crtc->pipe; 45 int ret; 46 47 if (!crtc_state->hw.active) 48 return; 49 50 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 51 const struct intel_plane_state *plane_state = 52 to_intel_plane_state(plane->base.state); 53 54 if (plane_state->uapi.visible) 55 intel_plane_disable_noatomic(crtc, plane); 56 } 57 58 state = drm_atomic_state_alloc(&i915->drm); 59 if (!state) { 60 drm_dbg_kms(&i915->drm, 61 "failed to disable [CRTC:%d:%s], out of memory", 62 crtc->base.base.id, crtc->base.name); 63 return; 64 } 65 66 state->acquire_ctx = ctx; 67 68 /* Everything's already locked, -EDEADLK can't happen. */ 69 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 70 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 71 72 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret); 73 74 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc); 75 76 drm_atomic_state_put(state); 77 78 drm_dbg_kms(&i915->drm, 79 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 80 crtc->base.base.id, crtc->base.name); 81 82 crtc->active = false; 83 crtc->base.enabled = false; 84 85 drm_WARN_ON(&i915->drm, 86 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 87 crtc_state->uapi.active = false; 88 crtc_state->uapi.connector_mask = 0; 89 crtc_state->uapi.encoder_mask = 0; 90 intel_crtc_free_hw_state(crtc_state); 91 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 92 93 for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) 94 encoder->base.crtc = NULL; 95 96 intel_fbc_disable(crtc); 97 intel_update_watermarks(i915); 98 intel_disable_shared_dpll(crtc_state); 99 100 intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains); 101 102 cdclk_state->min_cdclk[pipe] = 0; 103 cdclk_state->min_voltage_level[pipe] = 0; 104 cdclk_state->active_pipes &= ~BIT(pipe); 105 106 dbuf_state->active_pipes &= ~BIT(pipe); 107 108 bw_state->data_rate[pipe] = 0; 109 bw_state->num_active_planes[pipe] = 0; 110 } 111 112 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915) 113 { 114 struct intel_connector *connector; 115 struct drm_connector_list_iter conn_iter; 116 117 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 118 for_each_intel_connector_iter(connector, &conn_iter) { 119 struct drm_connector_state *conn_state = connector->base.state; 120 struct intel_encoder *encoder = 121 to_intel_encoder(connector->base.encoder); 122 123 if (conn_state->crtc) 124 drm_connector_put(&connector->base); 125 126 if (encoder) { 127 struct intel_crtc *crtc = 128 to_intel_crtc(encoder->base.crtc); 129 const struct intel_crtc_state *crtc_state = 130 to_intel_crtc_state(crtc->base.state); 131 132 conn_state->best_encoder = &encoder->base; 133 conn_state->crtc = &crtc->base; 134 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 135 136 drm_connector_get(&connector->base); 137 } else { 138 conn_state->best_encoder = NULL; 139 conn_state->crtc = NULL; 140 } 141 } 142 drm_connector_list_iter_end(&conn_iter); 143 } 144 145 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 146 { 147 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 148 return; 149 150 crtc_state->uapi.enable = crtc_state->hw.enable; 151 crtc_state->uapi.active = crtc_state->hw.active; 152 drm_WARN_ON(crtc_state->uapi.crtc->dev, 153 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 154 155 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 156 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 157 158 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 159 crtc_state->hw.degamma_lut); 160 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 161 crtc_state->hw.gamma_lut); 162 drm_property_replace_blob(&crtc_state->uapi.ctm, 163 crtc_state->hw.ctm); 164 } 165 166 static void 167 intel_sanitize_plane_mapping(struct drm_i915_private *i915) 168 { 169 struct intel_crtc *crtc; 170 171 if (DISPLAY_VER(i915) >= 4) 172 return; 173 174 for_each_intel_crtc(&i915->drm, crtc) { 175 struct intel_plane *plane = 176 to_intel_plane(crtc->base.primary); 177 struct intel_crtc *plane_crtc; 178 enum pipe pipe; 179 180 if (!plane->get_hw_state(plane, &pipe)) 181 continue; 182 183 if (pipe == crtc->pipe) 184 continue; 185 186 drm_dbg_kms(&i915->drm, 187 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 188 plane->base.base.id, plane->base.name); 189 190 plane_crtc = intel_crtc_for_pipe(i915, pipe); 191 intel_plane_disable_noatomic(plane_crtc, plane); 192 } 193 } 194 195 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 196 { 197 struct drm_device *dev = crtc->base.dev; 198 struct intel_encoder *encoder; 199 200 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 201 return true; 202 203 return false; 204 } 205 206 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 207 { 208 struct drm_device *dev = encoder->base.dev; 209 struct intel_connector *connector; 210 211 for_each_connector_on_encoder(dev, &encoder->base, connector) 212 return connector; 213 214 return NULL; 215 } 216 217 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state) 218 { 219 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 220 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 221 222 if (!crtc_state->hw.active && !HAS_GMCH(i915)) 223 return; 224 225 /* 226 * We start out with underrun reporting disabled to avoid races. 227 * For correct bookkeeping mark this on active crtcs. 228 * 229 * Also on gmch platforms we dont have any hardware bits to 230 * disable the underrun reporting. Which means we need to start 231 * out with underrun reporting disabled also on inactive pipes, 232 * since otherwise we'll complain about the garbage we read when 233 * e.g. coming up after runtime pm. 234 * 235 * No protection against concurrent access is required - at 236 * worst a fifo underrun happens which also sets this to false. 237 */ 238 crtc->cpu_fifo_underrun_disabled = true; 239 240 /* 241 * We track the PCH trancoder underrun reporting state 242 * within the crtc. With crtc for pipe A housing the underrun 243 * reporting state for PCH transcoder A, crtc for pipe B housing 244 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 245 * and marking underrun reporting as disabled for the non-existing 246 * PCH transcoders B and C would prevent enabling the south 247 * error interrupt (see cpt_can_enable_serr_int()). 248 */ 249 if (intel_has_pch_trancoder(i915, crtc->pipe)) 250 crtc->pch_fifo_underrun_disabled = true; 251 } 252 253 static void intel_sanitize_crtc(struct intel_crtc *crtc, 254 struct drm_modeset_acquire_ctx *ctx) 255 { 256 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 257 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 258 259 if (crtc_state->hw.active) { 260 struct intel_plane *plane; 261 262 /* Disable everything but the primary plane */ 263 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 264 const struct intel_plane_state *plane_state = 265 to_intel_plane_state(plane->base.state); 266 267 if (plane_state->uapi.visible && 268 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 269 intel_plane_disable_noatomic(crtc, plane); 270 } 271 272 /* Disable any background color/etc. set by the BIOS */ 273 intel_color_commit_noarm(crtc_state); 274 intel_color_commit_arm(crtc_state); 275 } 276 277 /* 278 * Adjust the state of the output pipe according to whether we have 279 * active connectors/encoders. 280 */ 281 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 282 !intel_crtc_is_bigjoiner_slave(crtc_state)) 283 intel_crtc_disable_noatomic(crtc, ctx); 284 } 285 286 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 287 { 288 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 289 290 /* 291 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 292 * the hardware when a high res displays plugged in. DPLL P 293 * divider is zero, and the pipe timings are bonkers. We'll 294 * try to disable everything in that case. 295 * 296 * FIXME would be nice to be able to sanitize this state 297 * without several WARNs, but for now let's take the easy 298 * road. 299 */ 300 return IS_SANDYBRIDGE(i915) && 301 crtc_state->hw.active && 302 crtc_state->shared_dpll && 303 crtc_state->port_clock == 0; 304 } 305 306 static void intel_sanitize_encoder(struct intel_encoder *encoder) 307 { 308 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 309 struct intel_connector *connector; 310 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 311 struct intel_crtc_state *crtc_state = crtc ? 312 to_intel_crtc_state(crtc->base.state) : NULL; 313 314 /* 315 * We need to check both for a crtc link (meaning that the encoder is 316 * active and trying to read from a pipe) and the pipe itself being 317 * active. 318 */ 319 bool has_active_crtc = crtc_state && 320 crtc_state->hw.active; 321 322 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 323 drm_dbg_kms(&i915->drm, 324 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 325 pipe_name(crtc->pipe)); 326 has_active_crtc = false; 327 } 328 329 connector = intel_encoder_find_connector(encoder); 330 if (connector && !has_active_crtc) { 331 drm_dbg_kms(&i915->drm, 332 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 333 encoder->base.base.id, 334 encoder->base.name); 335 336 /* 337 * Connector is active, but has no active pipe. This is fallout 338 * from our resume register restoring. Disable the encoder 339 * manually again. 340 */ 341 if (crtc_state) { 342 struct drm_encoder *best_encoder; 343 344 drm_dbg_kms(&i915->drm, 345 "[ENCODER:%d:%s] manually disabled\n", 346 encoder->base.base.id, 347 encoder->base.name); 348 349 /* avoid oopsing in case the hooks consult best_encoder */ 350 best_encoder = connector->base.state->best_encoder; 351 connector->base.state->best_encoder = &encoder->base; 352 353 /* FIXME NULL atomic state passed! */ 354 if (encoder->disable) 355 encoder->disable(NULL, encoder, crtc_state, 356 connector->base.state); 357 if (encoder->post_disable) 358 encoder->post_disable(NULL, encoder, crtc_state, 359 connector->base.state); 360 361 connector->base.state->best_encoder = best_encoder; 362 } 363 encoder->base.crtc = NULL; 364 365 /* 366 * Inconsistent output/port/pipe state happens presumably due to 367 * a bug in one of the get_hw_state functions. Or someplace else 368 * in our code, like the register restore mess on resume. Clamp 369 * things to off as a safer default. 370 */ 371 connector->base.dpms = DRM_MODE_DPMS_OFF; 372 connector->base.encoder = NULL; 373 } 374 375 /* notify opregion of the sanitized encoder state */ 376 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 377 378 if (HAS_DDI(i915)) 379 intel_ddi_sanitize_encoder_pll_mapping(encoder); 380 } 381 382 /* FIXME read out full plane state for all planes */ 383 static void readout_plane_state(struct drm_i915_private *i915) 384 { 385 struct intel_plane *plane; 386 struct intel_crtc *crtc; 387 388 for_each_intel_plane(&i915->drm, plane) { 389 struct intel_plane_state *plane_state = 390 to_intel_plane_state(plane->base.state); 391 struct intel_crtc_state *crtc_state; 392 enum pipe pipe = PIPE_A; 393 bool visible; 394 395 visible = plane->get_hw_state(plane, &pipe); 396 397 crtc = intel_crtc_for_pipe(i915, pipe); 398 crtc_state = to_intel_crtc_state(crtc->base.state); 399 400 intel_set_plane_visible(crtc_state, plane_state, visible); 401 402 drm_dbg_kms(&i915->drm, 403 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 404 plane->base.base.id, plane->base.name, 405 str_enabled_disabled(visible), pipe_name(pipe)); 406 } 407 408 for_each_intel_crtc(&i915->drm, crtc) { 409 struct intel_crtc_state *crtc_state = 410 to_intel_crtc_state(crtc->base.state); 411 412 intel_plane_fixup_bitmasks(crtc_state); 413 } 414 } 415 416 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) 417 { 418 struct intel_cdclk_state *cdclk_state = 419 to_intel_cdclk_state(i915->display.cdclk.obj.state); 420 struct intel_dbuf_state *dbuf_state = 421 to_intel_dbuf_state(i915->display.dbuf.obj.state); 422 enum pipe pipe; 423 struct intel_crtc *crtc; 424 struct intel_encoder *encoder; 425 struct intel_connector *connector; 426 struct drm_connector_list_iter conn_iter; 427 u8 active_pipes = 0; 428 429 for_each_intel_crtc(&i915->drm, crtc) { 430 struct intel_crtc_state *crtc_state = 431 to_intel_crtc_state(crtc->base.state); 432 433 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 434 intel_crtc_free_hw_state(crtc_state); 435 intel_crtc_state_reset(crtc_state, crtc); 436 437 intel_crtc_get_pipe_config(crtc_state); 438 439 crtc_state->hw.enable = crtc_state->hw.active; 440 441 crtc->base.enabled = crtc_state->hw.enable; 442 crtc->active = crtc_state->hw.active; 443 444 if (crtc_state->hw.active) 445 active_pipes |= BIT(crtc->pipe); 446 447 drm_dbg_kms(&i915->drm, 448 "[CRTC:%d:%s] hw state readout: %s\n", 449 crtc->base.base.id, crtc->base.name, 450 str_enabled_disabled(crtc_state->hw.active)); 451 } 452 453 cdclk_state->active_pipes = active_pipes; 454 dbuf_state->active_pipes = active_pipes; 455 456 readout_plane_state(i915); 457 458 for_each_intel_encoder(&i915->drm, encoder) { 459 struct intel_crtc_state *crtc_state = NULL; 460 461 pipe = 0; 462 463 if (encoder->get_hw_state(encoder, &pipe)) { 464 crtc = intel_crtc_for_pipe(i915, pipe); 465 crtc_state = to_intel_crtc_state(crtc->base.state); 466 467 encoder->base.crtc = &crtc->base; 468 intel_encoder_get_config(encoder, crtc_state); 469 470 /* read out to slave crtc as well for bigjoiner */ 471 if (crtc_state->bigjoiner_pipes) { 472 struct intel_crtc *slave_crtc; 473 474 /* encoder should read be linked to bigjoiner master */ 475 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 476 477 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 478 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 479 struct intel_crtc_state *slave_crtc_state; 480 481 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 482 intel_encoder_get_config(encoder, slave_crtc_state); 483 } 484 } 485 } else { 486 encoder->base.crtc = NULL; 487 } 488 489 if (encoder->sync_state) 490 encoder->sync_state(encoder, crtc_state); 491 492 drm_dbg_kms(&i915->drm, 493 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 494 encoder->base.base.id, encoder->base.name, 495 str_enabled_disabled(encoder->base.crtc), 496 pipe_name(pipe)); 497 } 498 499 intel_dpll_readout_hw_state(i915); 500 501 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 502 for_each_intel_connector_iter(connector, &conn_iter) { 503 if (connector->get_hw_state(connector)) { 504 struct intel_crtc_state *crtc_state; 505 struct intel_crtc *crtc; 506 507 connector->base.dpms = DRM_MODE_DPMS_ON; 508 509 encoder = intel_attached_encoder(connector); 510 connector->base.encoder = &encoder->base; 511 512 crtc = to_intel_crtc(encoder->base.crtc); 513 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 514 515 if (crtc_state && crtc_state->hw.active) { 516 /* 517 * This has to be done during hardware readout 518 * because anything calling .crtc_disable may 519 * rely on the connector_mask being accurate. 520 */ 521 crtc_state->uapi.connector_mask |= 522 drm_connector_mask(&connector->base); 523 crtc_state->uapi.encoder_mask |= 524 drm_encoder_mask(&encoder->base); 525 } 526 } else { 527 connector->base.dpms = DRM_MODE_DPMS_OFF; 528 connector->base.encoder = NULL; 529 } 530 drm_dbg_kms(&i915->drm, 531 "[CONNECTOR:%d:%s] hw state readout: %s\n", 532 connector->base.base.id, connector->base.name, 533 str_enabled_disabled(connector->base.encoder)); 534 } 535 drm_connector_list_iter_end(&conn_iter); 536 537 for_each_intel_crtc(&i915->drm, crtc) { 538 struct intel_bw_state *bw_state = 539 to_intel_bw_state(i915->display.bw.obj.state); 540 struct intel_crtc_state *crtc_state = 541 to_intel_crtc_state(crtc->base.state); 542 struct intel_plane *plane; 543 int min_cdclk = 0; 544 545 if (crtc_state->hw.active) { 546 /* 547 * The initial mode needs to be set in order to keep 548 * the atomic core happy. It wants a valid mode if the 549 * crtc's enabled, so we do the above call. 550 * 551 * But we don't set all the derived state fully, hence 552 * set a flag to indicate that a full recalculation is 553 * needed on the next commit. 554 */ 555 crtc_state->inherited = true; 556 557 intel_crtc_update_active_timings(crtc_state); 558 559 intel_crtc_copy_hw_to_uapi_state(crtc_state); 560 } 561 562 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 563 const struct intel_plane_state *plane_state = 564 to_intel_plane_state(plane->base.state); 565 566 /* 567 * FIXME don't have the fb yet, so can't 568 * use intel_plane_data_rate() :( 569 */ 570 if (plane_state->uapi.visible) 571 crtc_state->data_rate[plane->id] = 572 4 * crtc_state->pixel_rate; 573 /* 574 * FIXME don't have the fb yet, so can't 575 * use plane->min_cdclk() :( 576 */ 577 if (plane_state->uapi.visible && plane->min_cdclk) { 578 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10) 579 crtc_state->min_cdclk[plane->id] = 580 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 581 else 582 crtc_state->min_cdclk[plane->id] = 583 crtc_state->pixel_rate; 584 } 585 drm_dbg_kms(&i915->drm, 586 "[PLANE:%d:%s] min_cdclk %d kHz\n", 587 plane->base.base.id, plane->base.name, 588 crtc_state->min_cdclk[plane->id]); 589 } 590 591 if (crtc_state->hw.active) { 592 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 593 if (drm_WARN_ON(&i915->drm, min_cdclk < 0)) 594 min_cdclk = 0; 595 } 596 597 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 598 cdclk_state->min_voltage_level[crtc->pipe] = 599 crtc_state->min_voltage_level; 600 601 intel_bw_crtc_update(bw_state, crtc_state); 602 } 603 } 604 605 static void 606 get_encoder_power_domains(struct drm_i915_private *i915) 607 { 608 struct intel_encoder *encoder; 609 610 for_each_intel_encoder(&i915->drm, encoder) { 611 struct intel_crtc_state *crtc_state; 612 613 if (!encoder->get_power_domains) 614 continue; 615 616 /* 617 * MST-primary and inactive encoders don't have a crtc state 618 * and neither of these require any power domain references. 619 */ 620 if (!encoder->base.crtc) 621 continue; 622 623 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 624 encoder->get_power_domains(encoder, crtc_state); 625 } 626 } 627 628 static void intel_early_display_was(struct drm_i915_private *i915) 629 { 630 /* 631 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 632 * Also known as Wa_14010480278. 633 */ 634 if (IS_DISPLAY_VER(i915, 10, 12)) 635 intel_de_write(i915, GEN9_CLKGATE_DIS_0, 636 intel_de_read(i915, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 637 638 if (IS_HASWELL(i915)) { 639 /* 640 * WaRsPkgCStateDisplayPMReq:hsw 641 * System hang if this isn't done before disabling all planes! 642 */ 643 intel_de_write(i915, CHICKEN_PAR1_1, 644 intel_de_read(i915, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 645 } 646 647 if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) { 648 /* Display WA #1142:kbl,cfl,cml */ 649 intel_de_rmw(i915, CHICKEN_PAR1_1, 650 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 651 intel_de_rmw(i915, CHICKEN_MISC_2, 652 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 653 KBL_ARB_FILL_SPARE_14); 654 } 655 } 656 657 void intel_modeset_setup_hw_state(struct drm_i915_private *i915, 658 struct drm_modeset_acquire_ctx *ctx) 659 { 660 struct intel_encoder *encoder; 661 struct intel_crtc *crtc; 662 intel_wakeref_t wakeref; 663 664 wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 665 666 intel_early_display_was(i915); 667 intel_modeset_readout_hw_state(i915); 668 669 /* HW state is read out, now we need to sanitize this mess. */ 670 get_encoder_power_domains(i915); 671 672 intel_pch_sanitize(i915); 673 674 /* 675 * intel_sanitize_plane_mapping() may need to do vblank 676 * waits, so we need vblank interrupts restored beforehand. 677 */ 678 for_each_intel_crtc(&i915->drm, crtc) { 679 struct intel_crtc_state *crtc_state = 680 to_intel_crtc_state(crtc->base.state); 681 682 intel_sanitize_fifo_underrun_reporting(crtc_state); 683 684 drm_crtc_vblank_reset(&crtc->base); 685 686 if (crtc_state->hw.active) 687 intel_crtc_vblank_on(crtc_state); 688 } 689 690 intel_fbc_sanitize(i915); 691 692 intel_sanitize_plane_mapping(i915); 693 694 for_each_intel_encoder(&i915->drm, encoder) 695 intel_sanitize_encoder(encoder); 696 697 for_each_intel_crtc(&i915->drm, crtc) { 698 struct intel_crtc_state *crtc_state = 699 to_intel_crtc_state(crtc->base.state); 700 701 intel_sanitize_crtc(crtc, ctx); 702 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state"); 703 } 704 705 intel_modeset_update_connector_atomic_state(i915); 706 707 intel_dpll_sanitize_state(i915); 708 709 if (IS_G4X(i915)) { 710 g4x_wm_get_hw_state(i915); 711 g4x_wm_sanitize(i915); 712 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 713 vlv_wm_get_hw_state(i915); 714 vlv_wm_sanitize(i915); 715 } else if (DISPLAY_VER(i915) >= 9) { 716 skl_wm_get_hw_state(i915); 717 skl_wm_sanitize(i915); 718 } else if (HAS_PCH_SPLIT(i915)) { 719 ilk_wm_get_hw_state(i915); 720 } 721 722 for_each_intel_crtc(&i915->drm, crtc) { 723 struct intel_crtc_state *crtc_state = 724 to_intel_crtc_state(crtc->base.state); 725 struct intel_power_domain_mask put_domains; 726 727 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains); 728 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 729 intel_modeset_put_crtc_power_domains(crtc, &put_domains); 730 } 731 732 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 733 734 intel_power_domains_sanitize_state(i915); 735 } 736