1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 * 5 * Read out the current hardware modeset state, and sanitize it to the current 6 * state. 7 */ 8 9 #include <drm/drm_atomic_uapi.h> 10 #include <drm/drm_atomic_state_helper.h> 11 12 #include "i915_drv.h" 13 #include "i915_reg.h" 14 #include "i9xx_wm.h" 15 #include "intel_atomic.h" 16 #include "intel_bw.h" 17 #include "intel_color.h" 18 #include "intel_crtc.h" 19 #include "intel_crtc_state_dump.h" 20 #include "intel_ddi.h" 21 #include "intel_de.h" 22 #include "intel_display.h" 23 #include "intel_display_power.h" 24 #include "intel_display_types.h" 25 #include "intel_dmc.h" 26 #include "intel_fifo_underrun.h" 27 #include "intel_modeset_setup.h" 28 #include "intel_pch_display.h" 29 #include "intel_vblank.h" 30 #include "intel_wm.h" 31 #include "skl_watermark.h" 32 33 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 34 struct drm_modeset_acquire_ctx *ctx) 35 { 36 struct intel_encoder *encoder; 37 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 38 struct intel_bw_state *bw_state = 39 to_intel_bw_state(i915->display.bw.obj.state); 40 struct intel_cdclk_state *cdclk_state = 41 to_intel_cdclk_state(i915->display.cdclk.obj.state); 42 struct intel_dbuf_state *dbuf_state = 43 to_intel_dbuf_state(i915->display.dbuf.obj.state); 44 struct intel_crtc_state *crtc_state = 45 to_intel_crtc_state(crtc->base.state); 46 struct intel_plane *plane; 47 struct drm_atomic_state *state; 48 struct intel_crtc_state *temp_crtc_state; 49 enum pipe pipe = crtc->pipe; 50 int ret; 51 52 if (!crtc_state->hw.active) 53 return; 54 55 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 56 const struct intel_plane_state *plane_state = 57 to_intel_plane_state(plane->base.state); 58 59 if (plane_state->uapi.visible) 60 intel_plane_disable_noatomic(crtc, plane); 61 } 62 63 state = drm_atomic_state_alloc(&i915->drm); 64 if (!state) { 65 drm_dbg_kms(&i915->drm, 66 "failed to disable [CRTC:%d:%s], out of memory", 67 crtc->base.base.id, crtc->base.name); 68 return; 69 } 70 71 state->acquire_ctx = ctx; 72 73 /* Everything's already locked, -EDEADLK can't happen. */ 74 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 75 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 76 77 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret); 78 79 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc); 80 81 drm_atomic_state_put(state); 82 83 drm_dbg_kms(&i915->drm, 84 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 85 crtc->base.base.id, crtc->base.name); 86 87 crtc->active = false; 88 crtc->base.enabled = false; 89 90 drm_WARN_ON(&i915->drm, 91 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 92 crtc_state->uapi.active = false; 93 crtc_state->uapi.connector_mask = 0; 94 crtc_state->uapi.encoder_mask = 0; 95 intel_crtc_free_hw_state(crtc_state); 96 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 97 98 for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) 99 encoder->base.crtc = NULL; 100 101 intel_fbc_disable(crtc); 102 intel_update_watermarks(i915); 103 intel_disable_shared_dpll(crtc_state); 104 105 intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains); 106 107 cdclk_state->min_cdclk[pipe] = 0; 108 cdclk_state->min_voltage_level[pipe] = 0; 109 cdclk_state->active_pipes &= ~BIT(pipe); 110 111 dbuf_state->active_pipes &= ~BIT(pipe); 112 113 bw_state->data_rate[pipe] = 0; 114 bw_state->num_active_planes[pipe] = 0; 115 } 116 117 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915) 118 { 119 struct intel_connector *connector; 120 struct drm_connector_list_iter conn_iter; 121 122 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 123 for_each_intel_connector_iter(connector, &conn_iter) { 124 struct drm_connector_state *conn_state = connector->base.state; 125 struct intel_encoder *encoder = 126 to_intel_encoder(connector->base.encoder); 127 128 if (conn_state->crtc) 129 drm_connector_put(&connector->base); 130 131 if (encoder) { 132 struct intel_crtc *crtc = 133 to_intel_crtc(encoder->base.crtc); 134 const struct intel_crtc_state *crtc_state = 135 to_intel_crtc_state(crtc->base.state); 136 137 conn_state->best_encoder = &encoder->base; 138 conn_state->crtc = &crtc->base; 139 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 140 141 drm_connector_get(&connector->base); 142 } else { 143 conn_state->best_encoder = NULL; 144 conn_state->crtc = NULL; 145 } 146 } 147 drm_connector_list_iter_end(&conn_iter); 148 } 149 150 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 151 { 152 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 153 return; 154 155 crtc_state->uapi.enable = crtc_state->hw.enable; 156 crtc_state->uapi.active = crtc_state->hw.active; 157 drm_WARN_ON(crtc_state->uapi.crtc->dev, 158 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 159 160 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 161 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 162 163 /* assume 1:1 mapping */ 164 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 165 crtc_state->pre_csc_lut); 166 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 167 crtc_state->post_csc_lut); 168 169 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 170 crtc_state->hw.degamma_lut); 171 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 172 crtc_state->hw.gamma_lut); 173 drm_property_replace_blob(&crtc_state->uapi.ctm, 174 crtc_state->hw.ctm); 175 } 176 177 static void 178 intel_sanitize_plane_mapping(struct drm_i915_private *i915) 179 { 180 struct intel_crtc *crtc; 181 182 if (DISPLAY_VER(i915) >= 4) 183 return; 184 185 for_each_intel_crtc(&i915->drm, crtc) { 186 struct intel_plane *plane = 187 to_intel_plane(crtc->base.primary); 188 struct intel_crtc *plane_crtc; 189 enum pipe pipe; 190 191 if (!plane->get_hw_state(plane, &pipe)) 192 continue; 193 194 if (pipe == crtc->pipe) 195 continue; 196 197 drm_dbg_kms(&i915->drm, 198 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 199 plane->base.base.id, plane->base.name); 200 201 plane_crtc = intel_crtc_for_pipe(i915, pipe); 202 intel_plane_disable_noatomic(plane_crtc, plane); 203 } 204 } 205 206 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 207 { 208 struct drm_device *dev = crtc->base.dev; 209 struct intel_encoder *encoder; 210 211 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 212 return true; 213 214 return false; 215 } 216 217 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 218 { 219 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 220 struct drm_connector_list_iter conn_iter; 221 struct intel_connector *connector; 222 struct intel_connector *found_connector = NULL; 223 224 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 225 for_each_intel_connector_iter(connector, &conn_iter) { 226 if (&encoder->base == connector->base.encoder) { 227 found_connector = connector; 228 break; 229 } 230 } 231 drm_connector_list_iter_end(&conn_iter); 232 233 return found_connector; 234 } 235 236 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state) 237 { 238 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 239 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 240 241 /* 242 * We start out with underrun reporting disabled on active 243 * pipes to avoid races. 244 * 245 * Also on gmch platforms we dont have any hardware bits to 246 * disable the underrun reporting. Which means we need to start 247 * out with underrun reporting disabled also on inactive pipes, 248 * since otherwise we'll complain about the garbage we read when 249 * e.g. coming up after runtime pm. 250 * 251 * No protection against concurrent access is required - at 252 * worst a fifo underrun happens which also sets this to false. 253 */ 254 intel_init_fifo_underrun_reporting(i915, crtc, 255 !crtc_state->hw.active && 256 !HAS_GMCH(i915)); 257 } 258 259 static void intel_sanitize_crtc(struct intel_crtc *crtc, 260 struct drm_modeset_acquire_ctx *ctx) 261 { 262 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 263 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 264 265 if (crtc_state->hw.active) { 266 struct intel_plane *plane; 267 268 /* Disable everything but the primary plane */ 269 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 270 const struct intel_plane_state *plane_state = 271 to_intel_plane_state(plane->base.state); 272 273 if (plane_state->uapi.visible && 274 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 275 intel_plane_disable_noatomic(crtc, plane); 276 } 277 278 /* Disable any background color/etc. set by the BIOS */ 279 intel_color_commit_noarm(crtc_state); 280 intel_color_commit_arm(crtc_state); 281 } 282 283 /* 284 * Adjust the state of the output pipe according to whether we have 285 * active connectors/encoders. 286 */ 287 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 288 !intel_crtc_is_bigjoiner_slave(crtc_state)) 289 intel_crtc_disable_noatomic(crtc, ctx); 290 } 291 292 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 293 { 294 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 295 296 /* 297 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 298 * the hardware when a high res displays plugged in. DPLL P 299 * divider is zero, and the pipe timings are bonkers. We'll 300 * try to disable everything in that case. 301 * 302 * FIXME would be nice to be able to sanitize this state 303 * without several WARNs, but for now let's take the easy 304 * road. 305 */ 306 return IS_SANDYBRIDGE(i915) && 307 crtc_state->hw.active && 308 crtc_state->shared_dpll && 309 crtc_state->port_clock == 0; 310 } 311 312 static void intel_sanitize_encoder(struct intel_encoder *encoder) 313 { 314 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 315 struct intel_connector *connector; 316 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 317 struct intel_crtc_state *crtc_state = crtc ? 318 to_intel_crtc_state(crtc->base.state) : NULL; 319 320 /* 321 * We need to check both for a crtc link (meaning that the encoder is 322 * active and trying to read from a pipe) and the pipe itself being 323 * active. 324 */ 325 bool has_active_crtc = crtc_state && 326 crtc_state->hw.active; 327 328 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 329 drm_dbg_kms(&i915->drm, 330 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 331 pipe_name(crtc->pipe)); 332 has_active_crtc = false; 333 } 334 335 connector = intel_encoder_find_connector(encoder); 336 if (connector && !has_active_crtc) { 337 drm_dbg_kms(&i915->drm, 338 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 339 encoder->base.base.id, 340 encoder->base.name); 341 342 /* 343 * Connector is active, but has no active pipe. This is fallout 344 * from our resume register restoring. Disable the encoder 345 * manually again. 346 */ 347 if (crtc_state) { 348 struct drm_encoder *best_encoder; 349 350 drm_dbg_kms(&i915->drm, 351 "[ENCODER:%d:%s] manually disabled\n", 352 encoder->base.base.id, 353 encoder->base.name); 354 355 /* avoid oopsing in case the hooks consult best_encoder */ 356 best_encoder = connector->base.state->best_encoder; 357 connector->base.state->best_encoder = &encoder->base; 358 359 /* FIXME NULL atomic state passed! */ 360 if (encoder->disable) 361 encoder->disable(NULL, encoder, crtc_state, 362 connector->base.state); 363 if (encoder->post_disable) 364 encoder->post_disable(NULL, encoder, crtc_state, 365 connector->base.state); 366 367 connector->base.state->best_encoder = best_encoder; 368 } 369 encoder->base.crtc = NULL; 370 371 /* 372 * Inconsistent output/port/pipe state happens presumably due to 373 * a bug in one of the get_hw_state functions. Or someplace else 374 * in our code, like the register restore mess on resume. Clamp 375 * things to off as a safer default. 376 */ 377 connector->base.dpms = DRM_MODE_DPMS_OFF; 378 connector->base.encoder = NULL; 379 } 380 381 /* notify opregion of the sanitized encoder state */ 382 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 383 384 if (HAS_DDI(i915)) 385 intel_ddi_sanitize_encoder_pll_mapping(encoder); 386 } 387 388 /* FIXME read out full plane state for all planes */ 389 static void readout_plane_state(struct drm_i915_private *i915) 390 { 391 struct intel_plane *plane; 392 struct intel_crtc *crtc; 393 394 for_each_intel_plane(&i915->drm, plane) { 395 struct intel_plane_state *plane_state = 396 to_intel_plane_state(plane->base.state); 397 struct intel_crtc_state *crtc_state; 398 enum pipe pipe = PIPE_A; 399 bool visible; 400 401 visible = plane->get_hw_state(plane, &pipe); 402 403 crtc = intel_crtc_for_pipe(i915, pipe); 404 crtc_state = to_intel_crtc_state(crtc->base.state); 405 406 intel_set_plane_visible(crtc_state, plane_state, visible); 407 408 drm_dbg_kms(&i915->drm, 409 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 410 plane->base.base.id, plane->base.name, 411 str_enabled_disabled(visible), pipe_name(pipe)); 412 } 413 414 for_each_intel_crtc(&i915->drm, crtc) { 415 struct intel_crtc_state *crtc_state = 416 to_intel_crtc_state(crtc->base.state); 417 418 intel_plane_fixup_bitmasks(crtc_state); 419 } 420 } 421 422 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) 423 { 424 struct intel_cdclk_state *cdclk_state = 425 to_intel_cdclk_state(i915->display.cdclk.obj.state); 426 struct intel_dbuf_state *dbuf_state = 427 to_intel_dbuf_state(i915->display.dbuf.obj.state); 428 enum pipe pipe; 429 struct intel_crtc *crtc; 430 struct intel_encoder *encoder; 431 struct intel_connector *connector; 432 struct drm_connector_list_iter conn_iter; 433 u8 active_pipes = 0; 434 435 for_each_intel_crtc(&i915->drm, crtc) { 436 struct intel_crtc_state *crtc_state = 437 to_intel_crtc_state(crtc->base.state); 438 439 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 440 intel_crtc_free_hw_state(crtc_state); 441 intel_crtc_state_reset(crtc_state, crtc); 442 443 intel_crtc_get_pipe_config(crtc_state); 444 445 crtc_state->hw.enable = crtc_state->hw.active; 446 447 crtc->base.enabled = crtc_state->hw.enable; 448 crtc->active = crtc_state->hw.active; 449 450 if (crtc_state->hw.active) 451 active_pipes |= BIT(crtc->pipe); 452 453 drm_dbg_kms(&i915->drm, 454 "[CRTC:%d:%s] hw state readout: %s\n", 455 crtc->base.base.id, crtc->base.name, 456 str_enabled_disabled(crtc_state->hw.active)); 457 } 458 459 cdclk_state->active_pipes = active_pipes; 460 dbuf_state->active_pipes = active_pipes; 461 462 readout_plane_state(i915); 463 464 for_each_intel_encoder(&i915->drm, encoder) { 465 struct intel_crtc_state *crtc_state = NULL; 466 467 pipe = 0; 468 469 if (encoder->get_hw_state(encoder, &pipe)) { 470 crtc = intel_crtc_for_pipe(i915, pipe); 471 crtc_state = to_intel_crtc_state(crtc->base.state); 472 473 encoder->base.crtc = &crtc->base; 474 intel_encoder_get_config(encoder, crtc_state); 475 476 /* read out to slave crtc as well for bigjoiner */ 477 if (crtc_state->bigjoiner_pipes) { 478 struct intel_crtc *slave_crtc; 479 480 /* encoder should read be linked to bigjoiner master */ 481 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 482 483 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 484 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 485 struct intel_crtc_state *slave_crtc_state; 486 487 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 488 intel_encoder_get_config(encoder, slave_crtc_state); 489 } 490 } 491 } else { 492 encoder->base.crtc = NULL; 493 } 494 495 if (encoder->sync_state) 496 encoder->sync_state(encoder, crtc_state); 497 498 drm_dbg_kms(&i915->drm, 499 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 500 encoder->base.base.id, encoder->base.name, 501 str_enabled_disabled(encoder->base.crtc), 502 pipe_name(pipe)); 503 } 504 505 intel_dpll_readout_hw_state(i915); 506 507 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 508 for_each_intel_connector_iter(connector, &conn_iter) { 509 if (connector->get_hw_state(connector)) { 510 struct intel_crtc_state *crtc_state; 511 struct intel_crtc *crtc; 512 513 connector->base.dpms = DRM_MODE_DPMS_ON; 514 515 encoder = intel_attached_encoder(connector); 516 connector->base.encoder = &encoder->base; 517 518 crtc = to_intel_crtc(encoder->base.crtc); 519 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 520 521 if (crtc_state && crtc_state->hw.active) { 522 /* 523 * This has to be done during hardware readout 524 * because anything calling .crtc_disable may 525 * rely on the connector_mask being accurate. 526 */ 527 crtc_state->uapi.connector_mask |= 528 drm_connector_mask(&connector->base); 529 crtc_state->uapi.encoder_mask |= 530 drm_encoder_mask(&encoder->base); 531 } 532 } else { 533 connector->base.dpms = DRM_MODE_DPMS_OFF; 534 connector->base.encoder = NULL; 535 } 536 drm_dbg_kms(&i915->drm, 537 "[CONNECTOR:%d:%s] hw state readout: %s\n", 538 connector->base.base.id, connector->base.name, 539 str_enabled_disabled(connector->base.encoder)); 540 } 541 drm_connector_list_iter_end(&conn_iter); 542 543 for_each_intel_crtc(&i915->drm, crtc) { 544 struct intel_bw_state *bw_state = 545 to_intel_bw_state(i915->display.bw.obj.state); 546 struct intel_crtc_state *crtc_state = 547 to_intel_crtc_state(crtc->base.state); 548 struct intel_plane *plane; 549 int min_cdclk = 0; 550 551 if (crtc_state->hw.active) { 552 /* 553 * The initial mode needs to be set in order to keep 554 * the atomic core happy. It wants a valid mode if the 555 * crtc's enabled, so we do the above call. 556 * 557 * But we don't set all the derived state fully, hence 558 * set a flag to indicate that a full recalculation is 559 * needed on the next commit. 560 */ 561 crtc_state->inherited = true; 562 563 intel_crtc_update_active_timings(crtc_state); 564 565 intel_crtc_copy_hw_to_uapi_state(crtc_state); 566 } 567 568 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 569 const struct intel_plane_state *plane_state = 570 to_intel_plane_state(plane->base.state); 571 572 /* 573 * FIXME don't have the fb yet, so can't 574 * use intel_plane_data_rate() :( 575 */ 576 if (plane_state->uapi.visible) 577 crtc_state->data_rate[plane->id] = 578 4 * crtc_state->pixel_rate; 579 /* 580 * FIXME don't have the fb yet, so can't 581 * use plane->min_cdclk() :( 582 */ 583 if (plane_state->uapi.visible && plane->min_cdclk) { 584 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10) 585 crtc_state->min_cdclk[plane->id] = 586 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 587 else 588 crtc_state->min_cdclk[plane->id] = 589 crtc_state->pixel_rate; 590 } 591 drm_dbg_kms(&i915->drm, 592 "[PLANE:%d:%s] min_cdclk %d kHz\n", 593 plane->base.base.id, plane->base.name, 594 crtc_state->min_cdclk[plane->id]); 595 } 596 597 if (crtc_state->hw.active) { 598 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 599 if (drm_WARN_ON(&i915->drm, min_cdclk < 0)) 600 min_cdclk = 0; 601 } 602 603 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 604 cdclk_state->min_voltage_level[crtc->pipe] = 605 crtc_state->min_voltage_level; 606 607 intel_bw_crtc_update(bw_state, crtc_state); 608 } 609 } 610 611 static void 612 get_encoder_power_domains(struct drm_i915_private *i915) 613 { 614 struct intel_encoder *encoder; 615 616 for_each_intel_encoder(&i915->drm, encoder) { 617 struct intel_crtc_state *crtc_state; 618 619 if (!encoder->get_power_domains) 620 continue; 621 622 /* 623 * MST-primary and inactive encoders don't have a crtc state 624 * and neither of these require any power domain references. 625 */ 626 if (!encoder->base.crtc) 627 continue; 628 629 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 630 encoder->get_power_domains(encoder, crtc_state); 631 } 632 } 633 634 static void intel_early_display_was(struct drm_i915_private *i915) 635 { 636 /* 637 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 638 * Also known as Wa_14010480278. 639 */ 640 if (IS_DISPLAY_VER(i915, 10, 12)) 641 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS); 642 643 /* 644 * WaRsPkgCStateDisplayPMReq:hsw 645 * System hang if this isn't done before disabling all planes! 646 */ 647 if (IS_HASWELL(i915)) 648 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES); 649 650 if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) { 651 /* Display WA #1142:kbl,cfl,cml */ 652 intel_de_rmw(i915, CHICKEN_PAR1_1, 653 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 654 intel_de_rmw(i915, CHICKEN_MISC_2, 655 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 656 KBL_ARB_FILL_SPARE_14); 657 } 658 } 659 660 void intel_modeset_setup_hw_state(struct drm_i915_private *i915, 661 struct drm_modeset_acquire_ctx *ctx) 662 { 663 struct intel_encoder *encoder; 664 struct intel_crtc *crtc; 665 intel_wakeref_t wakeref; 666 667 wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 668 669 intel_early_display_was(i915); 670 intel_modeset_readout_hw_state(i915); 671 672 /* HW state is read out, now we need to sanitize this mess. */ 673 get_encoder_power_domains(i915); 674 675 intel_pch_sanitize(i915); 676 677 /* 678 * intel_sanitize_plane_mapping() may need to do vblank 679 * waits, so we need vblank interrupts restored beforehand. 680 */ 681 for_each_intel_crtc(&i915->drm, crtc) { 682 struct intel_crtc_state *crtc_state = 683 to_intel_crtc_state(crtc->base.state); 684 685 intel_sanitize_fifo_underrun_reporting(crtc_state); 686 687 drm_crtc_vblank_reset(&crtc->base); 688 689 if (crtc_state->hw.active) { 690 intel_dmc_enable_pipe(i915, crtc->pipe); 691 intel_crtc_vblank_on(crtc_state); 692 } 693 } 694 695 intel_fbc_sanitize(i915); 696 697 intel_sanitize_plane_mapping(i915); 698 699 for_each_intel_encoder(&i915->drm, encoder) 700 intel_sanitize_encoder(encoder); 701 702 for_each_intel_crtc(&i915->drm, crtc) { 703 struct intel_crtc_state *crtc_state = 704 to_intel_crtc_state(crtc->base.state); 705 706 intel_sanitize_crtc(crtc, ctx); 707 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state"); 708 } 709 710 intel_modeset_update_connector_atomic_state(i915); 711 712 intel_dpll_sanitize_state(i915); 713 714 intel_wm_get_hw_state(i915); 715 716 for_each_intel_crtc(&i915->drm, crtc) { 717 struct intel_crtc_state *crtc_state = 718 to_intel_crtc_state(crtc->base.state); 719 struct intel_power_domain_mask put_domains; 720 721 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains); 722 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 723 intel_modeset_put_crtc_power_domains(crtc, &put_domains); 724 } 725 726 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 727 728 intel_power_domains_sanitize_state(i915); 729 } 730