1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * 24 */ 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_dp_dual_mode_helper.h> 28 #include <drm/drm_edid.h> 29 30 #include "intel_de.h" 31 #include "intel_display_types.h" 32 #include "intel_dp.h" 33 #include "intel_lspcon.h" 34 #include "intel_hdmi.h" 35 36 /* LSPCON OUI Vendor ID(signatures) */ 37 #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 38 #define LSPCON_VENDOR_MCA_OUI 0x0060AD 39 40 #define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 41 #define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511 42 43 /* AUX addresses to write MCA AVI IF */ 44 #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 45 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF 46 #define LSPCON_MCA_AVI_IF_KICKOFF (1 << 0) 47 #define LSPCON_MCA_AVI_IF_HANDLED (1 << 1) 48 49 /* AUX addresses to write Parade AVI IF */ 50 #define LSPCON_PARADE_AVI_IF_WRITE_OFFSET 0x516 51 #define LSPCON_PARADE_AVI_IF_CTRL 0x51E 52 #define LSPCON_PARADE_AVI_IF_KICKOFF (1 << 7) 53 #define LSPCON_PARADE_AVI_IF_DATA_SIZE 32 54 55 static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon) 56 { 57 struct intel_digital_port *dig_port = 58 container_of(lspcon, struct intel_digital_port, lspcon); 59 60 return &dig_port->dp; 61 } 62 63 static const char *lspcon_mode_name(enum drm_lspcon_mode mode) 64 { 65 switch (mode) { 66 case DRM_LSPCON_MODE_PCON: 67 return "PCON"; 68 case DRM_LSPCON_MODE_LS: 69 return "LS"; 70 case DRM_LSPCON_MODE_INVALID: 71 return "INVALID"; 72 default: 73 MISSING_CASE(mode); 74 return "INVALID"; 75 } 76 } 77 78 static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) 79 { 80 struct intel_dp *dp = lspcon_to_intel_dp(lspcon); 81 struct drm_dp_dpcd_ident *ident; 82 u32 vendor_oui; 83 84 if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) { 85 DRM_ERROR("Can't read description\n"); 86 return false; 87 } 88 89 ident = &dp->desc.ident; 90 vendor_oui = (ident->oui[0] << 16) | (ident->oui[1] << 8) | 91 ident->oui[2]; 92 93 switch (vendor_oui) { 94 case LSPCON_VENDOR_MCA_OUI: 95 lspcon->vendor = LSPCON_VENDOR_MCA; 96 DRM_DEBUG_KMS("Vendor: Mega Chips\n"); 97 break; 98 99 case LSPCON_VENDOR_PARADE_OUI: 100 lspcon->vendor = LSPCON_VENDOR_PARADE; 101 DRM_DEBUG_KMS("Vendor: Parade Tech\n"); 102 break; 103 104 default: 105 DRM_ERROR("Invalid/Unknown vendor OUI\n"); 106 return false; 107 } 108 109 return true; 110 } 111 112 static u32 get_hdr_status_reg(struct intel_lspcon *lspcon) 113 { 114 if (lspcon->vendor == LSPCON_VENDOR_MCA) 115 return DPCD_MCA_LSPCON_HDR_STATUS; 116 else 117 return DPCD_PARADE_LSPCON_HDR_STATUS; 118 } 119 120 void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) 121 { 122 struct intel_digital_port *dig_port = 123 container_of(lspcon, struct intel_digital_port, lspcon); 124 struct drm_device *dev = dig_port->base.base.dev; 125 struct intel_dp *dp = lspcon_to_intel_dp(lspcon); 126 u8 hdr_caps; 127 int ret; 128 129 ret = drm_dp_dpcd_read(&dp->aux, get_hdr_status_reg(lspcon), 130 &hdr_caps, 1); 131 132 if (ret < 0) { 133 drm_dbg_kms(dev, "HDR capability detection failed\n"); 134 lspcon->hdr_supported = false; 135 } else if (hdr_caps & 0x1) { 136 drm_dbg_kms(dev, "LSPCON capable of HDR\n"); 137 lspcon->hdr_supported = true; 138 } 139 } 140 141 static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) 142 { 143 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 144 enum drm_lspcon_mode current_mode; 145 struct i2c_adapter *adapter = &intel_dp->aux.ddc; 146 147 if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter, ¤t_mode)) { 148 DRM_DEBUG_KMS("Error reading LSPCON mode\n"); 149 return DRM_LSPCON_MODE_INVALID; 150 } 151 return current_mode; 152 } 153 154 static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon, 155 enum drm_lspcon_mode mode) 156 { 157 enum drm_lspcon_mode current_mode; 158 159 current_mode = lspcon_get_current_mode(lspcon); 160 if (current_mode == mode) 161 goto out; 162 163 DRM_DEBUG_KMS("Waiting for LSPCON mode %s to settle\n", 164 lspcon_mode_name(mode)); 165 166 wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400); 167 if (current_mode != mode) 168 DRM_ERROR("LSPCON mode hasn't settled\n"); 169 170 out: 171 DRM_DEBUG_KMS("Current LSPCON mode %s\n", 172 lspcon_mode_name(current_mode)); 173 174 return current_mode; 175 } 176 177 static int lspcon_change_mode(struct intel_lspcon *lspcon, 178 enum drm_lspcon_mode mode) 179 { 180 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 181 int err; 182 enum drm_lspcon_mode current_mode; 183 struct i2c_adapter *adapter = &intel_dp->aux.ddc; 184 185 err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter, ¤t_mode); 186 if (err) { 187 DRM_ERROR("Error reading LSPCON mode\n"); 188 return err; 189 } 190 191 if (current_mode == mode) { 192 DRM_DEBUG_KMS("Current mode = desired LSPCON mode\n"); 193 return 0; 194 } 195 196 err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, adapter, mode); 197 if (err < 0) { 198 DRM_ERROR("LSPCON mode change failed\n"); 199 return err; 200 } 201 202 lspcon->mode = mode; 203 DRM_DEBUG_KMS("LSPCON mode changed done\n"); 204 return 0; 205 } 206 207 static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon) 208 { 209 u8 rev; 210 211 if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV, 212 &rev) != 1) { 213 DRM_DEBUG_KMS("Native AUX CH down\n"); 214 return false; 215 } 216 217 DRM_DEBUG_KMS("Native AUX CH up, DPCD version: %d.%d\n", 218 rev >> 4, rev & 0xf); 219 220 return true; 221 } 222 223 static bool lspcon_probe(struct intel_lspcon *lspcon) 224 { 225 int retry; 226 enum drm_dp_dual_mode_type adaptor_type; 227 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 228 struct i2c_adapter *adapter = &intel_dp->aux.ddc; 229 enum drm_lspcon_mode expected_mode; 230 231 expected_mode = lspcon_wake_native_aux_ch(lspcon) ? 232 DRM_LSPCON_MODE_PCON : DRM_LSPCON_MODE_LS; 233 234 /* Lets probe the adaptor and check its type */ 235 for (retry = 0; retry < 6; retry++) { 236 if (retry) 237 usleep_range(500, 1000); 238 239 adaptor_type = drm_dp_dual_mode_detect(intel_dp->aux.drm_dev, adapter); 240 if (adaptor_type == DRM_DP_DUAL_MODE_LSPCON) 241 break; 242 } 243 244 if (adaptor_type != DRM_DP_DUAL_MODE_LSPCON) { 245 DRM_DEBUG_KMS("No LSPCON detected, found %s\n", 246 drm_dp_get_dual_mode_type_name(adaptor_type)); 247 return false; 248 } 249 250 /* Yay ... got a LSPCON device */ 251 DRM_DEBUG_KMS("LSPCON detected\n"); 252 lspcon->mode = lspcon_wait_mode(lspcon, expected_mode); 253 254 /* 255 * In the SW state machine, lets Put LSPCON in PCON mode only. 256 * In this way, it will work with both HDMI 1.4 sinks as well as HDMI 257 * 2.0 sinks. 258 */ 259 if (lspcon->mode != DRM_LSPCON_MODE_PCON) { 260 if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) { 261 DRM_ERROR("LSPCON mode change to PCON failed\n"); 262 return false; 263 } 264 } 265 return true; 266 } 267 268 static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon) 269 { 270 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 271 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 272 unsigned long start = jiffies; 273 274 while (1) { 275 if (intel_digital_port_connected(&dig_port->base)) { 276 DRM_DEBUG_KMS("LSPCON recovering in PCON mode after %u ms\n", 277 jiffies_to_msecs(jiffies - start)); 278 return; 279 } 280 281 if (time_after(jiffies, start + msecs_to_jiffies(1000))) 282 break; 283 284 usleep_range(10000, 15000); 285 } 286 287 DRM_DEBUG_KMS("LSPCON DP descriptor mismatch after resume\n"); 288 } 289 290 static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux) 291 { 292 u8 avi_if_ctrl; 293 u8 retry; 294 ssize_t ret; 295 296 /* Check if LSPCON FW is ready for data */ 297 for (retry = 0; retry < 5; retry++) { 298 if (retry) 299 usleep_range(200, 300); 300 301 ret = drm_dp_dpcd_read(aux, LSPCON_PARADE_AVI_IF_CTRL, 302 &avi_if_ctrl, 1); 303 if (ret < 0) { 304 DRM_ERROR("Failed to read AVI IF control\n"); 305 return false; 306 } 307 308 if ((avi_if_ctrl & LSPCON_PARADE_AVI_IF_KICKOFF) == 0) 309 return true; 310 } 311 312 DRM_ERROR("Parade FW not ready to accept AVI IF\n"); 313 return false; 314 } 315 316 static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux, 317 u8 *avi_buf) 318 { 319 u8 avi_if_ctrl; 320 u8 block_count = 0; 321 u8 *data; 322 u16 reg; 323 ssize_t ret; 324 325 while (block_count < 4) { 326 if (!lspcon_parade_fw_ready(aux)) { 327 DRM_DEBUG_KMS("LSPCON FW not ready, block %d\n", 328 block_count); 329 return false; 330 } 331 332 reg = LSPCON_PARADE_AVI_IF_WRITE_OFFSET; 333 data = avi_buf + block_count * 8; 334 ret = drm_dp_dpcd_write(aux, reg, data, 8); 335 if (ret < 0) { 336 DRM_ERROR("Failed to write AVI IF block %d\n", 337 block_count); 338 return false; 339 } 340 341 /* 342 * Once a block of data is written, we have to inform the FW 343 * about this by writing into avi infoframe control register: 344 * - set the kickoff bit[7] to 1 345 * - write the block no. to bits[1:0] 346 */ 347 reg = LSPCON_PARADE_AVI_IF_CTRL; 348 avi_if_ctrl = LSPCON_PARADE_AVI_IF_KICKOFF | block_count; 349 ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1); 350 if (ret < 0) { 351 DRM_ERROR("Failed to update (0x%x), block %d\n", 352 reg, block_count); 353 return false; 354 } 355 356 block_count++; 357 } 358 359 DRM_DEBUG_KMS("Wrote AVI IF blocks successfully\n"); 360 return true; 361 } 362 363 static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux, 364 const u8 *frame, 365 ssize_t len) 366 { 367 u8 avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, }; 368 369 /* 370 * Parade's frames contains 32 bytes of data, divided 371 * into 4 frames: 372 * Token byte (first byte of first frame, must be non-zero) 373 * HB0 to HB2 from AVI IF (3 bytes header) 374 * PB0 to PB27 from AVI IF (28 bytes data) 375 * So it should look like this 376 * first block: | <token> <HB0-HB2> <DB0-DB3> | 377 * next 3 blocks: |<DB4-DB11>|<DB12-DB19>|<DB20-DB28>| 378 */ 379 380 if (len > LSPCON_PARADE_AVI_IF_DATA_SIZE - 1) { 381 DRM_ERROR("Invalid length of infoframes\n"); 382 return false; 383 } 384 385 memcpy(&avi_if[1], frame, len); 386 387 if (!_lspcon_parade_write_infoframe_blocks(aux, avi_if)) { 388 DRM_DEBUG_KMS("Failed to write infoframe blocks\n"); 389 return false; 390 } 391 392 return true; 393 } 394 395 static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux, 396 const u8 *buffer, ssize_t len) 397 { 398 int ret; 399 u32 val = 0; 400 u32 retry; 401 u16 reg; 402 const u8 *data = buffer; 403 404 reg = LSPCON_MCA_AVI_IF_WRITE_OFFSET; 405 while (val < len) { 406 /* DPCD write for AVI IF can fail on a slow FW day, so retry */ 407 for (retry = 0; retry < 5; retry++) { 408 ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1); 409 if (ret == 1) { 410 break; 411 } else if (retry < 4) { 412 mdelay(50); 413 continue; 414 } else { 415 DRM_ERROR("DPCD write failed at:0x%x\n", reg); 416 return false; 417 } 418 } 419 val++; reg++; data++; 420 } 421 422 val = 0; 423 reg = LSPCON_MCA_AVI_IF_CTRL; 424 ret = drm_dp_dpcd_read(aux, reg, &val, 1); 425 if (ret < 0) { 426 DRM_ERROR("DPCD read failed, address 0x%x\n", reg); 427 return false; 428 } 429 430 /* Indicate LSPCON chip about infoframe, clear bit 1 and set bit 0 */ 431 val &= ~LSPCON_MCA_AVI_IF_HANDLED; 432 val |= LSPCON_MCA_AVI_IF_KICKOFF; 433 434 ret = drm_dp_dpcd_write(aux, reg, &val, 1); 435 if (ret < 0) { 436 DRM_ERROR("DPCD read failed, address 0x%x\n", reg); 437 return false; 438 } 439 440 val = 0; 441 ret = drm_dp_dpcd_read(aux, reg, &val, 1); 442 if (ret < 0) { 443 DRM_ERROR("DPCD read failed, address 0x%x\n", reg); 444 return false; 445 } 446 447 if (val == LSPCON_MCA_AVI_IF_HANDLED) 448 DRM_DEBUG_KMS("AVI IF handled by FW\n"); 449 450 return true; 451 } 452 453 void lspcon_write_infoframe(struct intel_encoder *encoder, 454 const struct intel_crtc_state *crtc_state, 455 unsigned int type, 456 const void *frame, ssize_t len) 457 { 458 bool ret = true; 459 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 460 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); 461 462 switch (type) { 463 case HDMI_INFOFRAME_TYPE_AVI: 464 if (lspcon->vendor == LSPCON_VENDOR_MCA) 465 ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, 466 frame, len); 467 else 468 ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, 469 frame, len); 470 break; 471 case HDMI_PACKET_TYPE_GAMUT_METADATA: 472 drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n"); 473 /* It uses the legacy hsw implementation for the same */ 474 hsw_write_infoframe(encoder, crtc_state, type, frame, len); 475 break; 476 default: 477 return; 478 } 479 480 if (!ret) { 481 DRM_ERROR("Failed to write infoframes\n"); 482 return; 483 } 484 } 485 486 void lspcon_read_infoframe(struct intel_encoder *encoder, 487 const struct intel_crtc_state *crtc_state, 488 unsigned int type, 489 void *frame, ssize_t len) 490 { 491 /* FIXME implement for AVI Infoframe as well */ 492 if (type == HDMI_PACKET_TYPE_GAMUT_METADATA) 493 hsw_read_infoframe(encoder, crtc_state, type, 494 frame, len); 495 } 496 497 void lspcon_set_infoframes(struct intel_encoder *encoder, 498 bool enable, 499 const struct intel_crtc_state *crtc_state, 500 const struct drm_connector_state *conn_state) 501 { 502 ssize_t ret; 503 union hdmi_infoframe frame; 504 u8 buf[VIDEO_DIP_DATA_SIZE]; 505 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 506 struct intel_lspcon *lspcon = &dig_port->lspcon; 507 const struct drm_display_mode *adjusted_mode = 508 &crtc_state->hw.adjusted_mode; 509 510 if (!lspcon->active) { 511 DRM_ERROR("Writing infoframes while LSPCON disabled ?\n"); 512 return; 513 } 514 515 /* FIXME precompute infoframes */ 516 517 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 518 conn_state->connector, 519 adjusted_mode); 520 if (ret < 0) { 521 DRM_ERROR("couldn't fill AVI infoframe\n"); 522 return; 523 } 524 525 /* 526 * Currently there is no interface defined to 527 * check user preference between RGB/YCBCR444 528 * or YCBCR420. So the only possible case for 529 * YCBCR444 usage is driving YCBCR420 output 530 * with LSPCON, when pipe is configured for 531 * YCBCR444 output and LSPCON takes care of 532 * downsampling it. 533 */ 534 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 535 frame.avi.colorspace = HDMI_COLORSPACE_YUV420; 536 else 537 frame.avi.colorspace = HDMI_COLORSPACE_RGB; 538 539 /* Set the Colorspace as per the HDMI spec */ 540 drm_hdmi_avi_infoframe_colorspace(&frame.avi, conn_state); 541 542 /* nonsense combination */ 543 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 544 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 545 546 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 547 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 548 conn_state->connector, 549 adjusted_mode, 550 crtc_state->limited_color_range ? 551 HDMI_QUANTIZATION_RANGE_LIMITED : 552 HDMI_QUANTIZATION_RANGE_FULL); 553 } else { 554 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 555 frame.avi.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 556 } 557 558 drm_hdmi_avi_infoframe_content_type(&frame.avi, conn_state); 559 560 ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf)); 561 if (ret < 0) { 562 DRM_ERROR("Failed to pack AVI IF\n"); 563 return; 564 } 565 566 dig_port->write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, 567 buf, ret); 568 } 569 570 static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) 571 { 572 int ret; 573 u32 val = 0; 574 u16 reg = LSPCON_MCA_AVI_IF_CTRL; 575 576 ret = drm_dp_dpcd_read(aux, reg, &val, 1); 577 if (ret < 0) { 578 DRM_ERROR("DPCD read failed, address 0x%x\n", reg); 579 return false; 580 } 581 582 return val & LSPCON_MCA_AVI_IF_KICKOFF; 583 } 584 585 static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux) 586 { 587 int ret; 588 u32 val = 0; 589 u16 reg = LSPCON_PARADE_AVI_IF_CTRL; 590 591 ret = drm_dp_dpcd_read(aux, reg, &val, 1); 592 if (ret < 0) { 593 DRM_ERROR("DPCD read failed, address 0x%x\n", reg); 594 return false; 595 } 596 597 return val & LSPCON_PARADE_AVI_IF_KICKOFF; 598 } 599 600 u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, 601 const struct intel_crtc_state *pipe_config) 602 { 603 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 604 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); 605 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 606 bool infoframes_enabled; 607 u32 val = 0; 608 u32 mask, tmp; 609 610 if (lspcon->vendor == LSPCON_VENDOR_MCA) 611 infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); 612 else 613 infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); 614 615 if (infoframes_enabled) 616 val |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 617 618 if (lspcon->hdr_supported) { 619 tmp = intel_de_read(dev_priv, 620 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 621 mask = VIDEO_DIP_ENABLE_GMP_HSW; 622 623 if (tmp & mask) 624 val |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 625 } 626 627 return val; 628 } 629 630 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) 631 { 632 lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON); 633 } 634 635 bool lspcon_init(struct intel_digital_port *dig_port) 636 { 637 struct intel_dp *dp = &dig_port->dp; 638 struct intel_lspcon *lspcon = &dig_port->lspcon; 639 struct drm_connector *connector = &dp->attached_connector->base; 640 641 lspcon->active = false; 642 lspcon->mode = DRM_LSPCON_MODE_INVALID; 643 644 if (!lspcon_probe(lspcon)) { 645 DRM_ERROR("Failed to probe lspcon\n"); 646 return false; 647 } 648 649 if (drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd) != 0) { 650 DRM_ERROR("LSPCON DPCD read failed\n"); 651 return false; 652 } 653 654 if (!lspcon_detect_vendor(lspcon)) { 655 DRM_ERROR("LSPCON vendor detection failed\n"); 656 return false; 657 } 658 659 connector->ycbcr_420_allowed = true; 660 lspcon->active = true; 661 DRM_DEBUG_KMS("Success: LSPCON init\n"); 662 return true; 663 } 664 665 u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, 666 const struct intel_crtc_state *pipe_config) 667 { 668 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 669 670 return dig_port->infoframes_enabled(encoder, pipe_config); 671 } 672 673 void lspcon_resume(struct intel_digital_port *dig_port) 674 { 675 struct intel_lspcon *lspcon = &dig_port->lspcon; 676 struct drm_device *dev = dig_port->base.base.dev; 677 struct drm_i915_private *dev_priv = to_i915(dev); 678 enum drm_lspcon_mode expected_mode; 679 680 if (!intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) 681 return; 682 683 if (!lspcon->active) { 684 if (!lspcon_init(dig_port)) { 685 DRM_ERROR("LSPCON init failed on port %c\n", 686 port_name(dig_port->base.port)); 687 return; 688 } 689 } 690 691 if (lspcon_wake_native_aux_ch(lspcon)) { 692 expected_mode = DRM_LSPCON_MODE_PCON; 693 lspcon_resume_in_pcon_wa(lspcon); 694 } else { 695 expected_mode = DRM_LSPCON_MODE_LS; 696 } 697 698 if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON) 699 return; 700 701 if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON)) 702 DRM_ERROR("LSPCON resume failed\n"); 703 else 704 DRM_DEBUG_KMS("LSPCON resume success\n"); 705 } 706