1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * 24 */ 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_dp_dual_mode_helper.h> 28 #include <drm/drm_edid.h> 29 30 #include "intel_display_types.h" 31 #include "intel_dp.h" 32 #include "intel_lspcon.h" 33 #include "intel_hdmi.h" 34 35 /* LSPCON OUI Vendor ID(signatures) */ 36 #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 37 #define LSPCON_VENDOR_MCA_OUI 0x0060AD 38 39 #define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 40 #define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511 41 42 /* AUX addresses to write MCA AVI IF */ 43 #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 44 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF 45 #define LSPCON_MCA_AVI_IF_KICKOFF (1 << 0) 46 #define LSPCON_MCA_AVI_IF_HANDLED (1 << 1) 47 48 /* AUX addresses to write Parade AVI IF */ 49 #define LSPCON_PARADE_AVI_IF_WRITE_OFFSET 0x516 50 #define LSPCON_PARADE_AVI_IF_CTRL 0x51E 51 #define LSPCON_PARADE_AVI_IF_KICKOFF (1 << 7) 52 #define LSPCON_PARADE_AVI_IF_DATA_SIZE 32 53 54 static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon) 55 { 56 struct intel_digital_port *dig_port = 57 container_of(lspcon, struct intel_digital_port, lspcon); 58 59 return &dig_port->dp; 60 } 61 62 static const char *lspcon_mode_name(enum drm_lspcon_mode mode) 63 { 64 switch (mode) { 65 case DRM_LSPCON_MODE_PCON: 66 return "PCON"; 67 case DRM_LSPCON_MODE_LS: 68 return "LS"; 69 case DRM_LSPCON_MODE_INVALID: 70 return "INVALID"; 71 default: 72 MISSING_CASE(mode); 73 return "INVALID"; 74 } 75 } 76 77 static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) 78 { 79 struct intel_dp *dp = lspcon_to_intel_dp(lspcon); 80 struct drm_dp_dpcd_ident *ident; 81 u32 vendor_oui; 82 83 if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) { 84 DRM_ERROR("Can't read description\n"); 85 return false; 86 } 87 88 ident = &dp->desc.ident; 89 vendor_oui = (ident->oui[0] << 16) | (ident->oui[1] << 8) | 90 ident->oui[2]; 91 92 switch (vendor_oui) { 93 case LSPCON_VENDOR_MCA_OUI: 94 lspcon->vendor = LSPCON_VENDOR_MCA; 95 DRM_DEBUG_KMS("Vendor: Mega Chips\n"); 96 break; 97 98 case LSPCON_VENDOR_PARADE_OUI: 99 lspcon->vendor = LSPCON_VENDOR_PARADE; 100 DRM_DEBUG_KMS("Vendor: Parade Tech\n"); 101 break; 102 103 default: 104 DRM_ERROR("Invalid/Unknown vendor OUI\n"); 105 return false; 106 } 107 108 return true; 109 } 110 111 static u32 get_hdr_status_reg(struct intel_lspcon *lspcon) 112 { 113 if (lspcon->vendor == LSPCON_VENDOR_MCA) 114 return DPCD_MCA_LSPCON_HDR_STATUS; 115 else 116 return DPCD_PARADE_LSPCON_HDR_STATUS; 117 } 118 119 void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) 120 { 121 struct intel_digital_port *dig_port = 122 container_of(lspcon, struct intel_digital_port, lspcon); 123 struct drm_device *dev = dig_port->base.base.dev; 124 struct intel_dp *dp = lspcon_to_intel_dp(lspcon); 125 u8 hdr_caps; 126 int ret; 127 128 ret = drm_dp_dpcd_read(&dp->aux, get_hdr_status_reg(lspcon), 129 &hdr_caps, 1); 130 131 if (ret < 0) { 132 drm_dbg_kms(dev, "HDR capability detection failed\n"); 133 lspcon->hdr_supported = false; 134 } else if (hdr_caps & 0x1) { 135 drm_dbg_kms(dev, "LSPCON capable of HDR\n"); 136 lspcon->hdr_supported = true; 137 } 138 } 139 140 static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) 141 { 142 enum drm_lspcon_mode current_mode; 143 struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc; 144 145 if (drm_lspcon_get_mode(adapter, ¤t_mode)) { 146 DRM_DEBUG_KMS("Error reading LSPCON mode\n"); 147 return DRM_LSPCON_MODE_INVALID; 148 } 149 return current_mode; 150 } 151 152 static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon, 153 enum drm_lspcon_mode mode) 154 { 155 enum drm_lspcon_mode current_mode; 156 157 current_mode = lspcon_get_current_mode(lspcon); 158 if (current_mode == mode) 159 goto out; 160 161 DRM_DEBUG_KMS("Waiting for LSPCON mode %s to settle\n", 162 lspcon_mode_name(mode)); 163 164 wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400); 165 if (current_mode != mode) 166 DRM_ERROR("LSPCON mode hasn't settled\n"); 167 168 out: 169 DRM_DEBUG_KMS("Current LSPCON mode %s\n", 170 lspcon_mode_name(current_mode)); 171 172 return current_mode; 173 } 174 175 static int lspcon_change_mode(struct intel_lspcon *lspcon, 176 enum drm_lspcon_mode mode) 177 { 178 int err; 179 enum drm_lspcon_mode current_mode; 180 struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc; 181 182 err = drm_lspcon_get_mode(adapter, ¤t_mode); 183 if (err) { 184 DRM_ERROR("Error reading LSPCON mode\n"); 185 return err; 186 } 187 188 if (current_mode == mode) { 189 DRM_DEBUG_KMS("Current mode = desired LSPCON mode\n"); 190 return 0; 191 } 192 193 err = drm_lspcon_set_mode(adapter, mode); 194 if (err < 0) { 195 DRM_ERROR("LSPCON mode change failed\n"); 196 return err; 197 } 198 199 lspcon->mode = mode; 200 DRM_DEBUG_KMS("LSPCON mode changed done\n"); 201 return 0; 202 } 203 204 static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon) 205 { 206 u8 rev; 207 208 if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV, 209 &rev) != 1) { 210 DRM_DEBUG_KMS("Native AUX CH down\n"); 211 return false; 212 } 213 214 DRM_DEBUG_KMS("Native AUX CH up, DPCD version: %d.%d\n", 215 rev >> 4, rev & 0xf); 216 217 return true; 218 } 219 220 static bool lspcon_probe(struct intel_lspcon *lspcon) 221 { 222 int retry; 223 enum drm_dp_dual_mode_type adaptor_type; 224 struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc; 225 enum drm_lspcon_mode expected_mode; 226 227 expected_mode = lspcon_wake_native_aux_ch(lspcon) ? 228 DRM_LSPCON_MODE_PCON : DRM_LSPCON_MODE_LS; 229 230 /* Lets probe the adaptor and check its type */ 231 for (retry = 0; retry < 6; retry++) { 232 if (retry) 233 usleep_range(500, 1000); 234 235 adaptor_type = drm_dp_dual_mode_detect(adapter); 236 if (adaptor_type == DRM_DP_DUAL_MODE_LSPCON) 237 break; 238 } 239 240 if (adaptor_type != DRM_DP_DUAL_MODE_LSPCON) { 241 DRM_DEBUG_KMS("No LSPCON detected, found %s\n", 242 drm_dp_get_dual_mode_type_name(adaptor_type)); 243 return false; 244 } 245 246 /* Yay ... got a LSPCON device */ 247 DRM_DEBUG_KMS("LSPCON detected\n"); 248 lspcon->mode = lspcon_wait_mode(lspcon, expected_mode); 249 250 /* 251 * In the SW state machine, lets Put LSPCON in PCON mode only. 252 * In this way, it will work with both HDMI 1.4 sinks as well as HDMI 253 * 2.0 sinks. 254 */ 255 if (lspcon->mode != DRM_LSPCON_MODE_PCON) { 256 if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) { 257 DRM_ERROR("LSPCON mode change to PCON failed\n"); 258 return false; 259 } 260 } 261 return true; 262 } 263 264 static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon) 265 { 266 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 267 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 268 unsigned long start = jiffies; 269 270 while (1) { 271 if (intel_digital_port_connected(&dig_port->base)) { 272 DRM_DEBUG_KMS("LSPCON recovering in PCON mode after %u ms\n", 273 jiffies_to_msecs(jiffies - start)); 274 return; 275 } 276 277 if (time_after(jiffies, start + msecs_to_jiffies(1000))) 278 break; 279 280 usleep_range(10000, 15000); 281 } 282 283 DRM_DEBUG_KMS("LSPCON DP descriptor mismatch after resume\n"); 284 } 285 286 static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux) 287 { 288 u8 avi_if_ctrl; 289 u8 retry; 290 ssize_t ret; 291 292 /* Check if LSPCON FW is ready for data */ 293 for (retry = 0; retry < 5; retry++) { 294 if (retry) 295 usleep_range(200, 300); 296 297 ret = drm_dp_dpcd_read(aux, LSPCON_PARADE_AVI_IF_CTRL, 298 &avi_if_ctrl, 1); 299 if (ret < 0) { 300 DRM_ERROR("Failed to read AVI IF control\n"); 301 return false; 302 } 303 304 if ((avi_if_ctrl & LSPCON_PARADE_AVI_IF_KICKOFF) == 0) 305 return true; 306 } 307 308 DRM_ERROR("Parade FW not ready to accept AVI IF\n"); 309 return false; 310 } 311 312 static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux, 313 u8 *avi_buf) 314 { 315 u8 avi_if_ctrl; 316 u8 block_count = 0; 317 u8 *data; 318 u16 reg; 319 ssize_t ret; 320 321 while (block_count < 4) { 322 if (!lspcon_parade_fw_ready(aux)) { 323 DRM_DEBUG_KMS("LSPCON FW not ready, block %d\n", 324 block_count); 325 return false; 326 } 327 328 reg = LSPCON_PARADE_AVI_IF_WRITE_OFFSET; 329 data = avi_buf + block_count * 8; 330 ret = drm_dp_dpcd_write(aux, reg, data, 8); 331 if (ret < 0) { 332 DRM_ERROR("Failed to write AVI IF block %d\n", 333 block_count); 334 return false; 335 } 336 337 /* 338 * Once a block of data is written, we have to inform the FW 339 * about this by writing into avi infoframe control register: 340 * - set the kickoff bit[7] to 1 341 * - write the block no. to bits[1:0] 342 */ 343 reg = LSPCON_PARADE_AVI_IF_CTRL; 344 avi_if_ctrl = LSPCON_PARADE_AVI_IF_KICKOFF | block_count; 345 ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1); 346 if (ret < 0) { 347 DRM_ERROR("Failed to update (0x%x), block %d\n", 348 reg, block_count); 349 return false; 350 } 351 352 block_count++; 353 } 354 355 DRM_DEBUG_KMS("Wrote AVI IF blocks successfully\n"); 356 return true; 357 } 358 359 static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux, 360 const u8 *frame, 361 ssize_t len) 362 { 363 u8 avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, }; 364 365 /* 366 * Parade's frames contains 32 bytes of data, divided 367 * into 4 frames: 368 * Token byte (first byte of first frame, must be non-zero) 369 * HB0 to HB2 from AVI IF (3 bytes header) 370 * PB0 to PB27 from AVI IF (28 bytes data) 371 * So it should look like this 372 * first block: | <token> <HB0-HB2> <DB0-DB3> | 373 * next 3 blocks: |<DB4-DB11>|<DB12-DB19>|<DB20-DB28>| 374 */ 375 376 if (len > LSPCON_PARADE_AVI_IF_DATA_SIZE - 1) { 377 DRM_ERROR("Invalid length of infoframes\n"); 378 return false; 379 } 380 381 memcpy(&avi_if[1], frame, len); 382 383 if (!_lspcon_parade_write_infoframe_blocks(aux, avi_if)) { 384 DRM_DEBUG_KMS("Failed to write infoframe blocks\n"); 385 return false; 386 } 387 388 return true; 389 } 390 391 static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux, 392 const u8 *buffer, ssize_t len) 393 { 394 int ret; 395 u32 val = 0; 396 u32 retry; 397 u16 reg; 398 const u8 *data = buffer; 399 400 reg = LSPCON_MCA_AVI_IF_WRITE_OFFSET; 401 while (val < len) { 402 /* DPCD write for AVI IF can fail on a slow FW day, so retry */ 403 for (retry = 0; retry < 5; retry++) { 404 ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1); 405 if (ret == 1) { 406 break; 407 } else if (retry < 4) { 408 mdelay(50); 409 continue; 410 } else { 411 DRM_ERROR("DPCD write failed at:0x%x\n", reg); 412 return false; 413 } 414 } 415 val++; reg++; data++; 416 } 417 418 val = 0; 419 reg = LSPCON_MCA_AVI_IF_CTRL; 420 ret = drm_dp_dpcd_read(aux, reg, &val, 1); 421 if (ret < 0) { 422 DRM_ERROR("DPCD read failed, address 0x%x\n", reg); 423 return false; 424 } 425 426 /* Indicate LSPCON chip about infoframe, clear bit 1 and set bit 0 */ 427 val &= ~LSPCON_MCA_AVI_IF_HANDLED; 428 val |= LSPCON_MCA_AVI_IF_KICKOFF; 429 430 ret = drm_dp_dpcd_write(aux, reg, &val, 1); 431 if (ret < 0) { 432 DRM_ERROR("DPCD read failed, address 0x%x\n", reg); 433 return false; 434 } 435 436 val = 0; 437 ret = drm_dp_dpcd_read(aux, reg, &val, 1); 438 if (ret < 0) { 439 DRM_ERROR("DPCD read failed, address 0x%x\n", reg); 440 return false; 441 } 442 443 if (val == LSPCON_MCA_AVI_IF_HANDLED) 444 DRM_DEBUG_KMS("AVI IF handled by FW\n"); 445 446 return true; 447 } 448 449 void lspcon_write_infoframe(struct intel_encoder *encoder, 450 const struct intel_crtc_state *crtc_state, 451 unsigned int type, 452 const void *frame, ssize_t len) 453 { 454 bool ret = true; 455 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 456 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); 457 458 switch (type) { 459 case HDMI_INFOFRAME_TYPE_AVI: 460 if (lspcon->vendor == LSPCON_VENDOR_MCA) 461 ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, 462 frame, len); 463 else 464 ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, 465 frame, len); 466 break; 467 case HDMI_PACKET_TYPE_GAMUT_METADATA: 468 drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n"); 469 /* It uses the legacy hsw implementation for the same */ 470 hsw_write_infoframe(encoder, crtc_state, type, frame, len); 471 break; 472 default: 473 return; 474 } 475 476 if (!ret) { 477 DRM_ERROR("Failed to write infoframes\n"); 478 return; 479 } 480 } 481 482 void lspcon_read_infoframe(struct intel_encoder *encoder, 483 const struct intel_crtc_state *crtc_state, 484 unsigned int type, 485 void *frame, ssize_t len) 486 { 487 /* FIXME implement for AVI Infoframe as well */ 488 if (type == HDMI_PACKET_TYPE_GAMUT_METADATA) 489 hsw_read_infoframe(encoder, crtc_state, type, 490 frame, len); 491 } 492 493 void lspcon_set_infoframes(struct intel_encoder *encoder, 494 bool enable, 495 const struct intel_crtc_state *crtc_state, 496 const struct drm_connector_state *conn_state) 497 { 498 ssize_t ret; 499 union hdmi_infoframe frame; 500 u8 buf[VIDEO_DIP_DATA_SIZE]; 501 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 502 struct intel_lspcon *lspcon = &dig_port->lspcon; 503 const struct drm_display_mode *adjusted_mode = 504 &crtc_state->hw.adjusted_mode; 505 506 if (!lspcon->active) { 507 DRM_ERROR("Writing infoframes while LSPCON disabled ?\n"); 508 return; 509 } 510 511 /* FIXME precompute infoframes */ 512 513 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 514 conn_state->connector, 515 adjusted_mode); 516 if (ret < 0) { 517 DRM_ERROR("couldn't fill AVI infoframe\n"); 518 return; 519 } 520 521 /* 522 * Currently there is no interface defined to 523 * check user preference between RGB/YCBCR444 524 * or YCBCR420. So the only possible case for 525 * YCBCR444 usage is driving YCBCR420 output 526 * with LSPCON, when pipe is configured for 527 * YCBCR444 output and LSPCON takes care of 528 * downsampling it. 529 */ 530 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 531 frame.avi.colorspace = HDMI_COLORSPACE_YUV420; 532 else 533 frame.avi.colorspace = HDMI_COLORSPACE_RGB; 534 535 /* Set the Colorspace as per the HDMI spec */ 536 drm_hdmi_avi_infoframe_colorspace(&frame.avi, conn_state); 537 538 /* nonsense combination */ 539 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 540 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 541 542 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 543 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 544 conn_state->connector, 545 adjusted_mode, 546 crtc_state->limited_color_range ? 547 HDMI_QUANTIZATION_RANGE_LIMITED : 548 HDMI_QUANTIZATION_RANGE_FULL); 549 } else { 550 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 551 frame.avi.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 552 } 553 554 drm_hdmi_avi_infoframe_content_type(&frame.avi, conn_state); 555 556 ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf)); 557 if (ret < 0) { 558 DRM_ERROR("Failed to pack AVI IF\n"); 559 return; 560 } 561 562 dig_port->write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, 563 buf, ret); 564 } 565 566 static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) 567 { 568 int ret; 569 u32 val = 0; 570 u16 reg = LSPCON_MCA_AVI_IF_CTRL; 571 572 ret = drm_dp_dpcd_read(aux, reg, &val, 1); 573 if (ret < 0) { 574 DRM_ERROR("DPCD read failed, address 0x%x\n", reg); 575 return false; 576 } 577 578 return val & LSPCON_MCA_AVI_IF_KICKOFF; 579 } 580 581 static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux) 582 { 583 int ret; 584 u32 val = 0; 585 u16 reg = LSPCON_PARADE_AVI_IF_CTRL; 586 587 ret = drm_dp_dpcd_read(aux, reg, &val, 1); 588 if (ret < 0) { 589 DRM_ERROR("DPCD read failed, address 0x%x\n", reg); 590 return false; 591 } 592 593 return val & LSPCON_PARADE_AVI_IF_KICKOFF; 594 } 595 596 u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, 597 const struct intel_crtc_state *pipe_config) 598 { 599 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 600 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); 601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 602 bool infoframes_enabled; 603 u32 val = 0; 604 u32 mask, tmp; 605 606 if (lspcon->vendor == LSPCON_VENDOR_MCA) 607 infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); 608 else 609 infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); 610 611 if (infoframes_enabled) 612 val |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 613 614 if (lspcon->hdr_supported) { 615 tmp = intel_de_read(dev_priv, 616 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 617 mask = VIDEO_DIP_ENABLE_GMP_HSW; 618 619 if (tmp & mask) 620 val |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 621 } 622 623 return val; 624 } 625 626 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) 627 { 628 lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON); 629 } 630 631 bool lspcon_init(struct intel_digital_port *dig_port) 632 { 633 struct intel_dp *dp = &dig_port->dp; 634 struct intel_lspcon *lspcon = &dig_port->lspcon; 635 struct drm_connector *connector = &dp->attached_connector->base; 636 637 lspcon->active = false; 638 lspcon->mode = DRM_LSPCON_MODE_INVALID; 639 640 if (!lspcon_probe(lspcon)) { 641 DRM_ERROR("Failed to probe lspcon\n"); 642 return false; 643 } 644 645 if (drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd) != 0) { 646 DRM_ERROR("LSPCON DPCD read failed\n"); 647 return false; 648 } 649 650 if (!lspcon_detect_vendor(lspcon)) { 651 DRM_ERROR("LSPCON vendor detection failed\n"); 652 return false; 653 } 654 655 connector->ycbcr_420_allowed = true; 656 lspcon->active = true; 657 DRM_DEBUG_KMS("Success: LSPCON init\n"); 658 return true; 659 } 660 661 u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, 662 const struct intel_crtc_state *pipe_config) 663 { 664 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 665 666 return dig_port->infoframes_enabled(encoder, pipe_config); 667 } 668 669 void lspcon_resume(struct intel_digital_port *dig_port) 670 { 671 struct intel_lspcon *lspcon = &dig_port->lspcon; 672 struct drm_device *dev = dig_port->base.base.dev; 673 struct drm_i915_private *dev_priv = to_i915(dev); 674 enum drm_lspcon_mode expected_mode; 675 676 if (!intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) 677 return; 678 679 if (!lspcon->active) { 680 if (!lspcon_init(dig_port)) { 681 DRM_ERROR("LSPCON init failed on port %c\n", 682 port_name(dig_port->base.port)); 683 return; 684 } 685 } 686 687 if (lspcon_wake_native_aux_ch(lspcon)) { 688 expected_mode = DRM_LSPCON_MODE_PCON; 689 lspcon_resume_in_pcon_wa(lspcon); 690 } else { 691 expected_mode = DRM_LSPCON_MODE_LS; 692 } 693 694 if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON) 695 return; 696 697 if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON)) 698 DRM_ERROR("LSPCON resume failed\n"); 699 else 700 DRM_DEBUG_KMS("LSPCON resume success\n"); 701 } 702