1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_de.h" 9 #include "intel_display_irq.h" 10 #include "intel_display_types.h" 11 #include "intel_dp_aux.h" 12 #include "intel_gmbus.h" 13 #include "intel_hotplug.h" 14 #include "intel_hotplug_irq.h" 15 16 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val); 17 typedef u32 (*hotplug_enables_func)(struct intel_encoder *encoder); 18 typedef u32 (*hotplug_mask_func)(enum hpd_pin pin); 19 20 static const u32 hpd_ilk[HPD_NUM_PINS] = { 21 [HPD_PORT_A] = DE_DP_A_HOTPLUG, 22 }; 23 24 static const u32 hpd_ivb[HPD_NUM_PINS] = { 25 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, 26 }; 27 28 static const u32 hpd_bdw[HPD_NUM_PINS] = { 29 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 30 }; 31 32 static const u32 hpd_ibx[HPD_NUM_PINS] = { 33 [HPD_CRT] = SDE_CRT_HOTPLUG, 34 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, 35 [HPD_PORT_B] = SDE_PORTB_HOTPLUG, 36 [HPD_PORT_C] = SDE_PORTC_HOTPLUG, 37 [HPD_PORT_D] = SDE_PORTD_HOTPLUG, 38 }; 39 40 static const u32 hpd_cpt[HPD_NUM_PINS] = { 41 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, 42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, 43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 46 }; 47 48 static const u32 hpd_spt[HPD_NUM_PINS] = { 49 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 53 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT, 54 }; 55 56 static const u32 hpd_mask_i915[HPD_NUM_PINS] = { 57 [HPD_CRT] = CRT_HOTPLUG_INT_EN, 58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, 59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, 60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, 61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, 62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN, 63 }; 64 65 static const u32 hpd_status_g4x[HPD_NUM_PINS] = { 66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, 68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, 69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 72 }; 73 74 static const u32 hpd_status_i915[HPD_NUM_PINS] = { 75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, 77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, 78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 81 }; 82 83 static const u32 hpd_bxt[HPD_NUM_PINS] = { 84 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 85 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B), 86 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C), 87 }; 88 89 static const u32 hpd_gen11[HPD_NUM_PINS] = { 90 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1), 91 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2), 92 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3), 93 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4), 94 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5), 95 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6), 96 }; 97 98 static const u32 hpd_xelpdp[HPD_NUM_PINS] = { 99 [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1), 100 [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2), 101 [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3), 102 [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4), 103 }; 104 105 static const u32 hpd_icp[HPD_NUM_PINS] = { 106 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 107 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 108 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 109 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), 110 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), 111 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), 112 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 113 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5), 114 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6), 115 }; 116 117 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = { 118 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 119 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 120 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 121 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D), 122 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1), 123 }; 124 125 static const u32 hpd_mtp[HPD_NUM_PINS] = { 126 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 127 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 128 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), 129 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), 130 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), 131 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 132 }; 133 134 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) 135 { 136 struct intel_hotplug *hpd = &dev_priv->display.hotplug; 137 138 if (HAS_GMCH(dev_priv)) { 139 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 140 IS_CHERRYVIEW(dev_priv)) 141 hpd->hpd = hpd_status_g4x; 142 else 143 hpd->hpd = hpd_status_i915; 144 return; 145 } 146 147 if (DISPLAY_VER(dev_priv) >= 14) 148 hpd->hpd = hpd_xelpdp; 149 else if (DISPLAY_VER(dev_priv) >= 11) 150 hpd->hpd = hpd_gen11; 151 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 152 hpd->hpd = hpd_bxt; 153 else if (DISPLAY_VER(dev_priv) == 9) 154 hpd->hpd = NULL; /* no north HPD on SKL */ 155 else if (DISPLAY_VER(dev_priv) >= 8) 156 hpd->hpd = hpd_bdw; 157 else if (DISPLAY_VER(dev_priv) >= 7) 158 hpd->hpd = hpd_ivb; 159 else 160 hpd->hpd = hpd_ilk; 161 162 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && 163 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) 164 return; 165 166 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 167 hpd->pch_hpd = hpd_sde_dg1; 168 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) 169 hpd->pch_hpd = hpd_mtp; 170 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 171 hpd->pch_hpd = hpd_icp; 172 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) 173 hpd->pch_hpd = hpd_spt; 174 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv)) 175 hpd->pch_hpd = hpd_cpt; 176 else if (HAS_PCH_IBX(dev_priv)) 177 hpd->pch_hpd = hpd_ibx; 178 else 179 MISSING_CASE(INTEL_PCH_TYPE(dev_priv)); 180 } 181 182 /* For display hotplug interrupt */ 183 void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, 184 u32 mask, u32 bits) 185 { 186 lockdep_assert_held(&dev_priv->irq_lock); 187 drm_WARN_ON(&dev_priv->drm, bits & ~mask); 188 189 intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN, mask, bits); 190 } 191 192 /** 193 * i915_hotplug_interrupt_update - update hotplug interrupt enable 194 * @dev_priv: driver private 195 * @mask: bits to update 196 * @bits: bits to enable 197 * NOTE: the HPD enable bits are modified both inside and outside 198 * of an interrupt context. To avoid that read-modify-write cycles 199 * interfer, these bits are protected by a spinlock. Since this 200 * function is usually not called from a context where the lock is 201 * held already, this function acquires the lock itself. A non-locking 202 * version is also available. 203 */ 204 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, 205 u32 mask, 206 u32 bits) 207 { 208 spin_lock_irq(&dev_priv->irq_lock); 209 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); 210 spin_unlock_irq(&dev_priv->irq_lock); 211 } 212 213 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 214 { 215 switch (pin) { 216 case HPD_PORT_TC1: 217 case HPD_PORT_TC2: 218 case HPD_PORT_TC3: 219 case HPD_PORT_TC4: 220 case HPD_PORT_TC5: 221 case HPD_PORT_TC6: 222 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin); 223 default: 224 return false; 225 } 226 } 227 228 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 229 { 230 switch (pin) { 231 case HPD_PORT_A: 232 return val & PORTA_HOTPLUG_LONG_DETECT; 233 case HPD_PORT_B: 234 return val & PORTB_HOTPLUG_LONG_DETECT; 235 case HPD_PORT_C: 236 return val & PORTC_HOTPLUG_LONG_DETECT; 237 default: 238 return false; 239 } 240 } 241 242 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 243 { 244 switch (pin) { 245 case HPD_PORT_A: 246 case HPD_PORT_B: 247 case HPD_PORT_C: 248 case HPD_PORT_D: 249 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin); 250 default: 251 return false; 252 } 253 } 254 255 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 256 { 257 switch (pin) { 258 case HPD_PORT_TC1: 259 case HPD_PORT_TC2: 260 case HPD_PORT_TC3: 261 case HPD_PORT_TC4: 262 case HPD_PORT_TC5: 263 case HPD_PORT_TC6: 264 return val & ICP_TC_HPD_LONG_DETECT(pin); 265 default: 266 return false; 267 } 268 } 269 270 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) 271 { 272 switch (pin) { 273 case HPD_PORT_E: 274 return val & PORTE_HOTPLUG_LONG_DETECT; 275 default: 276 return false; 277 } 278 } 279 280 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 281 { 282 switch (pin) { 283 case HPD_PORT_A: 284 return val & PORTA_HOTPLUG_LONG_DETECT; 285 case HPD_PORT_B: 286 return val & PORTB_HOTPLUG_LONG_DETECT; 287 case HPD_PORT_C: 288 return val & PORTC_HOTPLUG_LONG_DETECT; 289 case HPD_PORT_D: 290 return val & PORTD_HOTPLUG_LONG_DETECT; 291 default: 292 return false; 293 } 294 } 295 296 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 297 { 298 switch (pin) { 299 case HPD_PORT_A: 300 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; 301 default: 302 return false; 303 } 304 } 305 306 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 307 { 308 switch (pin) { 309 case HPD_PORT_B: 310 return val & PORTB_HOTPLUG_LONG_DETECT; 311 case HPD_PORT_C: 312 return val & PORTC_HOTPLUG_LONG_DETECT; 313 case HPD_PORT_D: 314 return val & PORTD_HOTPLUG_LONG_DETECT; 315 default: 316 return false; 317 } 318 } 319 320 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 321 { 322 switch (pin) { 323 case HPD_PORT_B: 324 return val & PORTB_HOTPLUG_INT_LONG_PULSE; 325 case HPD_PORT_C: 326 return val & PORTC_HOTPLUG_INT_LONG_PULSE; 327 case HPD_PORT_D: 328 return val & PORTD_HOTPLUG_INT_LONG_PULSE; 329 default: 330 return false; 331 } 332 } 333 334 /* 335 * Get a bit mask of pins that have triggered, and which ones may be long. 336 * This can be called multiple times with the same masks to accumulate 337 * hotplug detection results from several registers. 338 * 339 * Note that the caller is expected to zero out the masks initially. 340 */ 341 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv, 342 u32 *pin_mask, u32 *long_mask, 343 u32 hotplug_trigger, u32 dig_hotplug_reg, 344 const u32 hpd[HPD_NUM_PINS], 345 bool long_pulse_detect(enum hpd_pin pin, u32 val)) 346 { 347 enum hpd_pin pin; 348 349 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); 350 351 for_each_hpd_pin(pin) { 352 if ((hpd[pin] & hotplug_trigger) == 0) 353 continue; 354 355 *pin_mask |= BIT(pin); 356 357 if (long_pulse_detect(pin, dig_hotplug_reg)) 358 *long_mask |= BIT(pin); 359 } 360 361 drm_dbg(&dev_priv->drm, 362 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n", 363 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); 364 } 365 366 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, 367 const u32 hpd[HPD_NUM_PINS]) 368 { 369 struct intel_encoder *encoder; 370 u32 enabled_irqs = 0; 371 372 for_each_intel_encoder(&dev_priv->drm, encoder) 373 if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) 374 enabled_irqs |= hpd[encoder->hpd_pin]; 375 376 return enabled_irqs; 377 } 378 379 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv, 380 const u32 hpd[HPD_NUM_PINS]) 381 { 382 struct intel_encoder *encoder; 383 u32 hotplug_irqs = 0; 384 385 for_each_intel_encoder(&dev_priv->drm, encoder) 386 hotplug_irqs |= hpd[encoder->hpd_pin]; 387 388 return hotplug_irqs; 389 } 390 391 static u32 intel_hpd_hotplug_mask(struct drm_i915_private *i915, 392 hotplug_mask_func hotplug_mask) 393 { 394 enum hpd_pin pin; 395 u32 hotplug = 0; 396 397 for_each_hpd_pin(pin) 398 hotplug |= hotplug_mask(pin); 399 400 return hotplug; 401 } 402 403 static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915, 404 hotplug_enables_func hotplug_enables) 405 { 406 struct intel_encoder *encoder; 407 u32 hotplug = 0; 408 409 for_each_intel_encoder(&i915->drm, encoder) 410 hotplug |= hotplug_enables(encoder); 411 412 return hotplug; 413 } 414 415 u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) 416 { 417 u32 hotplug_status = 0, hotplug_status_mask; 418 int i; 419 420 if (IS_G4X(dev_priv) || 421 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 422 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | 423 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; 424 else 425 hotplug_status_mask = HOTPLUG_INT_STATUS_I915; 426 427 /* 428 * We absolutely have to clear all the pending interrupt 429 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port 430 * interrupt bit won't have an edge, and the i965/g4x 431 * edge triggered IIR will not notice that an interrupt 432 * is still pending. We can't use PORT_HOTPLUG_EN to 433 * guarantee the edge as the act of toggling the enable 434 * bits can itself generate a new hotplug interrupt :( 435 */ 436 for (i = 0; i < 10; i++) { 437 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask; 438 439 if (tmp == 0) 440 return hotplug_status; 441 442 hotplug_status |= tmp; 443 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status); 444 } 445 446 drm_WARN_ONCE(&dev_priv->drm, 1, 447 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", 448 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); 449 450 return hotplug_status; 451 } 452 453 void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_status) 454 { 455 u32 pin_mask = 0, long_mask = 0; 456 u32 hotplug_trigger; 457 458 if (IS_G4X(dev_priv) || 459 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 460 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; 461 else 462 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 463 464 if (hotplug_trigger) { 465 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 466 hotplug_trigger, hotplug_trigger, 467 dev_priv->display.hotplug.hpd, 468 i9xx_port_hotplug_long_detect); 469 470 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 471 } 472 473 if ((IS_G4X(dev_priv) || 474 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 475 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 476 intel_dp_aux_irq_handler(dev_priv); 477 } 478 479 void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger) 480 { 481 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 482 483 /* 484 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU 485 * unless we touch the hotplug register, even if hotplug_trigger is 486 * zero. Not acking leads to "The master control interrupt lied (SDE)!" 487 * errors. 488 */ 489 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 490 if (!hotplug_trigger) { 491 u32 mask = PORTA_HOTPLUG_STATUS_MASK | 492 PORTD_HOTPLUG_STATUS_MASK | 493 PORTC_HOTPLUG_STATUS_MASK | 494 PORTB_HOTPLUG_STATUS_MASK; 495 dig_hotplug_reg &= ~mask; 496 } 497 498 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); 499 if (!hotplug_trigger) 500 return; 501 502 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 503 hotplug_trigger, dig_hotplug_reg, 504 dev_priv->display.hotplug.pch_hpd, 505 pch_port_hotplug_long_detect); 506 507 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 508 } 509 510 void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir) 511 { 512 enum hpd_pin pin; 513 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK); 514 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK; 515 u32 pin_mask = 0, long_mask = 0; 516 517 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) { 518 u32 val; 519 520 if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger)) 521 continue; 522 523 pin_mask |= BIT(pin); 524 525 val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin)); 526 intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val); 527 528 if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT)) 529 long_mask |= BIT(pin); 530 } 531 532 if (pin_mask) { 533 drm_dbg(&i915->drm, 534 "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n", 535 hotplug_trigger, pin_mask, long_mask); 536 537 intel_hpd_irq_handler(i915, pin_mask, long_mask); 538 } 539 540 if (trigger_aux) 541 intel_dp_aux_irq_handler(i915); 542 543 if (!pin_mask && !trigger_aux) 544 drm_err(&i915->drm, 545 "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir); 546 } 547 548 void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 549 { 550 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP; 551 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP; 552 u32 pin_mask = 0, long_mask = 0; 553 554 if (ddi_hotplug_trigger) { 555 u32 dig_hotplug_reg; 556 557 /* Locking due to DSI native GPIO sequences */ 558 spin_lock(&dev_priv->irq_lock); 559 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI, 0, 0); 560 spin_unlock(&dev_priv->irq_lock); 561 562 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 563 ddi_hotplug_trigger, dig_hotplug_reg, 564 dev_priv->display.hotplug.pch_hpd, 565 icp_ddi_port_hotplug_long_detect); 566 } 567 568 if (tc_hotplug_trigger) { 569 u32 dig_hotplug_reg; 570 571 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC, 0, 0); 572 573 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 574 tc_hotplug_trigger, dig_hotplug_reg, 575 dev_priv->display.hotplug.pch_hpd, 576 icp_tc_port_hotplug_long_detect); 577 } 578 579 if (pin_mask) 580 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 581 582 if (pch_iir & SDE_GMBUS_ICP) 583 intel_gmbus_irq_handler(dev_priv); 584 } 585 586 void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 587 { 588 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & 589 ~SDE_PORTE_HOTPLUG_SPT; 590 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; 591 u32 pin_mask = 0, long_mask = 0; 592 593 if (hotplug_trigger) { 594 u32 dig_hotplug_reg; 595 596 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0); 597 598 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 599 hotplug_trigger, dig_hotplug_reg, 600 dev_priv->display.hotplug.pch_hpd, 601 spt_port_hotplug_long_detect); 602 } 603 604 if (hotplug2_trigger) { 605 u32 dig_hotplug_reg; 606 607 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2, 0, 0); 608 609 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 610 hotplug2_trigger, dig_hotplug_reg, 611 dev_priv->display.hotplug.pch_hpd, 612 spt_port_hotplug2_long_detect); 613 } 614 615 if (pin_mask) 616 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 617 618 if (pch_iir & SDE_GMBUS_CPT) 619 intel_gmbus_irq_handler(dev_priv); 620 } 621 622 void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger) 623 { 624 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 625 626 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0); 627 628 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 629 hotplug_trigger, dig_hotplug_reg, 630 dev_priv->display.hotplug.hpd, 631 ilk_port_hotplug_long_detect); 632 633 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 634 } 635 636 void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger) 637 { 638 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 639 640 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0); 641 642 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 643 hotplug_trigger, dig_hotplug_reg, 644 dev_priv->display.hotplug.hpd, 645 bxt_port_hotplug_long_detect); 646 647 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 648 } 649 650 void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) 651 { 652 u32 pin_mask = 0, long_mask = 0; 653 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; 654 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; 655 656 if (trigger_tc) { 657 u32 dig_hotplug_reg; 658 659 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, 0, 0); 660 661 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 662 trigger_tc, dig_hotplug_reg, 663 dev_priv->display.hotplug.hpd, 664 gen11_port_hotplug_long_detect); 665 } 666 667 if (trigger_tbt) { 668 u32 dig_hotplug_reg; 669 670 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, 0, 0); 671 672 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 673 trigger_tbt, dig_hotplug_reg, 674 dev_priv->display.hotplug.hpd, 675 gen11_port_hotplug_long_detect); 676 } 677 678 if (pin_mask) 679 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 680 else 681 drm_err(&dev_priv->drm, 682 "Unexpected DE HPD interrupt 0x%08x\n", iir); 683 } 684 685 static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin) 686 { 687 switch (hpd_pin) { 688 case HPD_PORT_A: 689 return PORTA_HOTPLUG_ENABLE; 690 case HPD_PORT_B: 691 return PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_MASK; 692 case HPD_PORT_C: 693 return PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_MASK; 694 case HPD_PORT_D: 695 return PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_MASK; 696 default: 697 return 0; 698 } 699 } 700 701 static u32 ibx_hotplug_enables(struct intel_encoder *encoder) 702 { 703 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 704 705 switch (encoder->hpd_pin) { 706 case HPD_PORT_A: 707 /* 708 * When CPU and PCH are on the same package, port A 709 * HPD must be enabled in both north and south. 710 */ 711 return HAS_PCH_LPT_LP(i915) ? 712 PORTA_HOTPLUG_ENABLE : 0; 713 case HPD_PORT_B: 714 return PORTB_HOTPLUG_ENABLE | 715 PORTB_PULSE_DURATION_2ms; 716 case HPD_PORT_C: 717 return PORTC_HOTPLUG_ENABLE | 718 PORTC_PULSE_DURATION_2ms; 719 case HPD_PORT_D: 720 return PORTD_HOTPLUG_ENABLE | 721 PORTD_PULSE_DURATION_2ms; 722 default: 723 return 0; 724 } 725 } 726 727 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) 728 { 729 /* 730 * Enable digital hotplug on the PCH, and configure the DP short pulse 731 * duration to 2ms (which is the minimum in the Display Port spec). 732 * The pulse duration bits are reserved on LPT+. 733 */ 734 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 735 intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask), 736 intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables)); 737 } 738 739 static void ibx_hpd_enable_detection(struct intel_encoder *encoder) 740 { 741 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 742 743 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG, 744 ibx_hotplug_mask(encoder->hpd_pin), 745 ibx_hotplug_enables(encoder)); 746 } 747 748 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) 749 { 750 u32 hotplug_irqs, enabled_irqs; 751 752 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 753 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 754 755 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 756 757 ibx_hpd_detection_setup(dev_priv); 758 } 759 760 static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin) 761 { 762 switch (hpd_pin) { 763 case HPD_PORT_A: 764 case HPD_PORT_B: 765 case HPD_PORT_C: 766 case HPD_PORT_D: 767 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin); 768 default: 769 return 0; 770 } 771 } 772 773 static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder) 774 { 775 return icp_ddi_hotplug_mask(encoder->hpd_pin); 776 } 777 778 static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin) 779 { 780 switch (hpd_pin) { 781 case HPD_PORT_TC1: 782 case HPD_PORT_TC2: 783 case HPD_PORT_TC3: 784 case HPD_PORT_TC4: 785 case HPD_PORT_TC5: 786 case HPD_PORT_TC6: 787 return ICP_TC_HPD_ENABLE(hpd_pin); 788 default: 789 return 0; 790 } 791 } 792 793 static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder) 794 { 795 return icp_tc_hotplug_mask(encoder->hpd_pin); 796 } 797 798 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv) 799 { 800 intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI, 801 intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask), 802 intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables)); 803 } 804 805 static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder) 806 { 807 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 808 809 intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_DDI, 810 icp_ddi_hotplug_mask(encoder->hpd_pin), 811 icp_ddi_hotplug_enables(encoder)); 812 } 813 814 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) 815 { 816 intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC, 817 intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask), 818 intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables)); 819 } 820 821 static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder) 822 { 823 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 824 825 intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_TC, 826 icp_tc_hotplug_mask(encoder->hpd_pin), 827 icp_tc_hotplug_enables(encoder)); 828 } 829 830 static void icp_hpd_enable_detection(struct intel_encoder *encoder) 831 { 832 icp_ddi_hpd_enable_detection(encoder); 833 icp_tc_hpd_enable_detection(encoder); 834 } 835 836 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv) 837 { 838 u32 hotplug_irqs, enabled_irqs; 839 840 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 841 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 842 843 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP) 844 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 845 846 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 847 848 icp_ddi_hpd_detection_setup(dev_priv); 849 icp_tc_hpd_detection_setup(dev_priv); 850 } 851 852 static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin) 853 { 854 switch (hpd_pin) { 855 case HPD_PORT_TC1: 856 case HPD_PORT_TC2: 857 case HPD_PORT_TC3: 858 case HPD_PORT_TC4: 859 case HPD_PORT_TC5: 860 case HPD_PORT_TC6: 861 return GEN11_HOTPLUG_CTL_ENABLE(hpd_pin); 862 default: 863 return 0; 864 } 865 } 866 867 static u32 gen11_hotplug_enables(struct intel_encoder *encoder) 868 { 869 return gen11_hotplug_mask(encoder->hpd_pin); 870 } 871 872 static void dg1_hpd_invert(struct drm_i915_private *i915) 873 { 874 u32 val = (INVERT_DDIA_HPD | 875 INVERT_DDIB_HPD | 876 INVERT_DDIC_HPD | 877 INVERT_DDID_HPD); 878 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1, 0, val); 879 } 880 881 static void dg1_hpd_enable_detection(struct intel_encoder *encoder) 882 { 883 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 884 885 dg1_hpd_invert(i915); 886 icp_hpd_enable_detection(encoder); 887 } 888 889 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) 890 { 891 dg1_hpd_invert(dev_priv); 892 icp_hpd_irq_setup(dev_priv); 893 } 894 895 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) 896 { 897 intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, 898 intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask), 899 intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables)); 900 } 901 902 static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder) 903 { 904 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 905 906 intel_uncore_rmw(&i915->uncore, GEN11_TC_HOTPLUG_CTL, 907 gen11_hotplug_mask(encoder->hpd_pin), 908 gen11_hotplug_enables(encoder)); 909 } 910 911 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv) 912 { 913 intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, 914 intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask), 915 intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables)); 916 } 917 918 static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder) 919 { 920 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 921 922 intel_uncore_rmw(&i915->uncore, GEN11_TBT_HOTPLUG_CTL, 923 gen11_hotplug_mask(encoder->hpd_pin), 924 gen11_hotplug_enables(encoder)); 925 } 926 927 static void gen11_hpd_enable_detection(struct intel_encoder *encoder) 928 { 929 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 930 931 gen11_tc_hpd_enable_detection(encoder); 932 gen11_tbt_hpd_enable_detection(encoder); 933 934 if (INTEL_PCH_TYPE(i915) >= PCH_ICP) 935 icp_hpd_enable_detection(encoder); 936 } 937 938 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) 939 { 940 u32 hotplug_irqs, enabled_irqs; 941 942 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd); 943 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd); 944 945 intel_uncore_rmw(&dev_priv->uncore, GEN11_DE_HPD_IMR, hotplug_irqs, 946 ~enabled_irqs & hotplug_irqs); 947 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); 948 949 gen11_tc_hpd_detection_setup(dev_priv); 950 gen11_tbt_hpd_detection_setup(dev_priv); 951 952 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 953 icp_hpd_irq_setup(dev_priv); 954 } 955 956 static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin) 957 { 958 switch (hpd_pin) { 959 case HPD_PORT_A: 960 case HPD_PORT_B: 961 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin); 962 default: 963 return 0; 964 } 965 } 966 967 static u32 mtp_ddi_hotplug_enables(struct intel_encoder *encoder) 968 { 969 return mtp_ddi_hotplug_mask(encoder->hpd_pin); 970 } 971 972 static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin) 973 { 974 switch (hpd_pin) { 975 case HPD_PORT_TC1: 976 case HPD_PORT_TC2: 977 case HPD_PORT_TC3: 978 case HPD_PORT_TC4: 979 return ICP_TC_HPD_ENABLE(hpd_pin); 980 default: 981 return 0; 982 } 983 } 984 985 static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder) 986 { 987 return mtp_tc_hotplug_mask(encoder->hpd_pin); 988 } 989 990 static void mtp_ddi_hpd_detection_setup(struct drm_i915_private *i915) 991 { 992 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, 993 intel_hpd_hotplug_mask(i915, mtp_ddi_hotplug_mask), 994 intel_hpd_hotplug_enables(i915, mtp_ddi_hotplug_enables)); 995 } 996 997 static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder) 998 { 999 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1000 1001 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, 1002 mtp_ddi_hotplug_mask(encoder->hpd_pin), 1003 mtp_ddi_hotplug_enables(encoder)); 1004 } 1005 1006 static void mtp_tc_hpd_detection_setup(struct drm_i915_private *i915) 1007 { 1008 intel_de_rmw(i915, SHOTPLUG_CTL_TC, 1009 intel_hpd_hotplug_mask(i915, mtp_tc_hotplug_mask), 1010 intel_hpd_hotplug_enables(i915, mtp_tc_hotplug_enables)); 1011 } 1012 1013 static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder) 1014 { 1015 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1016 1017 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, 1018 mtp_tc_hotplug_mask(encoder->hpd_pin), 1019 mtp_tc_hotplug_enables(encoder)); 1020 } 1021 1022 static void mtp_hpd_invert(struct drm_i915_private *i915) 1023 { 1024 u32 val = (INVERT_DDIA_HPD | 1025 INVERT_DDIB_HPD | 1026 INVERT_DDIC_HPD | 1027 INVERT_TC1_HPD | 1028 INVERT_TC2_HPD | 1029 INVERT_TC3_HPD | 1030 INVERT_TC4_HPD | 1031 INVERT_DDID_HPD_MTP | 1032 INVERT_DDIE_HPD); 1033 intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val); 1034 } 1035 1036 static void mtp_hpd_enable_detection(struct intel_encoder *encoder) 1037 { 1038 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1039 1040 mtp_hpd_invert(i915); 1041 mtp_ddi_hpd_enable_detection(encoder); 1042 mtp_tc_hpd_enable_detection(encoder); 1043 } 1044 1045 static void mtp_hpd_irq_setup(struct drm_i915_private *i915) 1046 { 1047 u32 hotplug_irqs, enabled_irqs; 1048 1049 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd); 1050 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd); 1051 1052 intel_de_write(i915, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 1053 1054 mtp_hpd_invert(i915); 1055 ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs); 1056 1057 mtp_ddi_hpd_detection_setup(i915); 1058 mtp_tc_hpd_detection_setup(i915); 1059 } 1060 1061 static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin) 1062 { 1063 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4; 1064 } 1065 1066 static void _xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915, 1067 enum hpd_pin hpd_pin, bool enable) 1068 { 1069 u32 mask = XELPDP_TBT_HOTPLUG_ENABLE | 1070 XELPDP_DP_ALT_HOTPLUG_ENABLE; 1071 1072 if (!is_xelpdp_pica_hpd_pin(hpd_pin)) 1073 return; 1074 1075 intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin), 1076 mask, enable ? mask : 0); 1077 } 1078 1079 static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder) 1080 { 1081 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1082 1083 _xelpdp_pica_hpd_detection_setup(i915, encoder->hpd_pin, true); 1084 } 1085 1086 static void xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915) 1087 { 1088 struct intel_encoder *encoder; 1089 u32 available_pins = 0; 1090 enum hpd_pin pin; 1091 1092 BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS); 1093 1094 for_each_intel_encoder(&i915->drm, encoder) 1095 available_pins |= BIT(encoder->hpd_pin); 1096 1097 for_each_hpd_pin(pin) 1098 _xelpdp_pica_hpd_detection_setup(i915, pin, available_pins & BIT(pin)); 1099 } 1100 1101 static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder) 1102 { 1103 xelpdp_pica_hpd_enable_detection(encoder); 1104 mtp_hpd_enable_detection(encoder); 1105 } 1106 1107 static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915) 1108 { 1109 u32 hotplug_irqs, enabled_irqs; 1110 1111 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd); 1112 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.hpd); 1113 1114 intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs, 1115 ~enabled_irqs & hotplug_irqs); 1116 intel_uncore_posting_read(&i915->uncore, PICAINTERRUPT_IMR); 1117 1118 xelpdp_pica_hpd_detection_setup(i915); 1119 1120 if (INTEL_PCH_TYPE(i915) >= PCH_MTP) 1121 mtp_hpd_irq_setup(i915); 1122 } 1123 1124 static u32 spt_hotplug_mask(enum hpd_pin hpd_pin) 1125 { 1126 switch (hpd_pin) { 1127 case HPD_PORT_A: 1128 return PORTA_HOTPLUG_ENABLE; 1129 case HPD_PORT_B: 1130 return PORTB_HOTPLUG_ENABLE; 1131 case HPD_PORT_C: 1132 return PORTC_HOTPLUG_ENABLE; 1133 case HPD_PORT_D: 1134 return PORTD_HOTPLUG_ENABLE; 1135 default: 1136 return 0; 1137 } 1138 } 1139 1140 static u32 spt_hotplug_enables(struct intel_encoder *encoder) 1141 { 1142 return spt_hotplug_mask(encoder->hpd_pin); 1143 } 1144 1145 static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin) 1146 { 1147 switch (hpd_pin) { 1148 case HPD_PORT_E: 1149 return PORTE_HOTPLUG_ENABLE; 1150 default: 1151 return 0; 1152 } 1153 } 1154 1155 static u32 spt_hotplug2_enables(struct intel_encoder *encoder) 1156 { 1157 return spt_hotplug2_mask(encoder->hpd_pin); 1158 } 1159 1160 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) 1161 { 1162 /* Display WA #1179 WaHardHangonHotPlug: cnp */ 1163 if (HAS_PCH_CNP(dev_priv)) { 1164 intel_uncore_rmw(&dev_priv->uncore, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK, 1165 CHASSIS_CLK_REQ_DURATION(0xf)); 1166 } 1167 1168 /* Enable digital hotplug on the PCH */ 1169 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 1170 intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask), 1171 intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables)); 1172 1173 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2, 1174 intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask), 1175 intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables)); 1176 } 1177 1178 static void spt_hpd_enable_detection(struct intel_encoder *encoder) 1179 { 1180 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1181 1182 /* Display WA #1179 WaHardHangonHotPlug: cnp */ 1183 if (HAS_PCH_CNP(i915)) { 1184 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1, 1185 CHASSIS_CLK_REQ_DURATION_MASK, 1186 CHASSIS_CLK_REQ_DURATION(0xf)); 1187 } 1188 1189 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG, 1190 spt_hotplug_mask(encoder->hpd_pin), 1191 spt_hotplug_enables(encoder)); 1192 1193 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG2, 1194 spt_hotplug2_mask(encoder->hpd_pin), 1195 spt_hotplug2_enables(encoder)); 1196 } 1197 1198 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) 1199 { 1200 u32 hotplug_irqs, enabled_irqs; 1201 1202 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 1203 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 1204 1205 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 1206 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 1207 1208 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 1209 1210 spt_hpd_detection_setup(dev_priv); 1211 } 1212 1213 static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin) 1214 { 1215 switch (hpd_pin) { 1216 case HPD_PORT_A: 1217 return DIGITAL_PORTA_HOTPLUG_ENABLE | 1218 DIGITAL_PORTA_PULSE_DURATION_MASK; 1219 default: 1220 return 0; 1221 } 1222 } 1223 1224 static u32 ilk_hotplug_enables(struct intel_encoder *encoder) 1225 { 1226 switch (encoder->hpd_pin) { 1227 case HPD_PORT_A: 1228 return DIGITAL_PORTA_HOTPLUG_ENABLE | 1229 DIGITAL_PORTA_PULSE_DURATION_2ms; 1230 default: 1231 return 0; 1232 } 1233 } 1234 1235 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) 1236 { 1237 /* 1238 * Enable digital hotplug on the CPU, and configure the DP short pulse 1239 * duration to 2ms (which is the minimum in the Display Port spec) 1240 * The pulse duration bits are reserved on HSW+. 1241 */ 1242 intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, 1243 intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask), 1244 intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables)); 1245 } 1246 1247 static void ilk_hpd_enable_detection(struct intel_encoder *encoder) 1248 { 1249 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1250 1251 intel_uncore_rmw(&i915->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, 1252 ilk_hotplug_mask(encoder->hpd_pin), 1253 ilk_hotplug_enables(encoder)); 1254 1255 ibx_hpd_enable_detection(encoder); 1256 } 1257 1258 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) 1259 { 1260 u32 hotplug_irqs, enabled_irqs; 1261 1262 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd); 1263 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd); 1264 1265 if (DISPLAY_VER(dev_priv) >= 8) 1266 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); 1267 else 1268 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); 1269 1270 ilk_hpd_detection_setup(dev_priv); 1271 1272 ibx_hpd_irq_setup(dev_priv); 1273 } 1274 1275 static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin) 1276 { 1277 switch (hpd_pin) { 1278 case HPD_PORT_A: 1279 return PORTA_HOTPLUG_ENABLE | BXT_DDIA_HPD_INVERT; 1280 case HPD_PORT_B: 1281 return PORTB_HOTPLUG_ENABLE | BXT_DDIB_HPD_INVERT; 1282 case HPD_PORT_C: 1283 return PORTC_HOTPLUG_ENABLE | BXT_DDIC_HPD_INVERT; 1284 default: 1285 return 0; 1286 } 1287 } 1288 1289 static u32 bxt_hotplug_enables(struct intel_encoder *encoder) 1290 { 1291 u32 hotplug; 1292 1293 switch (encoder->hpd_pin) { 1294 case HPD_PORT_A: 1295 hotplug = PORTA_HOTPLUG_ENABLE; 1296 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1297 hotplug |= BXT_DDIA_HPD_INVERT; 1298 return hotplug; 1299 case HPD_PORT_B: 1300 hotplug = PORTB_HOTPLUG_ENABLE; 1301 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1302 hotplug |= BXT_DDIB_HPD_INVERT; 1303 return hotplug; 1304 case HPD_PORT_C: 1305 hotplug = PORTC_HOTPLUG_ENABLE; 1306 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1307 hotplug |= BXT_DDIC_HPD_INVERT; 1308 return hotplug; 1309 default: 1310 return 0; 1311 } 1312 } 1313 1314 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) 1315 { 1316 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 1317 intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask), 1318 intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables)); 1319 } 1320 1321 static void bxt_hpd_enable_detection(struct intel_encoder *encoder) 1322 { 1323 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1324 1325 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG, 1326 bxt_hotplug_mask(encoder->hpd_pin), 1327 bxt_hotplug_enables(encoder)); 1328 } 1329 1330 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) 1331 { 1332 u32 hotplug_irqs, enabled_irqs; 1333 1334 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd); 1335 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd); 1336 1337 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); 1338 1339 bxt_hpd_detection_setup(dev_priv); 1340 } 1341 1342 static void i915_hpd_enable_detection(struct intel_encoder *encoder) 1343 { 1344 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1345 u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin]; 1346 1347 /* HPD sense and interrupt enable are one and the same */ 1348 i915_hotplug_interrupt_update(i915, hotplug_en, hotplug_en); 1349 } 1350 1351 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) 1352 { 1353 u32 hotplug_en; 1354 1355 lockdep_assert_held(&dev_priv->irq_lock); 1356 1357 /* 1358 * Note HDMI and DP share hotplug bits. Enable bits are the same for all 1359 * generations. 1360 */ 1361 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); 1362 /* 1363 * Programming the CRT detection parameters tends to generate a spurious 1364 * hotplug event about three seconds later. So just do it once. 1365 */ 1366 if (IS_G4X(dev_priv)) 1367 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 1368 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 1369 1370 /* Ignore TV since it's buggy */ 1371 i915_hotplug_interrupt_update_locked(dev_priv, 1372 HOTPLUG_INT_EN_MASK | 1373 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | 1374 CRT_HOTPLUG_ACTIVATION_PERIOD_64, 1375 hotplug_en); 1376 } 1377 1378 struct intel_hotplug_funcs { 1379 /* Enable HPD sense and interrupts for all present encoders */ 1380 void (*hpd_irq_setup)(struct drm_i915_private *i915); 1381 /* Enable HPD sense for a single encoder */ 1382 void (*hpd_enable_detection)(struct intel_encoder *encoder); 1383 }; 1384 1385 #define HPD_FUNCS(platform) \ 1386 static const struct intel_hotplug_funcs platform##_hpd_funcs = { \ 1387 .hpd_irq_setup = platform##_hpd_irq_setup, \ 1388 .hpd_enable_detection = platform##_hpd_enable_detection, \ 1389 } 1390 1391 HPD_FUNCS(i915); 1392 HPD_FUNCS(xelpdp); 1393 HPD_FUNCS(dg1); 1394 HPD_FUNCS(gen11); 1395 HPD_FUNCS(bxt); 1396 HPD_FUNCS(icp); 1397 HPD_FUNCS(spt); 1398 HPD_FUNCS(ilk); 1399 #undef HPD_FUNCS 1400 1401 void intel_hpd_enable_detection(struct intel_encoder *encoder) 1402 { 1403 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1404 1405 if (i915->display.funcs.hotplug) 1406 i915->display.funcs.hotplug->hpd_enable_detection(encoder); 1407 } 1408 1409 void intel_hpd_irq_setup(struct drm_i915_private *i915) 1410 { 1411 if (i915->display_irqs_enabled && i915->display.funcs.hotplug) 1412 i915->display.funcs.hotplug->hpd_irq_setup(i915); 1413 } 1414 1415 void intel_hotplug_irq_init(struct drm_i915_private *i915) 1416 { 1417 intel_hpd_init_pins(i915); 1418 1419 intel_hpd_init_early(i915); 1420 1421 if (HAS_GMCH(i915)) { 1422 if (I915_HAS_HOTPLUG(i915)) 1423 i915->display.funcs.hotplug = &i915_hpd_funcs; 1424 } else { 1425 if (HAS_PCH_DG2(i915)) 1426 i915->display.funcs.hotplug = &icp_hpd_funcs; 1427 else if (HAS_PCH_DG1(i915)) 1428 i915->display.funcs.hotplug = &dg1_hpd_funcs; 1429 else if (DISPLAY_VER(i915) >= 14) 1430 i915->display.funcs.hotplug = &xelpdp_hpd_funcs; 1431 else if (DISPLAY_VER(i915) >= 11) 1432 i915->display.funcs.hotplug = &gen11_hpd_funcs; 1433 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 1434 i915->display.funcs.hotplug = &bxt_hpd_funcs; 1435 else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) 1436 i915->display.funcs.hotplug = &icp_hpd_funcs; 1437 else if (INTEL_PCH_TYPE(i915) >= PCH_SPT) 1438 i915->display.funcs.hotplug = &spt_hpd_funcs; 1439 else 1440 i915->display.funcs.hotplug = &ilk_hpd_funcs; 1441 } 1442 } 1443