1 /*
2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2009 Intel Corporation
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *	Eric Anholt <eric@anholt.net>
26  *	Jesse Barnes <jesse.barnes@intel.com>
27  */
28 
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
34 
35 #include <drm/display/drm_hdcp_helper.h>
36 #include <drm/display/drm_hdmi_helper.h>
37 #include <drm/display/drm_scdc_helper.h>
38 #include <drm/drm_atomic_helper.h>
39 #include <drm/drm_crtc.h>
40 #include <drm/drm_edid.h>
41 #include <drm/intel_lpe_audio.h>
42 
43 #include "i915_debugfs.h"
44 #include "i915_drv.h"
45 #include "i915_reg.h"
46 #include "intel_atomic.h"
47 #include "intel_audio.h"
48 #include "intel_connector.h"
49 #include "intel_ddi.h"
50 #include "intel_de.h"
51 #include "intel_display_types.h"
52 #include "intel_dp.h"
53 #include "intel_gmbus.h"
54 #include "intel_hdcp.h"
55 #include "intel_hdcp_regs.h"
56 #include "intel_hdmi.h"
57 #include "intel_lspcon.h"
58 #include "intel_panel.h"
59 #include "intel_snps_phy.h"
60 
61 static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
62 {
63 	return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
64 }
65 
66 static void
67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
68 {
69 	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
70 	u32 enabled_bits;
71 
72 	enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
73 
74 	drm_WARN(&dev_priv->drm,
75 		 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
76 		 "HDMI port enabled, expecting disabled\n");
77 }
78 
79 static void
80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
81 				     enum transcoder cpu_transcoder)
82 {
83 	drm_WARN(&dev_priv->drm,
84 		 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
85 		 TRANS_DDI_FUNC_ENABLE,
86 		 "HDMI transcoder function enabled, expecting disabled\n");
87 }
88 
89 static u32 g4x_infoframe_index(unsigned int type)
90 {
91 	switch (type) {
92 	case HDMI_PACKET_TYPE_GAMUT_METADATA:
93 		return VIDEO_DIP_SELECT_GAMUT;
94 	case HDMI_INFOFRAME_TYPE_AVI:
95 		return VIDEO_DIP_SELECT_AVI;
96 	case HDMI_INFOFRAME_TYPE_SPD:
97 		return VIDEO_DIP_SELECT_SPD;
98 	case HDMI_INFOFRAME_TYPE_VENDOR:
99 		return VIDEO_DIP_SELECT_VENDOR;
100 	default:
101 		MISSING_CASE(type);
102 		return 0;
103 	}
104 }
105 
106 static u32 g4x_infoframe_enable(unsigned int type)
107 {
108 	switch (type) {
109 	case HDMI_PACKET_TYPE_GENERAL_CONTROL:
110 		return VIDEO_DIP_ENABLE_GCP;
111 	case HDMI_PACKET_TYPE_GAMUT_METADATA:
112 		return VIDEO_DIP_ENABLE_GAMUT;
113 	case DP_SDP_VSC:
114 		return 0;
115 	case HDMI_INFOFRAME_TYPE_AVI:
116 		return VIDEO_DIP_ENABLE_AVI;
117 	case HDMI_INFOFRAME_TYPE_SPD:
118 		return VIDEO_DIP_ENABLE_SPD;
119 	case HDMI_INFOFRAME_TYPE_VENDOR:
120 		return VIDEO_DIP_ENABLE_VENDOR;
121 	case HDMI_INFOFRAME_TYPE_DRM:
122 		return 0;
123 	default:
124 		MISSING_CASE(type);
125 		return 0;
126 	}
127 }
128 
129 static u32 hsw_infoframe_enable(unsigned int type)
130 {
131 	switch (type) {
132 	case HDMI_PACKET_TYPE_GENERAL_CONTROL:
133 		return VIDEO_DIP_ENABLE_GCP_HSW;
134 	case HDMI_PACKET_TYPE_GAMUT_METADATA:
135 		return VIDEO_DIP_ENABLE_GMP_HSW;
136 	case DP_SDP_VSC:
137 		return VIDEO_DIP_ENABLE_VSC_HSW;
138 	case DP_SDP_PPS:
139 		return VDIP_ENABLE_PPS;
140 	case HDMI_INFOFRAME_TYPE_AVI:
141 		return VIDEO_DIP_ENABLE_AVI_HSW;
142 	case HDMI_INFOFRAME_TYPE_SPD:
143 		return VIDEO_DIP_ENABLE_SPD_HSW;
144 	case HDMI_INFOFRAME_TYPE_VENDOR:
145 		return VIDEO_DIP_ENABLE_VS_HSW;
146 	case HDMI_INFOFRAME_TYPE_DRM:
147 		return VIDEO_DIP_ENABLE_DRM_GLK;
148 	default:
149 		MISSING_CASE(type);
150 		return 0;
151 	}
152 }
153 
154 static i915_reg_t
155 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
156 		 enum transcoder cpu_transcoder,
157 		 unsigned int type,
158 		 int i)
159 {
160 	switch (type) {
161 	case HDMI_PACKET_TYPE_GAMUT_METADATA:
162 		return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
163 	case DP_SDP_VSC:
164 		return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
165 	case DP_SDP_PPS:
166 		return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
167 	case HDMI_INFOFRAME_TYPE_AVI:
168 		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
169 	case HDMI_INFOFRAME_TYPE_SPD:
170 		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
171 	case HDMI_INFOFRAME_TYPE_VENDOR:
172 		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
173 	case HDMI_INFOFRAME_TYPE_DRM:
174 		return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
175 	default:
176 		MISSING_CASE(type);
177 		return INVALID_MMIO_REG;
178 	}
179 }
180 
181 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
182 			     unsigned int type)
183 {
184 	switch (type) {
185 	case DP_SDP_VSC:
186 		return VIDEO_DIP_VSC_DATA_SIZE;
187 	case DP_SDP_PPS:
188 		return VIDEO_DIP_PPS_DATA_SIZE;
189 	case HDMI_PACKET_TYPE_GAMUT_METADATA:
190 		if (DISPLAY_VER(dev_priv) >= 11)
191 			return VIDEO_DIP_GMP_DATA_SIZE;
192 		else
193 			return VIDEO_DIP_DATA_SIZE;
194 	default:
195 		return VIDEO_DIP_DATA_SIZE;
196 	}
197 }
198 
199 static void g4x_write_infoframe(struct intel_encoder *encoder,
200 				const struct intel_crtc_state *crtc_state,
201 				unsigned int type,
202 				const void *frame, ssize_t len)
203 {
204 	const u32 *data = frame;
205 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
206 	u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
207 	int i;
208 
209 	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
210 		 "Writing DIP with CTL reg disabled\n");
211 
212 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
213 	val |= g4x_infoframe_index(type);
214 
215 	val &= ~g4x_infoframe_enable(type);
216 
217 	intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
218 
219 	for (i = 0; i < len; i += 4) {
220 		intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
221 		data++;
222 	}
223 	/* Write every possible data byte to force correct ECC calculation. */
224 	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
225 		intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
226 
227 	val |= g4x_infoframe_enable(type);
228 	val &= ~VIDEO_DIP_FREQ_MASK;
229 	val |= VIDEO_DIP_FREQ_VSYNC;
230 
231 	intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
232 	intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
233 }
234 
235 static void g4x_read_infoframe(struct intel_encoder *encoder,
236 			       const struct intel_crtc_state *crtc_state,
237 			       unsigned int type,
238 			       void *frame, ssize_t len)
239 {
240 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
241 	u32 val, *data = frame;
242 	int i;
243 
244 	val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
245 
246 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
247 	val |= g4x_infoframe_index(type);
248 
249 	intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
250 
251 	for (i = 0; i < len; i += 4)
252 		*data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
253 }
254 
255 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
256 				  const struct intel_crtc_state *pipe_config)
257 {
258 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
259 	u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
260 
261 	if ((val & VIDEO_DIP_ENABLE) == 0)
262 		return 0;
263 
264 	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
265 		return 0;
266 
267 	return val & (VIDEO_DIP_ENABLE_AVI |
268 		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
269 }
270 
271 static void ibx_write_infoframe(struct intel_encoder *encoder,
272 				const struct intel_crtc_state *crtc_state,
273 				unsigned int type,
274 				const void *frame, ssize_t len)
275 {
276 	const u32 *data = frame;
277 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
278 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
279 	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
280 	u32 val = intel_de_read(dev_priv, reg);
281 	int i;
282 
283 	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
284 		 "Writing DIP with CTL reg disabled\n");
285 
286 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
287 	val |= g4x_infoframe_index(type);
288 
289 	val &= ~g4x_infoframe_enable(type);
290 
291 	intel_de_write(dev_priv, reg, val);
292 
293 	for (i = 0; i < len; i += 4) {
294 		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
295 			       *data);
296 		data++;
297 	}
298 	/* Write every possible data byte to force correct ECC calculation. */
299 	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
300 		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
301 
302 	val |= g4x_infoframe_enable(type);
303 	val &= ~VIDEO_DIP_FREQ_MASK;
304 	val |= VIDEO_DIP_FREQ_VSYNC;
305 
306 	intel_de_write(dev_priv, reg, val);
307 	intel_de_posting_read(dev_priv, reg);
308 }
309 
310 static void ibx_read_infoframe(struct intel_encoder *encoder,
311 			       const struct intel_crtc_state *crtc_state,
312 			       unsigned int type,
313 			       void *frame, ssize_t len)
314 {
315 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
316 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
317 	u32 val, *data = frame;
318 	int i;
319 
320 	val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
321 
322 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
323 	val |= g4x_infoframe_index(type);
324 
325 	intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
326 
327 	for (i = 0; i < len; i += 4)
328 		*data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
329 }
330 
331 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
332 				  const struct intel_crtc_state *pipe_config)
333 {
334 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
335 	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
336 	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
337 	u32 val = intel_de_read(dev_priv, reg);
338 
339 	if ((val & VIDEO_DIP_ENABLE) == 0)
340 		return 0;
341 
342 	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
343 		return 0;
344 
345 	return val & (VIDEO_DIP_ENABLE_AVI |
346 		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
347 		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
348 }
349 
350 static void cpt_write_infoframe(struct intel_encoder *encoder,
351 				const struct intel_crtc_state *crtc_state,
352 				unsigned int type,
353 				const void *frame, ssize_t len)
354 {
355 	const u32 *data = frame;
356 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
357 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
358 	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
359 	u32 val = intel_de_read(dev_priv, reg);
360 	int i;
361 
362 	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
363 		 "Writing DIP with CTL reg disabled\n");
364 
365 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
366 	val |= g4x_infoframe_index(type);
367 
368 	/* The DIP control register spec says that we need to update the AVI
369 	 * infoframe without clearing its enable bit */
370 	if (type != HDMI_INFOFRAME_TYPE_AVI)
371 		val &= ~g4x_infoframe_enable(type);
372 
373 	intel_de_write(dev_priv, reg, val);
374 
375 	for (i = 0; i < len; i += 4) {
376 		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
377 			       *data);
378 		data++;
379 	}
380 	/* Write every possible data byte to force correct ECC calculation. */
381 	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
382 		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
383 
384 	val |= g4x_infoframe_enable(type);
385 	val &= ~VIDEO_DIP_FREQ_MASK;
386 	val |= VIDEO_DIP_FREQ_VSYNC;
387 
388 	intel_de_write(dev_priv, reg, val);
389 	intel_de_posting_read(dev_priv, reg);
390 }
391 
392 static void cpt_read_infoframe(struct intel_encoder *encoder,
393 			       const struct intel_crtc_state *crtc_state,
394 			       unsigned int type,
395 			       void *frame, ssize_t len)
396 {
397 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
398 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
399 	u32 val, *data = frame;
400 	int i;
401 
402 	val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
403 
404 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
405 	val |= g4x_infoframe_index(type);
406 
407 	intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
408 
409 	for (i = 0; i < len; i += 4)
410 		*data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
411 }
412 
413 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
414 				  const struct intel_crtc_state *pipe_config)
415 {
416 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
417 	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
418 	u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
419 
420 	if ((val & VIDEO_DIP_ENABLE) == 0)
421 		return 0;
422 
423 	return val & (VIDEO_DIP_ENABLE_AVI |
424 		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
425 		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
426 }
427 
428 static void vlv_write_infoframe(struct intel_encoder *encoder,
429 				const struct intel_crtc_state *crtc_state,
430 				unsigned int type,
431 				const void *frame, ssize_t len)
432 {
433 	const u32 *data = frame;
434 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
435 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
436 	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
437 	u32 val = intel_de_read(dev_priv, reg);
438 	int i;
439 
440 	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
441 		 "Writing DIP with CTL reg disabled\n");
442 
443 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
444 	val |= g4x_infoframe_index(type);
445 
446 	val &= ~g4x_infoframe_enable(type);
447 
448 	intel_de_write(dev_priv, reg, val);
449 
450 	for (i = 0; i < len; i += 4) {
451 		intel_de_write(dev_priv,
452 			       VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
453 		data++;
454 	}
455 	/* Write every possible data byte to force correct ECC calculation. */
456 	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
457 		intel_de_write(dev_priv,
458 			       VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
459 
460 	val |= g4x_infoframe_enable(type);
461 	val &= ~VIDEO_DIP_FREQ_MASK;
462 	val |= VIDEO_DIP_FREQ_VSYNC;
463 
464 	intel_de_write(dev_priv, reg, val);
465 	intel_de_posting_read(dev_priv, reg);
466 }
467 
468 static void vlv_read_infoframe(struct intel_encoder *encoder,
469 			       const struct intel_crtc_state *crtc_state,
470 			       unsigned int type,
471 			       void *frame, ssize_t len)
472 {
473 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
474 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
475 	u32 val, *data = frame;
476 	int i;
477 
478 	val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
479 
480 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
481 	val |= g4x_infoframe_index(type);
482 
483 	intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
484 
485 	for (i = 0; i < len; i += 4)
486 		*data++ = intel_de_read(dev_priv,
487 				        VLV_TVIDEO_DIP_DATA(crtc->pipe));
488 }
489 
490 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
491 				  const struct intel_crtc_state *pipe_config)
492 {
493 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
494 	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
495 	u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
496 
497 	if ((val & VIDEO_DIP_ENABLE) == 0)
498 		return 0;
499 
500 	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
501 		return 0;
502 
503 	return val & (VIDEO_DIP_ENABLE_AVI |
504 		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
505 		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
506 }
507 
508 void hsw_write_infoframe(struct intel_encoder *encoder,
509 			 const struct intel_crtc_state *crtc_state,
510 			 unsigned int type,
511 			 const void *frame, ssize_t len)
512 {
513 	const u32 *data = frame;
514 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
515 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
516 	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
517 	int data_size;
518 	int i;
519 	u32 val = intel_de_read(dev_priv, ctl_reg);
520 
521 	data_size = hsw_dip_data_size(dev_priv, type);
522 
523 	drm_WARN_ON(&dev_priv->drm, len > data_size);
524 
525 	val &= ~hsw_infoframe_enable(type);
526 	intel_de_write(dev_priv, ctl_reg, val);
527 
528 	for (i = 0; i < len; i += 4) {
529 		intel_de_write(dev_priv,
530 			       hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
531 			       *data);
532 		data++;
533 	}
534 	/* Write every possible data byte to force correct ECC calculation. */
535 	for (; i < data_size; i += 4)
536 		intel_de_write(dev_priv,
537 			       hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
538 			       0);
539 
540 	/* Wa_14013475917 */
541 	if (IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC)
542 		return;
543 
544 	val |= hsw_infoframe_enable(type);
545 	intel_de_write(dev_priv, ctl_reg, val);
546 	intel_de_posting_read(dev_priv, ctl_reg);
547 }
548 
549 void hsw_read_infoframe(struct intel_encoder *encoder,
550 			const struct intel_crtc_state *crtc_state,
551 			unsigned int type, void *frame, ssize_t len)
552 {
553 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
554 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
555 	u32 *data = frame;
556 	int i;
557 
558 	for (i = 0; i < len; i += 4)
559 		*data++ = intel_de_read(dev_priv,
560 				        hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
561 }
562 
563 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
564 				  const struct intel_crtc_state *pipe_config)
565 {
566 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
567 	u32 val = intel_de_read(dev_priv,
568 				HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
569 	u32 mask;
570 
571 	mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
572 		VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
573 		VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
574 
575 	if (DISPLAY_VER(dev_priv) >= 10)
576 		mask |= VIDEO_DIP_ENABLE_DRM_GLK;
577 
578 	return val & mask;
579 }
580 
581 static const u8 infoframe_type_to_idx[] = {
582 	HDMI_PACKET_TYPE_GENERAL_CONTROL,
583 	HDMI_PACKET_TYPE_GAMUT_METADATA,
584 	DP_SDP_VSC,
585 	HDMI_INFOFRAME_TYPE_AVI,
586 	HDMI_INFOFRAME_TYPE_SPD,
587 	HDMI_INFOFRAME_TYPE_VENDOR,
588 	HDMI_INFOFRAME_TYPE_DRM,
589 };
590 
591 u32 intel_hdmi_infoframe_enable(unsigned int type)
592 {
593 	int i;
594 
595 	for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
596 		if (infoframe_type_to_idx[i] == type)
597 			return BIT(i);
598 	}
599 
600 	return 0;
601 }
602 
603 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
604 				  const struct intel_crtc_state *crtc_state)
605 {
606 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
607 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
608 	u32 val, ret = 0;
609 	int i;
610 
611 	val = dig_port->infoframes_enabled(encoder, crtc_state);
612 
613 	/* map from hardware bits to dip idx */
614 	for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
615 		unsigned int type = infoframe_type_to_idx[i];
616 
617 		if (HAS_DDI(dev_priv)) {
618 			if (val & hsw_infoframe_enable(type))
619 				ret |= BIT(i);
620 		} else {
621 			if (val & g4x_infoframe_enable(type))
622 				ret |= BIT(i);
623 		}
624 	}
625 
626 	return ret;
627 }
628 
629 /*
630  * The data we write to the DIP data buffer registers is 1 byte bigger than the
631  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
632  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
633  * used for both technologies.
634  *
635  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
636  * DW1:       DB3       | DB2 | DB1 | DB0
637  * DW2:       DB7       | DB6 | DB5 | DB4
638  * DW3: ...
639  *
640  * (HB is Header Byte, DB is Data Byte)
641  *
642  * The hdmi pack() functions don't know about that hardware specific hole so we
643  * trick them by giving an offset into the buffer and moving back the header
644  * bytes by one.
645  */
646 static void intel_write_infoframe(struct intel_encoder *encoder,
647 				  const struct intel_crtc_state *crtc_state,
648 				  enum hdmi_infoframe_type type,
649 				  const union hdmi_infoframe *frame)
650 {
651 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
652 	u8 buffer[VIDEO_DIP_DATA_SIZE];
653 	ssize_t len;
654 
655 	if ((crtc_state->infoframes.enable &
656 	     intel_hdmi_infoframe_enable(type)) == 0)
657 		return;
658 
659 	if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
660 		return;
661 
662 	/* see comment above for the reason for this offset */
663 	len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
664 	if (drm_WARN_ON(encoder->base.dev, len < 0))
665 		return;
666 
667 	/* Insert the 'hole' (see big comment above) at position 3 */
668 	memmove(&buffer[0], &buffer[1], 3);
669 	buffer[3] = 0;
670 	len++;
671 
672 	dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
673 }
674 
675 void intel_read_infoframe(struct intel_encoder *encoder,
676 			  const struct intel_crtc_state *crtc_state,
677 			  enum hdmi_infoframe_type type,
678 			  union hdmi_infoframe *frame)
679 {
680 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
681 	u8 buffer[VIDEO_DIP_DATA_SIZE];
682 	int ret;
683 
684 	if ((crtc_state->infoframes.enable &
685 	     intel_hdmi_infoframe_enable(type)) == 0)
686 		return;
687 
688 	dig_port->read_infoframe(encoder, crtc_state,
689 				       type, buffer, sizeof(buffer));
690 
691 	/* Fill the 'hole' (see big comment above) at position 3 */
692 	memmove(&buffer[1], &buffer[0], 3);
693 
694 	/* see comment above for the reason for this offset */
695 	ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
696 	if (ret) {
697 		drm_dbg_kms(encoder->base.dev,
698 			    "Failed to unpack infoframe type 0x%02x\n", type);
699 		return;
700 	}
701 
702 	if (frame->any.type != type)
703 		drm_dbg_kms(encoder->base.dev,
704 			    "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
705 			    frame->any.type, type);
706 }
707 
708 static bool
709 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
710 				 struct intel_crtc_state *crtc_state,
711 				 struct drm_connector_state *conn_state)
712 {
713 	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
714 	const struct drm_display_mode *adjusted_mode =
715 		&crtc_state->hw.adjusted_mode;
716 	struct drm_connector *connector = conn_state->connector;
717 	int ret;
718 
719 	if (!crtc_state->has_infoframe)
720 		return true;
721 
722 	crtc_state->infoframes.enable |=
723 		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
724 
725 	ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
726 						       adjusted_mode);
727 	if (ret)
728 		return false;
729 
730 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
731 		frame->colorspace = HDMI_COLORSPACE_YUV420;
732 	else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
733 		frame->colorspace = HDMI_COLORSPACE_YUV444;
734 	else
735 		frame->colorspace = HDMI_COLORSPACE_RGB;
736 
737 	drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
738 
739 	/* nonsense combination */
740 	drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
741 		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
742 
743 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
744 		drm_hdmi_avi_infoframe_quant_range(frame, connector,
745 						   adjusted_mode,
746 						   crtc_state->limited_color_range ?
747 						   HDMI_QUANTIZATION_RANGE_LIMITED :
748 						   HDMI_QUANTIZATION_RANGE_FULL);
749 	} else {
750 		frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
751 		frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
752 	}
753 
754 	drm_hdmi_avi_infoframe_content_type(frame, conn_state);
755 
756 	/* TODO: handle pixel repetition for YCBCR420 outputs */
757 
758 	ret = hdmi_avi_infoframe_check(frame);
759 	if (drm_WARN_ON(encoder->base.dev, ret))
760 		return false;
761 
762 	return true;
763 }
764 
765 static bool
766 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
767 				 struct intel_crtc_state *crtc_state,
768 				 struct drm_connector_state *conn_state)
769 {
770 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
771 	struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
772 	int ret;
773 
774 	if (!crtc_state->has_infoframe)
775 		return true;
776 
777 	crtc_state->infoframes.enable |=
778 		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
779 
780 	if (IS_DGFX(i915))
781 		ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
782 	else
783 		ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
784 
785 	if (drm_WARN_ON(encoder->base.dev, ret))
786 		return false;
787 
788 	frame->sdi = HDMI_SPD_SDI_PC;
789 
790 	ret = hdmi_spd_infoframe_check(frame);
791 	if (drm_WARN_ON(encoder->base.dev, ret))
792 		return false;
793 
794 	return true;
795 }
796 
797 static bool
798 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
799 				  struct intel_crtc_state *crtc_state,
800 				  struct drm_connector_state *conn_state)
801 {
802 	struct hdmi_vendor_infoframe *frame =
803 		&crtc_state->infoframes.hdmi.vendor.hdmi;
804 	const struct drm_display_info *info =
805 		&conn_state->connector->display_info;
806 	int ret;
807 
808 	if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
809 		return true;
810 
811 	crtc_state->infoframes.enable |=
812 		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
813 
814 	ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
815 							  conn_state->connector,
816 							  &crtc_state->hw.adjusted_mode);
817 	if (drm_WARN_ON(encoder->base.dev, ret))
818 		return false;
819 
820 	ret = hdmi_vendor_infoframe_check(frame);
821 	if (drm_WARN_ON(encoder->base.dev, ret))
822 		return false;
823 
824 	return true;
825 }
826 
827 static bool
828 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
829 				 struct intel_crtc_state *crtc_state,
830 				 struct drm_connector_state *conn_state)
831 {
832 	struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
833 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
834 	int ret;
835 
836 	if (DISPLAY_VER(dev_priv) < 10)
837 		return true;
838 
839 	if (!crtc_state->has_infoframe)
840 		return true;
841 
842 	if (!conn_state->hdr_output_metadata)
843 		return true;
844 
845 	crtc_state->infoframes.enable |=
846 		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
847 
848 	ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
849 	if (ret < 0) {
850 		drm_dbg_kms(&dev_priv->drm,
851 			    "couldn't set HDR metadata in infoframe\n");
852 		return false;
853 	}
854 
855 	ret = hdmi_drm_infoframe_check(frame);
856 	if (drm_WARN_ON(&dev_priv->drm, ret))
857 		return false;
858 
859 	return true;
860 }
861 
862 static void g4x_set_infoframes(struct intel_encoder *encoder,
863 			       bool enable,
864 			       const struct intel_crtc_state *crtc_state,
865 			       const struct drm_connector_state *conn_state)
866 {
867 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
868 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
869 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
870 	i915_reg_t reg = VIDEO_DIP_CTL;
871 	u32 val = intel_de_read(dev_priv, reg);
872 	u32 port = VIDEO_DIP_PORT(encoder->port);
873 
874 	assert_hdmi_port_disabled(intel_hdmi);
875 
876 	/* If the registers were not initialized yet, they might be zeroes,
877 	 * which means we're selecting the AVI DIP and we're setting its
878 	 * frequency to once. This seems to really confuse the HW and make
879 	 * things stop working (the register spec says the AVI always needs to
880 	 * be sent every VSync). So here we avoid writing to the register more
881 	 * than we need and also explicitly select the AVI DIP and explicitly
882 	 * set its frequency to every VSync. Avoiding to write it twice seems to
883 	 * be enough to solve the problem, but being defensive shouldn't hurt us
884 	 * either. */
885 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
886 
887 	if (!enable) {
888 		if (!(val & VIDEO_DIP_ENABLE))
889 			return;
890 		if (port != (val & VIDEO_DIP_PORT_MASK)) {
891 			drm_dbg_kms(&dev_priv->drm,
892 				    "video DIP still enabled on port %c\n",
893 				    (val & VIDEO_DIP_PORT_MASK) >> 29);
894 			return;
895 		}
896 		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
897 			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
898 		intel_de_write(dev_priv, reg, val);
899 		intel_de_posting_read(dev_priv, reg);
900 		return;
901 	}
902 
903 	if (port != (val & VIDEO_DIP_PORT_MASK)) {
904 		if (val & VIDEO_DIP_ENABLE) {
905 			drm_dbg_kms(&dev_priv->drm,
906 				    "video DIP already enabled on port %c\n",
907 				    (val & VIDEO_DIP_PORT_MASK) >> 29);
908 			return;
909 		}
910 		val &= ~VIDEO_DIP_PORT_MASK;
911 		val |= port;
912 	}
913 
914 	val |= VIDEO_DIP_ENABLE;
915 	val &= ~(VIDEO_DIP_ENABLE_AVI |
916 		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
917 
918 	intel_de_write(dev_priv, reg, val);
919 	intel_de_posting_read(dev_priv, reg);
920 
921 	intel_write_infoframe(encoder, crtc_state,
922 			      HDMI_INFOFRAME_TYPE_AVI,
923 			      &crtc_state->infoframes.avi);
924 	intel_write_infoframe(encoder, crtc_state,
925 			      HDMI_INFOFRAME_TYPE_SPD,
926 			      &crtc_state->infoframes.spd);
927 	intel_write_infoframe(encoder, crtc_state,
928 			      HDMI_INFOFRAME_TYPE_VENDOR,
929 			      &crtc_state->infoframes.hdmi);
930 }
931 
932 /*
933  * Determine if default_phase=1 can be indicated in the GCP infoframe.
934  *
935  * From HDMI specification 1.4a:
936  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
937  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
938  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
939  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
940  *   phase of 0
941  */
942 static bool gcp_default_phase_possible(int pipe_bpp,
943 				       const struct drm_display_mode *mode)
944 {
945 	unsigned int pixels_per_group;
946 
947 	switch (pipe_bpp) {
948 	case 30:
949 		/* 4 pixels in 5 clocks */
950 		pixels_per_group = 4;
951 		break;
952 	case 36:
953 		/* 2 pixels in 3 clocks */
954 		pixels_per_group = 2;
955 		break;
956 	case 48:
957 		/* 1 pixel in 2 clocks */
958 		pixels_per_group = 1;
959 		break;
960 	default:
961 		/* phase information not relevant for 8bpc */
962 		return false;
963 	}
964 
965 	return mode->crtc_hdisplay % pixels_per_group == 0 &&
966 		mode->crtc_htotal % pixels_per_group == 0 &&
967 		mode->crtc_hblank_start % pixels_per_group == 0 &&
968 		mode->crtc_hblank_end % pixels_per_group == 0 &&
969 		mode->crtc_hsync_start % pixels_per_group == 0 &&
970 		mode->crtc_hsync_end % pixels_per_group == 0 &&
971 		((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
972 		 mode->crtc_htotal/2 % pixels_per_group == 0);
973 }
974 
975 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
976 					 const struct intel_crtc_state *crtc_state,
977 					 const struct drm_connector_state *conn_state)
978 {
979 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
980 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
981 	i915_reg_t reg;
982 
983 	if ((crtc_state->infoframes.enable &
984 	     intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
985 		return false;
986 
987 	if (HAS_DDI(dev_priv))
988 		reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
989 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
990 		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
991 	else if (HAS_PCH_SPLIT(dev_priv))
992 		reg = TVIDEO_DIP_GCP(crtc->pipe);
993 	else
994 		return false;
995 
996 	intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
997 
998 	return true;
999 }
1000 
1001 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
1002 				   struct intel_crtc_state *crtc_state)
1003 {
1004 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1005 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1006 	i915_reg_t reg;
1007 
1008 	if ((crtc_state->infoframes.enable &
1009 	     intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1010 		return;
1011 
1012 	if (HAS_DDI(dev_priv))
1013 		reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1014 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1015 		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1016 	else if (HAS_PCH_SPLIT(dev_priv))
1017 		reg = TVIDEO_DIP_GCP(crtc->pipe);
1018 	else
1019 		return;
1020 
1021 	crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1022 }
1023 
1024 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1025 					     struct intel_crtc_state *crtc_state,
1026 					     struct drm_connector_state *conn_state)
1027 {
1028 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1029 
1030 	if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1031 		return;
1032 
1033 	crtc_state->infoframes.enable |=
1034 		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1035 
1036 	/* Indicate color indication for deep color mode */
1037 	if (crtc_state->pipe_bpp > 24)
1038 		crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1039 
1040 	/* Enable default_phase whenever the display mode is suitably aligned */
1041 	if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1042 				       &crtc_state->hw.adjusted_mode))
1043 		crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1044 }
1045 
1046 static void ibx_set_infoframes(struct intel_encoder *encoder,
1047 			       bool enable,
1048 			       const struct intel_crtc_state *crtc_state,
1049 			       const struct drm_connector_state *conn_state)
1050 {
1051 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1052 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1053 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1054 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1055 	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1056 	u32 val = intel_de_read(dev_priv, reg);
1057 	u32 port = VIDEO_DIP_PORT(encoder->port);
1058 
1059 	assert_hdmi_port_disabled(intel_hdmi);
1060 
1061 	/* See the big comment in g4x_set_infoframes() */
1062 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1063 
1064 	if (!enable) {
1065 		if (!(val & VIDEO_DIP_ENABLE))
1066 			return;
1067 		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1068 			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1069 			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1070 		intel_de_write(dev_priv, reg, val);
1071 		intel_de_posting_read(dev_priv, reg);
1072 		return;
1073 	}
1074 
1075 	if (port != (val & VIDEO_DIP_PORT_MASK)) {
1076 		drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1077 			 "DIP already enabled on port %c\n",
1078 			 (val & VIDEO_DIP_PORT_MASK) >> 29);
1079 		val &= ~VIDEO_DIP_PORT_MASK;
1080 		val |= port;
1081 	}
1082 
1083 	val |= VIDEO_DIP_ENABLE;
1084 	val &= ~(VIDEO_DIP_ENABLE_AVI |
1085 		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1086 		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1087 
1088 	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1089 		val |= VIDEO_DIP_ENABLE_GCP;
1090 
1091 	intel_de_write(dev_priv, reg, val);
1092 	intel_de_posting_read(dev_priv, reg);
1093 
1094 	intel_write_infoframe(encoder, crtc_state,
1095 			      HDMI_INFOFRAME_TYPE_AVI,
1096 			      &crtc_state->infoframes.avi);
1097 	intel_write_infoframe(encoder, crtc_state,
1098 			      HDMI_INFOFRAME_TYPE_SPD,
1099 			      &crtc_state->infoframes.spd);
1100 	intel_write_infoframe(encoder, crtc_state,
1101 			      HDMI_INFOFRAME_TYPE_VENDOR,
1102 			      &crtc_state->infoframes.hdmi);
1103 }
1104 
1105 static void cpt_set_infoframes(struct intel_encoder *encoder,
1106 			       bool enable,
1107 			       const struct intel_crtc_state *crtc_state,
1108 			       const struct drm_connector_state *conn_state)
1109 {
1110 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1111 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1112 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1113 	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1114 	u32 val = intel_de_read(dev_priv, reg);
1115 
1116 	assert_hdmi_port_disabled(intel_hdmi);
1117 
1118 	/* See the big comment in g4x_set_infoframes() */
1119 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1120 
1121 	if (!enable) {
1122 		if (!(val & VIDEO_DIP_ENABLE))
1123 			return;
1124 		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1125 			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1126 			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1127 		intel_de_write(dev_priv, reg, val);
1128 		intel_de_posting_read(dev_priv, reg);
1129 		return;
1130 	}
1131 
1132 	/* Set both together, unset both together: see the spec. */
1133 	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1134 	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1135 		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1136 
1137 	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1138 		val |= VIDEO_DIP_ENABLE_GCP;
1139 
1140 	intel_de_write(dev_priv, reg, val);
1141 	intel_de_posting_read(dev_priv, reg);
1142 
1143 	intel_write_infoframe(encoder, crtc_state,
1144 			      HDMI_INFOFRAME_TYPE_AVI,
1145 			      &crtc_state->infoframes.avi);
1146 	intel_write_infoframe(encoder, crtc_state,
1147 			      HDMI_INFOFRAME_TYPE_SPD,
1148 			      &crtc_state->infoframes.spd);
1149 	intel_write_infoframe(encoder, crtc_state,
1150 			      HDMI_INFOFRAME_TYPE_VENDOR,
1151 			      &crtc_state->infoframes.hdmi);
1152 }
1153 
1154 static void vlv_set_infoframes(struct intel_encoder *encoder,
1155 			       bool enable,
1156 			       const struct intel_crtc_state *crtc_state,
1157 			       const struct drm_connector_state *conn_state)
1158 {
1159 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1160 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1161 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1162 	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1163 	u32 val = intel_de_read(dev_priv, reg);
1164 	u32 port = VIDEO_DIP_PORT(encoder->port);
1165 
1166 	assert_hdmi_port_disabled(intel_hdmi);
1167 
1168 	/* See the big comment in g4x_set_infoframes() */
1169 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1170 
1171 	if (!enable) {
1172 		if (!(val & VIDEO_DIP_ENABLE))
1173 			return;
1174 		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1175 			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1176 			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1177 		intel_de_write(dev_priv, reg, val);
1178 		intel_de_posting_read(dev_priv, reg);
1179 		return;
1180 	}
1181 
1182 	if (port != (val & VIDEO_DIP_PORT_MASK)) {
1183 		drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1184 			 "DIP already enabled on port %c\n",
1185 			 (val & VIDEO_DIP_PORT_MASK) >> 29);
1186 		val &= ~VIDEO_DIP_PORT_MASK;
1187 		val |= port;
1188 	}
1189 
1190 	val |= VIDEO_DIP_ENABLE;
1191 	val &= ~(VIDEO_DIP_ENABLE_AVI |
1192 		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1193 		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1194 
1195 	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1196 		val |= VIDEO_DIP_ENABLE_GCP;
1197 
1198 	intel_de_write(dev_priv, reg, val);
1199 	intel_de_posting_read(dev_priv, reg);
1200 
1201 	intel_write_infoframe(encoder, crtc_state,
1202 			      HDMI_INFOFRAME_TYPE_AVI,
1203 			      &crtc_state->infoframes.avi);
1204 	intel_write_infoframe(encoder, crtc_state,
1205 			      HDMI_INFOFRAME_TYPE_SPD,
1206 			      &crtc_state->infoframes.spd);
1207 	intel_write_infoframe(encoder, crtc_state,
1208 			      HDMI_INFOFRAME_TYPE_VENDOR,
1209 			      &crtc_state->infoframes.hdmi);
1210 }
1211 
1212 static void hsw_set_infoframes(struct intel_encoder *encoder,
1213 			       bool enable,
1214 			       const struct intel_crtc_state *crtc_state,
1215 			       const struct drm_connector_state *conn_state)
1216 {
1217 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1218 	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1219 	u32 val = intel_de_read(dev_priv, reg);
1220 
1221 	assert_hdmi_transcoder_func_disabled(dev_priv,
1222 					     crtc_state->cpu_transcoder);
1223 
1224 	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1225 		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1226 		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1227 		 VIDEO_DIP_ENABLE_DRM_GLK);
1228 
1229 	if (!enable) {
1230 		intel_de_write(dev_priv, reg, val);
1231 		intel_de_posting_read(dev_priv, reg);
1232 		return;
1233 	}
1234 
1235 	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1236 		val |= VIDEO_DIP_ENABLE_GCP_HSW;
1237 
1238 	intel_de_write(dev_priv, reg, val);
1239 	intel_de_posting_read(dev_priv, reg);
1240 
1241 	intel_write_infoframe(encoder, crtc_state,
1242 			      HDMI_INFOFRAME_TYPE_AVI,
1243 			      &crtc_state->infoframes.avi);
1244 	intel_write_infoframe(encoder, crtc_state,
1245 			      HDMI_INFOFRAME_TYPE_SPD,
1246 			      &crtc_state->infoframes.spd);
1247 	intel_write_infoframe(encoder, crtc_state,
1248 			      HDMI_INFOFRAME_TYPE_VENDOR,
1249 			      &crtc_state->infoframes.hdmi);
1250 	intel_write_infoframe(encoder, crtc_state,
1251 			      HDMI_INFOFRAME_TYPE_DRM,
1252 			      &crtc_state->infoframes.drm);
1253 }
1254 
1255 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1256 {
1257 	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1258 	struct i2c_adapter *adapter;
1259 
1260 	if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1261 		return;
1262 
1263 	adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1264 
1265 	drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1266 		    enable ? "Enabling" : "Disabling");
1267 
1268 	drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1269 }
1270 
1271 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1272 				unsigned int offset, void *buffer, size_t size)
1273 {
1274 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1275 	struct intel_hdmi *hdmi = &dig_port->hdmi;
1276 	struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1277 							      hdmi->ddc_bus);
1278 	int ret;
1279 	u8 start = offset & 0xff;
1280 	struct i2c_msg msgs[] = {
1281 		{
1282 			.addr = DRM_HDCP_DDC_ADDR,
1283 			.flags = 0,
1284 			.len = 1,
1285 			.buf = &start,
1286 		},
1287 		{
1288 			.addr = DRM_HDCP_DDC_ADDR,
1289 			.flags = I2C_M_RD,
1290 			.len = size,
1291 			.buf = buffer
1292 		}
1293 	};
1294 	ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1295 	if (ret == ARRAY_SIZE(msgs))
1296 		return 0;
1297 	return ret >= 0 ? -EIO : ret;
1298 }
1299 
1300 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1301 				 unsigned int offset, void *buffer, size_t size)
1302 {
1303 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1304 	struct intel_hdmi *hdmi = &dig_port->hdmi;
1305 	struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1306 							      hdmi->ddc_bus);
1307 	int ret;
1308 	u8 *write_buf;
1309 	struct i2c_msg msg;
1310 
1311 	write_buf = kzalloc(size + 1, GFP_KERNEL);
1312 	if (!write_buf)
1313 		return -ENOMEM;
1314 
1315 	write_buf[0] = offset & 0xff;
1316 	memcpy(&write_buf[1], buffer, size);
1317 
1318 	msg.addr = DRM_HDCP_DDC_ADDR;
1319 	msg.flags = 0,
1320 	msg.len = size + 1,
1321 	msg.buf = write_buf;
1322 
1323 	ret = i2c_transfer(adapter, &msg, 1);
1324 	if (ret == 1)
1325 		ret = 0;
1326 	else if (ret >= 0)
1327 		ret = -EIO;
1328 
1329 	kfree(write_buf);
1330 	return ret;
1331 }
1332 
1333 static
1334 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1335 				  u8 *an)
1336 {
1337 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1338 	struct intel_hdmi *hdmi = &dig_port->hdmi;
1339 	struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1340 							      hdmi->ddc_bus);
1341 	int ret;
1342 
1343 	ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1344 				    DRM_HDCP_AN_LEN);
1345 	if (ret) {
1346 		drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1347 			    ret);
1348 		return ret;
1349 	}
1350 
1351 	ret = intel_gmbus_output_aksv(adapter);
1352 	if (ret < 0) {
1353 		drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1354 		return ret;
1355 	}
1356 	return 0;
1357 }
1358 
1359 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1360 				     u8 *bksv)
1361 {
1362 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1363 
1364 	int ret;
1365 	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1366 				   DRM_HDCP_KSV_LEN);
1367 	if (ret)
1368 		drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1369 			    ret);
1370 	return ret;
1371 }
1372 
1373 static
1374 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1375 				 u8 *bstatus)
1376 {
1377 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1378 
1379 	int ret;
1380 	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1381 				   bstatus, DRM_HDCP_BSTATUS_LEN);
1382 	if (ret)
1383 		drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1384 			    ret);
1385 	return ret;
1386 }
1387 
1388 static
1389 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1390 				     bool *repeater_present)
1391 {
1392 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1393 	int ret;
1394 	u8 val;
1395 
1396 	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1397 	if (ret) {
1398 		drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1399 			    ret);
1400 		return ret;
1401 	}
1402 	*repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1403 	return 0;
1404 }
1405 
1406 static
1407 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1408 				  u8 *ri_prime)
1409 {
1410 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1411 
1412 	int ret;
1413 	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1414 				   ri_prime, DRM_HDCP_RI_LEN);
1415 	if (ret)
1416 		drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1417 			    ret);
1418 	return ret;
1419 }
1420 
1421 static
1422 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1423 				   bool *ksv_ready)
1424 {
1425 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1426 	int ret;
1427 	u8 val;
1428 
1429 	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1430 	if (ret) {
1431 		drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1432 			    ret);
1433 		return ret;
1434 	}
1435 	*ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1436 	return 0;
1437 }
1438 
1439 static
1440 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1441 				  int num_downstream, u8 *ksv_fifo)
1442 {
1443 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1444 	int ret;
1445 	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1446 				   ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1447 	if (ret) {
1448 		drm_dbg_kms(&i915->drm,
1449 			    "Read ksv fifo over DDC failed (%d)\n", ret);
1450 		return ret;
1451 	}
1452 	return 0;
1453 }
1454 
1455 static
1456 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1457 				      int i, u32 *part)
1458 {
1459 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1460 	int ret;
1461 
1462 	if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1463 		return -EINVAL;
1464 
1465 	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1466 				   part, DRM_HDCP_V_PRIME_PART_LEN);
1467 	if (ret)
1468 		drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1469 			    i, ret);
1470 	return ret;
1471 }
1472 
1473 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1474 					   enum transcoder cpu_transcoder)
1475 {
1476 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1477 	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1478 	struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1479 	u32 scanline;
1480 	int ret;
1481 
1482 	for (;;) {
1483 		scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1484 		if (scanline > 100 && scanline < 200)
1485 			break;
1486 		usleep_range(25, 50);
1487 	}
1488 
1489 	ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1490 					 false, TRANS_DDI_HDCP_SIGNALLING);
1491 	if (ret) {
1492 		drm_err(&dev_priv->drm,
1493 			"Disable HDCP signalling failed (%d)\n", ret);
1494 		return ret;
1495 	}
1496 
1497 	ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1498 					 true, TRANS_DDI_HDCP_SIGNALLING);
1499 	if (ret) {
1500 		drm_err(&dev_priv->drm,
1501 			"Enable HDCP signalling failed (%d)\n", ret);
1502 		return ret;
1503 	}
1504 
1505 	return 0;
1506 }
1507 
1508 static
1509 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1510 				      enum transcoder cpu_transcoder,
1511 				      bool enable)
1512 {
1513 	struct intel_hdmi *hdmi = &dig_port->hdmi;
1514 	struct intel_connector *connector = hdmi->attached_connector;
1515 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1516 	int ret;
1517 
1518 	if (!enable)
1519 		usleep_range(6, 60); /* Bspec says >= 6us */
1520 
1521 	ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1522 					 cpu_transcoder, enable,
1523 					 TRANS_DDI_HDCP_SIGNALLING);
1524 	if (ret) {
1525 		drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1526 			enable ? "Enable" : "Disable", ret);
1527 		return ret;
1528 	}
1529 
1530 	/*
1531 	 * WA: To fix incorrect positioning of the window of
1532 	 * opportunity and enc_en signalling in KABYLAKE.
1533 	 */
1534 	if (IS_KABYLAKE(dev_priv) && enable)
1535 		return kbl_repositioning_enc_en_signal(connector,
1536 						       cpu_transcoder);
1537 
1538 	return 0;
1539 }
1540 
1541 static
1542 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1543 				     struct intel_connector *connector)
1544 {
1545 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1546 	enum port port = dig_port->base.port;
1547 	enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1548 	int ret;
1549 	union {
1550 		u32 reg;
1551 		u8 shim[DRM_HDCP_RI_LEN];
1552 	} ri;
1553 
1554 	ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1555 	if (ret)
1556 		return false;
1557 
1558 	intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1559 
1560 	/* Wait for Ri prime match */
1561 	if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1562 		      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1563 		     (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1564 		drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1565 			intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1566 							port)));
1567 		return false;
1568 	}
1569 	return true;
1570 }
1571 
1572 static
1573 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1574 				struct intel_connector *connector)
1575 {
1576 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1577 	int retry;
1578 
1579 	for (retry = 0; retry < 3; retry++)
1580 		if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1581 			return true;
1582 
1583 	drm_err(&i915->drm, "Link check failed\n");
1584 	return false;
1585 }
1586 
1587 struct hdcp2_hdmi_msg_timeout {
1588 	u8 msg_id;
1589 	u16 timeout;
1590 };
1591 
1592 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1593 	{ HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1594 	{ HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1595 	{ HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1596 	{ HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1597 	{ HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1598 };
1599 
1600 static
1601 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1602 				    u8 *rx_status)
1603 {
1604 	return intel_hdmi_hdcp_read(dig_port,
1605 				    HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1606 				    rx_status,
1607 				    HDCP_2_2_HDMI_RXSTATUS_LEN);
1608 }
1609 
1610 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1611 {
1612 	int i;
1613 
1614 	if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1615 		if (is_paired)
1616 			return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1617 		else
1618 			return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1619 	}
1620 
1621 	for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1622 		if (hdcp2_msg_timeout[i].msg_id == msg_id)
1623 			return hdcp2_msg_timeout[i].timeout;
1624 	}
1625 
1626 	return -EINVAL;
1627 }
1628 
1629 static int
1630 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1631 			      u8 msg_id, bool *msg_ready,
1632 			      ssize_t *msg_sz)
1633 {
1634 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1635 	u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1636 	int ret;
1637 
1638 	ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1639 	if (ret < 0) {
1640 		drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1641 			    ret);
1642 		return ret;
1643 	}
1644 
1645 	*msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1646 		  rx_status[0]);
1647 
1648 	if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1649 		*msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1650 			     *msg_sz);
1651 	else
1652 		*msg_ready = *msg_sz;
1653 
1654 	return 0;
1655 }
1656 
1657 static ssize_t
1658 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1659 			      u8 msg_id, bool paired)
1660 {
1661 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1662 	bool msg_ready = false;
1663 	int timeout, ret;
1664 	ssize_t msg_sz = 0;
1665 
1666 	timeout = get_hdcp2_msg_timeout(msg_id, paired);
1667 	if (timeout < 0)
1668 		return timeout;
1669 
1670 	ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1671 							     msg_id, &msg_ready,
1672 							     &msg_sz),
1673 			 !ret && msg_ready && msg_sz, timeout * 1000,
1674 			 1000, 5 * 1000);
1675 	if (ret)
1676 		drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1677 			    msg_id, ret, timeout);
1678 
1679 	return ret ? ret : msg_sz;
1680 }
1681 
1682 static
1683 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1684 			       void *buf, size_t size)
1685 {
1686 	unsigned int offset;
1687 
1688 	offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1689 	return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1690 }
1691 
1692 static
1693 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1694 			      u8 msg_id, void *buf, size_t size)
1695 {
1696 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1697 	struct intel_hdmi *hdmi = &dig_port->hdmi;
1698 	struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1699 	unsigned int offset;
1700 	ssize_t ret;
1701 
1702 	ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1703 					    hdcp->is_paired);
1704 	if (ret < 0)
1705 		return ret;
1706 
1707 	/*
1708 	 * Available msg size should be equal to or lesser than the
1709 	 * available buffer.
1710 	 */
1711 	if (ret > size) {
1712 		drm_dbg_kms(&i915->drm,
1713 			    "msg_sz(%zd) is more than exp size(%zu)\n",
1714 			    ret, size);
1715 		return -EINVAL;
1716 	}
1717 
1718 	offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1719 	ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1720 	if (ret)
1721 		drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1722 			    msg_id, ret);
1723 
1724 	return ret;
1725 }
1726 
1727 static
1728 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1729 				struct intel_connector *connector)
1730 {
1731 	u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1732 	int ret;
1733 
1734 	ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1735 	if (ret)
1736 		return ret;
1737 
1738 	/*
1739 	 * Re-auth request and Link Integrity Failures are represented by
1740 	 * same bit. i.e reauth_req.
1741 	 */
1742 	if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1743 		ret = HDCP_REAUTH_REQUEST;
1744 	else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1745 		ret = HDCP_TOPOLOGY_CHANGE;
1746 
1747 	return ret;
1748 }
1749 
1750 static
1751 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1752 			     bool *capable)
1753 {
1754 	u8 hdcp2_version;
1755 	int ret;
1756 
1757 	*capable = false;
1758 	ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1759 				   &hdcp2_version, sizeof(hdcp2_version));
1760 	if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1761 		*capable = true;
1762 
1763 	return ret;
1764 }
1765 
1766 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1767 	.write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1768 	.read_bksv = intel_hdmi_hdcp_read_bksv,
1769 	.read_bstatus = intel_hdmi_hdcp_read_bstatus,
1770 	.repeater_present = intel_hdmi_hdcp_repeater_present,
1771 	.read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1772 	.read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1773 	.read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1774 	.read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1775 	.toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1776 	.check_link = intel_hdmi_hdcp_check_link,
1777 	.write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1778 	.read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1779 	.check_2_2_link	= intel_hdmi_hdcp2_check_link,
1780 	.hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1781 	.protocol = HDCP_PROTOCOL_HDMI,
1782 };
1783 
1784 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1785 {
1786 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1787 	int max_tmds_clock, vbt_max_tmds_clock;
1788 
1789 	if (DISPLAY_VER(dev_priv) >= 10)
1790 		max_tmds_clock = 594000;
1791 	else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1792 		max_tmds_clock = 300000;
1793 	else if (DISPLAY_VER(dev_priv) >= 5)
1794 		max_tmds_clock = 225000;
1795 	else
1796 		max_tmds_clock = 165000;
1797 
1798 	vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1799 	if (vbt_max_tmds_clock)
1800 		max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1801 
1802 	return max_tmds_clock;
1803 }
1804 
1805 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1806 				const struct drm_connector_state *conn_state)
1807 {
1808 	return hdmi->has_hdmi_sink &&
1809 		READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1810 }
1811 
1812 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1813 {
1814 	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1815 }
1816 
1817 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1818 				 bool respect_downstream_limits,
1819 				 bool has_hdmi_sink)
1820 {
1821 	struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1822 	int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1823 
1824 	if (respect_downstream_limits) {
1825 		struct intel_connector *connector = hdmi->attached_connector;
1826 		const struct drm_display_info *info = &connector->base.display_info;
1827 
1828 		if (hdmi->dp_dual_mode.max_tmds_clock)
1829 			max_tmds_clock = min(max_tmds_clock,
1830 					     hdmi->dp_dual_mode.max_tmds_clock);
1831 
1832 		if (info->max_tmds_clock)
1833 			max_tmds_clock = min(max_tmds_clock,
1834 					     info->max_tmds_clock);
1835 		else if (!has_hdmi_sink)
1836 			max_tmds_clock = min(max_tmds_clock, 165000);
1837 	}
1838 
1839 	return max_tmds_clock;
1840 }
1841 
1842 static enum drm_mode_status
1843 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1844 		      int clock, bool respect_downstream_limits,
1845 		      bool has_hdmi_sink)
1846 {
1847 	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1848 	enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1849 
1850 	if (clock < 25000)
1851 		return MODE_CLOCK_LOW;
1852 	if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1853 					  has_hdmi_sink))
1854 		return MODE_CLOCK_HIGH;
1855 
1856 	/* GLK DPLL can't generate 446-480 MHz */
1857 	if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1858 		return MODE_CLOCK_RANGE;
1859 
1860 	/* BXT/GLK DPLL can't generate 223-240 MHz */
1861 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1862 	    clock > 223333 && clock < 240000)
1863 		return MODE_CLOCK_RANGE;
1864 
1865 	/* CHV DPLL can't generate 216-240 MHz */
1866 	if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1867 		return MODE_CLOCK_RANGE;
1868 
1869 	/* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1870 	if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
1871 		return MODE_CLOCK_RANGE;
1872 
1873 	/* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1874 	if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
1875 		return MODE_CLOCK_RANGE;
1876 
1877 	/*
1878 	 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1879 	 * set of link rates.
1880 	 *
1881 	 * FIXME: We will hopefully get an algorithmic way of programming
1882 	 * the MPLLB for HDMI in the future.
1883 	 */
1884 	if (IS_DG2(dev_priv))
1885 		return intel_snps_phy_check_hdmi_link_rate(clock);
1886 
1887 	return MODE_OK;
1888 }
1889 
1890 int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
1891 {
1892 	/* YCBCR420 TMDS rate requirement is half the pixel clock */
1893 	if (ycbcr420_output)
1894 		clock /= 2;
1895 
1896 	/*
1897 	 * Need to adjust the port link by:
1898 	 *  1.5x for 12bpc
1899 	 *  1.25x for 10bpc
1900 	 */
1901 	return DIV_ROUND_CLOSEST(clock * bpc, 8);
1902 }
1903 
1904 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
1905 {
1906 	switch (bpc) {
1907 	case 12:
1908 		return !HAS_GMCH(i915);
1909 	case 10:
1910 		return DISPLAY_VER(i915) >= 11;
1911 	case 8:
1912 		return true;
1913 	default:
1914 		MISSING_CASE(bpc);
1915 		return false;
1916 	}
1917 }
1918 
1919 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1920 					 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1921 {
1922 	const struct drm_display_info *info = &connector->display_info;
1923 	const struct drm_hdmi_info *hdmi = &info->hdmi;
1924 
1925 	switch (bpc) {
1926 	case 12:
1927 		if (!has_hdmi_sink)
1928 			return false;
1929 
1930 		if (ycbcr420_output)
1931 			return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1932 		else
1933 			return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1934 	case 10:
1935 		if (!has_hdmi_sink)
1936 			return false;
1937 
1938 		if (ycbcr420_output)
1939 			return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1940 		else
1941 			return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1942 	case 8:
1943 		return true;
1944 	default:
1945 		MISSING_CASE(bpc);
1946 		return false;
1947 	}
1948 }
1949 
1950 static enum drm_mode_status
1951 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1952 			    bool has_hdmi_sink, bool ycbcr420_output)
1953 {
1954 	struct drm_i915_private *i915 = to_i915(connector->dev);
1955 	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1956 	enum drm_mode_status status = MODE_OK;
1957 	int bpc;
1958 
1959 	/*
1960 	 * Try all color depths since valid port clock range
1961 	 * can have holes. Any mode that can be used with at
1962 	 * least one color depth is accepted.
1963 	 */
1964 	for (bpc = 12; bpc >= 8; bpc -= 2) {
1965 		int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
1966 
1967 		if (!intel_hdmi_source_bpc_possible(i915, bpc))
1968 			continue;
1969 
1970 		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
1971 			continue;
1972 
1973 		status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
1974 		if (status == MODE_OK)
1975 			return MODE_OK;
1976 	}
1977 
1978 	/* can never happen */
1979 	drm_WARN_ON(&i915->drm, status == MODE_OK);
1980 
1981 	return status;
1982 }
1983 
1984 static enum drm_mode_status
1985 intel_hdmi_mode_valid(struct drm_connector *connector,
1986 		      struct drm_display_mode *mode)
1987 {
1988 	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1989 	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1990 	enum drm_mode_status status;
1991 	int clock = mode->clock;
1992 	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1993 	bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1994 	bool ycbcr_420_only;
1995 
1996 	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1997 		clock *= 2;
1998 
1999 	if (clock > max_dotclk)
2000 		return MODE_CLOCK_HIGH;
2001 
2002 	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2003 		if (!has_hdmi_sink)
2004 			return MODE_CLOCK_LOW;
2005 		clock *= 2;
2006 	}
2007 
2008 	/*
2009 	 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2010 	 * enumerated only if FRL is supported. Current platforms do not support
2011 	 * FRL so prune the higher resolution modes that require doctclock more
2012 	 * than 600MHz.
2013 	 */
2014 	if (clock > 600000)
2015 		return MODE_CLOCK_HIGH;
2016 
2017 	ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2018 
2019 	status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
2020 	if (status != MODE_OK) {
2021 		if (ycbcr_420_only ||
2022 		    !connector->ycbcr_420_allowed ||
2023 		    !drm_mode_is_420_also(&connector->display_info, mode))
2024 			return status;
2025 
2026 		status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
2027 		if (status != MODE_OK)
2028 			return status;
2029 	}
2030 
2031 	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2032 }
2033 
2034 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2035 			     int bpc, bool has_hdmi_sink, bool ycbcr420_output)
2036 {
2037 	struct drm_atomic_state *state = crtc_state->uapi.state;
2038 	struct drm_connector_state *connector_state;
2039 	struct drm_connector *connector;
2040 	int i;
2041 
2042 	for_each_new_connector_in_state(state, connector, connector_state, i) {
2043 		if (connector_state->crtc != crtc_state->uapi.crtc)
2044 			continue;
2045 
2046 		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
2047 			return false;
2048 	}
2049 
2050 	return true;
2051 }
2052 
2053 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2054 {
2055 	struct drm_i915_private *dev_priv =
2056 		to_i915(crtc_state->uapi.crtc->dev);
2057 	const struct drm_display_mode *adjusted_mode =
2058 		&crtc_state->hw.adjusted_mode;
2059 
2060 	if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
2061 		return false;
2062 
2063 	/* Display Wa_1405510057:icl,ehl */
2064 	if (intel_hdmi_is_ycbcr420(crtc_state) &&
2065 	    bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2066 	    (adjusted_mode->crtc_hblank_end -
2067 	     adjusted_mode->crtc_hblank_start) % 8 == 2)
2068 		return false;
2069 
2070 	return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
2071 				       intel_hdmi_is_ycbcr420(crtc_state));
2072 }
2073 
2074 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2075 				  struct intel_crtc_state *crtc_state,
2076 				  int clock, bool respect_downstream_limits)
2077 {
2078 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2079 	bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
2080 	int bpc;
2081 
2082 	/*
2083 	 * pipe_bpp could already be below 8bpc due to FDI
2084 	 * bandwidth constraints. HDMI minimum is 8bpc however.
2085 	 */
2086 	bpc = max(crtc_state->pipe_bpp / 3, 8);
2087 
2088 	/*
2089 	 * We will never exceed downstream TMDS clock limits while
2090 	 * attempting deep color. If the user insists on forcing an
2091 	 * out of spec mode they will have to be satisfied with 8bpc.
2092 	 */
2093 	if (!respect_downstream_limits)
2094 		bpc = 8;
2095 
2096 	for (; bpc >= 8; bpc -= 2) {
2097 		int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
2098 
2099 		if (hdmi_bpc_possible(crtc_state, bpc) &&
2100 		    hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2101 					  respect_downstream_limits,
2102 					  crtc_state->has_hdmi_sink) == MODE_OK)
2103 			return bpc;
2104 	}
2105 
2106 	return -EINVAL;
2107 }
2108 
2109 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2110 				    struct intel_crtc_state *crtc_state,
2111 				    bool respect_downstream_limits)
2112 {
2113 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2114 	const struct drm_display_mode *adjusted_mode =
2115 		&crtc_state->hw.adjusted_mode;
2116 	int bpc, clock = adjusted_mode->crtc_clock;
2117 
2118 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2119 		clock *= 2;
2120 
2121 	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2122 				     respect_downstream_limits);
2123 	if (bpc < 0)
2124 		return bpc;
2125 
2126 	crtc_state->port_clock =
2127 		intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
2128 
2129 	/*
2130 	 * pipe_bpp could already be below 8bpc due to
2131 	 * FDI bandwidth constraints. We shouldn't bump it
2132 	 * back up to the HDMI minimum 8bpc in that case.
2133 	 */
2134 	crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2135 
2136 	drm_dbg_kms(&i915->drm,
2137 		    "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2138 		    bpc, crtc_state->pipe_bpp);
2139 
2140 	return 0;
2141 }
2142 
2143 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2144 				    const struct drm_connector_state *conn_state)
2145 {
2146 	const struct intel_digital_connector_state *intel_conn_state =
2147 		to_intel_digital_connector_state(conn_state);
2148 	const struct drm_display_mode *adjusted_mode =
2149 		&crtc_state->hw.adjusted_mode;
2150 
2151 	/*
2152 	 * Our YCbCr output is always limited range.
2153 	 * crtc_state->limited_color_range only applies to RGB,
2154 	 * and it must never be set for YCbCr or we risk setting
2155 	 * some conflicting bits in PIPECONF which will mess up
2156 	 * the colors on the monitor.
2157 	 */
2158 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2159 		return false;
2160 
2161 	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2162 		/* See CEA-861-E - 5.1 Default Encoding Parameters */
2163 		return crtc_state->has_hdmi_sink &&
2164 			drm_default_rgb_quant_range(adjusted_mode) ==
2165 			HDMI_QUANTIZATION_RANGE_LIMITED;
2166 	} else {
2167 		return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2168 	}
2169 }
2170 
2171 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2172 				 const struct intel_crtc_state *crtc_state,
2173 				 const struct drm_connector_state *conn_state)
2174 {
2175 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2176 	const struct intel_digital_connector_state *intel_conn_state =
2177 		to_intel_digital_connector_state(conn_state);
2178 
2179 	if (!crtc_state->has_hdmi_sink)
2180 		return false;
2181 
2182 	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2183 		return intel_hdmi->has_audio;
2184 	else
2185 		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2186 }
2187 
2188 static enum intel_output_format
2189 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state,
2190 			 struct intel_connector *connector,
2191 			 bool ycbcr_420_output)
2192 {
2193 	if (!crtc_state->has_hdmi_sink)
2194 		return INTEL_OUTPUT_FORMAT_RGB;
2195 
2196 	if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2197 		return INTEL_OUTPUT_FORMAT_YCBCR420;
2198 	else
2199 		return INTEL_OUTPUT_FORMAT_RGB;
2200 }
2201 
2202 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2203 					    struct intel_crtc_state *crtc_state,
2204 					    const struct drm_connector_state *conn_state,
2205 					    bool respect_downstream_limits)
2206 {
2207 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
2208 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2209 	const struct drm_display_info *info = &connector->base.display_info;
2210 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
2211 	bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2212 	int ret;
2213 
2214 	crtc_state->output_format =
2215 		intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only);
2216 
2217 	if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
2218 		drm_dbg_kms(&i915->drm,
2219 			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2220 		crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2221 	}
2222 
2223 	ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2224 	if (ret) {
2225 		if (intel_hdmi_is_ycbcr420(crtc_state) ||
2226 		    !connector->base.ycbcr_420_allowed ||
2227 		    !drm_mode_is_420_also(info, adjusted_mode))
2228 			return ret;
2229 
2230 		crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true);
2231 		ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2232 	}
2233 
2234 	return ret;
2235 }
2236 
2237 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
2238 {
2239 	return crtc_state->uapi.encoder_mask &&
2240 		!is_power_of_2(crtc_state->uapi.encoder_mask);
2241 }
2242 
2243 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2244 			      struct intel_crtc_state *pipe_config,
2245 			      struct drm_connector_state *conn_state)
2246 {
2247 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2248 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2249 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2250 	struct drm_connector *connector = conn_state->connector;
2251 	struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2252 	int ret;
2253 
2254 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2255 		return -EINVAL;
2256 
2257 	if (!connector->interlace_allowed &&
2258 	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2259 		return -EINVAL;
2260 
2261 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2262 	pipe_config->has_hdmi_sink =
2263 		intel_has_hdmi_sink(intel_hdmi, conn_state) &&
2264 		!intel_hdmi_is_cloned(pipe_config);
2265 
2266 	if (pipe_config->has_hdmi_sink)
2267 		pipe_config->has_infoframe = true;
2268 
2269 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2270 		pipe_config->pixel_multiplier = 2;
2271 
2272 	pipe_config->has_audio =
2273 		intel_hdmi_has_audio(encoder, pipe_config, conn_state) &&
2274 		intel_audio_compute_config(encoder, pipe_config, conn_state);
2275 
2276 	/*
2277 	 * Try to respect downstream TMDS clock limits first, if
2278 	 * that fails assume the user might know something we don't.
2279 	 */
2280 	ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2281 	if (ret)
2282 		ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2283 	if (ret) {
2284 		drm_dbg_kms(&dev_priv->drm,
2285 			    "unsupported HDMI clock (%d kHz), rejecting mode\n",
2286 			    pipe_config->hw.adjusted_mode.crtc_clock);
2287 		return ret;
2288 	}
2289 
2290 	if (intel_hdmi_is_ycbcr420(pipe_config)) {
2291 		ret = intel_panel_fitting(pipe_config, conn_state);
2292 		if (ret)
2293 			return ret;
2294 	}
2295 
2296 	pipe_config->limited_color_range =
2297 		intel_hdmi_limited_color_range(pipe_config, conn_state);
2298 
2299 	if (conn_state->picture_aspect_ratio)
2300 		adjusted_mode->picture_aspect_ratio =
2301 			conn_state->picture_aspect_ratio;
2302 
2303 	pipe_config->lane_count = 4;
2304 
2305 	if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2306 		if (scdc->scrambling.low_rates)
2307 			pipe_config->hdmi_scrambling = true;
2308 
2309 		if (pipe_config->port_clock > 340000) {
2310 			pipe_config->hdmi_scrambling = true;
2311 			pipe_config->hdmi_high_tmds_clock_ratio = true;
2312 		}
2313 	}
2314 
2315 	intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2316 					 conn_state);
2317 
2318 	if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2319 		drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2320 		return -EINVAL;
2321 	}
2322 
2323 	if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2324 		drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2325 		return -EINVAL;
2326 	}
2327 
2328 	if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2329 		drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2330 		return -EINVAL;
2331 	}
2332 
2333 	if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2334 		drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2335 		return -EINVAL;
2336 	}
2337 
2338 	return 0;
2339 }
2340 
2341 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2342 {
2343 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2344 
2345 	/*
2346 	 * Give a hand to buggy BIOSen which forget to turn
2347 	 * the TMDS output buffers back on after a reboot.
2348 	 */
2349 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2350 }
2351 
2352 static void
2353 intel_hdmi_unset_edid(struct drm_connector *connector)
2354 {
2355 	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2356 
2357 	intel_hdmi->has_hdmi_sink = false;
2358 	intel_hdmi->has_audio = false;
2359 
2360 	intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2361 	intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2362 
2363 	drm_edid_free(to_intel_connector(connector)->detect_edid);
2364 	to_intel_connector(connector)->detect_edid = NULL;
2365 }
2366 
2367 static void
2368 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
2369 {
2370 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2371 	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2372 	enum port port = hdmi_to_dig_port(hdmi)->base.port;
2373 	struct i2c_adapter *adapter =
2374 		intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2375 	enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2376 
2377 	/*
2378 	 * Type 1 DVI adaptors are not required to implement any
2379 	 * registers, so we can't always detect their presence.
2380 	 * Ideally we should be able to check the state of the
2381 	 * CONFIG1 pin, but no such luck on our hardware.
2382 	 *
2383 	 * The only method left to us is to check the VBT to see
2384 	 * if the port is a dual mode capable DP port.
2385 	 */
2386 	if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2387 		if (!connector->force &&
2388 		    intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2389 			drm_dbg_kms(&dev_priv->drm,
2390 				    "Assuming DP dual mode adaptor presence based on VBT\n");
2391 			type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2392 		} else {
2393 			type = DRM_DP_DUAL_MODE_NONE;
2394 		}
2395 	}
2396 
2397 	if (type == DRM_DP_DUAL_MODE_NONE)
2398 		return;
2399 
2400 	hdmi->dp_dual_mode.type = type;
2401 	hdmi->dp_dual_mode.max_tmds_clock =
2402 		drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2403 
2404 	drm_dbg_kms(&dev_priv->drm,
2405 		    "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2406 		    drm_dp_get_dual_mode_type_name(type),
2407 		    hdmi->dp_dual_mode.max_tmds_clock);
2408 
2409 	/* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2410 	if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2411 	    !intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2412 		drm_dbg_kms(&dev_priv->drm,
2413 			    "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2414 		hdmi->dp_dual_mode.max_tmds_clock = 0;
2415 	}
2416 }
2417 
2418 static bool
2419 intel_hdmi_set_edid(struct drm_connector *connector)
2420 {
2421 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2422 	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2423 	intel_wakeref_t wakeref;
2424 	const struct drm_edid *drm_edid;
2425 	const struct edid *edid;
2426 	bool connected = false;
2427 	struct i2c_adapter *i2c;
2428 
2429 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2430 
2431 	i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2432 
2433 	drm_edid = drm_edid_read_ddc(connector, i2c);
2434 
2435 	if (!drm_edid && !intel_gmbus_is_forced_bit(i2c)) {
2436 		drm_dbg_kms(&dev_priv->drm,
2437 			    "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2438 		intel_gmbus_force_bit(i2c, true);
2439 		drm_edid = drm_edid_read_ddc(connector, i2c);
2440 		intel_gmbus_force_bit(i2c, false);
2441 	}
2442 
2443 	/* Below we depend on display info having been updated */
2444 	drm_edid_connector_update(connector, drm_edid);
2445 
2446 	to_intel_connector(connector)->detect_edid = drm_edid;
2447 
2448 	/* FIXME: Get rid of drm_edid_raw() */
2449 	edid = drm_edid_raw(drm_edid);
2450 	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2451 		intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2452 		intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2453 
2454 		intel_hdmi_dp_dual_mode_detect(connector);
2455 
2456 		connected = true;
2457 	}
2458 
2459 	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2460 
2461 	cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2462 
2463 	return connected;
2464 }
2465 
2466 static enum drm_connector_status
2467 intel_hdmi_detect(struct drm_connector *connector, bool force)
2468 {
2469 	enum drm_connector_status status = connector_status_disconnected;
2470 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2471 	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2472 	struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2473 	intel_wakeref_t wakeref;
2474 
2475 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2476 		    connector->base.id, connector->name);
2477 
2478 	if (!INTEL_DISPLAY_ENABLED(dev_priv))
2479 		return connector_status_disconnected;
2480 
2481 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2482 
2483 	if (DISPLAY_VER(dev_priv) >= 11 &&
2484 	    !intel_digital_port_connected(encoder))
2485 		goto out;
2486 
2487 	intel_hdmi_unset_edid(connector);
2488 
2489 	if (intel_hdmi_set_edid(connector))
2490 		status = connector_status_connected;
2491 
2492 out:
2493 	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2494 
2495 	if (status != connector_status_connected)
2496 		cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2497 
2498 	/*
2499 	 * Make sure the refs for power wells enabled during detect are
2500 	 * dropped to avoid a new detect cycle triggered by HPD polling.
2501 	 */
2502 	intel_display_power_flush_work(dev_priv);
2503 
2504 	return status;
2505 }
2506 
2507 static void
2508 intel_hdmi_force(struct drm_connector *connector)
2509 {
2510 	struct drm_i915_private *i915 = to_i915(connector->dev);
2511 
2512 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2513 		    connector->base.id, connector->name);
2514 
2515 	intel_hdmi_unset_edid(connector);
2516 
2517 	if (connector->status != connector_status_connected)
2518 		return;
2519 
2520 	intel_hdmi_set_edid(connector);
2521 }
2522 
2523 static int intel_hdmi_get_modes(struct drm_connector *connector)
2524 {
2525 	/* drm_edid_connector_update() done in ->detect() or ->force() */
2526 	return drm_edid_connector_add_modes(connector);
2527 }
2528 
2529 static struct i2c_adapter *
2530 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2531 {
2532 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2533 	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2534 
2535 	return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2536 }
2537 
2538 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2539 {
2540 	struct drm_i915_private *i915 = to_i915(connector->dev);
2541 	struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2542 	struct kobject *i2c_kobj = &adapter->dev.kobj;
2543 	struct kobject *connector_kobj = &connector->kdev->kobj;
2544 	int ret;
2545 
2546 	ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2547 	if (ret)
2548 		drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2549 }
2550 
2551 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2552 {
2553 	struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2554 	struct kobject *i2c_kobj = &adapter->dev.kobj;
2555 	struct kobject *connector_kobj = &connector->kdev->kobj;
2556 
2557 	sysfs_remove_link(connector_kobj, i2c_kobj->name);
2558 }
2559 
2560 static int
2561 intel_hdmi_connector_register(struct drm_connector *connector)
2562 {
2563 	int ret;
2564 
2565 	ret = intel_connector_register(connector);
2566 	if (ret)
2567 		return ret;
2568 
2569 	intel_hdmi_create_i2c_symlink(connector);
2570 
2571 	return ret;
2572 }
2573 
2574 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2575 {
2576 	struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2577 
2578 	cec_notifier_conn_unregister(n);
2579 
2580 	intel_hdmi_remove_i2c_symlink(connector);
2581 	intel_connector_unregister(connector);
2582 }
2583 
2584 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2585 	.detect = intel_hdmi_detect,
2586 	.force = intel_hdmi_force,
2587 	.fill_modes = drm_helper_probe_single_connector_modes,
2588 	.atomic_get_property = intel_digital_connector_atomic_get_property,
2589 	.atomic_set_property = intel_digital_connector_atomic_set_property,
2590 	.late_register = intel_hdmi_connector_register,
2591 	.early_unregister = intel_hdmi_connector_unregister,
2592 	.destroy = intel_connector_destroy,
2593 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2594 	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
2595 };
2596 
2597 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2598 	.get_modes = intel_hdmi_get_modes,
2599 	.mode_valid = intel_hdmi_mode_valid,
2600 	.atomic_check = intel_digital_connector_atomic_check,
2601 };
2602 
2603 static void
2604 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2605 {
2606 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2607 
2608 	intel_attach_force_audio_property(connector);
2609 	intel_attach_broadcast_rgb_property(connector);
2610 	intel_attach_aspect_ratio_property(connector);
2611 
2612 	intel_attach_hdmi_colorspace_property(connector);
2613 	drm_connector_attach_content_type_property(connector);
2614 
2615 	if (DISPLAY_VER(dev_priv) >= 10)
2616 		drm_connector_attach_hdr_output_metadata_property(connector);
2617 
2618 	if (!HAS_GMCH(dev_priv))
2619 		drm_connector_attach_max_bpc_property(connector, 8, 12);
2620 }
2621 
2622 /*
2623  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2624  * @encoder: intel_encoder
2625  * @connector: drm_connector
2626  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2627  *  or reset the high tmds clock ratio for scrambling
2628  * @scrambling: bool to Indicate if the function needs to set or reset
2629  *  sink scrambling
2630  *
2631  * This function handles scrambling on HDMI 2.0 capable sinks.
2632  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2633  * it enables scrambling. This should be called before enabling the HDMI
2634  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2635  * detect a scrambled clock within 100 ms.
2636  *
2637  * Returns:
2638  * True on success, false on failure.
2639  */
2640 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2641 				       struct drm_connector *connector,
2642 				       bool high_tmds_clock_ratio,
2643 				       bool scrambling)
2644 {
2645 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2646 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2647 	struct drm_scrambling *sink_scrambling =
2648 		&connector->display_info.hdmi.scdc.scrambling;
2649 	struct i2c_adapter *adapter =
2650 		intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2651 
2652 	if (!sink_scrambling->supported)
2653 		return true;
2654 
2655 	drm_dbg_kms(&dev_priv->drm,
2656 		    "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2657 		    connector->base.id, connector->name,
2658 		    str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2659 
2660 	/* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2661 	return drm_scdc_set_high_tmds_clock_ratio(adapter,
2662 						  high_tmds_clock_ratio) &&
2663 		drm_scdc_set_scrambling(adapter, scrambling);
2664 }
2665 
2666 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2667 {
2668 	u8 ddc_pin;
2669 
2670 	switch (port) {
2671 	case PORT_B:
2672 		ddc_pin = GMBUS_PIN_DPB;
2673 		break;
2674 	case PORT_C:
2675 		ddc_pin = GMBUS_PIN_DPC;
2676 		break;
2677 	case PORT_D:
2678 		ddc_pin = GMBUS_PIN_DPD_CHV;
2679 		break;
2680 	default:
2681 		MISSING_CASE(port);
2682 		ddc_pin = GMBUS_PIN_DPB;
2683 		break;
2684 	}
2685 	return ddc_pin;
2686 }
2687 
2688 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2689 {
2690 	u8 ddc_pin;
2691 
2692 	switch (port) {
2693 	case PORT_B:
2694 		ddc_pin = GMBUS_PIN_1_BXT;
2695 		break;
2696 	case PORT_C:
2697 		ddc_pin = GMBUS_PIN_2_BXT;
2698 		break;
2699 	default:
2700 		MISSING_CASE(port);
2701 		ddc_pin = GMBUS_PIN_1_BXT;
2702 		break;
2703 	}
2704 	return ddc_pin;
2705 }
2706 
2707 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2708 			      enum port port)
2709 {
2710 	u8 ddc_pin;
2711 
2712 	switch (port) {
2713 	case PORT_B:
2714 		ddc_pin = GMBUS_PIN_1_BXT;
2715 		break;
2716 	case PORT_C:
2717 		ddc_pin = GMBUS_PIN_2_BXT;
2718 		break;
2719 	case PORT_D:
2720 		ddc_pin = GMBUS_PIN_4_CNP;
2721 		break;
2722 	case PORT_F:
2723 		ddc_pin = GMBUS_PIN_3_BXT;
2724 		break;
2725 	default:
2726 		MISSING_CASE(port);
2727 		ddc_pin = GMBUS_PIN_1_BXT;
2728 		break;
2729 	}
2730 	return ddc_pin;
2731 }
2732 
2733 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2734 {
2735 	enum phy phy = intel_port_to_phy(dev_priv, port);
2736 
2737 	if (intel_phy_is_combo(dev_priv, phy))
2738 		return GMBUS_PIN_1_BXT + port;
2739 	else if (intel_phy_is_tc(dev_priv, phy))
2740 		return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2741 
2742 	drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2743 	return GMBUS_PIN_2_BXT;
2744 }
2745 
2746 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2747 {
2748 	enum phy phy = intel_port_to_phy(dev_priv, port);
2749 	u8 ddc_pin;
2750 
2751 	switch (phy) {
2752 	case PHY_A:
2753 		ddc_pin = GMBUS_PIN_1_BXT;
2754 		break;
2755 	case PHY_B:
2756 		ddc_pin = GMBUS_PIN_2_BXT;
2757 		break;
2758 	case PHY_C:
2759 		ddc_pin = GMBUS_PIN_9_TC1_ICP;
2760 		break;
2761 	default:
2762 		MISSING_CASE(phy);
2763 		ddc_pin = GMBUS_PIN_1_BXT;
2764 		break;
2765 	}
2766 	return ddc_pin;
2767 }
2768 
2769 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2770 {
2771 	enum phy phy = intel_port_to_phy(dev_priv, port);
2772 
2773 	WARN_ON(port == PORT_C);
2774 
2775 	/*
2776 	 * Pin mapping for RKL depends on which PCH is present.  With TGP, the
2777 	 * final two outputs use type-c pins, even though they're actually
2778 	 * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2779 	 * all outputs.
2780 	 */
2781 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2782 		return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2783 
2784 	return GMBUS_PIN_1_BXT + phy;
2785 }
2786 
2787 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2788 {
2789 	enum phy phy = intel_port_to_phy(i915, port);
2790 
2791 	drm_WARN_ON(&i915->drm, port == PORT_A);
2792 
2793 	/*
2794 	 * Pin mapping for GEN9 BC depends on which PCH is present.  With TGP,
2795 	 * final two outputs use type-c pins, even though they're actually
2796 	 * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2797 	 * all outputs.
2798 	 */
2799 	if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2800 		return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2801 
2802 	return GMBUS_PIN_1_BXT + phy;
2803 }
2804 
2805 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2806 {
2807 	return intel_port_to_phy(dev_priv, port) + 1;
2808 }
2809 
2810 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2811 {
2812 	enum phy phy = intel_port_to_phy(dev_priv, port);
2813 
2814 	WARN_ON(port == PORT_B || port == PORT_C);
2815 
2816 	/*
2817 	 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2818 	 * except first combo output.
2819 	 */
2820 	if (phy == PHY_A)
2821 		return GMBUS_PIN_1_BXT;
2822 
2823 	return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2824 }
2825 
2826 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2827 			      enum port port)
2828 {
2829 	u8 ddc_pin;
2830 
2831 	switch (port) {
2832 	case PORT_B:
2833 		ddc_pin = GMBUS_PIN_DPB;
2834 		break;
2835 	case PORT_C:
2836 		ddc_pin = GMBUS_PIN_DPC;
2837 		break;
2838 	case PORT_D:
2839 		ddc_pin = GMBUS_PIN_DPD;
2840 		break;
2841 	default:
2842 		MISSING_CASE(port);
2843 		ddc_pin = GMBUS_PIN_DPB;
2844 		break;
2845 	}
2846 	return ddc_pin;
2847 }
2848 
2849 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2850 {
2851 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2852 	enum port port = encoder->port;
2853 	u8 ddc_pin;
2854 
2855 	ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2856 	if (ddc_pin) {
2857 		drm_dbg_kms(&dev_priv->drm,
2858 			    "Using DDC pin 0x%x for port %c (VBT)\n",
2859 			    ddc_pin, port_name(port));
2860 		return ddc_pin;
2861 	}
2862 
2863 	if (IS_ALDERLAKE_S(dev_priv))
2864 		ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2865 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2866 		ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2867 	else if (IS_ROCKETLAKE(dev_priv))
2868 		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2869 	else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2870 		ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2871 	else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
2872 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2873 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2874 		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2875 	else if (HAS_PCH_CNP(dev_priv))
2876 		ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2877 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2878 		ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2879 	else if (IS_CHERRYVIEW(dev_priv))
2880 		ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2881 	else
2882 		ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2883 
2884 	drm_dbg_kms(&dev_priv->drm,
2885 		    "Using DDC pin 0x%x for port %c (platform default)\n",
2886 		    ddc_pin, port_name(port));
2887 
2888 	return ddc_pin;
2889 }
2890 
2891 void intel_infoframe_init(struct intel_digital_port *dig_port)
2892 {
2893 	struct drm_i915_private *dev_priv =
2894 		to_i915(dig_port->base.base.dev);
2895 
2896 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2897 		dig_port->write_infoframe = vlv_write_infoframe;
2898 		dig_port->read_infoframe = vlv_read_infoframe;
2899 		dig_port->set_infoframes = vlv_set_infoframes;
2900 		dig_port->infoframes_enabled = vlv_infoframes_enabled;
2901 	} else if (IS_G4X(dev_priv)) {
2902 		dig_port->write_infoframe = g4x_write_infoframe;
2903 		dig_port->read_infoframe = g4x_read_infoframe;
2904 		dig_port->set_infoframes = g4x_set_infoframes;
2905 		dig_port->infoframes_enabled = g4x_infoframes_enabled;
2906 	} else if (HAS_DDI(dev_priv)) {
2907 		if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2908 			dig_port->write_infoframe = lspcon_write_infoframe;
2909 			dig_port->read_infoframe = lspcon_read_infoframe;
2910 			dig_port->set_infoframes = lspcon_set_infoframes;
2911 			dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2912 		} else {
2913 			dig_port->write_infoframe = hsw_write_infoframe;
2914 			dig_port->read_infoframe = hsw_read_infoframe;
2915 			dig_port->set_infoframes = hsw_set_infoframes;
2916 			dig_port->infoframes_enabled = hsw_infoframes_enabled;
2917 		}
2918 	} else if (HAS_PCH_IBX(dev_priv)) {
2919 		dig_port->write_infoframe = ibx_write_infoframe;
2920 		dig_port->read_infoframe = ibx_read_infoframe;
2921 		dig_port->set_infoframes = ibx_set_infoframes;
2922 		dig_port->infoframes_enabled = ibx_infoframes_enabled;
2923 	} else {
2924 		dig_port->write_infoframe = cpt_write_infoframe;
2925 		dig_port->read_infoframe = cpt_read_infoframe;
2926 		dig_port->set_infoframes = cpt_set_infoframes;
2927 		dig_port->infoframes_enabled = cpt_infoframes_enabled;
2928 	}
2929 }
2930 
2931 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2932 			       struct intel_connector *intel_connector)
2933 {
2934 	struct drm_connector *connector = &intel_connector->base;
2935 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2936 	struct intel_encoder *intel_encoder = &dig_port->base;
2937 	struct drm_device *dev = intel_encoder->base.dev;
2938 	struct drm_i915_private *dev_priv = to_i915(dev);
2939 	struct i2c_adapter *ddc;
2940 	enum port port = intel_encoder->port;
2941 	struct cec_connector_info conn_info;
2942 
2943 	drm_dbg_kms(&dev_priv->drm,
2944 		    "Adding HDMI connector on [ENCODER:%d:%s]\n",
2945 		    intel_encoder->base.base.id, intel_encoder->base.name);
2946 
2947 	if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2948 		return;
2949 
2950 	if (drm_WARN(dev, dig_port->max_lanes < 4,
2951 		     "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2952 		     dig_port->max_lanes, intel_encoder->base.base.id,
2953 		     intel_encoder->base.name))
2954 		return;
2955 
2956 	intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2957 	ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2958 
2959 	drm_connector_init_with_ddc(dev, connector,
2960 				    &intel_hdmi_connector_funcs,
2961 				    DRM_MODE_CONNECTOR_HDMIA,
2962 				    ddc);
2963 	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2964 
2965 	if (DISPLAY_VER(dev_priv) < 12)
2966 		connector->interlace_allowed = true;
2967 
2968 	connector->stereo_allowed = true;
2969 
2970 	if (DISPLAY_VER(dev_priv) >= 10)
2971 		connector->ycbcr_420_allowed = true;
2972 
2973 	intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2974 
2975 	if (HAS_DDI(dev_priv))
2976 		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2977 	else
2978 		intel_connector->get_hw_state = intel_connector_get_hw_state;
2979 
2980 	intel_hdmi_add_properties(intel_hdmi, connector);
2981 
2982 	intel_connector_attach_encoder(intel_connector, intel_encoder);
2983 	intel_hdmi->attached_connector = intel_connector;
2984 
2985 	if (is_hdcp_supported(dev_priv, port)) {
2986 		int ret = intel_hdcp_init(intel_connector, dig_port,
2987 					  &intel_hdmi_hdcp_shim);
2988 		if (ret)
2989 			drm_dbg_kms(&dev_priv->drm,
2990 				    "HDCP init failed, skipping.\n");
2991 	}
2992 
2993 	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2994 	 * 0xd.  Failure to do so will result in spurious interrupts being
2995 	 * generated on the port when a cable is not attached.
2996 	 */
2997 	if (IS_G45(dev_priv)) {
2998 		u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2999 		intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
3000 		               (temp & ~0xf) | 0xd);
3001 	}
3002 
3003 	cec_fill_conn_info_from_drm(&conn_info, connector);
3004 
3005 	intel_hdmi->cec_notifier =
3006 		cec_notifier_conn_register(dev->dev, port_identifier(port),
3007 					   &conn_info);
3008 	if (!intel_hdmi->cec_notifier)
3009 		drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
3010 }
3011 
3012 /*
3013  * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3014  * @vactive: Vactive of a display mode
3015  *
3016  * @return: appropriate dsc slice height for a given mode.
3017  */
3018 int intel_hdmi_dsc_get_slice_height(int vactive)
3019 {
3020 	int slice_height;
3021 
3022 	/*
3023 	 * Slice Height determination : HDMI2.1 Section 7.7.5.2
3024 	 * Select smallest slice height >=96, that results in a valid PPS and
3025 	 * requires minimum padding lines required for final slice.
3026 	 *
3027 	 * Assumption : Vactive is even.
3028 	 */
3029 	for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3030 		if (vactive % slice_height == 0)
3031 			return slice_height;
3032 
3033 	return 0;
3034 }
3035 
3036 /*
3037  * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3038  * and dsc decoder capabilities
3039  *
3040  * @crtc_state: intel crtc_state
3041  * @src_max_slices: maximum slices supported by the DSC encoder
3042  * @src_max_slice_width: maximum slice width supported by DSC encoder
3043  * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3044  * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3045  *
3046  * @return: num of dsc slices that can be supported by the dsc encoder
3047  * and decoder.
3048  */
3049 int
3050 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3051 			      int src_max_slices, int src_max_slice_width,
3052 			      int hdmi_max_slices, int hdmi_throughput)
3053 {
3054 /* Pixel rates in KPixels/sec */
3055 #define HDMI_DSC_PEAK_PIXEL_RATE		2720000
3056 /*
3057  * Rates at which the source and sink are required to process pixels in each
3058  * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3059  */
3060 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0		340000
3061 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1		400000
3062 
3063 /* Spec limits the slice width to 2720 pixels */
3064 #define MAX_HDMI_SLICE_WIDTH			2720
3065 	int kslice_adjust;
3066 	int adjusted_clk_khz;
3067 	int min_slices;
3068 	int target_slices;
3069 	int max_throughput; /* max clock freq. in khz per slice */
3070 	int max_slice_width;
3071 	int slice_width;
3072 	int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3073 
3074 	if (!hdmi_throughput)
3075 		return 0;
3076 
3077 	/*
3078 	 * Slice Width determination : HDMI2.1 Section 7.7.5.1
3079 	 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3080 	 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3081 	 * dividing adjusted clock value by 10.
3082 	 */
3083 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3084 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3085 		kslice_adjust = 10;
3086 	else
3087 		kslice_adjust = 5;
3088 
3089 	/*
3090 	 * As per spec, the rate at which the source and the sink process
3091 	 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3092 	 * This depends upon the pixel clock rate and output formats
3093 	 * (kslice adjust).
3094 	 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3095 	 * at max 340MHz, otherwise they can be processed at max 400MHz.
3096 	 */
3097 
3098 	adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3099 
3100 	if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3101 		max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3102 	else
3103 		max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3104 
3105 	/*
3106 	 * Taking into account the sink's capability for maximum
3107 	 * clock per slice (in MHz) as read from HF-VSDB.
3108 	 */
3109 	max_throughput = min(max_throughput, hdmi_throughput * 1000);
3110 
3111 	min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3112 	max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3113 
3114 	/*
3115 	 * Keep on increasing the num of slices/line, starting from min_slices
3116 	 * per line till we get such a number, for which the slice_width is
3117 	 * just less than max_slice_width. The slices/line selected should be
3118 	 * less than or equal to the max horizontal slices that the combination
3119 	 * of PCON encoder and HDMI decoder can support.
3120 	 */
3121 	slice_width = max_slice_width;
3122 
3123 	do {
3124 		if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3125 			target_slices = 1;
3126 		else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3127 			target_slices = 2;
3128 		else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3129 			target_slices = 4;
3130 		else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3131 			target_slices = 8;
3132 		else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3133 			target_slices = 12;
3134 		else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3135 			target_slices = 16;
3136 		else
3137 			return 0;
3138 
3139 		slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3140 		if (slice_width >= max_slice_width)
3141 			min_slices = target_slices + 1;
3142 	} while (slice_width >= max_slice_width);
3143 
3144 	return target_slices;
3145 }
3146 
3147 /*
3148  * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3149  * source and sink capabilities.
3150  *
3151  * @src_fraction_bpp: fractional bpp supported by the source
3152  * @slice_width: dsc slice width supported by the source and sink
3153  * @num_slices: num of slices supported by the source and sink
3154  * @output_format: video output format
3155  * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3156  * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3157  *
3158  * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3159  */
3160 int
3161 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3162 		       int output_format, bool hdmi_all_bpp,
3163 		       int hdmi_max_chunk_bytes)
3164 {
3165 	int max_dsc_bpp, min_dsc_bpp;
3166 	int target_bytes;
3167 	bool bpp_found = false;
3168 	int bpp_decrement_x16;
3169 	int bpp_target;
3170 	int bpp_target_x16;
3171 
3172 	/*
3173 	 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3174 	 * Start with the max bpp and keep on decrementing with
3175 	 * fractional bpp, if supported by PCON DSC encoder
3176 	 *
3177 	 * for each bpp we check if no of bytes can be supported by HDMI sink
3178 	 */
3179 
3180 	/* Assuming: bpc as 8*/
3181 	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3182 		min_dsc_bpp = 6;
3183 		max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3184 	} else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3185 		   output_format == INTEL_OUTPUT_FORMAT_RGB) {
3186 		min_dsc_bpp = 8;
3187 		max_dsc_bpp = 3 * 8; /* 3*bpc */
3188 	} else {
3189 		/* Assuming 4:2:2 encoding */
3190 		min_dsc_bpp = 7;
3191 		max_dsc_bpp = 2 * 8; /* 2*bpc */
3192 	}
3193 
3194 	/*
3195 	 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3196 	 * Section 7.7.34 : Source shall not enable compressed Video
3197 	 * Transport with bpp_target settings above 12 bpp unless
3198 	 * DSC_all_bpp is set to 1.
3199 	 */
3200 	if (!hdmi_all_bpp)
3201 		max_dsc_bpp = min(max_dsc_bpp, 12);
3202 
3203 	/*
3204 	 * The Sink has a limit of compressed data in bytes for a scanline,
3205 	 * as described in max_chunk_bytes field in HFVSDB block of edid.
3206 	 * The no. of bytes depend on the target bits per pixel that the
3207 	 * source configures. So we start with the max_bpp and calculate
3208 	 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3209 	 * till we get the target_chunk_bytes just less than what the sink's
3210 	 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3211 	 *
3212 	 * The decrement is according to the fractional support from PCON DSC
3213 	 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3214 	 *
3215 	 * bpp_target_x16 = bpp_target * 16
3216 	 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3217 	 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3218 	 */
3219 
3220 	bpp_target = max_dsc_bpp;
3221 
3222 	/* src does not support fractional bpp implies decrement by 16 for bppx16 */
3223 	if (!src_fractional_bpp)
3224 		src_fractional_bpp = 1;
3225 	bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3226 	bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3227 
3228 	while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3229 		int bpp;
3230 
3231 		bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3232 		target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3233 		if (target_bytes <= hdmi_max_chunk_bytes) {
3234 			bpp_found = true;
3235 			break;
3236 		}
3237 		bpp_target_x16 -= bpp_decrement_x16;
3238 	}
3239 	if (bpp_found)
3240 		return bpp_target_x16;
3241 
3242 	return 0;
3243 }
3244