1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_hdcp.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <drm/intel_lpe_audio.h> 40 41 #include "i915_debugfs.h" 42 #include "i915_drv.h" 43 #include "intel_atomic.h" 44 #include "intel_connector.h" 45 #include "intel_ddi.h" 46 #include "intel_de.h" 47 #include "intel_display_types.h" 48 #include "intel_dp.h" 49 #include "intel_gmbus.h" 50 #include "intel_hdcp.h" 51 #include "intel_hdmi.h" 52 #include "intel_lspcon.h" 53 #include "intel_panel.h" 54 #include "intel_snps_phy.h" 55 56 static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi) 57 { 58 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev); 59 } 60 61 static void 62 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 63 { 64 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi); 65 u32 enabled_bits; 66 67 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 68 69 drm_WARN(&dev_priv->drm, 70 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 71 "HDMI port enabled, expecting disabled\n"); 72 } 73 74 static void 75 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 76 enum transcoder cpu_transcoder) 77 { 78 drm_WARN(&dev_priv->drm, 79 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 80 TRANS_DDI_FUNC_ENABLE, 81 "HDMI transcoder function enabled, expecting disabled\n"); 82 } 83 84 static u32 g4x_infoframe_index(unsigned int type) 85 { 86 switch (type) { 87 case HDMI_PACKET_TYPE_GAMUT_METADATA: 88 return VIDEO_DIP_SELECT_GAMUT; 89 case HDMI_INFOFRAME_TYPE_AVI: 90 return VIDEO_DIP_SELECT_AVI; 91 case HDMI_INFOFRAME_TYPE_SPD: 92 return VIDEO_DIP_SELECT_SPD; 93 case HDMI_INFOFRAME_TYPE_VENDOR: 94 return VIDEO_DIP_SELECT_VENDOR; 95 default: 96 MISSING_CASE(type); 97 return 0; 98 } 99 } 100 101 static u32 g4x_infoframe_enable(unsigned int type) 102 { 103 switch (type) { 104 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 105 return VIDEO_DIP_ENABLE_GCP; 106 case HDMI_PACKET_TYPE_GAMUT_METADATA: 107 return VIDEO_DIP_ENABLE_GAMUT; 108 case DP_SDP_VSC: 109 return 0; 110 case HDMI_INFOFRAME_TYPE_AVI: 111 return VIDEO_DIP_ENABLE_AVI; 112 case HDMI_INFOFRAME_TYPE_SPD: 113 return VIDEO_DIP_ENABLE_SPD; 114 case HDMI_INFOFRAME_TYPE_VENDOR: 115 return VIDEO_DIP_ENABLE_VENDOR; 116 case HDMI_INFOFRAME_TYPE_DRM: 117 return 0; 118 default: 119 MISSING_CASE(type); 120 return 0; 121 } 122 } 123 124 static u32 hsw_infoframe_enable(unsigned int type) 125 { 126 switch (type) { 127 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 128 return VIDEO_DIP_ENABLE_GCP_HSW; 129 case HDMI_PACKET_TYPE_GAMUT_METADATA: 130 return VIDEO_DIP_ENABLE_GMP_HSW; 131 case DP_SDP_VSC: 132 return VIDEO_DIP_ENABLE_VSC_HSW; 133 case DP_SDP_PPS: 134 return VDIP_ENABLE_PPS; 135 case HDMI_INFOFRAME_TYPE_AVI: 136 return VIDEO_DIP_ENABLE_AVI_HSW; 137 case HDMI_INFOFRAME_TYPE_SPD: 138 return VIDEO_DIP_ENABLE_SPD_HSW; 139 case HDMI_INFOFRAME_TYPE_VENDOR: 140 return VIDEO_DIP_ENABLE_VS_HSW; 141 case HDMI_INFOFRAME_TYPE_DRM: 142 return VIDEO_DIP_ENABLE_DRM_GLK; 143 default: 144 MISSING_CASE(type); 145 return 0; 146 } 147 } 148 149 static i915_reg_t 150 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 151 enum transcoder cpu_transcoder, 152 unsigned int type, 153 int i) 154 { 155 switch (type) { 156 case HDMI_PACKET_TYPE_GAMUT_METADATA: 157 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 158 case DP_SDP_VSC: 159 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 160 case DP_SDP_PPS: 161 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 162 case HDMI_INFOFRAME_TYPE_AVI: 163 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 164 case HDMI_INFOFRAME_TYPE_SPD: 165 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 166 case HDMI_INFOFRAME_TYPE_VENDOR: 167 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 168 case HDMI_INFOFRAME_TYPE_DRM: 169 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 170 default: 171 MISSING_CASE(type); 172 return INVALID_MMIO_REG; 173 } 174 } 175 176 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 177 unsigned int type) 178 { 179 switch (type) { 180 case DP_SDP_VSC: 181 return VIDEO_DIP_VSC_DATA_SIZE; 182 case DP_SDP_PPS: 183 return VIDEO_DIP_PPS_DATA_SIZE; 184 case HDMI_PACKET_TYPE_GAMUT_METADATA: 185 if (DISPLAY_VER(dev_priv) >= 11) 186 return VIDEO_DIP_GMP_DATA_SIZE; 187 else 188 return VIDEO_DIP_DATA_SIZE; 189 default: 190 return VIDEO_DIP_DATA_SIZE; 191 } 192 } 193 194 static void g4x_write_infoframe(struct intel_encoder *encoder, 195 const struct intel_crtc_state *crtc_state, 196 unsigned int type, 197 const void *frame, ssize_t len) 198 { 199 const u32 *data = frame; 200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 201 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 202 int i; 203 204 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 205 "Writing DIP with CTL reg disabled\n"); 206 207 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 208 val |= g4x_infoframe_index(type); 209 210 val &= ~g4x_infoframe_enable(type); 211 212 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 213 214 for (i = 0; i < len; i += 4) { 215 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 216 data++; 217 } 218 /* Write every possible data byte to force correct ECC calculation. */ 219 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 220 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 221 222 val |= g4x_infoframe_enable(type); 223 val &= ~VIDEO_DIP_FREQ_MASK; 224 val |= VIDEO_DIP_FREQ_VSYNC; 225 226 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 227 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 228 } 229 230 static void g4x_read_infoframe(struct intel_encoder *encoder, 231 const struct intel_crtc_state *crtc_state, 232 unsigned int type, 233 void *frame, ssize_t len) 234 { 235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 236 u32 val, *data = frame; 237 int i; 238 239 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 240 241 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 242 val |= g4x_infoframe_index(type); 243 244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 245 246 for (i = 0; i < len; i += 4) 247 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 248 } 249 250 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 251 const struct intel_crtc_state *pipe_config) 252 { 253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 254 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 255 256 if ((val & VIDEO_DIP_ENABLE) == 0) 257 return 0; 258 259 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 260 return 0; 261 262 return val & (VIDEO_DIP_ENABLE_AVI | 263 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 264 } 265 266 static void ibx_write_infoframe(struct intel_encoder *encoder, 267 const struct intel_crtc_state *crtc_state, 268 unsigned int type, 269 const void *frame, ssize_t len) 270 { 271 const u32 *data = frame; 272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 274 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 275 u32 val = intel_de_read(dev_priv, reg); 276 int i; 277 278 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 279 "Writing DIP with CTL reg disabled\n"); 280 281 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 282 val |= g4x_infoframe_index(type); 283 284 val &= ~g4x_infoframe_enable(type); 285 286 intel_de_write(dev_priv, reg, val); 287 288 for (i = 0; i < len; i += 4) { 289 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 290 *data); 291 data++; 292 } 293 /* Write every possible data byte to force correct ECC calculation. */ 294 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 295 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 296 297 val |= g4x_infoframe_enable(type); 298 val &= ~VIDEO_DIP_FREQ_MASK; 299 val |= VIDEO_DIP_FREQ_VSYNC; 300 301 intel_de_write(dev_priv, reg, val); 302 intel_de_posting_read(dev_priv, reg); 303 } 304 305 static void ibx_read_infoframe(struct intel_encoder *encoder, 306 const struct intel_crtc_state *crtc_state, 307 unsigned int type, 308 void *frame, ssize_t len) 309 { 310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 311 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 312 u32 val, *data = frame; 313 int i; 314 315 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 316 317 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 318 val |= g4x_infoframe_index(type); 319 320 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 321 322 for (i = 0; i < len; i += 4) 323 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 324 } 325 326 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 327 const struct intel_crtc_state *pipe_config) 328 { 329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 330 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 331 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 332 u32 val = intel_de_read(dev_priv, reg); 333 334 if ((val & VIDEO_DIP_ENABLE) == 0) 335 return 0; 336 337 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 338 return 0; 339 340 return val & (VIDEO_DIP_ENABLE_AVI | 341 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 342 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 343 } 344 345 static void cpt_write_infoframe(struct intel_encoder *encoder, 346 const struct intel_crtc_state *crtc_state, 347 unsigned int type, 348 const void *frame, ssize_t len) 349 { 350 const u32 *data = frame; 351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 352 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 353 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 354 u32 val = intel_de_read(dev_priv, reg); 355 int i; 356 357 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 358 "Writing DIP with CTL reg disabled\n"); 359 360 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 361 val |= g4x_infoframe_index(type); 362 363 /* The DIP control register spec says that we need to update the AVI 364 * infoframe without clearing its enable bit */ 365 if (type != HDMI_INFOFRAME_TYPE_AVI) 366 val &= ~g4x_infoframe_enable(type); 367 368 intel_de_write(dev_priv, reg, val); 369 370 for (i = 0; i < len; i += 4) { 371 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 372 *data); 373 data++; 374 } 375 /* Write every possible data byte to force correct ECC calculation. */ 376 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 377 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 378 379 val |= g4x_infoframe_enable(type); 380 val &= ~VIDEO_DIP_FREQ_MASK; 381 val |= VIDEO_DIP_FREQ_VSYNC; 382 383 intel_de_write(dev_priv, reg, val); 384 intel_de_posting_read(dev_priv, reg); 385 } 386 387 static void cpt_read_infoframe(struct intel_encoder *encoder, 388 const struct intel_crtc_state *crtc_state, 389 unsigned int type, 390 void *frame, ssize_t len) 391 { 392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 394 u32 val, *data = frame; 395 int i; 396 397 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 398 399 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 400 val |= g4x_infoframe_index(type); 401 402 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 403 404 for (i = 0; i < len; i += 4) 405 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 406 } 407 408 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 409 const struct intel_crtc_state *pipe_config) 410 { 411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 412 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 413 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 414 415 if ((val & VIDEO_DIP_ENABLE) == 0) 416 return 0; 417 418 return val & (VIDEO_DIP_ENABLE_AVI | 419 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 420 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 421 } 422 423 static void vlv_write_infoframe(struct intel_encoder *encoder, 424 const struct intel_crtc_state *crtc_state, 425 unsigned int type, 426 const void *frame, ssize_t len) 427 { 428 const u32 *data = frame; 429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 430 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 431 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 432 u32 val = intel_de_read(dev_priv, reg); 433 int i; 434 435 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 436 "Writing DIP with CTL reg disabled\n"); 437 438 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 439 val |= g4x_infoframe_index(type); 440 441 val &= ~g4x_infoframe_enable(type); 442 443 intel_de_write(dev_priv, reg, val); 444 445 for (i = 0; i < len; i += 4) { 446 intel_de_write(dev_priv, 447 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 448 data++; 449 } 450 /* Write every possible data byte to force correct ECC calculation. */ 451 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 452 intel_de_write(dev_priv, 453 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 454 455 val |= g4x_infoframe_enable(type); 456 val &= ~VIDEO_DIP_FREQ_MASK; 457 val |= VIDEO_DIP_FREQ_VSYNC; 458 459 intel_de_write(dev_priv, reg, val); 460 intel_de_posting_read(dev_priv, reg); 461 } 462 463 static void vlv_read_infoframe(struct intel_encoder *encoder, 464 const struct intel_crtc_state *crtc_state, 465 unsigned int type, 466 void *frame, ssize_t len) 467 { 468 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 469 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 470 u32 val, *data = frame; 471 int i; 472 473 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); 474 475 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 476 val |= g4x_infoframe_index(type); 477 478 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 479 480 for (i = 0; i < len; i += 4) 481 *data++ = intel_de_read(dev_priv, 482 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 483 } 484 485 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 486 const struct intel_crtc_state *pipe_config) 487 { 488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 489 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 490 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 491 492 if ((val & VIDEO_DIP_ENABLE) == 0) 493 return 0; 494 495 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 496 return 0; 497 498 return val & (VIDEO_DIP_ENABLE_AVI | 499 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 500 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 501 } 502 503 void hsw_write_infoframe(struct intel_encoder *encoder, 504 const struct intel_crtc_state *crtc_state, 505 unsigned int type, 506 const void *frame, ssize_t len) 507 { 508 const u32 *data = frame; 509 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 511 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 512 int data_size; 513 int i; 514 u32 val = intel_de_read(dev_priv, ctl_reg); 515 516 data_size = hsw_dip_data_size(dev_priv, type); 517 518 drm_WARN_ON(&dev_priv->drm, len > data_size); 519 520 val &= ~hsw_infoframe_enable(type); 521 intel_de_write(dev_priv, ctl_reg, val); 522 523 for (i = 0; i < len; i += 4) { 524 intel_de_write(dev_priv, 525 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 526 *data); 527 data++; 528 } 529 /* Write every possible data byte to force correct ECC calculation. */ 530 for (; i < data_size; i += 4) 531 intel_de_write(dev_priv, 532 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 533 0); 534 535 /* Wa_14013475917 */ 536 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr && 537 type == DP_SDP_VSC) 538 return; 539 540 val |= hsw_infoframe_enable(type); 541 intel_de_write(dev_priv, ctl_reg, val); 542 intel_de_posting_read(dev_priv, ctl_reg); 543 } 544 545 void hsw_read_infoframe(struct intel_encoder *encoder, 546 const struct intel_crtc_state *crtc_state, 547 unsigned int type, void *frame, ssize_t len) 548 { 549 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 551 u32 *data = frame; 552 int i; 553 554 for (i = 0; i < len; i += 4) 555 *data++ = intel_de_read(dev_priv, 556 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 557 } 558 559 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 560 const struct intel_crtc_state *pipe_config) 561 { 562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 563 u32 val = intel_de_read(dev_priv, 564 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 565 u32 mask; 566 567 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 568 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 569 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 570 571 if (DISPLAY_VER(dev_priv) >= 10) 572 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 573 574 return val & mask; 575 } 576 577 static const u8 infoframe_type_to_idx[] = { 578 HDMI_PACKET_TYPE_GENERAL_CONTROL, 579 HDMI_PACKET_TYPE_GAMUT_METADATA, 580 DP_SDP_VSC, 581 HDMI_INFOFRAME_TYPE_AVI, 582 HDMI_INFOFRAME_TYPE_SPD, 583 HDMI_INFOFRAME_TYPE_VENDOR, 584 HDMI_INFOFRAME_TYPE_DRM, 585 }; 586 587 u32 intel_hdmi_infoframe_enable(unsigned int type) 588 { 589 int i; 590 591 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 592 if (infoframe_type_to_idx[i] == type) 593 return BIT(i); 594 } 595 596 return 0; 597 } 598 599 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 600 const struct intel_crtc_state *crtc_state) 601 { 602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 603 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 604 u32 val, ret = 0; 605 int i; 606 607 val = dig_port->infoframes_enabled(encoder, crtc_state); 608 609 /* map from hardware bits to dip idx */ 610 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 611 unsigned int type = infoframe_type_to_idx[i]; 612 613 if (HAS_DDI(dev_priv)) { 614 if (val & hsw_infoframe_enable(type)) 615 ret |= BIT(i); 616 } else { 617 if (val & g4x_infoframe_enable(type)) 618 ret |= BIT(i); 619 } 620 } 621 622 return ret; 623 } 624 625 /* 626 * The data we write to the DIP data buffer registers is 1 byte bigger than the 627 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 628 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 629 * used for both technologies. 630 * 631 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 632 * DW1: DB3 | DB2 | DB1 | DB0 633 * DW2: DB7 | DB6 | DB5 | DB4 634 * DW3: ... 635 * 636 * (HB is Header Byte, DB is Data Byte) 637 * 638 * The hdmi pack() functions don't know about that hardware specific hole so we 639 * trick them by giving an offset into the buffer and moving back the header 640 * bytes by one. 641 */ 642 static void intel_write_infoframe(struct intel_encoder *encoder, 643 const struct intel_crtc_state *crtc_state, 644 enum hdmi_infoframe_type type, 645 const union hdmi_infoframe *frame) 646 { 647 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 648 u8 buffer[VIDEO_DIP_DATA_SIZE]; 649 ssize_t len; 650 651 if ((crtc_state->infoframes.enable & 652 intel_hdmi_infoframe_enable(type)) == 0) 653 return; 654 655 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 656 return; 657 658 /* see comment above for the reason for this offset */ 659 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 660 if (drm_WARN_ON(encoder->base.dev, len < 0)) 661 return; 662 663 /* Insert the 'hole' (see big comment above) at position 3 */ 664 memmove(&buffer[0], &buffer[1], 3); 665 buffer[3] = 0; 666 len++; 667 668 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 669 } 670 671 void intel_read_infoframe(struct intel_encoder *encoder, 672 const struct intel_crtc_state *crtc_state, 673 enum hdmi_infoframe_type type, 674 union hdmi_infoframe *frame) 675 { 676 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 677 u8 buffer[VIDEO_DIP_DATA_SIZE]; 678 int ret; 679 680 if ((crtc_state->infoframes.enable & 681 intel_hdmi_infoframe_enable(type)) == 0) 682 return; 683 684 dig_port->read_infoframe(encoder, crtc_state, 685 type, buffer, sizeof(buffer)); 686 687 /* Fill the 'hole' (see big comment above) at position 3 */ 688 memmove(&buffer[1], &buffer[0], 3); 689 690 /* see comment above for the reason for this offset */ 691 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 692 if (ret) { 693 drm_dbg_kms(encoder->base.dev, 694 "Failed to unpack infoframe type 0x%02x\n", type); 695 return; 696 } 697 698 if (frame->any.type != type) 699 drm_dbg_kms(encoder->base.dev, 700 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 701 frame->any.type, type); 702 } 703 704 static bool 705 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 706 struct intel_crtc_state *crtc_state, 707 struct drm_connector_state *conn_state) 708 { 709 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 710 const struct drm_display_mode *adjusted_mode = 711 &crtc_state->hw.adjusted_mode; 712 struct drm_connector *connector = conn_state->connector; 713 int ret; 714 715 if (!crtc_state->has_infoframe) 716 return true; 717 718 crtc_state->infoframes.enable |= 719 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 720 721 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 722 adjusted_mode); 723 if (ret) 724 return false; 725 726 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 727 frame->colorspace = HDMI_COLORSPACE_YUV420; 728 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 729 frame->colorspace = HDMI_COLORSPACE_YUV444; 730 else 731 frame->colorspace = HDMI_COLORSPACE_RGB; 732 733 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 734 735 /* nonsense combination */ 736 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 737 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 738 739 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 740 drm_hdmi_avi_infoframe_quant_range(frame, connector, 741 adjusted_mode, 742 crtc_state->limited_color_range ? 743 HDMI_QUANTIZATION_RANGE_LIMITED : 744 HDMI_QUANTIZATION_RANGE_FULL); 745 } else { 746 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 747 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 748 } 749 750 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 751 752 /* TODO: handle pixel repetition for YCBCR420 outputs */ 753 754 ret = hdmi_avi_infoframe_check(frame); 755 if (drm_WARN_ON(encoder->base.dev, ret)) 756 return false; 757 758 return true; 759 } 760 761 static bool 762 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 763 struct intel_crtc_state *crtc_state, 764 struct drm_connector_state *conn_state) 765 { 766 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 767 int ret; 768 769 if (!crtc_state->has_infoframe) 770 return true; 771 772 crtc_state->infoframes.enable |= 773 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 774 775 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 776 if (drm_WARN_ON(encoder->base.dev, ret)) 777 return false; 778 779 frame->sdi = HDMI_SPD_SDI_PC; 780 781 ret = hdmi_spd_infoframe_check(frame); 782 if (drm_WARN_ON(encoder->base.dev, ret)) 783 return false; 784 785 return true; 786 } 787 788 static bool 789 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 790 struct intel_crtc_state *crtc_state, 791 struct drm_connector_state *conn_state) 792 { 793 struct hdmi_vendor_infoframe *frame = 794 &crtc_state->infoframes.hdmi.vendor.hdmi; 795 const struct drm_display_info *info = 796 &conn_state->connector->display_info; 797 int ret; 798 799 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 800 return true; 801 802 crtc_state->infoframes.enable |= 803 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 804 805 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 806 conn_state->connector, 807 &crtc_state->hw.adjusted_mode); 808 if (drm_WARN_ON(encoder->base.dev, ret)) 809 return false; 810 811 ret = hdmi_vendor_infoframe_check(frame); 812 if (drm_WARN_ON(encoder->base.dev, ret)) 813 return false; 814 815 return true; 816 } 817 818 static bool 819 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 820 struct intel_crtc_state *crtc_state, 821 struct drm_connector_state *conn_state) 822 { 823 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 825 int ret; 826 827 if (DISPLAY_VER(dev_priv) < 10) 828 return true; 829 830 if (!crtc_state->has_infoframe) 831 return true; 832 833 if (!conn_state->hdr_output_metadata) 834 return true; 835 836 crtc_state->infoframes.enable |= 837 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 838 839 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 840 if (ret < 0) { 841 drm_dbg_kms(&dev_priv->drm, 842 "couldn't set HDR metadata in infoframe\n"); 843 return false; 844 } 845 846 ret = hdmi_drm_infoframe_check(frame); 847 if (drm_WARN_ON(&dev_priv->drm, ret)) 848 return false; 849 850 return true; 851 } 852 853 static void g4x_set_infoframes(struct intel_encoder *encoder, 854 bool enable, 855 const struct intel_crtc_state *crtc_state, 856 const struct drm_connector_state *conn_state) 857 { 858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 860 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 861 i915_reg_t reg = VIDEO_DIP_CTL; 862 u32 val = intel_de_read(dev_priv, reg); 863 u32 port = VIDEO_DIP_PORT(encoder->port); 864 865 assert_hdmi_port_disabled(intel_hdmi); 866 867 /* If the registers were not initialized yet, they might be zeroes, 868 * which means we're selecting the AVI DIP and we're setting its 869 * frequency to once. This seems to really confuse the HW and make 870 * things stop working (the register spec says the AVI always needs to 871 * be sent every VSync). So here we avoid writing to the register more 872 * than we need and also explicitly select the AVI DIP and explicitly 873 * set its frequency to every VSync. Avoiding to write it twice seems to 874 * be enough to solve the problem, but being defensive shouldn't hurt us 875 * either. */ 876 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 877 878 if (!enable) { 879 if (!(val & VIDEO_DIP_ENABLE)) 880 return; 881 if (port != (val & VIDEO_DIP_PORT_MASK)) { 882 drm_dbg_kms(&dev_priv->drm, 883 "video DIP still enabled on port %c\n", 884 (val & VIDEO_DIP_PORT_MASK) >> 29); 885 return; 886 } 887 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 888 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 889 intel_de_write(dev_priv, reg, val); 890 intel_de_posting_read(dev_priv, reg); 891 return; 892 } 893 894 if (port != (val & VIDEO_DIP_PORT_MASK)) { 895 if (val & VIDEO_DIP_ENABLE) { 896 drm_dbg_kms(&dev_priv->drm, 897 "video DIP already enabled on port %c\n", 898 (val & VIDEO_DIP_PORT_MASK) >> 29); 899 return; 900 } 901 val &= ~VIDEO_DIP_PORT_MASK; 902 val |= port; 903 } 904 905 val |= VIDEO_DIP_ENABLE; 906 val &= ~(VIDEO_DIP_ENABLE_AVI | 907 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 908 909 intel_de_write(dev_priv, reg, val); 910 intel_de_posting_read(dev_priv, reg); 911 912 intel_write_infoframe(encoder, crtc_state, 913 HDMI_INFOFRAME_TYPE_AVI, 914 &crtc_state->infoframes.avi); 915 intel_write_infoframe(encoder, crtc_state, 916 HDMI_INFOFRAME_TYPE_SPD, 917 &crtc_state->infoframes.spd); 918 intel_write_infoframe(encoder, crtc_state, 919 HDMI_INFOFRAME_TYPE_VENDOR, 920 &crtc_state->infoframes.hdmi); 921 } 922 923 /* 924 * Determine if default_phase=1 can be indicated in the GCP infoframe. 925 * 926 * From HDMI specification 1.4a: 927 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 928 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 929 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 930 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 931 * phase of 0 932 */ 933 static bool gcp_default_phase_possible(int pipe_bpp, 934 const struct drm_display_mode *mode) 935 { 936 unsigned int pixels_per_group; 937 938 switch (pipe_bpp) { 939 case 30: 940 /* 4 pixels in 5 clocks */ 941 pixels_per_group = 4; 942 break; 943 case 36: 944 /* 2 pixels in 3 clocks */ 945 pixels_per_group = 2; 946 break; 947 case 48: 948 /* 1 pixel in 2 clocks */ 949 pixels_per_group = 1; 950 break; 951 default: 952 /* phase information not relevant for 8bpc */ 953 return false; 954 } 955 956 return mode->crtc_hdisplay % pixels_per_group == 0 && 957 mode->crtc_htotal % pixels_per_group == 0 && 958 mode->crtc_hblank_start % pixels_per_group == 0 && 959 mode->crtc_hblank_end % pixels_per_group == 0 && 960 mode->crtc_hsync_start % pixels_per_group == 0 && 961 mode->crtc_hsync_end % pixels_per_group == 0 && 962 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 963 mode->crtc_htotal/2 % pixels_per_group == 0); 964 } 965 966 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 967 const struct intel_crtc_state *crtc_state, 968 const struct drm_connector_state *conn_state) 969 { 970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 972 i915_reg_t reg; 973 974 if ((crtc_state->infoframes.enable & 975 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 976 return false; 977 978 if (HAS_DDI(dev_priv)) 979 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 980 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 981 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 982 else if (HAS_PCH_SPLIT(dev_priv)) 983 reg = TVIDEO_DIP_GCP(crtc->pipe); 984 else 985 return false; 986 987 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 988 989 return true; 990 } 991 992 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 993 struct intel_crtc_state *crtc_state) 994 { 995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 996 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 997 i915_reg_t reg; 998 999 if ((crtc_state->infoframes.enable & 1000 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1001 return; 1002 1003 if (HAS_DDI(dev_priv)) 1004 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1005 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1006 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1007 else if (HAS_PCH_SPLIT(dev_priv)) 1008 reg = TVIDEO_DIP_GCP(crtc->pipe); 1009 else 1010 return; 1011 1012 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1013 } 1014 1015 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1016 struct intel_crtc_state *crtc_state, 1017 struct drm_connector_state *conn_state) 1018 { 1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1020 1021 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1022 return; 1023 1024 crtc_state->infoframes.enable |= 1025 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1026 1027 /* Indicate color indication for deep color mode */ 1028 if (crtc_state->pipe_bpp > 24) 1029 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1030 1031 /* Enable default_phase whenever the display mode is suitably aligned */ 1032 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1033 &crtc_state->hw.adjusted_mode)) 1034 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1035 } 1036 1037 static void ibx_set_infoframes(struct intel_encoder *encoder, 1038 bool enable, 1039 const struct intel_crtc_state *crtc_state, 1040 const struct drm_connector_state *conn_state) 1041 { 1042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1043 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1045 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1046 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1047 u32 val = intel_de_read(dev_priv, reg); 1048 u32 port = VIDEO_DIP_PORT(encoder->port); 1049 1050 assert_hdmi_port_disabled(intel_hdmi); 1051 1052 /* See the big comment in g4x_set_infoframes() */ 1053 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1054 1055 if (!enable) { 1056 if (!(val & VIDEO_DIP_ENABLE)) 1057 return; 1058 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1059 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1060 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1061 intel_de_write(dev_priv, reg, val); 1062 intel_de_posting_read(dev_priv, reg); 1063 return; 1064 } 1065 1066 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1067 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1068 "DIP already enabled on port %c\n", 1069 (val & VIDEO_DIP_PORT_MASK) >> 29); 1070 val &= ~VIDEO_DIP_PORT_MASK; 1071 val |= port; 1072 } 1073 1074 val |= VIDEO_DIP_ENABLE; 1075 val &= ~(VIDEO_DIP_ENABLE_AVI | 1076 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1077 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1078 1079 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1080 val |= VIDEO_DIP_ENABLE_GCP; 1081 1082 intel_de_write(dev_priv, reg, val); 1083 intel_de_posting_read(dev_priv, reg); 1084 1085 intel_write_infoframe(encoder, crtc_state, 1086 HDMI_INFOFRAME_TYPE_AVI, 1087 &crtc_state->infoframes.avi); 1088 intel_write_infoframe(encoder, crtc_state, 1089 HDMI_INFOFRAME_TYPE_SPD, 1090 &crtc_state->infoframes.spd); 1091 intel_write_infoframe(encoder, crtc_state, 1092 HDMI_INFOFRAME_TYPE_VENDOR, 1093 &crtc_state->infoframes.hdmi); 1094 } 1095 1096 static void cpt_set_infoframes(struct intel_encoder *encoder, 1097 bool enable, 1098 const struct intel_crtc_state *crtc_state, 1099 const struct drm_connector_state *conn_state) 1100 { 1101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1102 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1103 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1104 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1105 u32 val = intel_de_read(dev_priv, reg); 1106 1107 assert_hdmi_port_disabled(intel_hdmi); 1108 1109 /* See the big comment in g4x_set_infoframes() */ 1110 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1111 1112 if (!enable) { 1113 if (!(val & VIDEO_DIP_ENABLE)) 1114 return; 1115 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1116 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1117 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1118 intel_de_write(dev_priv, reg, val); 1119 intel_de_posting_read(dev_priv, reg); 1120 return; 1121 } 1122 1123 /* Set both together, unset both together: see the spec. */ 1124 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1125 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1126 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1127 1128 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1129 val |= VIDEO_DIP_ENABLE_GCP; 1130 1131 intel_de_write(dev_priv, reg, val); 1132 intel_de_posting_read(dev_priv, reg); 1133 1134 intel_write_infoframe(encoder, crtc_state, 1135 HDMI_INFOFRAME_TYPE_AVI, 1136 &crtc_state->infoframes.avi); 1137 intel_write_infoframe(encoder, crtc_state, 1138 HDMI_INFOFRAME_TYPE_SPD, 1139 &crtc_state->infoframes.spd); 1140 intel_write_infoframe(encoder, crtc_state, 1141 HDMI_INFOFRAME_TYPE_VENDOR, 1142 &crtc_state->infoframes.hdmi); 1143 } 1144 1145 static void vlv_set_infoframes(struct intel_encoder *encoder, 1146 bool enable, 1147 const struct intel_crtc_state *crtc_state, 1148 const struct drm_connector_state *conn_state) 1149 { 1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1151 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1152 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1153 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1154 u32 val = intel_de_read(dev_priv, reg); 1155 u32 port = VIDEO_DIP_PORT(encoder->port); 1156 1157 assert_hdmi_port_disabled(intel_hdmi); 1158 1159 /* See the big comment in g4x_set_infoframes() */ 1160 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1161 1162 if (!enable) { 1163 if (!(val & VIDEO_DIP_ENABLE)) 1164 return; 1165 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1166 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1167 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1168 intel_de_write(dev_priv, reg, val); 1169 intel_de_posting_read(dev_priv, reg); 1170 return; 1171 } 1172 1173 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1174 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1175 "DIP already enabled on port %c\n", 1176 (val & VIDEO_DIP_PORT_MASK) >> 29); 1177 val &= ~VIDEO_DIP_PORT_MASK; 1178 val |= port; 1179 } 1180 1181 val |= VIDEO_DIP_ENABLE; 1182 val &= ~(VIDEO_DIP_ENABLE_AVI | 1183 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1184 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1185 1186 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1187 val |= VIDEO_DIP_ENABLE_GCP; 1188 1189 intel_de_write(dev_priv, reg, val); 1190 intel_de_posting_read(dev_priv, reg); 1191 1192 intel_write_infoframe(encoder, crtc_state, 1193 HDMI_INFOFRAME_TYPE_AVI, 1194 &crtc_state->infoframes.avi); 1195 intel_write_infoframe(encoder, crtc_state, 1196 HDMI_INFOFRAME_TYPE_SPD, 1197 &crtc_state->infoframes.spd); 1198 intel_write_infoframe(encoder, crtc_state, 1199 HDMI_INFOFRAME_TYPE_VENDOR, 1200 &crtc_state->infoframes.hdmi); 1201 } 1202 1203 static void hsw_set_infoframes(struct intel_encoder *encoder, 1204 bool enable, 1205 const struct intel_crtc_state *crtc_state, 1206 const struct drm_connector_state *conn_state) 1207 { 1208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1209 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1210 u32 val = intel_de_read(dev_priv, reg); 1211 1212 assert_hdmi_transcoder_func_disabled(dev_priv, 1213 crtc_state->cpu_transcoder); 1214 1215 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1216 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1217 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1218 VIDEO_DIP_ENABLE_DRM_GLK); 1219 1220 if (!enable) { 1221 intel_de_write(dev_priv, reg, val); 1222 intel_de_posting_read(dev_priv, reg); 1223 return; 1224 } 1225 1226 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1227 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1228 1229 intel_de_write(dev_priv, reg, val); 1230 intel_de_posting_read(dev_priv, reg); 1231 1232 intel_write_infoframe(encoder, crtc_state, 1233 HDMI_INFOFRAME_TYPE_AVI, 1234 &crtc_state->infoframes.avi); 1235 intel_write_infoframe(encoder, crtc_state, 1236 HDMI_INFOFRAME_TYPE_SPD, 1237 &crtc_state->infoframes.spd); 1238 intel_write_infoframe(encoder, crtc_state, 1239 HDMI_INFOFRAME_TYPE_VENDOR, 1240 &crtc_state->infoframes.hdmi); 1241 intel_write_infoframe(encoder, crtc_state, 1242 HDMI_INFOFRAME_TYPE_DRM, 1243 &crtc_state->infoframes.drm); 1244 } 1245 1246 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1247 { 1248 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1249 struct i2c_adapter *adapter; 1250 1251 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1252 return; 1253 1254 adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1255 1256 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", 1257 enable ? "Enabling" : "Disabling"); 1258 1259 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable); 1260 } 1261 1262 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1263 unsigned int offset, void *buffer, size_t size) 1264 { 1265 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1266 struct intel_hdmi *hdmi = &dig_port->hdmi; 1267 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1268 hdmi->ddc_bus); 1269 int ret; 1270 u8 start = offset & 0xff; 1271 struct i2c_msg msgs[] = { 1272 { 1273 .addr = DRM_HDCP_DDC_ADDR, 1274 .flags = 0, 1275 .len = 1, 1276 .buf = &start, 1277 }, 1278 { 1279 .addr = DRM_HDCP_DDC_ADDR, 1280 .flags = I2C_M_RD, 1281 .len = size, 1282 .buf = buffer 1283 } 1284 }; 1285 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1286 if (ret == ARRAY_SIZE(msgs)) 1287 return 0; 1288 return ret >= 0 ? -EIO : ret; 1289 } 1290 1291 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1292 unsigned int offset, void *buffer, size_t size) 1293 { 1294 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1295 struct intel_hdmi *hdmi = &dig_port->hdmi; 1296 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1297 hdmi->ddc_bus); 1298 int ret; 1299 u8 *write_buf; 1300 struct i2c_msg msg; 1301 1302 write_buf = kzalloc(size + 1, GFP_KERNEL); 1303 if (!write_buf) 1304 return -ENOMEM; 1305 1306 write_buf[0] = offset & 0xff; 1307 memcpy(&write_buf[1], buffer, size); 1308 1309 msg.addr = DRM_HDCP_DDC_ADDR; 1310 msg.flags = 0, 1311 msg.len = size + 1, 1312 msg.buf = write_buf; 1313 1314 ret = i2c_transfer(adapter, &msg, 1); 1315 if (ret == 1) 1316 ret = 0; 1317 else if (ret >= 0) 1318 ret = -EIO; 1319 1320 kfree(write_buf); 1321 return ret; 1322 } 1323 1324 static 1325 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1326 u8 *an) 1327 { 1328 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1329 struct intel_hdmi *hdmi = &dig_port->hdmi; 1330 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1331 hdmi->ddc_bus); 1332 int ret; 1333 1334 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1335 DRM_HDCP_AN_LEN); 1336 if (ret) { 1337 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", 1338 ret); 1339 return ret; 1340 } 1341 1342 ret = intel_gmbus_output_aksv(adapter); 1343 if (ret < 0) { 1344 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); 1345 return ret; 1346 } 1347 return 0; 1348 } 1349 1350 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1351 u8 *bksv) 1352 { 1353 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1354 1355 int ret; 1356 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1357 DRM_HDCP_KSV_LEN); 1358 if (ret) 1359 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", 1360 ret); 1361 return ret; 1362 } 1363 1364 static 1365 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1366 u8 *bstatus) 1367 { 1368 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1369 1370 int ret; 1371 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1372 bstatus, DRM_HDCP_BSTATUS_LEN); 1373 if (ret) 1374 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", 1375 ret); 1376 return ret; 1377 } 1378 1379 static 1380 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1381 bool *repeater_present) 1382 { 1383 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1384 int ret; 1385 u8 val; 1386 1387 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1388 if (ret) { 1389 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1390 ret); 1391 return ret; 1392 } 1393 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1394 return 0; 1395 } 1396 1397 static 1398 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1399 u8 *ri_prime) 1400 { 1401 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1402 1403 int ret; 1404 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1405 ri_prime, DRM_HDCP_RI_LEN); 1406 if (ret) 1407 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", 1408 ret); 1409 return ret; 1410 } 1411 1412 static 1413 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1414 bool *ksv_ready) 1415 { 1416 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1417 int ret; 1418 u8 val; 1419 1420 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1421 if (ret) { 1422 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1423 ret); 1424 return ret; 1425 } 1426 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1427 return 0; 1428 } 1429 1430 static 1431 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1432 int num_downstream, u8 *ksv_fifo) 1433 { 1434 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1435 int ret; 1436 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1437 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1438 if (ret) { 1439 drm_dbg_kms(&i915->drm, 1440 "Read ksv fifo over DDC failed (%d)\n", ret); 1441 return ret; 1442 } 1443 return 0; 1444 } 1445 1446 static 1447 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1448 int i, u32 *part) 1449 { 1450 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1451 int ret; 1452 1453 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1454 return -EINVAL; 1455 1456 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1457 part, DRM_HDCP_V_PRIME_PART_LEN); 1458 if (ret) 1459 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", 1460 i, ret); 1461 return ret; 1462 } 1463 1464 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1465 enum transcoder cpu_transcoder) 1466 { 1467 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1468 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1469 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1470 u32 scanline; 1471 int ret; 1472 1473 for (;;) { 1474 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe)); 1475 if (scanline > 100 && scanline < 200) 1476 break; 1477 usleep_range(25, 50); 1478 } 1479 1480 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1481 false, TRANS_DDI_HDCP_SIGNALLING); 1482 if (ret) { 1483 drm_err(&dev_priv->drm, 1484 "Disable HDCP signalling failed (%d)\n", ret); 1485 return ret; 1486 } 1487 1488 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1489 true, TRANS_DDI_HDCP_SIGNALLING); 1490 if (ret) { 1491 drm_err(&dev_priv->drm, 1492 "Enable HDCP signalling failed (%d)\n", ret); 1493 return ret; 1494 } 1495 1496 return 0; 1497 } 1498 1499 static 1500 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1501 enum transcoder cpu_transcoder, 1502 bool enable) 1503 { 1504 struct intel_hdmi *hdmi = &dig_port->hdmi; 1505 struct intel_connector *connector = hdmi->attached_connector; 1506 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1507 int ret; 1508 1509 if (!enable) 1510 usleep_range(6, 60); /* Bspec says >= 6us */ 1511 1512 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1513 cpu_transcoder, enable, 1514 TRANS_DDI_HDCP_SIGNALLING); 1515 if (ret) { 1516 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", 1517 enable ? "Enable" : "Disable", ret); 1518 return ret; 1519 } 1520 1521 /* 1522 * WA: To fix incorrect positioning of the window of 1523 * opportunity and enc_en signalling in KABYLAKE. 1524 */ 1525 if (IS_KABYLAKE(dev_priv) && enable) 1526 return kbl_repositioning_enc_en_signal(connector, 1527 cpu_transcoder); 1528 1529 return 0; 1530 } 1531 1532 static 1533 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1534 struct intel_connector *connector) 1535 { 1536 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1537 enum port port = dig_port->base.port; 1538 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1539 int ret; 1540 union { 1541 u32 reg; 1542 u8 shim[DRM_HDCP_RI_LEN]; 1543 } ri; 1544 1545 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1546 if (ret) 1547 return false; 1548 1549 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1550 1551 /* Wait for Ri prime match */ 1552 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1553 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1554 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1555 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", 1556 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1557 port))); 1558 return false; 1559 } 1560 return true; 1561 } 1562 1563 static 1564 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1565 struct intel_connector *connector) 1566 { 1567 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1568 int retry; 1569 1570 for (retry = 0; retry < 3; retry++) 1571 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1572 return true; 1573 1574 drm_err(&i915->drm, "Link check failed\n"); 1575 return false; 1576 } 1577 1578 struct hdcp2_hdmi_msg_timeout { 1579 u8 msg_id; 1580 u16 timeout; 1581 }; 1582 1583 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1584 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1585 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1586 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1587 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1588 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1589 }; 1590 1591 static 1592 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1593 u8 *rx_status) 1594 { 1595 return intel_hdmi_hdcp_read(dig_port, 1596 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1597 rx_status, 1598 HDCP_2_2_HDMI_RXSTATUS_LEN); 1599 } 1600 1601 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1602 { 1603 int i; 1604 1605 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1606 if (is_paired) 1607 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1608 else 1609 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1610 } 1611 1612 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1613 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1614 return hdcp2_msg_timeout[i].timeout; 1615 } 1616 1617 return -EINVAL; 1618 } 1619 1620 static int 1621 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1622 u8 msg_id, bool *msg_ready, 1623 ssize_t *msg_sz) 1624 { 1625 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1626 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1627 int ret; 1628 1629 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1630 if (ret < 0) { 1631 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", 1632 ret); 1633 return ret; 1634 } 1635 1636 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1637 rx_status[0]); 1638 1639 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1640 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1641 *msg_sz); 1642 else 1643 *msg_ready = *msg_sz; 1644 1645 return 0; 1646 } 1647 1648 static ssize_t 1649 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1650 u8 msg_id, bool paired) 1651 { 1652 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1653 bool msg_ready = false; 1654 int timeout, ret; 1655 ssize_t msg_sz = 0; 1656 1657 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1658 if (timeout < 0) 1659 return timeout; 1660 1661 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1662 msg_id, &msg_ready, 1663 &msg_sz), 1664 !ret && msg_ready && msg_sz, timeout * 1000, 1665 1000, 5 * 1000); 1666 if (ret) 1667 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", 1668 msg_id, ret, timeout); 1669 1670 return ret ? ret : msg_sz; 1671 } 1672 1673 static 1674 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, 1675 void *buf, size_t size) 1676 { 1677 unsigned int offset; 1678 1679 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1680 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1681 } 1682 1683 static 1684 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, 1685 u8 msg_id, void *buf, size_t size) 1686 { 1687 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1688 struct intel_hdmi *hdmi = &dig_port->hdmi; 1689 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1690 unsigned int offset; 1691 ssize_t ret; 1692 1693 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1694 hdcp->is_paired); 1695 if (ret < 0) 1696 return ret; 1697 1698 /* 1699 * Available msg size should be equal to or lesser than the 1700 * available buffer. 1701 */ 1702 if (ret > size) { 1703 drm_dbg_kms(&i915->drm, 1704 "msg_sz(%zd) is more than exp size(%zu)\n", 1705 ret, size); 1706 return -EINVAL; 1707 } 1708 1709 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1710 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1711 if (ret) 1712 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", 1713 msg_id, ret); 1714 1715 return ret; 1716 } 1717 1718 static 1719 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1720 struct intel_connector *connector) 1721 { 1722 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1723 int ret; 1724 1725 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1726 if (ret) 1727 return ret; 1728 1729 /* 1730 * Re-auth request and Link Integrity Failures are represented by 1731 * same bit. i.e reauth_req. 1732 */ 1733 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1734 ret = HDCP_REAUTH_REQUEST; 1735 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1736 ret = HDCP_TOPOLOGY_CHANGE; 1737 1738 return ret; 1739 } 1740 1741 static 1742 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, 1743 bool *capable) 1744 { 1745 u8 hdcp2_version; 1746 int ret; 1747 1748 *capable = false; 1749 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1750 &hdcp2_version, sizeof(hdcp2_version)); 1751 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1752 *capable = true; 1753 1754 return ret; 1755 } 1756 1757 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1758 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1759 .read_bksv = intel_hdmi_hdcp_read_bksv, 1760 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1761 .repeater_present = intel_hdmi_hdcp_repeater_present, 1762 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1763 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1764 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1765 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1766 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1767 .check_link = intel_hdmi_hdcp_check_link, 1768 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1769 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1770 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1771 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1772 .protocol = HDCP_PROTOCOL_HDMI, 1773 }; 1774 1775 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1776 { 1777 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1778 int max_tmds_clock, vbt_max_tmds_clock; 1779 1780 if (DISPLAY_VER(dev_priv) >= 10) 1781 max_tmds_clock = 594000; 1782 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 1783 max_tmds_clock = 300000; 1784 else if (DISPLAY_VER(dev_priv) >= 5) 1785 max_tmds_clock = 225000; 1786 else 1787 max_tmds_clock = 165000; 1788 1789 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); 1790 if (vbt_max_tmds_clock) 1791 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1792 1793 return max_tmds_clock; 1794 } 1795 1796 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1797 const struct drm_connector_state *conn_state) 1798 { 1799 return hdmi->has_hdmi_sink && 1800 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1801 } 1802 1803 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1804 { 1805 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1806 } 1807 1808 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1809 bool respect_downstream_limits, 1810 bool has_hdmi_sink) 1811 { 1812 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1813 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1814 1815 if (respect_downstream_limits) { 1816 struct intel_connector *connector = hdmi->attached_connector; 1817 const struct drm_display_info *info = &connector->base.display_info; 1818 1819 if (hdmi->dp_dual_mode.max_tmds_clock) 1820 max_tmds_clock = min(max_tmds_clock, 1821 hdmi->dp_dual_mode.max_tmds_clock); 1822 1823 if (info->max_tmds_clock) 1824 max_tmds_clock = min(max_tmds_clock, 1825 info->max_tmds_clock); 1826 else if (!has_hdmi_sink) 1827 max_tmds_clock = min(max_tmds_clock, 165000); 1828 } 1829 1830 return max_tmds_clock; 1831 } 1832 1833 static enum drm_mode_status 1834 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1835 int clock, bool respect_downstream_limits, 1836 bool has_hdmi_sink) 1837 { 1838 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1839 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port); 1840 1841 if (clock < 25000) 1842 return MODE_CLOCK_LOW; 1843 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1844 has_hdmi_sink)) 1845 return MODE_CLOCK_HIGH; 1846 1847 /* GLK DPLL can't generate 446-480 MHz */ 1848 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1849 return MODE_CLOCK_RANGE; 1850 1851 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1852 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1853 clock > 223333 && clock < 240000) 1854 return MODE_CLOCK_RANGE; 1855 1856 /* CHV DPLL can't generate 216-240 MHz */ 1857 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1858 return MODE_CLOCK_RANGE; 1859 1860 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1861 if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200) 1862 return MODE_CLOCK_RANGE; 1863 1864 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1865 if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800) 1866 return MODE_CLOCK_RANGE; 1867 1868 /* 1869 * SNPS PHYs' MPLLB table-based programming can only handle a fixed 1870 * set of link rates. 1871 * 1872 * FIXME: We will hopefully get an algorithmic way of programming 1873 * the MPLLB for HDMI in the future. 1874 */ 1875 if (IS_DG2(dev_priv)) 1876 return intel_snps_phy_check_hdmi_link_rate(clock); 1877 1878 return MODE_OK; 1879 } 1880 1881 int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output) 1882 { 1883 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1884 if (ycbcr420_output) 1885 clock /= 2; 1886 1887 /* 1888 * Need to adjust the port link by: 1889 * 1.5x for 12bpc 1890 * 1.25x for 10bpc 1891 */ 1892 return clock * bpc / 8; 1893 } 1894 1895 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc) 1896 { 1897 switch (bpc) { 1898 case 12: 1899 return !HAS_GMCH(i915); 1900 case 10: 1901 return DISPLAY_VER(i915) >= 11; 1902 case 8: 1903 return true; 1904 default: 1905 MISSING_CASE(bpc); 1906 return false; 1907 } 1908 } 1909 1910 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, 1911 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 1912 { 1913 const struct drm_display_info *info = &connector->display_info; 1914 const struct drm_hdmi_info *hdmi = &info->hdmi; 1915 1916 switch (bpc) { 1917 case 12: 1918 if (!has_hdmi_sink) 1919 return false; 1920 1921 if (ycbcr420_output) 1922 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1923 else 1924 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1925 case 10: 1926 if (!has_hdmi_sink) 1927 return false; 1928 1929 if (ycbcr420_output) 1930 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1931 else 1932 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1933 case 8: 1934 return true; 1935 default: 1936 MISSING_CASE(bpc); 1937 return false; 1938 } 1939 } 1940 1941 static enum drm_mode_status 1942 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, 1943 bool has_hdmi_sink, bool ycbcr420_output) 1944 { 1945 struct drm_i915_private *i915 = to_i915(connector->dev); 1946 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1947 enum drm_mode_status status = MODE_OK; 1948 int bpc; 1949 1950 /* 1951 * Try all color depths since valid port clock range 1952 * can have holes. Any mode that can be used with at 1953 * least one color depth is accepted. 1954 */ 1955 for (bpc = 12; bpc >= 8; bpc -= 2) { 1956 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output); 1957 1958 if (!intel_hdmi_source_bpc_possible(i915, bpc)) 1959 continue; 1960 1961 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output)) 1962 continue; 1963 1964 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 1965 if (status == MODE_OK) 1966 return MODE_OK; 1967 } 1968 1969 /* can never happen */ 1970 drm_WARN_ON(&i915->drm, status == MODE_OK); 1971 1972 return status; 1973 } 1974 1975 static enum drm_mode_status 1976 intel_hdmi_mode_valid(struct drm_connector *connector, 1977 struct drm_display_mode *mode) 1978 { 1979 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1980 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1981 enum drm_mode_status status; 1982 int clock = mode->clock; 1983 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1984 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 1985 bool ycbcr_420_only; 1986 1987 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1988 return MODE_NO_DBLESCAN; 1989 1990 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1991 clock *= 2; 1992 1993 if (clock > max_dotclk) 1994 return MODE_CLOCK_HIGH; 1995 1996 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1997 if (!has_hdmi_sink) 1998 return MODE_CLOCK_LOW; 1999 clock *= 2; 2000 } 2001 2002 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 2003 2004 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only); 2005 if (status != MODE_OK) { 2006 if (ycbcr_420_only || 2007 !connector->ycbcr_420_allowed || 2008 !drm_mode_is_420_also(&connector->display_info, mode)) 2009 return status; 2010 2011 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true); 2012 if (status != MODE_OK) 2013 return status; 2014 } 2015 2016 return intel_mode_valid_max_plane_size(dev_priv, mode, false); 2017 } 2018 2019 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2020 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 2021 { 2022 struct drm_atomic_state *state = crtc_state->uapi.state; 2023 struct drm_connector_state *connector_state; 2024 struct drm_connector *connector; 2025 int i; 2026 2027 for_each_new_connector_in_state(state, connector, connector_state, i) { 2028 if (connector_state->crtc != crtc_state->uapi.crtc) 2029 continue; 2030 2031 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output)) 2032 return false; 2033 } 2034 2035 return true; 2036 } 2037 2038 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2039 { 2040 struct drm_i915_private *dev_priv = 2041 to_i915(crtc_state->uapi.crtc->dev); 2042 const struct drm_display_mode *adjusted_mode = 2043 &crtc_state->hw.adjusted_mode; 2044 2045 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc)) 2046 return false; 2047 2048 /* 2049 * HDMI deep color affects the clocks, so it's only possible 2050 * when not cloning with other encoder types. 2051 */ 2052 if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI)) 2053 return false; 2054 2055 /* Display Wa_1405510057:icl,ehl */ 2056 if (intel_hdmi_is_ycbcr420(crtc_state) && 2057 bpc == 10 && DISPLAY_VER(dev_priv) == 11 && 2058 (adjusted_mode->crtc_hblank_end - 2059 adjusted_mode->crtc_hblank_start) % 8 == 2) 2060 return false; 2061 2062 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink, 2063 intel_hdmi_is_ycbcr420(crtc_state)); 2064 } 2065 2066 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2067 struct intel_crtc_state *crtc_state, 2068 int clock, bool respect_downstream_limits) 2069 { 2070 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2071 bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state); 2072 int bpc; 2073 2074 /* 2075 * pipe_bpp could already be below 8bpc due to FDI 2076 * bandwidth constraints. HDMI minimum is 8bpc however. 2077 */ 2078 bpc = max(crtc_state->pipe_bpp / 3, 8); 2079 2080 /* 2081 * We will never exceed downstream TMDS clock limits while 2082 * attempting deep color. If the user insists on forcing an 2083 * out of spec mode they will have to be satisfied with 8bpc. 2084 */ 2085 if (!respect_downstream_limits) 2086 bpc = 8; 2087 2088 for (; bpc >= 8; bpc -= 2) { 2089 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output); 2090 2091 if (hdmi_bpc_possible(crtc_state, bpc) && 2092 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2093 respect_downstream_limits, 2094 crtc_state->has_hdmi_sink) == MODE_OK) 2095 return bpc; 2096 } 2097 2098 return -EINVAL; 2099 } 2100 2101 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2102 struct intel_crtc_state *crtc_state, 2103 bool respect_downstream_limits) 2104 { 2105 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2106 const struct drm_display_mode *adjusted_mode = 2107 &crtc_state->hw.adjusted_mode; 2108 int bpc, clock = adjusted_mode->crtc_clock; 2109 2110 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2111 clock *= 2; 2112 2113 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2114 respect_downstream_limits); 2115 if (bpc < 0) 2116 return bpc; 2117 2118 crtc_state->port_clock = 2119 intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state)); 2120 2121 /* 2122 * pipe_bpp could already be below 8bpc due to 2123 * FDI bandwidth constraints. We shouldn't bump it 2124 * back up to the HDMI minimum 8bpc in that case. 2125 */ 2126 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2127 2128 drm_dbg_kms(&i915->drm, 2129 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2130 bpc, crtc_state->pipe_bpp); 2131 2132 return 0; 2133 } 2134 2135 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2136 const struct drm_connector_state *conn_state) 2137 { 2138 const struct intel_digital_connector_state *intel_conn_state = 2139 to_intel_digital_connector_state(conn_state); 2140 const struct drm_display_mode *adjusted_mode = 2141 &crtc_state->hw.adjusted_mode; 2142 2143 /* 2144 * Our YCbCr output is always limited range. 2145 * crtc_state->limited_color_range only applies to RGB, 2146 * and it must never be set for YCbCr or we risk setting 2147 * some conflicting bits in PIPECONF which will mess up 2148 * the colors on the monitor. 2149 */ 2150 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2151 return false; 2152 2153 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2154 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2155 return crtc_state->has_hdmi_sink && 2156 drm_default_rgb_quant_range(adjusted_mode) == 2157 HDMI_QUANTIZATION_RANGE_LIMITED; 2158 } else { 2159 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2160 } 2161 } 2162 2163 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2164 const struct intel_crtc_state *crtc_state, 2165 const struct drm_connector_state *conn_state) 2166 { 2167 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2168 const struct intel_digital_connector_state *intel_conn_state = 2169 to_intel_digital_connector_state(conn_state); 2170 2171 if (!crtc_state->has_hdmi_sink) 2172 return false; 2173 2174 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2175 return intel_hdmi->has_audio; 2176 else 2177 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2178 } 2179 2180 static enum intel_output_format 2181 intel_hdmi_output_format(struct intel_connector *connector, 2182 bool ycbcr_420_output) 2183 { 2184 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2185 return INTEL_OUTPUT_FORMAT_YCBCR420; 2186 else 2187 return INTEL_OUTPUT_FORMAT_RGB; 2188 } 2189 2190 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2191 struct intel_crtc_state *crtc_state, 2192 const struct drm_connector_state *conn_state, 2193 bool respect_downstream_limits) 2194 { 2195 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2196 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2197 const struct drm_display_info *info = &connector->base.display_info; 2198 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2199 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2200 int ret; 2201 2202 crtc_state->output_format = intel_hdmi_output_format(connector, ycbcr_420_only); 2203 2204 if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) { 2205 drm_dbg_kms(&i915->drm, 2206 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2207 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 2208 } 2209 2210 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2211 if (ret) { 2212 if (intel_hdmi_is_ycbcr420(crtc_state) || 2213 !connector->base.ycbcr_420_allowed || 2214 !drm_mode_is_420_also(info, adjusted_mode)) 2215 return ret; 2216 2217 crtc_state->output_format = intel_hdmi_output_format(connector, true); 2218 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2219 } 2220 2221 return ret; 2222 } 2223 2224 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2225 struct intel_crtc_state *pipe_config, 2226 struct drm_connector_state *conn_state) 2227 { 2228 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2229 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2230 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2231 struct drm_connector *connector = conn_state->connector; 2232 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2233 int ret; 2234 2235 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2236 return -EINVAL; 2237 2238 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2239 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, 2240 conn_state); 2241 2242 if (pipe_config->has_hdmi_sink) 2243 pipe_config->has_infoframe = true; 2244 2245 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2246 pipe_config->pixel_multiplier = 2; 2247 2248 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 2249 pipe_config->has_pch_encoder = true; 2250 2251 pipe_config->has_audio = 2252 intel_hdmi_has_audio(encoder, pipe_config, conn_state); 2253 2254 /* 2255 * Try to respect downstream TMDS clock limits first, if 2256 * that fails assume the user might know something we don't. 2257 */ 2258 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2259 if (ret) 2260 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2261 if (ret) { 2262 drm_dbg_kms(&dev_priv->drm, 2263 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2264 pipe_config->hw.adjusted_mode.crtc_clock); 2265 return ret; 2266 } 2267 2268 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2269 ret = intel_panel_fitting(pipe_config, conn_state); 2270 if (ret) 2271 return ret; 2272 } 2273 2274 pipe_config->limited_color_range = 2275 intel_hdmi_limited_color_range(pipe_config, conn_state); 2276 2277 if (conn_state->picture_aspect_ratio) 2278 adjusted_mode->picture_aspect_ratio = 2279 conn_state->picture_aspect_ratio; 2280 2281 pipe_config->lane_count = 4; 2282 2283 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) { 2284 if (scdc->scrambling.low_rates) 2285 pipe_config->hdmi_scrambling = true; 2286 2287 if (pipe_config->port_clock > 340000) { 2288 pipe_config->hdmi_scrambling = true; 2289 pipe_config->hdmi_high_tmds_clock_ratio = true; 2290 } 2291 } 2292 2293 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2294 conn_state); 2295 2296 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2297 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); 2298 return -EINVAL; 2299 } 2300 2301 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2302 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); 2303 return -EINVAL; 2304 } 2305 2306 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2307 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); 2308 return -EINVAL; 2309 } 2310 2311 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2312 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); 2313 return -EINVAL; 2314 } 2315 2316 return 0; 2317 } 2318 2319 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2320 { 2321 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2322 2323 /* 2324 * Give a hand to buggy BIOSen which forget to turn 2325 * the TMDS output buffers back on after a reboot. 2326 */ 2327 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2328 } 2329 2330 static void 2331 intel_hdmi_unset_edid(struct drm_connector *connector) 2332 { 2333 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2334 2335 intel_hdmi->has_hdmi_sink = false; 2336 intel_hdmi->has_audio = false; 2337 2338 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2339 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2340 2341 kfree(to_intel_connector(connector)->detect_edid); 2342 to_intel_connector(connector)->detect_edid = NULL; 2343 } 2344 2345 static void 2346 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 2347 { 2348 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2349 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2350 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2351 struct i2c_adapter *adapter = 2352 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2353 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter); 2354 2355 /* 2356 * Type 1 DVI adaptors are not required to implement any 2357 * registers, so we can't always detect their presence. 2358 * Ideally we should be able to check the state of the 2359 * CONFIG1 pin, but no such luck on our hardware. 2360 * 2361 * The only method left to us is to check the VBT to see 2362 * if the port is a dual mode capable DP port. But let's 2363 * only do that when we sucesfully read the EDID, to avoid 2364 * confusing log messages about DP dual mode adaptors when 2365 * there's nothing connected to the port. 2366 */ 2367 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2368 /* An overridden EDID imply that we want this port for testing. 2369 * Make sure not to set limits for that port. 2370 */ 2371 if (has_edid && !connector->override_edid && 2372 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2373 drm_dbg_kms(&dev_priv->drm, 2374 "Assuming DP dual mode adaptor presence based on VBT\n"); 2375 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2376 } else { 2377 type = DRM_DP_DUAL_MODE_NONE; 2378 } 2379 } 2380 2381 if (type == DRM_DP_DUAL_MODE_NONE) 2382 return; 2383 2384 hdmi->dp_dual_mode.type = type; 2385 hdmi->dp_dual_mode.max_tmds_clock = 2386 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter); 2387 2388 drm_dbg_kms(&dev_priv->drm, 2389 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2390 drm_dp_get_dual_mode_type_name(type), 2391 hdmi->dp_dual_mode.max_tmds_clock); 2392 2393 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2394 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) && 2395 !intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2396 drm_dbg_kms(&dev_priv->drm, 2397 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2398 hdmi->dp_dual_mode.max_tmds_clock = 0; 2399 } 2400 } 2401 2402 static bool 2403 intel_hdmi_set_edid(struct drm_connector *connector) 2404 { 2405 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2406 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2407 intel_wakeref_t wakeref; 2408 struct edid *edid; 2409 bool connected = false; 2410 struct i2c_adapter *i2c; 2411 2412 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2413 2414 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2415 2416 edid = drm_get_edid(connector, i2c); 2417 2418 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2419 drm_dbg_kms(&dev_priv->drm, 2420 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2421 intel_gmbus_force_bit(i2c, true); 2422 edid = drm_get_edid(connector, i2c); 2423 intel_gmbus_force_bit(i2c, false); 2424 } 2425 2426 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 2427 2428 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2429 2430 to_intel_connector(connector)->detect_edid = edid; 2431 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2432 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2433 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2434 2435 connected = true; 2436 } 2437 2438 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2439 2440 return connected; 2441 } 2442 2443 static enum drm_connector_status 2444 intel_hdmi_detect(struct drm_connector *connector, bool force) 2445 { 2446 enum drm_connector_status status = connector_status_disconnected; 2447 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2448 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2449 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2450 intel_wakeref_t wakeref; 2451 2452 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2453 connector->base.id, connector->name); 2454 2455 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 2456 return connector_status_disconnected; 2457 2458 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2459 2460 if (DISPLAY_VER(dev_priv) >= 11 && 2461 !intel_digital_port_connected(encoder)) 2462 goto out; 2463 2464 intel_hdmi_unset_edid(connector); 2465 2466 if (intel_hdmi_set_edid(connector)) 2467 status = connector_status_connected; 2468 2469 out: 2470 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2471 2472 if (status != connector_status_connected) 2473 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2474 2475 /* 2476 * Make sure the refs for power wells enabled during detect are 2477 * dropped to avoid a new detect cycle triggered by HPD polling. 2478 */ 2479 intel_display_power_flush_work(dev_priv); 2480 2481 return status; 2482 } 2483 2484 static void 2485 intel_hdmi_force(struct drm_connector *connector) 2486 { 2487 struct drm_i915_private *i915 = to_i915(connector->dev); 2488 2489 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2490 connector->base.id, connector->name); 2491 2492 intel_hdmi_unset_edid(connector); 2493 2494 if (connector->status != connector_status_connected) 2495 return; 2496 2497 intel_hdmi_set_edid(connector); 2498 } 2499 2500 static int intel_hdmi_get_modes(struct drm_connector *connector) 2501 { 2502 struct edid *edid; 2503 2504 edid = to_intel_connector(connector)->detect_edid; 2505 if (edid == NULL) 2506 return 0; 2507 2508 return intel_connector_update_modes(connector, edid); 2509 } 2510 2511 static struct i2c_adapter * 2512 intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2513 { 2514 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2515 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2516 2517 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2518 } 2519 2520 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2521 { 2522 struct drm_i915_private *i915 = to_i915(connector->dev); 2523 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2524 struct kobject *i2c_kobj = &adapter->dev.kobj; 2525 struct kobject *connector_kobj = &connector->kdev->kobj; 2526 int ret; 2527 2528 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2529 if (ret) 2530 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret); 2531 } 2532 2533 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2534 { 2535 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2536 struct kobject *i2c_kobj = &adapter->dev.kobj; 2537 struct kobject *connector_kobj = &connector->kdev->kobj; 2538 2539 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2540 } 2541 2542 static int 2543 intel_hdmi_connector_register(struct drm_connector *connector) 2544 { 2545 int ret; 2546 2547 ret = intel_connector_register(connector); 2548 if (ret) 2549 return ret; 2550 2551 intel_hdmi_create_i2c_symlink(connector); 2552 2553 return ret; 2554 } 2555 2556 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2557 { 2558 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2559 2560 cec_notifier_conn_unregister(n); 2561 2562 intel_hdmi_remove_i2c_symlink(connector); 2563 intel_connector_unregister(connector); 2564 } 2565 2566 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2567 .detect = intel_hdmi_detect, 2568 .force = intel_hdmi_force, 2569 .fill_modes = drm_helper_probe_single_connector_modes, 2570 .atomic_get_property = intel_digital_connector_atomic_get_property, 2571 .atomic_set_property = intel_digital_connector_atomic_set_property, 2572 .late_register = intel_hdmi_connector_register, 2573 .early_unregister = intel_hdmi_connector_unregister, 2574 .destroy = intel_connector_destroy, 2575 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2576 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2577 }; 2578 2579 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2580 .get_modes = intel_hdmi_get_modes, 2581 .mode_valid = intel_hdmi_mode_valid, 2582 .atomic_check = intel_digital_connector_atomic_check, 2583 }; 2584 2585 static void 2586 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2587 { 2588 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2589 2590 intel_attach_force_audio_property(connector); 2591 intel_attach_broadcast_rgb_property(connector); 2592 intel_attach_aspect_ratio_property(connector); 2593 2594 intel_attach_hdmi_colorspace_property(connector); 2595 drm_connector_attach_content_type_property(connector); 2596 2597 if (DISPLAY_VER(dev_priv) >= 10) 2598 drm_connector_attach_hdr_output_metadata_property(connector); 2599 2600 if (!HAS_GMCH(dev_priv)) 2601 drm_connector_attach_max_bpc_property(connector, 8, 12); 2602 } 2603 2604 /* 2605 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2606 * @encoder: intel_encoder 2607 * @connector: drm_connector 2608 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2609 * or reset the high tmds clock ratio for scrambling 2610 * @scrambling: bool to Indicate if the function needs to set or reset 2611 * sink scrambling 2612 * 2613 * This function handles scrambling on HDMI 2.0 capable sinks. 2614 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2615 * it enables scrambling. This should be called before enabling the HDMI 2616 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2617 * detect a scrambled clock within 100 ms. 2618 * 2619 * Returns: 2620 * True on success, false on failure. 2621 */ 2622 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2623 struct drm_connector *connector, 2624 bool high_tmds_clock_ratio, 2625 bool scrambling) 2626 { 2627 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2628 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2629 struct drm_scrambling *sink_scrambling = 2630 &connector->display_info.hdmi.scdc.scrambling; 2631 struct i2c_adapter *adapter = 2632 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2633 2634 if (!sink_scrambling->supported) 2635 return true; 2636 2637 drm_dbg_kms(&dev_priv->drm, 2638 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2639 connector->base.id, connector->name, 2640 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); 2641 2642 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2643 return drm_scdc_set_high_tmds_clock_ratio(adapter, 2644 high_tmds_clock_ratio) && 2645 drm_scdc_set_scrambling(adapter, scrambling); 2646 } 2647 2648 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2649 { 2650 u8 ddc_pin; 2651 2652 switch (port) { 2653 case PORT_B: 2654 ddc_pin = GMBUS_PIN_DPB; 2655 break; 2656 case PORT_C: 2657 ddc_pin = GMBUS_PIN_DPC; 2658 break; 2659 case PORT_D: 2660 ddc_pin = GMBUS_PIN_DPD_CHV; 2661 break; 2662 default: 2663 MISSING_CASE(port); 2664 ddc_pin = GMBUS_PIN_DPB; 2665 break; 2666 } 2667 return ddc_pin; 2668 } 2669 2670 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2671 { 2672 u8 ddc_pin; 2673 2674 switch (port) { 2675 case PORT_B: 2676 ddc_pin = GMBUS_PIN_1_BXT; 2677 break; 2678 case PORT_C: 2679 ddc_pin = GMBUS_PIN_2_BXT; 2680 break; 2681 default: 2682 MISSING_CASE(port); 2683 ddc_pin = GMBUS_PIN_1_BXT; 2684 break; 2685 } 2686 return ddc_pin; 2687 } 2688 2689 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2690 enum port port) 2691 { 2692 u8 ddc_pin; 2693 2694 switch (port) { 2695 case PORT_B: 2696 ddc_pin = GMBUS_PIN_1_BXT; 2697 break; 2698 case PORT_C: 2699 ddc_pin = GMBUS_PIN_2_BXT; 2700 break; 2701 case PORT_D: 2702 ddc_pin = GMBUS_PIN_4_CNP; 2703 break; 2704 case PORT_F: 2705 ddc_pin = GMBUS_PIN_3_BXT; 2706 break; 2707 default: 2708 MISSING_CASE(port); 2709 ddc_pin = GMBUS_PIN_1_BXT; 2710 break; 2711 } 2712 return ddc_pin; 2713 } 2714 2715 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2716 { 2717 enum phy phy = intel_port_to_phy(dev_priv, port); 2718 2719 if (intel_phy_is_combo(dev_priv, phy)) 2720 return GMBUS_PIN_1_BXT + port; 2721 else if (intel_phy_is_tc(dev_priv, phy)) 2722 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 2723 2724 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 2725 return GMBUS_PIN_2_BXT; 2726 } 2727 2728 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2729 { 2730 enum phy phy = intel_port_to_phy(dev_priv, port); 2731 u8 ddc_pin; 2732 2733 switch (phy) { 2734 case PHY_A: 2735 ddc_pin = GMBUS_PIN_1_BXT; 2736 break; 2737 case PHY_B: 2738 ddc_pin = GMBUS_PIN_2_BXT; 2739 break; 2740 case PHY_C: 2741 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2742 break; 2743 default: 2744 MISSING_CASE(phy); 2745 ddc_pin = GMBUS_PIN_1_BXT; 2746 break; 2747 } 2748 return ddc_pin; 2749 } 2750 2751 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2752 { 2753 enum phy phy = intel_port_to_phy(dev_priv, port); 2754 2755 WARN_ON(port == PORT_C); 2756 2757 /* 2758 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2759 * final two outputs use type-c pins, even though they're actually 2760 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2761 * all outputs. 2762 */ 2763 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2764 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2765 2766 return GMBUS_PIN_1_BXT + phy; 2767 } 2768 2769 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) 2770 { 2771 enum phy phy = intel_port_to_phy(i915, port); 2772 2773 drm_WARN_ON(&i915->drm, port == PORT_A); 2774 2775 /* 2776 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2777 * final two outputs use type-c pins, even though they're actually 2778 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2779 * all outputs. 2780 */ 2781 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2782 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2783 2784 return GMBUS_PIN_1_BXT + phy; 2785 } 2786 2787 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2788 { 2789 return intel_port_to_phy(dev_priv, port) + 1; 2790 } 2791 2792 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2793 { 2794 enum phy phy = intel_port_to_phy(dev_priv, port); 2795 2796 WARN_ON(port == PORT_B || port == PORT_C); 2797 2798 /* 2799 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2800 * except first combo output. 2801 */ 2802 if (phy == PHY_A) 2803 return GMBUS_PIN_1_BXT; 2804 2805 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2806 } 2807 2808 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2809 enum port port) 2810 { 2811 u8 ddc_pin; 2812 2813 switch (port) { 2814 case PORT_B: 2815 ddc_pin = GMBUS_PIN_DPB; 2816 break; 2817 case PORT_C: 2818 ddc_pin = GMBUS_PIN_DPC; 2819 break; 2820 case PORT_D: 2821 ddc_pin = GMBUS_PIN_DPD; 2822 break; 2823 default: 2824 MISSING_CASE(port); 2825 ddc_pin = GMBUS_PIN_DPB; 2826 break; 2827 } 2828 return ddc_pin; 2829 } 2830 2831 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2832 { 2833 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2834 enum port port = encoder->port; 2835 u8 ddc_pin; 2836 2837 ddc_pin = intel_bios_alternate_ddc_pin(encoder); 2838 if (ddc_pin) { 2839 drm_dbg_kms(&dev_priv->drm, 2840 "Using DDC pin 0x%x for port %c (VBT)\n", 2841 ddc_pin, port_name(port)); 2842 return ddc_pin; 2843 } 2844 2845 if (IS_ALDERLAKE_S(dev_priv)) 2846 ddc_pin = adls_port_to_ddc_pin(dev_priv, port); 2847 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2848 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); 2849 else if (IS_ROCKETLAKE(dev_priv)) 2850 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); 2851 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv)) 2852 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port); 2853 else if (HAS_PCH_MCC(dev_priv)) 2854 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 2855 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2856 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 2857 else if (HAS_PCH_CNP(dev_priv)) 2858 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 2859 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2860 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 2861 else if (IS_CHERRYVIEW(dev_priv)) 2862 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 2863 else 2864 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 2865 2866 drm_dbg_kms(&dev_priv->drm, 2867 "Using DDC pin 0x%x for port %c (platform default)\n", 2868 ddc_pin, port_name(port)); 2869 2870 return ddc_pin; 2871 } 2872 2873 void intel_infoframe_init(struct intel_digital_port *dig_port) 2874 { 2875 struct drm_i915_private *dev_priv = 2876 to_i915(dig_port->base.base.dev); 2877 2878 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2879 dig_port->write_infoframe = vlv_write_infoframe; 2880 dig_port->read_infoframe = vlv_read_infoframe; 2881 dig_port->set_infoframes = vlv_set_infoframes; 2882 dig_port->infoframes_enabled = vlv_infoframes_enabled; 2883 } else if (IS_G4X(dev_priv)) { 2884 dig_port->write_infoframe = g4x_write_infoframe; 2885 dig_port->read_infoframe = g4x_read_infoframe; 2886 dig_port->set_infoframes = g4x_set_infoframes; 2887 dig_port->infoframes_enabled = g4x_infoframes_enabled; 2888 } else if (HAS_DDI(dev_priv)) { 2889 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) { 2890 dig_port->write_infoframe = lspcon_write_infoframe; 2891 dig_port->read_infoframe = lspcon_read_infoframe; 2892 dig_port->set_infoframes = lspcon_set_infoframes; 2893 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 2894 } else { 2895 dig_port->write_infoframe = hsw_write_infoframe; 2896 dig_port->read_infoframe = hsw_read_infoframe; 2897 dig_port->set_infoframes = hsw_set_infoframes; 2898 dig_port->infoframes_enabled = hsw_infoframes_enabled; 2899 } 2900 } else if (HAS_PCH_IBX(dev_priv)) { 2901 dig_port->write_infoframe = ibx_write_infoframe; 2902 dig_port->read_infoframe = ibx_read_infoframe; 2903 dig_port->set_infoframes = ibx_set_infoframes; 2904 dig_port->infoframes_enabled = ibx_infoframes_enabled; 2905 } else { 2906 dig_port->write_infoframe = cpt_write_infoframe; 2907 dig_port->read_infoframe = cpt_read_infoframe; 2908 dig_port->set_infoframes = cpt_set_infoframes; 2909 dig_port->infoframes_enabled = cpt_infoframes_enabled; 2910 } 2911 } 2912 2913 void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 2914 struct intel_connector *intel_connector) 2915 { 2916 struct drm_connector *connector = &intel_connector->base; 2917 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2918 struct intel_encoder *intel_encoder = &dig_port->base; 2919 struct drm_device *dev = intel_encoder->base.dev; 2920 struct drm_i915_private *dev_priv = to_i915(dev); 2921 struct i2c_adapter *ddc; 2922 enum port port = intel_encoder->port; 2923 struct cec_connector_info conn_info; 2924 2925 drm_dbg_kms(&dev_priv->drm, 2926 "Adding HDMI connector on [ENCODER:%d:%s]\n", 2927 intel_encoder->base.base.id, intel_encoder->base.name); 2928 2929 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 2930 return; 2931 2932 if (drm_WARN(dev, dig_port->max_lanes < 4, 2933 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 2934 dig_port->max_lanes, intel_encoder->base.base.id, 2935 intel_encoder->base.name)) 2936 return; 2937 2938 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); 2939 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2940 2941 drm_connector_init_with_ddc(dev, connector, 2942 &intel_hdmi_connector_funcs, 2943 DRM_MODE_CONNECTOR_HDMIA, 2944 ddc); 2945 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 2946 2947 connector->interlace_allowed = 1; 2948 connector->doublescan_allowed = 0; 2949 connector->stereo_allowed = 1; 2950 2951 if (DISPLAY_VER(dev_priv) >= 10) 2952 connector->ycbcr_420_allowed = true; 2953 2954 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2955 2956 if (HAS_DDI(dev_priv)) 2957 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2958 else 2959 intel_connector->get_hw_state = intel_connector_get_hw_state; 2960 2961 intel_hdmi_add_properties(intel_hdmi, connector); 2962 2963 intel_connector_attach_encoder(intel_connector, intel_encoder); 2964 intel_hdmi->attached_connector = intel_connector; 2965 2966 if (is_hdcp_supported(dev_priv, port)) { 2967 int ret = intel_hdcp_init(intel_connector, dig_port, 2968 &intel_hdmi_hdcp_shim); 2969 if (ret) 2970 drm_dbg_kms(&dev_priv->drm, 2971 "HDCP init failed, skipping.\n"); 2972 } 2973 2974 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2975 * 0xd. Failure to do so will result in spurious interrupts being 2976 * generated on the port when a cable is not attached. 2977 */ 2978 if (IS_G45(dev_priv)) { 2979 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 2980 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 2981 (temp & ~0xf) | 0xd); 2982 } 2983 2984 cec_fill_conn_info_from_drm(&conn_info, connector); 2985 2986 intel_hdmi->cec_notifier = 2987 cec_notifier_conn_register(dev->dev, port_identifier(port), 2988 &conn_info); 2989 if (!intel_hdmi->cec_notifier) 2990 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); 2991 } 2992 2993 /* 2994 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 2995 * @vactive: Vactive of a display mode 2996 * 2997 * @return: appropriate dsc slice height for a given mode. 2998 */ 2999 int intel_hdmi_dsc_get_slice_height(int vactive) 3000 { 3001 int slice_height; 3002 3003 /* 3004 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3005 * Select smallest slice height >=96, that results in a valid PPS and 3006 * requires minimum padding lines required for final slice. 3007 * 3008 * Assumption : Vactive is even. 3009 */ 3010 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3011 if (vactive % slice_height == 0) 3012 return slice_height; 3013 3014 return 0; 3015 } 3016 3017 /* 3018 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3019 * and dsc decoder capabilities 3020 * 3021 * @crtc_state: intel crtc_state 3022 * @src_max_slices: maximum slices supported by the DSC encoder 3023 * @src_max_slice_width: maximum slice width supported by DSC encoder 3024 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3025 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3026 * 3027 * @return: num of dsc slices that can be supported by the dsc encoder 3028 * and decoder. 3029 */ 3030 int 3031 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3032 int src_max_slices, int src_max_slice_width, 3033 int hdmi_max_slices, int hdmi_throughput) 3034 { 3035 /* Pixel rates in KPixels/sec */ 3036 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3037 /* 3038 * Rates at which the source and sink are required to process pixels in each 3039 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3040 */ 3041 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3042 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3043 3044 /* Spec limits the slice width to 2720 pixels */ 3045 #define MAX_HDMI_SLICE_WIDTH 2720 3046 int kslice_adjust; 3047 int adjusted_clk_khz; 3048 int min_slices; 3049 int target_slices; 3050 int max_throughput; /* max clock freq. in khz per slice */ 3051 int max_slice_width; 3052 int slice_width; 3053 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3054 3055 if (!hdmi_throughput) 3056 return 0; 3057 3058 /* 3059 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3060 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3061 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3062 * dividing adjusted clock value by 10. 3063 */ 3064 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3065 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3066 kslice_adjust = 10; 3067 else 3068 kslice_adjust = 5; 3069 3070 /* 3071 * As per spec, the rate at which the source and the sink process 3072 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3073 * This depends upon the pixel clock rate and output formats 3074 * (kslice adjust). 3075 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3076 * at max 340MHz, otherwise they can be processed at max 400MHz. 3077 */ 3078 3079 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3080 3081 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3082 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3083 else 3084 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3085 3086 /* 3087 * Taking into account the sink's capability for maximum 3088 * clock per slice (in MHz) as read from HF-VSDB. 3089 */ 3090 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3091 3092 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3093 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3094 3095 /* 3096 * Keep on increasing the num of slices/line, starting from min_slices 3097 * per line till we get such a number, for which the slice_width is 3098 * just less than max_slice_width. The slices/line selected should be 3099 * less than or equal to the max horizontal slices that the combination 3100 * of PCON encoder and HDMI decoder can support. 3101 */ 3102 slice_width = max_slice_width; 3103 3104 do { 3105 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3106 target_slices = 1; 3107 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3108 target_slices = 2; 3109 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3110 target_slices = 4; 3111 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3112 target_slices = 8; 3113 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3114 target_slices = 12; 3115 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3116 target_slices = 16; 3117 else 3118 return 0; 3119 3120 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3121 if (slice_width >= max_slice_width) 3122 min_slices = target_slices + 1; 3123 } while (slice_width >= max_slice_width); 3124 3125 return target_slices; 3126 } 3127 3128 /* 3129 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3130 * source and sink capabilities. 3131 * 3132 * @src_fraction_bpp: fractional bpp supported by the source 3133 * @slice_width: dsc slice width supported by the source and sink 3134 * @num_slices: num of slices supported by the source and sink 3135 * @output_format: video output format 3136 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3137 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3138 * 3139 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3140 */ 3141 int 3142 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3143 int output_format, bool hdmi_all_bpp, 3144 int hdmi_max_chunk_bytes) 3145 { 3146 int max_dsc_bpp, min_dsc_bpp; 3147 int target_bytes; 3148 bool bpp_found = false; 3149 int bpp_decrement_x16; 3150 int bpp_target; 3151 int bpp_target_x16; 3152 3153 /* 3154 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3155 * Start with the max bpp and keep on decrementing with 3156 * fractional bpp, if supported by PCON DSC encoder 3157 * 3158 * for each bpp we check if no of bytes can be supported by HDMI sink 3159 */ 3160 3161 /* Assuming: bpc as 8*/ 3162 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3163 min_dsc_bpp = 6; 3164 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3165 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3166 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3167 min_dsc_bpp = 8; 3168 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3169 } else { 3170 /* Assuming 4:2:2 encoding */ 3171 min_dsc_bpp = 7; 3172 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3173 } 3174 3175 /* 3176 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3177 * Section 7.7.34 : Source shall not enable compressed Video 3178 * Transport with bpp_target settings above 12 bpp unless 3179 * DSC_all_bpp is set to 1. 3180 */ 3181 if (!hdmi_all_bpp) 3182 max_dsc_bpp = min(max_dsc_bpp, 12); 3183 3184 /* 3185 * The Sink has a limit of compressed data in bytes for a scanline, 3186 * as described in max_chunk_bytes field in HFVSDB block of edid. 3187 * The no. of bytes depend on the target bits per pixel that the 3188 * source configures. So we start with the max_bpp and calculate 3189 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3190 * till we get the target_chunk_bytes just less than what the sink's 3191 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3192 * 3193 * The decrement is according to the fractional support from PCON DSC 3194 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3195 * 3196 * bpp_target_x16 = bpp_target * 16 3197 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3198 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3199 */ 3200 3201 bpp_target = max_dsc_bpp; 3202 3203 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3204 if (!src_fractional_bpp) 3205 src_fractional_bpp = 1; 3206 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3207 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3208 3209 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3210 int bpp; 3211 3212 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3213 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3214 if (target_bytes <= hdmi_max_chunk_bytes) { 3215 bpp_found = true; 3216 break; 3217 } 3218 bpp_target_x16 -= bpp_decrement_x16; 3219 } 3220 if (bpp_found) 3221 return bpp_target_x16; 3222 3223 return 0; 3224 } 3225