1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_hdcp_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_edid.h> 41 #include <drm/intel_lpe_audio.h> 42 43 #include "i915_debugfs.h" 44 #include "i915_drv.h" 45 #include "i915_reg.h" 46 #include "intel_atomic.h" 47 #include "intel_connector.h" 48 #include "intel_ddi.h" 49 #include "intel_de.h" 50 #include "intel_display_types.h" 51 #include "intel_dp.h" 52 #include "intel_gmbus.h" 53 #include "intel_hdcp.h" 54 #include "intel_hdcp_regs.h" 55 #include "intel_hdmi.h" 56 #include "intel_lspcon.h" 57 #include "intel_panel.h" 58 #include "intel_snps_phy.h" 59 60 static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi) 61 { 62 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev); 63 } 64 65 static void 66 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 67 { 68 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi); 69 u32 enabled_bits; 70 71 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 72 73 drm_WARN(&dev_priv->drm, 74 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 75 "HDMI port enabled, expecting disabled\n"); 76 } 77 78 static void 79 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 80 enum transcoder cpu_transcoder) 81 { 82 drm_WARN(&dev_priv->drm, 83 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 84 TRANS_DDI_FUNC_ENABLE, 85 "HDMI transcoder function enabled, expecting disabled\n"); 86 } 87 88 static u32 g4x_infoframe_index(unsigned int type) 89 { 90 switch (type) { 91 case HDMI_PACKET_TYPE_GAMUT_METADATA: 92 return VIDEO_DIP_SELECT_GAMUT; 93 case HDMI_INFOFRAME_TYPE_AVI: 94 return VIDEO_DIP_SELECT_AVI; 95 case HDMI_INFOFRAME_TYPE_SPD: 96 return VIDEO_DIP_SELECT_SPD; 97 case HDMI_INFOFRAME_TYPE_VENDOR: 98 return VIDEO_DIP_SELECT_VENDOR; 99 default: 100 MISSING_CASE(type); 101 return 0; 102 } 103 } 104 105 static u32 g4x_infoframe_enable(unsigned int type) 106 { 107 switch (type) { 108 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 109 return VIDEO_DIP_ENABLE_GCP; 110 case HDMI_PACKET_TYPE_GAMUT_METADATA: 111 return VIDEO_DIP_ENABLE_GAMUT; 112 case DP_SDP_VSC: 113 return 0; 114 case HDMI_INFOFRAME_TYPE_AVI: 115 return VIDEO_DIP_ENABLE_AVI; 116 case HDMI_INFOFRAME_TYPE_SPD: 117 return VIDEO_DIP_ENABLE_SPD; 118 case HDMI_INFOFRAME_TYPE_VENDOR: 119 return VIDEO_DIP_ENABLE_VENDOR; 120 case HDMI_INFOFRAME_TYPE_DRM: 121 return 0; 122 default: 123 MISSING_CASE(type); 124 return 0; 125 } 126 } 127 128 static u32 hsw_infoframe_enable(unsigned int type) 129 { 130 switch (type) { 131 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 132 return VIDEO_DIP_ENABLE_GCP_HSW; 133 case HDMI_PACKET_TYPE_GAMUT_METADATA: 134 return VIDEO_DIP_ENABLE_GMP_HSW; 135 case DP_SDP_VSC: 136 return VIDEO_DIP_ENABLE_VSC_HSW; 137 case DP_SDP_PPS: 138 return VDIP_ENABLE_PPS; 139 case HDMI_INFOFRAME_TYPE_AVI: 140 return VIDEO_DIP_ENABLE_AVI_HSW; 141 case HDMI_INFOFRAME_TYPE_SPD: 142 return VIDEO_DIP_ENABLE_SPD_HSW; 143 case HDMI_INFOFRAME_TYPE_VENDOR: 144 return VIDEO_DIP_ENABLE_VS_HSW; 145 case HDMI_INFOFRAME_TYPE_DRM: 146 return VIDEO_DIP_ENABLE_DRM_GLK; 147 default: 148 MISSING_CASE(type); 149 return 0; 150 } 151 } 152 153 static i915_reg_t 154 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 155 enum transcoder cpu_transcoder, 156 unsigned int type, 157 int i) 158 { 159 switch (type) { 160 case HDMI_PACKET_TYPE_GAMUT_METADATA: 161 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 162 case DP_SDP_VSC: 163 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 164 case DP_SDP_PPS: 165 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 166 case HDMI_INFOFRAME_TYPE_AVI: 167 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 168 case HDMI_INFOFRAME_TYPE_SPD: 169 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 170 case HDMI_INFOFRAME_TYPE_VENDOR: 171 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 172 case HDMI_INFOFRAME_TYPE_DRM: 173 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 174 default: 175 MISSING_CASE(type); 176 return INVALID_MMIO_REG; 177 } 178 } 179 180 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 181 unsigned int type) 182 { 183 switch (type) { 184 case DP_SDP_VSC: 185 return VIDEO_DIP_VSC_DATA_SIZE; 186 case DP_SDP_PPS: 187 return VIDEO_DIP_PPS_DATA_SIZE; 188 case HDMI_PACKET_TYPE_GAMUT_METADATA: 189 if (DISPLAY_VER(dev_priv) >= 11) 190 return VIDEO_DIP_GMP_DATA_SIZE; 191 else 192 return VIDEO_DIP_DATA_SIZE; 193 default: 194 return VIDEO_DIP_DATA_SIZE; 195 } 196 } 197 198 static void g4x_write_infoframe(struct intel_encoder *encoder, 199 const struct intel_crtc_state *crtc_state, 200 unsigned int type, 201 const void *frame, ssize_t len) 202 { 203 const u32 *data = frame; 204 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 205 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 206 int i; 207 208 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 209 "Writing DIP with CTL reg disabled\n"); 210 211 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 212 val |= g4x_infoframe_index(type); 213 214 val &= ~g4x_infoframe_enable(type); 215 216 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 217 218 for (i = 0; i < len; i += 4) { 219 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 220 data++; 221 } 222 /* Write every possible data byte to force correct ECC calculation. */ 223 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 224 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 225 226 val |= g4x_infoframe_enable(type); 227 val &= ~VIDEO_DIP_FREQ_MASK; 228 val |= VIDEO_DIP_FREQ_VSYNC; 229 230 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 231 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 232 } 233 234 static void g4x_read_infoframe(struct intel_encoder *encoder, 235 const struct intel_crtc_state *crtc_state, 236 unsigned int type, 237 void *frame, ssize_t len) 238 { 239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 240 u32 val, *data = frame; 241 int i; 242 243 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 244 245 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 246 val |= g4x_infoframe_index(type); 247 248 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 249 250 for (i = 0; i < len; i += 4) 251 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 252 } 253 254 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 255 const struct intel_crtc_state *pipe_config) 256 { 257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 258 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 259 260 if ((val & VIDEO_DIP_ENABLE) == 0) 261 return 0; 262 263 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 264 return 0; 265 266 return val & (VIDEO_DIP_ENABLE_AVI | 267 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 268 } 269 270 static void ibx_write_infoframe(struct intel_encoder *encoder, 271 const struct intel_crtc_state *crtc_state, 272 unsigned int type, 273 const void *frame, ssize_t len) 274 { 275 const u32 *data = frame; 276 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 277 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 278 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 279 u32 val = intel_de_read(dev_priv, reg); 280 int i; 281 282 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 283 "Writing DIP with CTL reg disabled\n"); 284 285 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 286 val |= g4x_infoframe_index(type); 287 288 val &= ~g4x_infoframe_enable(type); 289 290 intel_de_write(dev_priv, reg, val); 291 292 for (i = 0; i < len; i += 4) { 293 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 294 *data); 295 data++; 296 } 297 /* Write every possible data byte to force correct ECC calculation. */ 298 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 299 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 300 301 val |= g4x_infoframe_enable(type); 302 val &= ~VIDEO_DIP_FREQ_MASK; 303 val |= VIDEO_DIP_FREQ_VSYNC; 304 305 intel_de_write(dev_priv, reg, val); 306 intel_de_posting_read(dev_priv, reg); 307 } 308 309 static void ibx_read_infoframe(struct intel_encoder *encoder, 310 const struct intel_crtc_state *crtc_state, 311 unsigned int type, 312 void *frame, ssize_t len) 313 { 314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 316 u32 val, *data = frame; 317 int i; 318 319 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 320 321 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 322 val |= g4x_infoframe_index(type); 323 324 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 325 326 for (i = 0; i < len; i += 4) 327 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 328 } 329 330 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 331 const struct intel_crtc_state *pipe_config) 332 { 333 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 334 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 335 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 336 u32 val = intel_de_read(dev_priv, reg); 337 338 if ((val & VIDEO_DIP_ENABLE) == 0) 339 return 0; 340 341 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 342 return 0; 343 344 return val & (VIDEO_DIP_ENABLE_AVI | 345 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 346 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 347 } 348 349 static void cpt_write_infoframe(struct intel_encoder *encoder, 350 const struct intel_crtc_state *crtc_state, 351 unsigned int type, 352 const void *frame, ssize_t len) 353 { 354 const u32 *data = frame; 355 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 356 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 357 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 358 u32 val = intel_de_read(dev_priv, reg); 359 int i; 360 361 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 362 "Writing DIP with CTL reg disabled\n"); 363 364 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 365 val |= g4x_infoframe_index(type); 366 367 /* The DIP control register spec says that we need to update the AVI 368 * infoframe without clearing its enable bit */ 369 if (type != HDMI_INFOFRAME_TYPE_AVI) 370 val &= ~g4x_infoframe_enable(type); 371 372 intel_de_write(dev_priv, reg, val); 373 374 for (i = 0; i < len; i += 4) { 375 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 376 *data); 377 data++; 378 } 379 /* Write every possible data byte to force correct ECC calculation. */ 380 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 381 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 382 383 val |= g4x_infoframe_enable(type); 384 val &= ~VIDEO_DIP_FREQ_MASK; 385 val |= VIDEO_DIP_FREQ_VSYNC; 386 387 intel_de_write(dev_priv, reg, val); 388 intel_de_posting_read(dev_priv, reg); 389 } 390 391 static void cpt_read_infoframe(struct intel_encoder *encoder, 392 const struct intel_crtc_state *crtc_state, 393 unsigned int type, 394 void *frame, ssize_t len) 395 { 396 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 397 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 398 u32 val, *data = frame; 399 int i; 400 401 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 402 403 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 404 val |= g4x_infoframe_index(type); 405 406 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 407 408 for (i = 0; i < len; i += 4) 409 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 410 } 411 412 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 413 const struct intel_crtc_state *pipe_config) 414 { 415 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 416 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 417 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 418 419 if ((val & VIDEO_DIP_ENABLE) == 0) 420 return 0; 421 422 return val & (VIDEO_DIP_ENABLE_AVI | 423 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 424 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 425 } 426 427 static void vlv_write_infoframe(struct intel_encoder *encoder, 428 const struct intel_crtc_state *crtc_state, 429 unsigned int type, 430 const void *frame, ssize_t len) 431 { 432 const u32 *data = frame; 433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 435 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 436 u32 val = intel_de_read(dev_priv, reg); 437 int i; 438 439 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 440 "Writing DIP with CTL reg disabled\n"); 441 442 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 443 val |= g4x_infoframe_index(type); 444 445 val &= ~g4x_infoframe_enable(type); 446 447 intel_de_write(dev_priv, reg, val); 448 449 for (i = 0; i < len; i += 4) { 450 intel_de_write(dev_priv, 451 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 452 data++; 453 } 454 /* Write every possible data byte to force correct ECC calculation. */ 455 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 456 intel_de_write(dev_priv, 457 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 458 459 val |= g4x_infoframe_enable(type); 460 val &= ~VIDEO_DIP_FREQ_MASK; 461 val |= VIDEO_DIP_FREQ_VSYNC; 462 463 intel_de_write(dev_priv, reg, val); 464 intel_de_posting_read(dev_priv, reg); 465 } 466 467 static void vlv_read_infoframe(struct intel_encoder *encoder, 468 const struct intel_crtc_state *crtc_state, 469 unsigned int type, 470 void *frame, ssize_t len) 471 { 472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 474 u32 val, *data = frame; 475 int i; 476 477 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); 478 479 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 480 val |= g4x_infoframe_index(type); 481 482 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 483 484 for (i = 0; i < len; i += 4) 485 *data++ = intel_de_read(dev_priv, 486 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 487 } 488 489 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 490 const struct intel_crtc_state *pipe_config) 491 { 492 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 493 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 494 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 495 496 if ((val & VIDEO_DIP_ENABLE) == 0) 497 return 0; 498 499 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 500 return 0; 501 502 return val & (VIDEO_DIP_ENABLE_AVI | 503 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 504 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 505 } 506 507 void hsw_write_infoframe(struct intel_encoder *encoder, 508 const struct intel_crtc_state *crtc_state, 509 unsigned int type, 510 const void *frame, ssize_t len) 511 { 512 const u32 *data = frame; 513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 514 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 515 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 516 int data_size; 517 int i; 518 u32 val = intel_de_read(dev_priv, ctl_reg); 519 520 data_size = hsw_dip_data_size(dev_priv, type); 521 522 drm_WARN_ON(&dev_priv->drm, len > data_size); 523 524 val &= ~hsw_infoframe_enable(type); 525 intel_de_write(dev_priv, ctl_reg, val); 526 527 for (i = 0; i < len; i += 4) { 528 intel_de_write(dev_priv, 529 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 530 *data); 531 data++; 532 } 533 /* Write every possible data byte to force correct ECC calculation. */ 534 for (; i < data_size; i += 4) 535 intel_de_write(dev_priv, 536 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 537 0); 538 539 /* Wa_14013475917 */ 540 if ((DISPLAY_VER(dev_priv) == 13 || 541 IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) && crtc_state->has_psr && 542 type == DP_SDP_VSC) 543 return; 544 545 val |= hsw_infoframe_enable(type); 546 intel_de_write(dev_priv, ctl_reg, val); 547 intel_de_posting_read(dev_priv, ctl_reg); 548 } 549 550 void hsw_read_infoframe(struct intel_encoder *encoder, 551 const struct intel_crtc_state *crtc_state, 552 unsigned int type, void *frame, ssize_t len) 553 { 554 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 555 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 556 u32 *data = frame; 557 int i; 558 559 for (i = 0; i < len; i += 4) 560 *data++ = intel_de_read(dev_priv, 561 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 562 } 563 564 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 565 const struct intel_crtc_state *pipe_config) 566 { 567 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 568 u32 val = intel_de_read(dev_priv, 569 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 570 u32 mask; 571 572 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 573 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 574 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 575 576 if (DISPLAY_VER(dev_priv) >= 10) 577 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 578 579 return val & mask; 580 } 581 582 static const u8 infoframe_type_to_idx[] = { 583 HDMI_PACKET_TYPE_GENERAL_CONTROL, 584 HDMI_PACKET_TYPE_GAMUT_METADATA, 585 DP_SDP_VSC, 586 HDMI_INFOFRAME_TYPE_AVI, 587 HDMI_INFOFRAME_TYPE_SPD, 588 HDMI_INFOFRAME_TYPE_VENDOR, 589 HDMI_INFOFRAME_TYPE_DRM, 590 }; 591 592 u32 intel_hdmi_infoframe_enable(unsigned int type) 593 { 594 int i; 595 596 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 597 if (infoframe_type_to_idx[i] == type) 598 return BIT(i); 599 } 600 601 return 0; 602 } 603 604 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 605 const struct intel_crtc_state *crtc_state) 606 { 607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 608 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 609 u32 val, ret = 0; 610 int i; 611 612 val = dig_port->infoframes_enabled(encoder, crtc_state); 613 614 /* map from hardware bits to dip idx */ 615 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 616 unsigned int type = infoframe_type_to_idx[i]; 617 618 if (HAS_DDI(dev_priv)) { 619 if (val & hsw_infoframe_enable(type)) 620 ret |= BIT(i); 621 } else { 622 if (val & g4x_infoframe_enable(type)) 623 ret |= BIT(i); 624 } 625 } 626 627 return ret; 628 } 629 630 /* 631 * The data we write to the DIP data buffer registers is 1 byte bigger than the 632 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 633 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 634 * used for both technologies. 635 * 636 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 637 * DW1: DB3 | DB2 | DB1 | DB0 638 * DW2: DB7 | DB6 | DB5 | DB4 639 * DW3: ... 640 * 641 * (HB is Header Byte, DB is Data Byte) 642 * 643 * The hdmi pack() functions don't know about that hardware specific hole so we 644 * trick them by giving an offset into the buffer and moving back the header 645 * bytes by one. 646 */ 647 static void intel_write_infoframe(struct intel_encoder *encoder, 648 const struct intel_crtc_state *crtc_state, 649 enum hdmi_infoframe_type type, 650 const union hdmi_infoframe *frame) 651 { 652 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 653 u8 buffer[VIDEO_DIP_DATA_SIZE]; 654 ssize_t len; 655 656 if ((crtc_state->infoframes.enable & 657 intel_hdmi_infoframe_enable(type)) == 0) 658 return; 659 660 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 661 return; 662 663 /* see comment above for the reason for this offset */ 664 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 665 if (drm_WARN_ON(encoder->base.dev, len < 0)) 666 return; 667 668 /* Insert the 'hole' (see big comment above) at position 3 */ 669 memmove(&buffer[0], &buffer[1], 3); 670 buffer[3] = 0; 671 len++; 672 673 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 674 } 675 676 void intel_read_infoframe(struct intel_encoder *encoder, 677 const struct intel_crtc_state *crtc_state, 678 enum hdmi_infoframe_type type, 679 union hdmi_infoframe *frame) 680 { 681 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 682 u8 buffer[VIDEO_DIP_DATA_SIZE]; 683 int ret; 684 685 if ((crtc_state->infoframes.enable & 686 intel_hdmi_infoframe_enable(type)) == 0) 687 return; 688 689 dig_port->read_infoframe(encoder, crtc_state, 690 type, buffer, sizeof(buffer)); 691 692 /* Fill the 'hole' (see big comment above) at position 3 */ 693 memmove(&buffer[1], &buffer[0], 3); 694 695 /* see comment above for the reason for this offset */ 696 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 697 if (ret) { 698 drm_dbg_kms(encoder->base.dev, 699 "Failed to unpack infoframe type 0x%02x\n", type); 700 return; 701 } 702 703 if (frame->any.type != type) 704 drm_dbg_kms(encoder->base.dev, 705 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 706 frame->any.type, type); 707 } 708 709 static bool 710 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 711 struct intel_crtc_state *crtc_state, 712 struct drm_connector_state *conn_state) 713 { 714 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 715 const struct drm_display_mode *adjusted_mode = 716 &crtc_state->hw.adjusted_mode; 717 struct drm_connector *connector = conn_state->connector; 718 int ret; 719 720 if (!crtc_state->has_infoframe) 721 return true; 722 723 crtc_state->infoframes.enable |= 724 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 725 726 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 727 adjusted_mode); 728 if (ret) 729 return false; 730 731 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 732 frame->colorspace = HDMI_COLORSPACE_YUV420; 733 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 734 frame->colorspace = HDMI_COLORSPACE_YUV444; 735 else 736 frame->colorspace = HDMI_COLORSPACE_RGB; 737 738 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 739 740 /* nonsense combination */ 741 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 742 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 743 744 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 745 drm_hdmi_avi_infoframe_quant_range(frame, connector, 746 adjusted_mode, 747 crtc_state->limited_color_range ? 748 HDMI_QUANTIZATION_RANGE_LIMITED : 749 HDMI_QUANTIZATION_RANGE_FULL); 750 } else { 751 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 752 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 753 } 754 755 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 756 757 /* TODO: handle pixel repetition for YCBCR420 outputs */ 758 759 ret = hdmi_avi_infoframe_check(frame); 760 if (drm_WARN_ON(encoder->base.dev, ret)) 761 return false; 762 763 return true; 764 } 765 766 static bool 767 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 768 struct intel_crtc_state *crtc_state, 769 struct drm_connector_state *conn_state) 770 { 771 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 772 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 773 int ret; 774 775 if (!crtc_state->has_infoframe) 776 return true; 777 778 crtc_state->infoframes.enable |= 779 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 780 781 if (IS_DGFX(i915)) 782 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 783 else 784 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 785 786 if (drm_WARN_ON(encoder->base.dev, ret)) 787 return false; 788 789 frame->sdi = HDMI_SPD_SDI_PC; 790 791 ret = hdmi_spd_infoframe_check(frame); 792 if (drm_WARN_ON(encoder->base.dev, ret)) 793 return false; 794 795 return true; 796 } 797 798 static bool 799 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 800 struct intel_crtc_state *crtc_state, 801 struct drm_connector_state *conn_state) 802 { 803 struct hdmi_vendor_infoframe *frame = 804 &crtc_state->infoframes.hdmi.vendor.hdmi; 805 const struct drm_display_info *info = 806 &conn_state->connector->display_info; 807 int ret; 808 809 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 810 return true; 811 812 crtc_state->infoframes.enable |= 813 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 814 815 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 816 conn_state->connector, 817 &crtc_state->hw.adjusted_mode); 818 if (drm_WARN_ON(encoder->base.dev, ret)) 819 return false; 820 821 ret = hdmi_vendor_infoframe_check(frame); 822 if (drm_WARN_ON(encoder->base.dev, ret)) 823 return false; 824 825 return true; 826 } 827 828 static bool 829 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 830 struct intel_crtc_state *crtc_state, 831 struct drm_connector_state *conn_state) 832 { 833 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 834 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 835 int ret; 836 837 if (DISPLAY_VER(dev_priv) < 10) 838 return true; 839 840 if (!crtc_state->has_infoframe) 841 return true; 842 843 if (!conn_state->hdr_output_metadata) 844 return true; 845 846 crtc_state->infoframes.enable |= 847 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 848 849 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 850 if (ret < 0) { 851 drm_dbg_kms(&dev_priv->drm, 852 "couldn't set HDR metadata in infoframe\n"); 853 return false; 854 } 855 856 ret = hdmi_drm_infoframe_check(frame); 857 if (drm_WARN_ON(&dev_priv->drm, ret)) 858 return false; 859 860 return true; 861 } 862 863 static void g4x_set_infoframes(struct intel_encoder *encoder, 864 bool enable, 865 const struct intel_crtc_state *crtc_state, 866 const struct drm_connector_state *conn_state) 867 { 868 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 869 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 870 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 871 i915_reg_t reg = VIDEO_DIP_CTL; 872 u32 val = intel_de_read(dev_priv, reg); 873 u32 port = VIDEO_DIP_PORT(encoder->port); 874 875 assert_hdmi_port_disabled(intel_hdmi); 876 877 /* If the registers were not initialized yet, they might be zeroes, 878 * which means we're selecting the AVI DIP and we're setting its 879 * frequency to once. This seems to really confuse the HW and make 880 * things stop working (the register spec says the AVI always needs to 881 * be sent every VSync). So here we avoid writing to the register more 882 * than we need and also explicitly select the AVI DIP and explicitly 883 * set its frequency to every VSync. Avoiding to write it twice seems to 884 * be enough to solve the problem, but being defensive shouldn't hurt us 885 * either. */ 886 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 887 888 if (!enable) { 889 if (!(val & VIDEO_DIP_ENABLE)) 890 return; 891 if (port != (val & VIDEO_DIP_PORT_MASK)) { 892 drm_dbg_kms(&dev_priv->drm, 893 "video DIP still enabled on port %c\n", 894 (val & VIDEO_DIP_PORT_MASK) >> 29); 895 return; 896 } 897 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 898 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 899 intel_de_write(dev_priv, reg, val); 900 intel_de_posting_read(dev_priv, reg); 901 return; 902 } 903 904 if (port != (val & VIDEO_DIP_PORT_MASK)) { 905 if (val & VIDEO_DIP_ENABLE) { 906 drm_dbg_kms(&dev_priv->drm, 907 "video DIP already enabled on port %c\n", 908 (val & VIDEO_DIP_PORT_MASK) >> 29); 909 return; 910 } 911 val &= ~VIDEO_DIP_PORT_MASK; 912 val |= port; 913 } 914 915 val |= VIDEO_DIP_ENABLE; 916 val &= ~(VIDEO_DIP_ENABLE_AVI | 917 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 918 919 intel_de_write(dev_priv, reg, val); 920 intel_de_posting_read(dev_priv, reg); 921 922 intel_write_infoframe(encoder, crtc_state, 923 HDMI_INFOFRAME_TYPE_AVI, 924 &crtc_state->infoframes.avi); 925 intel_write_infoframe(encoder, crtc_state, 926 HDMI_INFOFRAME_TYPE_SPD, 927 &crtc_state->infoframes.spd); 928 intel_write_infoframe(encoder, crtc_state, 929 HDMI_INFOFRAME_TYPE_VENDOR, 930 &crtc_state->infoframes.hdmi); 931 } 932 933 /* 934 * Determine if default_phase=1 can be indicated in the GCP infoframe. 935 * 936 * From HDMI specification 1.4a: 937 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 938 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 939 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 940 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 941 * phase of 0 942 */ 943 static bool gcp_default_phase_possible(int pipe_bpp, 944 const struct drm_display_mode *mode) 945 { 946 unsigned int pixels_per_group; 947 948 switch (pipe_bpp) { 949 case 30: 950 /* 4 pixels in 5 clocks */ 951 pixels_per_group = 4; 952 break; 953 case 36: 954 /* 2 pixels in 3 clocks */ 955 pixels_per_group = 2; 956 break; 957 case 48: 958 /* 1 pixel in 2 clocks */ 959 pixels_per_group = 1; 960 break; 961 default: 962 /* phase information not relevant for 8bpc */ 963 return false; 964 } 965 966 return mode->crtc_hdisplay % pixels_per_group == 0 && 967 mode->crtc_htotal % pixels_per_group == 0 && 968 mode->crtc_hblank_start % pixels_per_group == 0 && 969 mode->crtc_hblank_end % pixels_per_group == 0 && 970 mode->crtc_hsync_start % pixels_per_group == 0 && 971 mode->crtc_hsync_end % pixels_per_group == 0 && 972 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 973 mode->crtc_htotal/2 % pixels_per_group == 0); 974 } 975 976 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 977 const struct intel_crtc_state *crtc_state, 978 const struct drm_connector_state *conn_state) 979 { 980 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 981 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 982 i915_reg_t reg; 983 984 if ((crtc_state->infoframes.enable & 985 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 986 return false; 987 988 if (HAS_DDI(dev_priv)) 989 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 990 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 991 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 992 else if (HAS_PCH_SPLIT(dev_priv)) 993 reg = TVIDEO_DIP_GCP(crtc->pipe); 994 else 995 return false; 996 997 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 998 999 return true; 1000 } 1001 1002 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1003 struct intel_crtc_state *crtc_state) 1004 { 1005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1007 i915_reg_t reg; 1008 1009 if ((crtc_state->infoframes.enable & 1010 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1011 return; 1012 1013 if (HAS_DDI(dev_priv)) 1014 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1015 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1016 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1017 else if (HAS_PCH_SPLIT(dev_priv)) 1018 reg = TVIDEO_DIP_GCP(crtc->pipe); 1019 else 1020 return; 1021 1022 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1023 } 1024 1025 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1026 struct intel_crtc_state *crtc_state, 1027 struct drm_connector_state *conn_state) 1028 { 1029 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1030 1031 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1032 return; 1033 1034 crtc_state->infoframes.enable |= 1035 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1036 1037 /* Indicate color indication for deep color mode */ 1038 if (crtc_state->pipe_bpp > 24) 1039 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1040 1041 /* Enable default_phase whenever the display mode is suitably aligned */ 1042 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1043 &crtc_state->hw.adjusted_mode)) 1044 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1045 } 1046 1047 static void ibx_set_infoframes(struct intel_encoder *encoder, 1048 bool enable, 1049 const struct intel_crtc_state *crtc_state, 1050 const struct drm_connector_state *conn_state) 1051 { 1052 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1053 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1054 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1055 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1056 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1057 u32 val = intel_de_read(dev_priv, reg); 1058 u32 port = VIDEO_DIP_PORT(encoder->port); 1059 1060 assert_hdmi_port_disabled(intel_hdmi); 1061 1062 /* See the big comment in g4x_set_infoframes() */ 1063 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1064 1065 if (!enable) { 1066 if (!(val & VIDEO_DIP_ENABLE)) 1067 return; 1068 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1069 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1070 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1071 intel_de_write(dev_priv, reg, val); 1072 intel_de_posting_read(dev_priv, reg); 1073 return; 1074 } 1075 1076 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1077 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1078 "DIP already enabled on port %c\n", 1079 (val & VIDEO_DIP_PORT_MASK) >> 29); 1080 val &= ~VIDEO_DIP_PORT_MASK; 1081 val |= port; 1082 } 1083 1084 val |= VIDEO_DIP_ENABLE; 1085 val &= ~(VIDEO_DIP_ENABLE_AVI | 1086 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1087 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1088 1089 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1090 val |= VIDEO_DIP_ENABLE_GCP; 1091 1092 intel_de_write(dev_priv, reg, val); 1093 intel_de_posting_read(dev_priv, reg); 1094 1095 intel_write_infoframe(encoder, crtc_state, 1096 HDMI_INFOFRAME_TYPE_AVI, 1097 &crtc_state->infoframes.avi); 1098 intel_write_infoframe(encoder, crtc_state, 1099 HDMI_INFOFRAME_TYPE_SPD, 1100 &crtc_state->infoframes.spd); 1101 intel_write_infoframe(encoder, crtc_state, 1102 HDMI_INFOFRAME_TYPE_VENDOR, 1103 &crtc_state->infoframes.hdmi); 1104 } 1105 1106 static void cpt_set_infoframes(struct intel_encoder *encoder, 1107 bool enable, 1108 const struct intel_crtc_state *crtc_state, 1109 const struct drm_connector_state *conn_state) 1110 { 1111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1112 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1113 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1114 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1115 u32 val = intel_de_read(dev_priv, reg); 1116 1117 assert_hdmi_port_disabled(intel_hdmi); 1118 1119 /* See the big comment in g4x_set_infoframes() */ 1120 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1121 1122 if (!enable) { 1123 if (!(val & VIDEO_DIP_ENABLE)) 1124 return; 1125 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1126 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1127 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1128 intel_de_write(dev_priv, reg, val); 1129 intel_de_posting_read(dev_priv, reg); 1130 return; 1131 } 1132 1133 /* Set both together, unset both together: see the spec. */ 1134 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1135 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1136 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1137 1138 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1139 val |= VIDEO_DIP_ENABLE_GCP; 1140 1141 intel_de_write(dev_priv, reg, val); 1142 intel_de_posting_read(dev_priv, reg); 1143 1144 intel_write_infoframe(encoder, crtc_state, 1145 HDMI_INFOFRAME_TYPE_AVI, 1146 &crtc_state->infoframes.avi); 1147 intel_write_infoframe(encoder, crtc_state, 1148 HDMI_INFOFRAME_TYPE_SPD, 1149 &crtc_state->infoframes.spd); 1150 intel_write_infoframe(encoder, crtc_state, 1151 HDMI_INFOFRAME_TYPE_VENDOR, 1152 &crtc_state->infoframes.hdmi); 1153 } 1154 1155 static void vlv_set_infoframes(struct intel_encoder *encoder, 1156 bool enable, 1157 const struct intel_crtc_state *crtc_state, 1158 const struct drm_connector_state *conn_state) 1159 { 1160 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1161 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1162 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1163 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1164 u32 val = intel_de_read(dev_priv, reg); 1165 u32 port = VIDEO_DIP_PORT(encoder->port); 1166 1167 assert_hdmi_port_disabled(intel_hdmi); 1168 1169 /* See the big comment in g4x_set_infoframes() */ 1170 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1171 1172 if (!enable) { 1173 if (!(val & VIDEO_DIP_ENABLE)) 1174 return; 1175 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1176 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1177 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1178 intel_de_write(dev_priv, reg, val); 1179 intel_de_posting_read(dev_priv, reg); 1180 return; 1181 } 1182 1183 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1184 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1185 "DIP already enabled on port %c\n", 1186 (val & VIDEO_DIP_PORT_MASK) >> 29); 1187 val &= ~VIDEO_DIP_PORT_MASK; 1188 val |= port; 1189 } 1190 1191 val |= VIDEO_DIP_ENABLE; 1192 val &= ~(VIDEO_DIP_ENABLE_AVI | 1193 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1194 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1195 1196 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1197 val |= VIDEO_DIP_ENABLE_GCP; 1198 1199 intel_de_write(dev_priv, reg, val); 1200 intel_de_posting_read(dev_priv, reg); 1201 1202 intel_write_infoframe(encoder, crtc_state, 1203 HDMI_INFOFRAME_TYPE_AVI, 1204 &crtc_state->infoframes.avi); 1205 intel_write_infoframe(encoder, crtc_state, 1206 HDMI_INFOFRAME_TYPE_SPD, 1207 &crtc_state->infoframes.spd); 1208 intel_write_infoframe(encoder, crtc_state, 1209 HDMI_INFOFRAME_TYPE_VENDOR, 1210 &crtc_state->infoframes.hdmi); 1211 } 1212 1213 static void hsw_set_infoframes(struct intel_encoder *encoder, 1214 bool enable, 1215 const struct intel_crtc_state *crtc_state, 1216 const struct drm_connector_state *conn_state) 1217 { 1218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1219 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1220 u32 val = intel_de_read(dev_priv, reg); 1221 1222 assert_hdmi_transcoder_func_disabled(dev_priv, 1223 crtc_state->cpu_transcoder); 1224 1225 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1226 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1227 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1228 VIDEO_DIP_ENABLE_DRM_GLK); 1229 1230 if (!enable) { 1231 intel_de_write(dev_priv, reg, val); 1232 intel_de_posting_read(dev_priv, reg); 1233 return; 1234 } 1235 1236 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1237 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1238 1239 intel_de_write(dev_priv, reg, val); 1240 intel_de_posting_read(dev_priv, reg); 1241 1242 intel_write_infoframe(encoder, crtc_state, 1243 HDMI_INFOFRAME_TYPE_AVI, 1244 &crtc_state->infoframes.avi); 1245 intel_write_infoframe(encoder, crtc_state, 1246 HDMI_INFOFRAME_TYPE_SPD, 1247 &crtc_state->infoframes.spd); 1248 intel_write_infoframe(encoder, crtc_state, 1249 HDMI_INFOFRAME_TYPE_VENDOR, 1250 &crtc_state->infoframes.hdmi); 1251 intel_write_infoframe(encoder, crtc_state, 1252 HDMI_INFOFRAME_TYPE_DRM, 1253 &crtc_state->infoframes.drm); 1254 } 1255 1256 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1257 { 1258 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1259 struct i2c_adapter *adapter; 1260 1261 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1262 return; 1263 1264 adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1265 1266 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", 1267 enable ? "Enabling" : "Disabling"); 1268 1269 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable); 1270 } 1271 1272 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1273 unsigned int offset, void *buffer, size_t size) 1274 { 1275 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1276 struct intel_hdmi *hdmi = &dig_port->hdmi; 1277 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1278 hdmi->ddc_bus); 1279 int ret; 1280 u8 start = offset & 0xff; 1281 struct i2c_msg msgs[] = { 1282 { 1283 .addr = DRM_HDCP_DDC_ADDR, 1284 .flags = 0, 1285 .len = 1, 1286 .buf = &start, 1287 }, 1288 { 1289 .addr = DRM_HDCP_DDC_ADDR, 1290 .flags = I2C_M_RD, 1291 .len = size, 1292 .buf = buffer 1293 } 1294 }; 1295 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1296 if (ret == ARRAY_SIZE(msgs)) 1297 return 0; 1298 return ret >= 0 ? -EIO : ret; 1299 } 1300 1301 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1302 unsigned int offset, void *buffer, size_t size) 1303 { 1304 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1305 struct intel_hdmi *hdmi = &dig_port->hdmi; 1306 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1307 hdmi->ddc_bus); 1308 int ret; 1309 u8 *write_buf; 1310 struct i2c_msg msg; 1311 1312 write_buf = kzalloc(size + 1, GFP_KERNEL); 1313 if (!write_buf) 1314 return -ENOMEM; 1315 1316 write_buf[0] = offset & 0xff; 1317 memcpy(&write_buf[1], buffer, size); 1318 1319 msg.addr = DRM_HDCP_DDC_ADDR; 1320 msg.flags = 0, 1321 msg.len = size + 1, 1322 msg.buf = write_buf; 1323 1324 ret = i2c_transfer(adapter, &msg, 1); 1325 if (ret == 1) 1326 ret = 0; 1327 else if (ret >= 0) 1328 ret = -EIO; 1329 1330 kfree(write_buf); 1331 return ret; 1332 } 1333 1334 static 1335 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1336 u8 *an) 1337 { 1338 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1339 struct intel_hdmi *hdmi = &dig_port->hdmi; 1340 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1341 hdmi->ddc_bus); 1342 int ret; 1343 1344 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1345 DRM_HDCP_AN_LEN); 1346 if (ret) { 1347 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", 1348 ret); 1349 return ret; 1350 } 1351 1352 ret = intel_gmbus_output_aksv(adapter); 1353 if (ret < 0) { 1354 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); 1355 return ret; 1356 } 1357 return 0; 1358 } 1359 1360 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1361 u8 *bksv) 1362 { 1363 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1364 1365 int ret; 1366 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1367 DRM_HDCP_KSV_LEN); 1368 if (ret) 1369 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", 1370 ret); 1371 return ret; 1372 } 1373 1374 static 1375 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1376 u8 *bstatus) 1377 { 1378 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1379 1380 int ret; 1381 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1382 bstatus, DRM_HDCP_BSTATUS_LEN); 1383 if (ret) 1384 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", 1385 ret); 1386 return ret; 1387 } 1388 1389 static 1390 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1391 bool *repeater_present) 1392 { 1393 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1394 int ret; 1395 u8 val; 1396 1397 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1398 if (ret) { 1399 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1400 ret); 1401 return ret; 1402 } 1403 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1404 return 0; 1405 } 1406 1407 static 1408 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1409 u8 *ri_prime) 1410 { 1411 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1412 1413 int ret; 1414 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1415 ri_prime, DRM_HDCP_RI_LEN); 1416 if (ret) 1417 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", 1418 ret); 1419 return ret; 1420 } 1421 1422 static 1423 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1424 bool *ksv_ready) 1425 { 1426 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1427 int ret; 1428 u8 val; 1429 1430 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1431 if (ret) { 1432 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1433 ret); 1434 return ret; 1435 } 1436 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1437 return 0; 1438 } 1439 1440 static 1441 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1442 int num_downstream, u8 *ksv_fifo) 1443 { 1444 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1445 int ret; 1446 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1447 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1448 if (ret) { 1449 drm_dbg_kms(&i915->drm, 1450 "Read ksv fifo over DDC failed (%d)\n", ret); 1451 return ret; 1452 } 1453 return 0; 1454 } 1455 1456 static 1457 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1458 int i, u32 *part) 1459 { 1460 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1461 int ret; 1462 1463 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1464 return -EINVAL; 1465 1466 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1467 part, DRM_HDCP_V_PRIME_PART_LEN); 1468 if (ret) 1469 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", 1470 i, ret); 1471 return ret; 1472 } 1473 1474 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1475 enum transcoder cpu_transcoder) 1476 { 1477 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1478 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1479 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1480 u32 scanline; 1481 int ret; 1482 1483 for (;;) { 1484 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe)); 1485 if (scanline > 100 && scanline < 200) 1486 break; 1487 usleep_range(25, 50); 1488 } 1489 1490 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1491 false, TRANS_DDI_HDCP_SIGNALLING); 1492 if (ret) { 1493 drm_err(&dev_priv->drm, 1494 "Disable HDCP signalling failed (%d)\n", ret); 1495 return ret; 1496 } 1497 1498 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1499 true, TRANS_DDI_HDCP_SIGNALLING); 1500 if (ret) { 1501 drm_err(&dev_priv->drm, 1502 "Enable HDCP signalling failed (%d)\n", ret); 1503 return ret; 1504 } 1505 1506 return 0; 1507 } 1508 1509 static 1510 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1511 enum transcoder cpu_transcoder, 1512 bool enable) 1513 { 1514 struct intel_hdmi *hdmi = &dig_port->hdmi; 1515 struct intel_connector *connector = hdmi->attached_connector; 1516 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1517 int ret; 1518 1519 if (!enable) 1520 usleep_range(6, 60); /* Bspec says >= 6us */ 1521 1522 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1523 cpu_transcoder, enable, 1524 TRANS_DDI_HDCP_SIGNALLING); 1525 if (ret) { 1526 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", 1527 enable ? "Enable" : "Disable", ret); 1528 return ret; 1529 } 1530 1531 /* 1532 * WA: To fix incorrect positioning of the window of 1533 * opportunity and enc_en signalling in KABYLAKE. 1534 */ 1535 if (IS_KABYLAKE(dev_priv) && enable) 1536 return kbl_repositioning_enc_en_signal(connector, 1537 cpu_transcoder); 1538 1539 return 0; 1540 } 1541 1542 static 1543 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1544 struct intel_connector *connector) 1545 { 1546 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1547 enum port port = dig_port->base.port; 1548 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1549 int ret; 1550 union { 1551 u32 reg; 1552 u8 shim[DRM_HDCP_RI_LEN]; 1553 } ri; 1554 1555 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1556 if (ret) 1557 return false; 1558 1559 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1560 1561 /* Wait for Ri prime match */ 1562 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1563 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1564 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1565 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", 1566 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1567 port))); 1568 return false; 1569 } 1570 return true; 1571 } 1572 1573 static 1574 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1575 struct intel_connector *connector) 1576 { 1577 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1578 int retry; 1579 1580 for (retry = 0; retry < 3; retry++) 1581 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1582 return true; 1583 1584 drm_err(&i915->drm, "Link check failed\n"); 1585 return false; 1586 } 1587 1588 struct hdcp2_hdmi_msg_timeout { 1589 u8 msg_id; 1590 u16 timeout; 1591 }; 1592 1593 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1594 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1595 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1596 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1597 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1598 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1599 }; 1600 1601 static 1602 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1603 u8 *rx_status) 1604 { 1605 return intel_hdmi_hdcp_read(dig_port, 1606 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1607 rx_status, 1608 HDCP_2_2_HDMI_RXSTATUS_LEN); 1609 } 1610 1611 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1612 { 1613 int i; 1614 1615 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1616 if (is_paired) 1617 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1618 else 1619 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1620 } 1621 1622 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1623 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1624 return hdcp2_msg_timeout[i].timeout; 1625 } 1626 1627 return -EINVAL; 1628 } 1629 1630 static int 1631 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1632 u8 msg_id, bool *msg_ready, 1633 ssize_t *msg_sz) 1634 { 1635 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1636 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1637 int ret; 1638 1639 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1640 if (ret < 0) { 1641 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", 1642 ret); 1643 return ret; 1644 } 1645 1646 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1647 rx_status[0]); 1648 1649 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1650 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1651 *msg_sz); 1652 else 1653 *msg_ready = *msg_sz; 1654 1655 return 0; 1656 } 1657 1658 static ssize_t 1659 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1660 u8 msg_id, bool paired) 1661 { 1662 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1663 bool msg_ready = false; 1664 int timeout, ret; 1665 ssize_t msg_sz = 0; 1666 1667 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1668 if (timeout < 0) 1669 return timeout; 1670 1671 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1672 msg_id, &msg_ready, 1673 &msg_sz), 1674 !ret && msg_ready && msg_sz, timeout * 1000, 1675 1000, 5 * 1000); 1676 if (ret) 1677 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", 1678 msg_id, ret, timeout); 1679 1680 return ret ? ret : msg_sz; 1681 } 1682 1683 static 1684 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, 1685 void *buf, size_t size) 1686 { 1687 unsigned int offset; 1688 1689 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1690 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1691 } 1692 1693 static 1694 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, 1695 u8 msg_id, void *buf, size_t size) 1696 { 1697 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1698 struct intel_hdmi *hdmi = &dig_port->hdmi; 1699 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1700 unsigned int offset; 1701 ssize_t ret; 1702 1703 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1704 hdcp->is_paired); 1705 if (ret < 0) 1706 return ret; 1707 1708 /* 1709 * Available msg size should be equal to or lesser than the 1710 * available buffer. 1711 */ 1712 if (ret > size) { 1713 drm_dbg_kms(&i915->drm, 1714 "msg_sz(%zd) is more than exp size(%zu)\n", 1715 ret, size); 1716 return -EINVAL; 1717 } 1718 1719 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1720 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1721 if (ret) 1722 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", 1723 msg_id, ret); 1724 1725 return ret; 1726 } 1727 1728 static 1729 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1730 struct intel_connector *connector) 1731 { 1732 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1733 int ret; 1734 1735 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1736 if (ret) 1737 return ret; 1738 1739 /* 1740 * Re-auth request and Link Integrity Failures are represented by 1741 * same bit. i.e reauth_req. 1742 */ 1743 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1744 ret = HDCP_REAUTH_REQUEST; 1745 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1746 ret = HDCP_TOPOLOGY_CHANGE; 1747 1748 return ret; 1749 } 1750 1751 static 1752 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, 1753 bool *capable) 1754 { 1755 u8 hdcp2_version; 1756 int ret; 1757 1758 *capable = false; 1759 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1760 &hdcp2_version, sizeof(hdcp2_version)); 1761 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1762 *capable = true; 1763 1764 return ret; 1765 } 1766 1767 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1768 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1769 .read_bksv = intel_hdmi_hdcp_read_bksv, 1770 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1771 .repeater_present = intel_hdmi_hdcp_repeater_present, 1772 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1773 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1774 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1775 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1776 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1777 .check_link = intel_hdmi_hdcp_check_link, 1778 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1779 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1780 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1781 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1782 .protocol = HDCP_PROTOCOL_HDMI, 1783 }; 1784 1785 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1786 { 1787 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1788 int max_tmds_clock, vbt_max_tmds_clock; 1789 1790 if (DISPLAY_VER(dev_priv) >= 10) 1791 max_tmds_clock = 594000; 1792 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 1793 max_tmds_clock = 300000; 1794 else if (DISPLAY_VER(dev_priv) >= 5) 1795 max_tmds_clock = 225000; 1796 else 1797 max_tmds_clock = 165000; 1798 1799 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); 1800 if (vbt_max_tmds_clock) 1801 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1802 1803 return max_tmds_clock; 1804 } 1805 1806 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1807 const struct drm_connector_state *conn_state) 1808 { 1809 return hdmi->has_hdmi_sink && 1810 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1811 } 1812 1813 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1814 { 1815 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1816 } 1817 1818 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1819 bool respect_downstream_limits, 1820 bool has_hdmi_sink) 1821 { 1822 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1823 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1824 1825 if (respect_downstream_limits) { 1826 struct intel_connector *connector = hdmi->attached_connector; 1827 const struct drm_display_info *info = &connector->base.display_info; 1828 1829 if (hdmi->dp_dual_mode.max_tmds_clock) 1830 max_tmds_clock = min(max_tmds_clock, 1831 hdmi->dp_dual_mode.max_tmds_clock); 1832 1833 if (info->max_tmds_clock) 1834 max_tmds_clock = min(max_tmds_clock, 1835 info->max_tmds_clock); 1836 else if (!has_hdmi_sink) 1837 max_tmds_clock = min(max_tmds_clock, 165000); 1838 } 1839 1840 return max_tmds_clock; 1841 } 1842 1843 static enum drm_mode_status 1844 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1845 int clock, bool respect_downstream_limits, 1846 bool has_hdmi_sink) 1847 { 1848 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1849 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port); 1850 1851 if (clock < 25000) 1852 return MODE_CLOCK_LOW; 1853 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1854 has_hdmi_sink)) 1855 return MODE_CLOCK_HIGH; 1856 1857 /* GLK DPLL can't generate 446-480 MHz */ 1858 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1859 return MODE_CLOCK_RANGE; 1860 1861 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1862 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1863 clock > 223333 && clock < 240000) 1864 return MODE_CLOCK_RANGE; 1865 1866 /* CHV DPLL can't generate 216-240 MHz */ 1867 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1868 return MODE_CLOCK_RANGE; 1869 1870 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1871 if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200) 1872 return MODE_CLOCK_RANGE; 1873 1874 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1875 if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800) 1876 return MODE_CLOCK_RANGE; 1877 1878 /* 1879 * SNPS PHYs' MPLLB table-based programming can only handle a fixed 1880 * set of link rates. 1881 * 1882 * FIXME: We will hopefully get an algorithmic way of programming 1883 * the MPLLB for HDMI in the future. 1884 */ 1885 if (IS_DG2(dev_priv)) 1886 return intel_snps_phy_check_hdmi_link_rate(clock); 1887 1888 return MODE_OK; 1889 } 1890 1891 int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output) 1892 { 1893 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1894 if (ycbcr420_output) 1895 clock /= 2; 1896 1897 /* 1898 * Need to adjust the port link by: 1899 * 1.5x for 12bpc 1900 * 1.25x for 10bpc 1901 */ 1902 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1903 } 1904 1905 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc) 1906 { 1907 switch (bpc) { 1908 case 12: 1909 return !HAS_GMCH(i915); 1910 case 10: 1911 return DISPLAY_VER(i915) >= 11; 1912 case 8: 1913 return true; 1914 default: 1915 MISSING_CASE(bpc); 1916 return false; 1917 } 1918 } 1919 1920 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, 1921 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 1922 { 1923 const struct drm_display_info *info = &connector->display_info; 1924 const struct drm_hdmi_info *hdmi = &info->hdmi; 1925 1926 switch (bpc) { 1927 case 12: 1928 if (!has_hdmi_sink) 1929 return false; 1930 1931 if (ycbcr420_output) 1932 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1933 else 1934 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1935 case 10: 1936 if (!has_hdmi_sink) 1937 return false; 1938 1939 if (ycbcr420_output) 1940 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1941 else 1942 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1943 case 8: 1944 return true; 1945 default: 1946 MISSING_CASE(bpc); 1947 return false; 1948 } 1949 } 1950 1951 static enum drm_mode_status 1952 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, 1953 bool has_hdmi_sink, bool ycbcr420_output) 1954 { 1955 struct drm_i915_private *i915 = to_i915(connector->dev); 1956 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1957 enum drm_mode_status status = MODE_OK; 1958 int bpc; 1959 1960 /* 1961 * Try all color depths since valid port clock range 1962 * can have holes. Any mode that can be used with at 1963 * least one color depth is accepted. 1964 */ 1965 for (bpc = 12; bpc >= 8; bpc -= 2) { 1966 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output); 1967 1968 if (!intel_hdmi_source_bpc_possible(i915, bpc)) 1969 continue; 1970 1971 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output)) 1972 continue; 1973 1974 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 1975 if (status == MODE_OK) 1976 return MODE_OK; 1977 } 1978 1979 /* can never happen */ 1980 drm_WARN_ON(&i915->drm, status == MODE_OK); 1981 1982 return status; 1983 } 1984 1985 static enum drm_mode_status 1986 intel_hdmi_mode_valid(struct drm_connector *connector, 1987 struct drm_display_mode *mode) 1988 { 1989 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1990 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1991 enum drm_mode_status status; 1992 int clock = mode->clock; 1993 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1994 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 1995 bool ycbcr_420_only; 1996 1997 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1998 clock *= 2; 1999 2000 if (clock > max_dotclk) 2001 return MODE_CLOCK_HIGH; 2002 2003 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2004 if (!has_hdmi_sink) 2005 return MODE_CLOCK_LOW; 2006 clock *= 2; 2007 } 2008 2009 /* 2010 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2011 * enumerated only if FRL is supported. Current platforms do not support 2012 * FRL so prune the higher resolution modes that require doctclock more 2013 * than 600MHz. 2014 */ 2015 if (clock > 600000) 2016 return MODE_CLOCK_HIGH; 2017 2018 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 2019 2020 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only); 2021 if (status != MODE_OK) { 2022 if (ycbcr_420_only || 2023 !connector->ycbcr_420_allowed || 2024 !drm_mode_is_420_also(&connector->display_info, mode)) 2025 return status; 2026 2027 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true); 2028 if (status != MODE_OK) 2029 return status; 2030 } 2031 2032 return intel_mode_valid_max_plane_size(dev_priv, mode, false); 2033 } 2034 2035 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2036 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 2037 { 2038 struct drm_atomic_state *state = crtc_state->uapi.state; 2039 struct drm_connector_state *connector_state; 2040 struct drm_connector *connector; 2041 int i; 2042 2043 for_each_new_connector_in_state(state, connector, connector_state, i) { 2044 if (connector_state->crtc != crtc_state->uapi.crtc) 2045 continue; 2046 2047 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output)) 2048 return false; 2049 } 2050 2051 return true; 2052 } 2053 2054 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2055 { 2056 struct drm_i915_private *dev_priv = 2057 to_i915(crtc_state->uapi.crtc->dev); 2058 const struct drm_display_mode *adjusted_mode = 2059 &crtc_state->hw.adjusted_mode; 2060 2061 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc)) 2062 return false; 2063 2064 /* Display Wa_1405510057:icl,ehl */ 2065 if (intel_hdmi_is_ycbcr420(crtc_state) && 2066 bpc == 10 && DISPLAY_VER(dev_priv) == 11 && 2067 (adjusted_mode->crtc_hblank_end - 2068 adjusted_mode->crtc_hblank_start) % 8 == 2) 2069 return false; 2070 2071 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink, 2072 intel_hdmi_is_ycbcr420(crtc_state)); 2073 } 2074 2075 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2076 struct intel_crtc_state *crtc_state, 2077 int clock, bool respect_downstream_limits) 2078 { 2079 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2080 bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state); 2081 int bpc; 2082 2083 /* 2084 * pipe_bpp could already be below 8bpc due to FDI 2085 * bandwidth constraints. HDMI minimum is 8bpc however. 2086 */ 2087 bpc = max(crtc_state->pipe_bpp / 3, 8); 2088 2089 /* 2090 * We will never exceed downstream TMDS clock limits while 2091 * attempting deep color. If the user insists on forcing an 2092 * out of spec mode they will have to be satisfied with 8bpc. 2093 */ 2094 if (!respect_downstream_limits) 2095 bpc = 8; 2096 2097 for (; bpc >= 8; bpc -= 2) { 2098 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output); 2099 2100 if (hdmi_bpc_possible(crtc_state, bpc) && 2101 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2102 respect_downstream_limits, 2103 crtc_state->has_hdmi_sink) == MODE_OK) 2104 return bpc; 2105 } 2106 2107 return -EINVAL; 2108 } 2109 2110 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2111 struct intel_crtc_state *crtc_state, 2112 bool respect_downstream_limits) 2113 { 2114 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2115 const struct drm_display_mode *adjusted_mode = 2116 &crtc_state->hw.adjusted_mode; 2117 int bpc, clock = adjusted_mode->crtc_clock; 2118 2119 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2120 clock *= 2; 2121 2122 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2123 respect_downstream_limits); 2124 if (bpc < 0) 2125 return bpc; 2126 2127 crtc_state->port_clock = 2128 intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state)); 2129 2130 /* 2131 * pipe_bpp could already be below 8bpc due to 2132 * FDI bandwidth constraints. We shouldn't bump it 2133 * back up to the HDMI minimum 8bpc in that case. 2134 */ 2135 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2136 2137 drm_dbg_kms(&i915->drm, 2138 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2139 bpc, crtc_state->pipe_bpp); 2140 2141 return 0; 2142 } 2143 2144 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2145 const struct drm_connector_state *conn_state) 2146 { 2147 const struct intel_digital_connector_state *intel_conn_state = 2148 to_intel_digital_connector_state(conn_state); 2149 const struct drm_display_mode *adjusted_mode = 2150 &crtc_state->hw.adjusted_mode; 2151 2152 /* 2153 * Our YCbCr output is always limited range. 2154 * crtc_state->limited_color_range only applies to RGB, 2155 * and it must never be set for YCbCr or we risk setting 2156 * some conflicting bits in PIPECONF which will mess up 2157 * the colors on the monitor. 2158 */ 2159 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2160 return false; 2161 2162 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2163 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2164 return crtc_state->has_hdmi_sink && 2165 drm_default_rgb_quant_range(adjusted_mode) == 2166 HDMI_QUANTIZATION_RANGE_LIMITED; 2167 } else { 2168 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2169 } 2170 } 2171 2172 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2173 const struct intel_crtc_state *crtc_state, 2174 const struct drm_connector_state *conn_state) 2175 { 2176 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2177 const struct intel_digital_connector_state *intel_conn_state = 2178 to_intel_digital_connector_state(conn_state); 2179 2180 if (!crtc_state->has_hdmi_sink) 2181 return false; 2182 2183 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2184 return intel_hdmi->has_audio; 2185 else 2186 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2187 } 2188 2189 static enum intel_output_format 2190 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state, 2191 struct intel_connector *connector, 2192 bool ycbcr_420_output) 2193 { 2194 if (!crtc_state->has_hdmi_sink) 2195 return INTEL_OUTPUT_FORMAT_RGB; 2196 2197 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2198 return INTEL_OUTPUT_FORMAT_YCBCR420; 2199 else 2200 return INTEL_OUTPUT_FORMAT_RGB; 2201 } 2202 2203 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2204 struct intel_crtc_state *crtc_state, 2205 const struct drm_connector_state *conn_state, 2206 bool respect_downstream_limits) 2207 { 2208 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2209 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2210 const struct drm_display_info *info = &connector->base.display_info; 2211 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2212 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2213 int ret; 2214 2215 crtc_state->output_format = 2216 intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only); 2217 2218 if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) { 2219 drm_dbg_kms(&i915->drm, 2220 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2221 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 2222 } 2223 2224 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2225 if (ret) { 2226 if (intel_hdmi_is_ycbcr420(crtc_state) || 2227 !connector->base.ycbcr_420_allowed || 2228 !drm_mode_is_420_also(info, adjusted_mode)) 2229 return ret; 2230 2231 crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true); 2232 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2233 } 2234 2235 return ret; 2236 } 2237 2238 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2239 { 2240 return crtc_state->uapi.encoder_mask && 2241 !is_power_of_2(crtc_state->uapi.encoder_mask); 2242 } 2243 2244 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2245 struct intel_crtc_state *pipe_config, 2246 struct drm_connector_state *conn_state) 2247 { 2248 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2249 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2250 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2251 struct drm_connector *connector = conn_state->connector; 2252 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2253 int ret; 2254 2255 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2256 return -EINVAL; 2257 2258 if (!connector->interlace_allowed && 2259 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2260 return -EINVAL; 2261 2262 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2263 pipe_config->has_hdmi_sink = 2264 intel_has_hdmi_sink(intel_hdmi, conn_state) && 2265 !intel_hdmi_is_cloned(pipe_config); 2266 2267 if (pipe_config->has_hdmi_sink) 2268 pipe_config->has_infoframe = true; 2269 2270 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2271 pipe_config->pixel_multiplier = 2; 2272 2273 pipe_config->has_audio = 2274 intel_hdmi_has_audio(encoder, pipe_config, conn_state); 2275 2276 /* 2277 * Try to respect downstream TMDS clock limits first, if 2278 * that fails assume the user might know something we don't. 2279 */ 2280 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2281 if (ret) 2282 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2283 if (ret) { 2284 drm_dbg_kms(&dev_priv->drm, 2285 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2286 pipe_config->hw.adjusted_mode.crtc_clock); 2287 return ret; 2288 } 2289 2290 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2291 ret = intel_panel_fitting(pipe_config, conn_state); 2292 if (ret) 2293 return ret; 2294 } 2295 2296 pipe_config->limited_color_range = 2297 intel_hdmi_limited_color_range(pipe_config, conn_state); 2298 2299 if (conn_state->picture_aspect_ratio) 2300 adjusted_mode->picture_aspect_ratio = 2301 conn_state->picture_aspect_ratio; 2302 2303 pipe_config->lane_count = 4; 2304 2305 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) { 2306 if (scdc->scrambling.low_rates) 2307 pipe_config->hdmi_scrambling = true; 2308 2309 if (pipe_config->port_clock > 340000) { 2310 pipe_config->hdmi_scrambling = true; 2311 pipe_config->hdmi_high_tmds_clock_ratio = true; 2312 } 2313 } 2314 2315 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2316 conn_state); 2317 2318 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2319 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); 2320 return -EINVAL; 2321 } 2322 2323 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2324 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); 2325 return -EINVAL; 2326 } 2327 2328 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2329 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); 2330 return -EINVAL; 2331 } 2332 2333 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2334 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); 2335 return -EINVAL; 2336 } 2337 2338 return 0; 2339 } 2340 2341 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2342 { 2343 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2344 2345 /* 2346 * Give a hand to buggy BIOSen which forget to turn 2347 * the TMDS output buffers back on after a reboot. 2348 */ 2349 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2350 } 2351 2352 static void 2353 intel_hdmi_unset_edid(struct drm_connector *connector) 2354 { 2355 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2356 2357 intel_hdmi->has_hdmi_sink = false; 2358 intel_hdmi->has_audio = false; 2359 2360 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2361 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2362 2363 kfree(to_intel_connector(connector)->detect_edid); 2364 to_intel_connector(connector)->detect_edid = NULL; 2365 } 2366 2367 static void 2368 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) 2369 { 2370 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2371 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2372 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2373 struct i2c_adapter *adapter = 2374 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2375 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter); 2376 2377 /* 2378 * Type 1 DVI adaptors are not required to implement any 2379 * registers, so we can't always detect their presence. 2380 * Ideally we should be able to check the state of the 2381 * CONFIG1 pin, but no such luck on our hardware. 2382 * 2383 * The only method left to us is to check the VBT to see 2384 * if the port is a dual mode capable DP port. 2385 */ 2386 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2387 if (!connector->force && 2388 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2389 drm_dbg_kms(&dev_priv->drm, 2390 "Assuming DP dual mode adaptor presence based on VBT\n"); 2391 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2392 } else { 2393 type = DRM_DP_DUAL_MODE_NONE; 2394 } 2395 } 2396 2397 if (type == DRM_DP_DUAL_MODE_NONE) 2398 return; 2399 2400 hdmi->dp_dual_mode.type = type; 2401 hdmi->dp_dual_mode.max_tmds_clock = 2402 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter); 2403 2404 drm_dbg_kms(&dev_priv->drm, 2405 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2406 drm_dp_get_dual_mode_type_name(type), 2407 hdmi->dp_dual_mode.max_tmds_clock); 2408 2409 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2410 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) && 2411 !intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2412 drm_dbg_kms(&dev_priv->drm, 2413 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2414 hdmi->dp_dual_mode.max_tmds_clock = 0; 2415 } 2416 } 2417 2418 static bool 2419 intel_hdmi_set_edid(struct drm_connector *connector) 2420 { 2421 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2422 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2423 intel_wakeref_t wakeref; 2424 struct edid *edid; 2425 bool connected = false; 2426 struct i2c_adapter *i2c; 2427 2428 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2429 2430 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2431 2432 edid = drm_get_edid(connector, i2c); 2433 2434 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2435 drm_dbg_kms(&dev_priv->drm, 2436 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2437 intel_gmbus_force_bit(i2c, true); 2438 edid = drm_get_edid(connector, i2c); 2439 intel_gmbus_force_bit(i2c, false); 2440 } 2441 2442 to_intel_connector(connector)->detect_edid = edid; 2443 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2444 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2445 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2446 2447 intel_hdmi_dp_dual_mode_detect(connector); 2448 2449 connected = true; 2450 } 2451 2452 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2453 2454 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2455 2456 return connected; 2457 } 2458 2459 static enum drm_connector_status 2460 intel_hdmi_detect(struct drm_connector *connector, bool force) 2461 { 2462 enum drm_connector_status status = connector_status_disconnected; 2463 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2464 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2465 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2466 intel_wakeref_t wakeref; 2467 2468 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2469 connector->base.id, connector->name); 2470 2471 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 2472 return connector_status_disconnected; 2473 2474 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2475 2476 if (DISPLAY_VER(dev_priv) >= 11 && 2477 !intel_digital_port_connected(encoder)) 2478 goto out; 2479 2480 intel_hdmi_unset_edid(connector); 2481 2482 if (intel_hdmi_set_edid(connector)) 2483 status = connector_status_connected; 2484 2485 out: 2486 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2487 2488 if (status != connector_status_connected) 2489 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2490 2491 /* 2492 * Make sure the refs for power wells enabled during detect are 2493 * dropped to avoid a new detect cycle triggered by HPD polling. 2494 */ 2495 intel_display_power_flush_work(dev_priv); 2496 2497 return status; 2498 } 2499 2500 static void 2501 intel_hdmi_force(struct drm_connector *connector) 2502 { 2503 struct drm_i915_private *i915 = to_i915(connector->dev); 2504 2505 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2506 connector->base.id, connector->name); 2507 2508 intel_hdmi_unset_edid(connector); 2509 2510 if (connector->status != connector_status_connected) 2511 return; 2512 2513 intel_hdmi_set_edid(connector); 2514 } 2515 2516 static int intel_hdmi_get_modes(struct drm_connector *connector) 2517 { 2518 struct edid *edid; 2519 2520 edid = to_intel_connector(connector)->detect_edid; 2521 if (edid == NULL) 2522 return 0; 2523 2524 return intel_connector_update_modes(connector, edid); 2525 } 2526 2527 static struct i2c_adapter * 2528 intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2529 { 2530 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2531 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2532 2533 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2534 } 2535 2536 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2537 { 2538 struct drm_i915_private *i915 = to_i915(connector->dev); 2539 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2540 struct kobject *i2c_kobj = &adapter->dev.kobj; 2541 struct kobject *connector_kobj = &connector->kdev->kobj; 2542 int ret; 2543 2544 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2545 if (ret) 2546 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret); 2547 } 2548 2549 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2550 { 2551 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2552 struct kobject *i2c_kobj = &adapter->dev.kobj; 2553 struct kobject *connector_kobj = &connector->kdev->kobj; 2554 2555 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2556 } 2557 2558 static int 2559 intel_hdmi_connector_register(struct drm_connector *connector) 2560 { 2561 int ret; 2562 2563 ret = intel_connector_register(connector); 2564 if (ret) 2565 return ret; 2566 2567 intel_hdmi_create_i2c_symlink(connector); 2568 2569 return ret; 2570 } 2571 2572 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2573 { 2574 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2575 2576 cec_notifier_conn_unregister(n); 2577 2578 intel_hdmi_remove_i2c_symlink(connector); 2579 intel_connector_unregister(connector); 2580 } 2581 2582 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2583 .detect = intel_hdmi_detect, 2584 .force = intel_hdmi_force, 2585 .fill_modes = drm_helper_probe_single_connector_modes, 2586 .atomic_get_property = intel_digital_connector_atomic_get_property, 2587 .atomic_set_property = intel_digital_connector_atomic_set_property, 2588 .late_register = intel_hdmi_connector_register, 2589 .early_unregister = intel_hdmi_connector_unregister, 2590 .destroy = intel_connector_destroy, 2591 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2592 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2593 }; 2594 2595 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2596 .get_modes = intel_hdmi_get_modes, 2597 .mode_valid = intel_hdmi_mode_valid, 2598 .atomic_check = intel_digital_connector_atomic_check, 2599 }; 2600 2601 static void 2602 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2603 { 2604 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2605 2606 intel_attach_force_audio_property(connector); 2607 intel_attach_broadcast_rgb_property(connector); 2608 intel_attach_aspect_ratio_property(connector); 2609 2610 intel_attach_hdmi_colorspace_property(connector); 2611 drm_connector_attach_content_type_property(connector); 2612 2613 if (DISPLAY_VER(dev_priv) >= 10) 2614 drm_connector_attach_hdr_output_metadata_property(connector); 2615 2616 if (!HAS_GMCH(dev_priv)) 2617 drm_connector_attach_max_bpc_property(connector, 8, 12); 2618 } 2619 2620 /* 2621 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2622 * @encoder: intel_encoder 2623 * @connector: drm_connector 2624 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2625 * or reset the high tmds clock ratio for scrambling 2626 * @scrambling: bool to Indicate if the function needs to set or reset 2627 * sink scrambling 2628 * 2629 * This function handles scrambling on HDMI 2.0 capable sinks. 2630 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2631 * it enables scrambling. This should be called before enabling the HDMI 2632 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2633 * detect a scrambled clock within 100 ms. 2634 * 2635 * Returns: 2636 * True on success, false on failure. 2637 */ 2638 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2639 struct drm_connector *connector, 2640 bool high_tmds_clock_ratio, 2641 bool scrambling) 2642 { 2643 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2644 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2645 struct drm_scrambling *sink_scrambling = 2646 &connector->display_info.hdmi.scdc.scrambling; 2647 struct i2c_adapter *adapter = 2648 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2649 2650 if (!sink_scrambling->supported) 2651 return true; 2652 2653 drm_dbg_kms(&dev_priv->drm, 2654 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2655 connector->base.id, connector->name, 2656 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2657 2658 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2659 return drm_scdc_set_high_tmds_clock_ratio(adapter, 2660 high_tmds_clock_ratio) && 2661 drm_scdc_set_scrambling(adapter, scrambling); 2662 } 2663 2664 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2665 { 2666 u8 ddc_pin; 2667 2668 switch (port) { 2669 case PORT_B: 2670 ddc_pin = GMBUS_PIN_DPB; 2671 break; 2672 case PORT_C: 2673 ddc_pin = GMBUS_PIN_DPC; 2674 break; 2675 case PORT_D: 2676 ddc_pin = GMBUS_PIN_DPD_CHV; 2677 break; 2678 default: 2679 MISSING_CASE(port); 2680 ddc_pin = GMBUS_PIN_DPB; 2681 break; 2682 } 2683 return ddc_pin; 2684 } 2685 2686 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2687 { 2688 u8 ddc_pin; 2689 2690 switch (port) { 2691 case PORT_B: 2692 ddc_pin = GMBUS_PIN_1_BXT; 2693 break; 2694 case PORT_C: 2695 ddc_pin = GMBUS_PIN_2_BXT; 2696 break; 2697 default: 2698 MISSING_CASE(port); 2699 ddc_pin = GMBUS_PIN_1_BXT; 2700 break; 2701 } 2702 return ddc_pin; 2703 } 2704 2705 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2706 enum port port) 2707 { 2708 u8 ddc_pin; 2709 2710 switch (port) { 2711 case PORT_B: 2712 ddc_pin = GMBUS_PIN_1_BXT; 2713 break; 2714 case PORT_C: 2715 ddc_pin = GMBUS_PIN_2_BXT; 2716 break; 2717 case PORT_D: 2718 ddc_pin = GMBUS_PIN_4_CNP; 2719 break; 2720 case PORT_F: 2721 ddc_pin = GMBUS_PIN_3_BXT; 2722 break; 2723 default: 2724 MISSING_CASE(port); 2725 ddc_pin = GMBUS_PIN_1_BXT; 2726 break; 2727 } 2728 return ddc_pin; 2729 } 2730 2731 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2732 { 2733 enum phy phy = intel_port_to_phy(dev_priv, port); 2734 2735 if (intel_phy_is_combo(dev_priv, phy)) 2736 return GMBUS_PIN_1_BXT + port; 2737 else if (intel_phy_is_tc(dev_priv, phy)) 2738 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 2739 2740 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 2741 return GMBUS_PIN_2_BXT; 2742 } 2743 2744 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2745 { 2746 enum phy phy = intel_port_to_phy(dev_priv, port); 2747 u8 ddc_pin; 2748 2749 switch (phy) { 2750 case PHY_A: 2751 ddc_pin = GMBUS_PIN_1_BXT; 2752 break; 2753 case PHY_B: 2754 ddc_pin = GMBUS_PIN_2_BXT; 2755 break; 2756 case PHY_C: 2757 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2758 break; 2759 default: 2760 MISSING_CASE(phy); 2761 ddc_pin = GMBUS_PIN_1_BXT; 2762 break; 2763 } 2764 return ddc_pin; 2765 } 2766 2767 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2768 { 2769 enum phy phy = intel_port_to_phy(dev_priv, port); 2770 2771 WARN_ON(port == PORT_C); 2772 2773 /* 2774 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2775 * final two outputs use type-c pins, even though they're actually 2776 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2777 * all outputs. 2778 */ 2779 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2780 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2781 2782 return GMBUS_PIN_1_BXT + phy; 2783 } 2784 2785 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) 2786 { 2787 enum phy phy = intel_port_to_phy(i915, port); 2788 2789 drm_WARN_ON(&i915->drm, port == PORT_A); 2790 2791 /* 2792 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2793 * final two outputs use type-c pins, even though they're actually 2794 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2795 * all outputs. 2796 */ 2797 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2798 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2799 2800 return GMBUS_PIN_1_BXT + phy; 2801 } 2802 2803 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2804 { 2805 return intel_port_to_phy(dev_priv, port) + 1; 2806 } 2807 2808 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2809 { 2810 enum phy phy = intel_port_to_phy(dev_priv, port); 2811 2812 WARN_ON(port == PORT_B || port == PORT_C); 2813 2814 /* 2815 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2816 * except first combo output. 2817 */ 2818 if (phy == PHY_A) 2819 return GMBUS_PIN_1_BXT; 2820 2821 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2822 } 2823 2824 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2825 enum port port) 2826 { 2827 u8 ddc_pin; 2828 2829 switch (port) { 2830 case PORT_B: 2831 ddc_pin = GMBUS_PIN_DPB; 2832 break; 2833 case PORT_C: 2834 ddc_pin = GMBUS_PIN_DPC; 2835 break; 2836 case PORT_D: 2837 ddc_pin = GMBUS_PIN_DPD; 2838 break; 2839 default: 2840 MISSING_CASE(port); 2841 ddc_pin = GMBUS_PIN_DPB; 2842 break; 2843 } 2844 return ddc_pin; 2845 } 2846 2847 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2848 { 2849 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2850 enum port port = encoder->port; 2851 u8 ddc_pin; 2852 2853 ddc_pin = intel_bios_alternate_ddc_pin(encoder); 2854 if (ddc_pin) { 2855 drm_dbg_kms(&dev_priv->drm, 2856 "Using DDC pin 0x%x for port %c (VBT)\n", 2857 ddc_pin, port_name(port)); 2858 return ddc_pin; 2859 } 2860 2861 if (IS_ALDERLAKE_S(dev_priv)) 2862 ddc_pin = adls_port_to_ddc_pin(dev_priv, port); 2863 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2864 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); 2865 else if (IS_ROCKETLAKE(dev_priv)) 2866 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); 2867 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv)) 2868 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port); 2869 else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv)) 2870 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 2871 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2872 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 2873 else if (HAS_PCH_CNP(dev_priv)) 2874 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 2875 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2876 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 2877 else if (IS_CHERRYVIEW(dev_priv)) 2878 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 2879 else 2880 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 2881 2882 drm_dbg_kms(&dev_priv->drm, 2883 "Using DDC pin 0x%x for port %c (platform default)\n", 2884 ddc_pin, port_name(port)); 2885 2886 return ddc_pin; 2887 } 2888 2889 void intel_infoframe_init(struct intel_digital_port *dig_port) 2890 { 2891 struct drm_i915_private *dev_priv = 2892 to_i915(dig_port->base.base.dev); 2893 2894 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2895 dig_port->write_infoframe = vlv_write_infoframe; 2896 dig_port->read_infoframe = vlv_read_infoframe; 2897 dig_port->set_infoframes = vlv_set_infoframes; 2898 dig_port->infoframes_enabled = vlv_infoframes_enabled; 2899 } else if (IS_G4X(dev_priv)) { 2900 dig_port->write_infoframe = g4x_write_infoframe; 2901 dig_port->read_infoframe = g4x_read_infoframe; 2902 dig_port->set_infoframes = g4x_set_infoframes; 2903 dig_port->infoframes_enabled = g4x_infoframes_enabled; 2904 } else if (HAS_DDI(dev_priv)) { 2905 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) { 2906 dig_port->write_infoframe = lspcon_write_infoframe; 2907 dig_port->read_infoframe = lspcon_read_infoframe; 2908 dig_port->set_infoframes = lspcon_set_infoframes; 2909 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 2910 } else { 2911 dig_port->write_infoframe = hsw_write_infoframe; 2912 dig_port->read_infoframe = hsw_read_infoframe; 2913 dig_port->set_infoframes = hsw_set_infoframes; 2914 dig_port->infoframes_enabled = hsw_infoframes_enabled; 2915 } 2916 } else if (HAS_PCH_IBX(dev_priv)) { 2917 dig_port->write_infoframe = ibx_write_infoframe; 2918 dig_port->read_infoframe = ibx_read_infoframe; 2919 dig_port->set_infoframes = ibx_set_infoframes; 2920 dig_port->infoframes_enabled = ibx_infoframes_enabled; 2921 } else { 2922 dig_port->write_infoframe = cpt_write_infoframe; 2923 dig_port->read_infoframe = cpt_read_infoframe; 2924 dig_port->set_infoframes = cpt_set_infoframes; 2925 dig_port->infoframes_enabled = cpt_infoframes_enabled; 2926 } 2927 } 2928 2929 void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 2930 struct intel_connector *intel_connector) 2931 { 2932 struct drm_connector *connector = &intel_connector->base; 2933 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2934 struct intel_encoder *intel_encoder = &dig_port->base; 2935 struct drm_device *dev = intel_encoder->base.dev; 2936 struct drm_i915_private *dev_priv = to_i915(dev); 2937 struct i2c_adapter *ddc; 2938 enum port port = intel_encoder->port; 2939 struct cec_connector_info conn_info; 2940 2941 drm_dbg_kms(&dev_priv->drm, 2942 "Adding HDMI connector on [ENCODER:%d:%s]\n", 2943 intel_encoder->base.base.id, intel_encoder->base.name); 2944 2945 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 2946 return; 2947 2948 if (drm_WARN(dev, dig_port->max_lanes < 4, 2949 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 2950 dig_port->max_lanes, intel_encoder->base.base.id, 2951 intel_encoder->base.name)) 2952 return; 2953 2954 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); 2955 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2956 2957 drm_connector_init_with_ddc(dev, connector, 2958 &intel_hdmi_connector_funcs, 2959 DRM_MODE_CONNECTOR_HDMIA, 2960 ddc); 2961 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 2962 2963 if (DISPLAY_VER(dev_priv) < 12) 2964 connector->interlace_allowed = true; 2965 2966 connector->stereo_allowed = true; 2967 2968 if (DISPLAY_VER(dev_priv) >= 10) 2969 connector->ycbcr_420_allowed = true; 2970 2971 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2972 2973 if (HAS_DDI(dev_priv)) 2974 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2975 else 2976 intel_connector->get_hw_state = intel_connector_get_hw_state; 2977 2978 intel_hdmi_add_properties(intel_hdmi, connector); 2979 2980 intel_connector_attach_encoder(intel_connector, intel_encoder); 2981 intel_hdmi->attached_connector = intel_connector; 2982 2983 if (is_hdcp_supported(dev_priv, port)) { 2984 int ret = intel_hdcp_init(intel_connector, dig_port, 2985 &intel_hdmi_hdcp_shim); 2986 if (ret) 2987 drm_dbg_kms(&dev_priv->drm, 2988 "HDCP init failed, skipping.\n"); 2989 } 2990 2991 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2992 * 0xd. Failure to do so will result in spurious interrupts being 2993 * generated on the port when a cable is not attached. 2994 */ 2995 if (IS_G45(dev_priv)) { 2996 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 2997 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 2998 (temp & ~0xf) | 0xd); 2999 } 3000 3001 cec_fill_conn_info_from_drm(&conn_info, connector); 3002 3003 intel_hdmi->cec_notifier = 3004 cec_notifier_conn_register(dev->dev, port_identifier(port), 3005 &conn_info); 3006 if (!intel_hdmi->cec_notifier) 3007 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); 3008 } 3009 3010 /* 3011 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3012 * @vactive: Vactive of a display mode 3013 * 3014 * @return: appropriate dsc slice height for a given mode. 3015 */ 3016 int intel_hdmi_dsc_get_slice_height(int vactive) 3017 { 3018 int slice_height; 3019 3020 /* 3021 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3022 * Select smallest slice height >=96, that results in a valid PPS and 3023 * requires minimum padding lines required for final slice. 3024 * 3025 * Assumption : Vactive is even. 3026 */ 3027 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3028 if (vactive % slice_height == 0) 3029 return slice_height; 3030 3031 return 0; 3032 } 3033 3034 /* 3035 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3036 * and dsc decoder capabilities 3037 * 3038 * @crtc_state: intel crtc_state 3039 * @src_max_slices: maximum slices supported by the DSC encoder 3040 * @src_max_slice_width: maximum slice width supported by DSC encoder 3041 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3042 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3043 * 3044 * @return: num of dsc slices that can be supported by the dsc encoder 3045 * and decoder. 3046 */ 3047 int 3048 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3049 int src_max_slices, int src_max_slice_width, 3050 int hdmi_max_slices, int hdmi_throughput) 3051 { 3052 /* Pixel rates in KPixels/sec */ 3053 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3054 /* 3055 * Rates at which the source and sink are required to process pixels in each 3056 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3057 */ 3058 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3059 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3060 3061 /* Spec limits the slice width to 2720 pixels */ 3062 #define MAX_HDMI_SLICE_WIDTH 2720 3063 int kslice_adjust; 3064 int adjusted_clk_khz; 3065 int min_slices; 3066 int target_slices; 3067 int max_throughput; /* max clock freq. in khz per slice */ 3068 int max_slice_width; 3069 int slice_width; 3070 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3071 3072 if (!hdmi_throughput) 3073 return 0; 3074 3075 /* 3076 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3077 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3078 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3079 * dividing adjusted clock value by 10. 3080 */ 3081 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3082 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3083 kslice_adjust = 10; 3084 else 3085 kslice_adjust = 5; 3086 3087 /* 3088 * As per spec, the rate at which the source and the sink process 3089 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3090 * This depends upon the pixel clock rate and output formats 3091 * (kslice adjust). 3092 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3093 * at max 340MHz, otherwise they can be processed at max 400MHz. 3094 */ 3095 3096 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3097 3098 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3099 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3100 else 3101 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3102 3103 /* 3104 * Taking into account the sink's capability for maximum 3105 * clock per slice (in MHz) as read from HF-VSDB. 3106 */ 3107 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3108 3109 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3110 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3111 3112 /* 3113 * Keep on increasing the num of slices/line, starting from min_slices 3114 * per line till we get such a number, for which the slice_width is 3115 * just less than max_slice_width. The slices/line selected should be 3116 * less than or equal to the max horizontal slices that the combination 3117 * of PCON encoder and HDMI decoder can support. 3118 */ 3119 slice_width = max_slice_width; 3120 3121 do { 3122 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3123 target_slices = 1; 3124 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3125 target_slices = 2; 3126 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3127 target_slices = 4; 3128 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3129 target_slices = 8; 3130 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3131 target_slices = 12; 3132 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3133 target_slices = 16; 3134 else 3135 return 0; 3136 3137 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3138 if (slice_width >= max_slice_width) 3139 min_slices = target_slices + 1; 3140 } while (slice_width >= max_slice_width); 3141 3142 return target_slices; 3143 } 3144 3145 /* 3146 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3147 * source and sink capabilities. 3148 * 3149 * @src_fraction_bpp: fractional bpp supported by the source 3150 * @slice_width: dsc slice width supported by the source and sink 3151 * @num_slices: num of slices supported by the source and sink 3152 * @output_format: video output format 3153 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3154 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3155 * 3156 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3157 */ 3158 int 3159 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3160 int output_format, bool hdmi_all_bpp, 3161 int hdmi_max_chunk_bytes) 3162 { 3163 int max_dsc_bpp, min_dsc_bpp; 3164 int target_bytes; 3165 bool bpp_found = false; 3166 int bpp_decrement_x16; 3167 int bpp_target; 3168 int bpp_target_x16; 3169 3170 /* 3171 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3172 * Start with the max bpp and keep on decrementing with 3173 * fractional bpp, if supported by PCON DSC encoder 3174 * 3175 * for each bpp we check if no of bytes can be supported by HDMI sink 3176 */ 3177 3178 /* Assuming: bpc as 8*/ 3179 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3180 min_dsc_bpp = 6; 3181 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3182 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3183 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3184 min_dsc_bpp = 8; 3185 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3186 } else { 3187 /* Assuming 4:2:2 encoding */ 3188 min_dsc_bpp = 7; 3189 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3190 } 3191 3192 /* 3193 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3194 * Section 7.7.34 : Source shall not enable compressed Video 3195 * Transport with bpp_target settings above 12 bpp unless 3196 * DSC_all_bpp is set to 1. 3197 */ 3198 if (!hdmi_all_bpp) 3199 max_dsc_bpp = min(max_dsc_bpp, 12); 3200 3201 /* 3202 * The Sink has a limit of compressed data in bytes for a scanline, 3203 * as described in max_chunk_bytes field in HFVSDB block of edid. 3204 * The no. of bytes depend on the target bits per pixel that the 3205 * source configures. So we start with the max_bpp and calculate 3206 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3207 * till we get the target_chunk_bytes just less than what the sink's 3208 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3209 * 3210 * The decrement is according to the fractional support from PCON DSC 3211 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3212 * 3213 * bpp_target_x16 = bpp_target * 16 3214 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3215 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3216 */ 3217 3218 bpp_target = max_dsc_bpp; 3219 3220 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3221 if (!src_fractional_bpp) 3222 src_fractional_bpp = 1; 3223 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3224 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3225 3226 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3227 int bpp; 3228 3229 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3230 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3231 if (target_bytes <= hdmi_max_chunk_bytes) { 3232 bpp_found = true; 3233 break; 3234 } 3235 bpp_target_x16 -= bpp_decrement_x16; 3236 } 3237 if (bpp_found) 3238 return bpp_target_x16; 3239 3240 return 0; 3241 } 3242