1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_hdcp.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <drm/i915_drm.h> 40 #include <drm/intel_lpe_audio.h> 41 42 #include "i915_debugfs.h" 43 #include "i915_drv.h" 44 #include "intel_atomic.h" 45 #include "intel_audio.h" 46 #include "intel_connector.h" 47 #include "intel_ddi.h" 48 #include "intel_dp.h" 49 #include "intel_dpio_phy.h" 50 #include "intel_drv.h" 51 #include "intel_fifo_underrun.h" 52 #include "intel_gmbus.h" 53 #include "intel_hdcp.h" 54 #include "intel_hdmi.h" 55 #include "intel_hotplug.h" 56 #include "intel_lspcon.h" 57 #include "intel_sdvo.h" 58 #include "intel_panel.h" 59 #include "intel_sideband.h" 60 61 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 62 { 63 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 64 } 65 66 static void 67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 68 { 69 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 70 struct drm_i915_private *dev_priv = to_i915(dev); 71 u32 enabled_bits; 72 73 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 74 75 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 76 "HDMI port enabled, expecting disabled\n"); 77 } 78 79 static void 80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 81 enum transcoder cpu_transcoder) 82 { 83 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 84 TRANS_DDI_FUNC_ENABLE, 85 "HDMI transcoder function enabled, expecting disabled\n"); 86 } 87 88 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 89 { 90 struct intel_digital_port *intel_dig_port = 91 container_of(encoder, struct intel_digital_port, base.base); 92 return &intel_dig_port->hdmi; 93 } 94 95 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 96 { 97 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 98 } 99 100 static u32 g4x_infoframe_index(unsigned int type) 101 { 102 switch (type) { 103 case HDMI_PACKET_TYPE_GAMUT_METADATA: 104 return VIDEO_DIP_SELECT_GAMUT; 105 case HDMI_INFOFRAME_TYPE_AVI: 106 return VIDEO_DIP_SELECT_AVI; 107 case HDMI_INFOFRAME_TYPE_SPD: 108 return VIDEO_DIP_SELECT_SPD; 109 case HDMI_INFOFRAME_TYPE_VENDOR: 110 return VIDEO_DIP_SELECT_VENDOR; 111 default: 112 MISSING_CASE(type); 113 return 0; 114 } 115 } 116 117 static u32 g4x_infoframe_enable(unsigned int type) 118 { 119 switch (type) { 120 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 121 return VIDEO_DIP_ENABLE_GCP; 122 case HDMI_PACKET_TYPE_GAMUT_METADATA: 123 return VIDEO_DIP_ENABLE_GAMUT; 124 case DP_SDP_VSC: 125 return 0; 126 case HDMI_INFOFRAME_TYPE_AVI: 127 return VIDEO_DIP_ENABLE_AVI; 128 case HDMI_INFOFRAME_TYPE_SPD: 129 return VIDEO_DIP_ENABLE_SPD; 130 case HDMI_INFOFRAME_TYPE_VENDOR: 131 return VIDEO_DIP_ENABLE_VENDOR; 132 case HDMI_INFOFRAME_TYPE_DRM: 133 return 0; 134 default: 135 MISSING_CASE(type); 136 return 0; 137 } 138 } 139 140 static u32 hsw_infoframe_enable(unsigned int type) 141 { 142 switch (type) { 143 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 144 return VIDEO_DIP_ENABLE_GCP_HSW; 145 case HDMI_PACKET_TYPE_GAMUT_METADATA: 146 return VIDEO_DIP_ENABLE_GMP_HSW; 147 case DP_SDP_VSC: 148 return VIDEO_DIP_ENABLE_VSC_HSW; 149 case DP_SDP_PPS: 150 return VDIP_ENABLE_PPS; 151 case HDMI_INFOFRAME_TYPE_AVI: 152 return VIDEO_DIP_ENABLE_AVI_HSW; 153 case HDMI_INFOFRAME_TYPE_SPD: 154 return VIDEO_DIP_ENABLE_SPD_HSW; 155 case HDMI_INFOFRAME_TYPE_VENDOR: 156 return VIDEO_DIP_ENABLE_VS_HSW; 157 case HDMI_INFOFRAME_TYPE_DRM: 158 return VIDEO_DIP_ENABLE_DRM_GLK; 159 default: 160 MISSING_CASE(type); 161 return 0; 162 } 163 } 164 165 static i915_reg_t 166 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 167 enum transcoder cpu_transcoder, 168 unsigned int type, 169 int i) 170 { 171 switch (type) { 172 case HDMI_PACKET_TYPE_GAMUT_METADATA: 173 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 174 case DP_SDP_VSC: 175 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 176 case DP_SDP_PPS: 177 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 178 case HDMI_INFOFRAME_TYPE_AVI: 179 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 180 case HDMI_INFOFRAME_TYPE_SPD: 181 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 182 case HDMI_INFOFRAME_TYPE_VENDOR: 183 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 184 case HDMI_INFOFRAME_TYPE_DRM: 185 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 186 default: 187 MISSING_CASE(type); 188 return INVALID_MMIO_REG; 189 } 190 } 191 192 static int hsw_dip_data_size(unsigned int type) 193 { 194 switch (type) { 195 case DP_SDP_VSC: 196 return VIDEO_DIP_VSC_DATA_SIZE; 197 case DP_SDP_PPS: 198 return VIDEO_DIP_PPS_DATA_SIZE; 199 default: 200 return VIDEO_DIP_DATA_SIZE; 201 } 202 } 203 204 static void g4x_write_infoframe(struct intel_encoder *encoder, 205 const struct intel_crtc_state *crtc_state, 206 unsigned int type, 207 const void *frame, ssize_t len) 208 { 209 const u32 *data = frame; 210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 211 u32 val = I915_READ(VIDEO_DIP_CTL); 212 int i; 213 214 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 215 216 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 217 val |= g4x_infoframe_index(type); 218 219 val &= ~g4x_infoframe_enable(type); 220 221 I915_WRITE(VIDEO_DIP_CTL, val); 222 223 for (i = 0; i < len; i += 4) { 224 I915_WRITE(VIDEO_DIP_DATA, *data); 225 data++; 226 } 227 /* Write every possible data byte to force correct ECC calculation. */ 228 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 229 I915_WRITE(VIDEO_DIP_DATA, 0); 230 231 val |= g4x_infoframe_enable(type); 232 val &= ~VIDEO_DIP_FREQ_MASK; 233 val |= VIDEO_DIP_FREQ_VSYNC; 234 235 I915_WRITE(VIDEO_DIP_CTL, val); 236 POSTING_READ(VIDEO_DIP_CTL); 237 } 238 239 static void g4x_read_infoframe(struct intel_encoder *encoder, 240 const struct intel_crtc_state *crtc_state, 241 unsigned int type, 242 void *frame, ssize_t len) 243 { 244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 245 u32 val, *data = frame; 246 int i; 247 248 val = I915_READ(VIDEO_DIP_CTL); 249 250 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 251 val |= g4x_infoframe_index(type); 252 253 I915_WRITE(VIDEO_DIP_CTL, val); 254 255 for (i = 0; i < len; i += 4) 256 *data++ = I915_READ(VIDEO_DIP_DATA); 257 } 258 259 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 260 const struct intel_crtc_state *pipe_config) 261 { 262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 263 u32 val = I915_READ(VIDEO_DIP_CTL); 264 265 if ((val & VIDEO_DIP_ENABLE) == 0) 266 return 0; 267 268 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 269 return 0; 270 271 return val & (VIDEO_DIP_ENABLE_AVI | 272 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 273 } 274 275 static void ibx_write_infoframe(struct intel_encoder *encoder, 276 const struct intel_crtc_state *crtc_state, 277 unsigned int type, 278 const void *frame, ssize_t len) 279 { 280 const u32 *data = frame; 281 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 283 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 284 u32 val = I915_READ(reg); 285 int i; 286 287 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 288 289 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 290 val |= g4x_infoframe_index(type); 291 292 val &= ~g4x_infoframe_enable(type); 293 294 I915_WRITE(reg, val); 295 296 for (i = 0; i < len; i += 4) { 297 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 298 data++; 299 } 300 /* Write every possible data byte to force correct ECC calculation. */ 301 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 302 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 303 304 val |= g4x_infoframe_enable(type); 305 val &= ~VIDEO_DIP_FREQ_MASK; 306 val |= VIDEO_DIP_FREQ_VSYNC; 307 308 I915_WRITE(reg, val); 309 POSTING_READ(reg); 310 } 311 312 static void ibx_read_infoframe(struct intel_encoder *encoder, 313 const struct intel_crtc_state *crtc_state, 314 unsigned int type, 315 void *frame, ssize_t len) 316 { 317 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 318 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 319 u32 val, *data = frame; 320 int i; 321 322 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); 323 324 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 325 val |= g4x_infoframe_index(type); 326 327 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); 328 329 for (i = 0; i < len; i += 4) 330 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); 331 } 332 333 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 334 const struct intel_crtc_state *pipe_config) 335 { 336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 337 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 338 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 339 u32 val = I915_READ(reg); 340 341 if ((val & VIDEO_DIP_ENABLE) == 0) 342 return 0; 343 344 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 345 return 0; 346 347 return val & (VIDEO_DIP_ENABLE_AVI | 348 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 349 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 350 } 351 352 static void cpt_write_infoframe(struct intel_encoder *encoder, 353 const struct intel_crtc_state *crtc_state, 354 unsigned int type, 355 const void *frame, ssize_t len) 356 { 357 const u32 *data = frame; 358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 360 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 361 u32 val = I915_READ(reg); 362 int i; 363 364 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 365 366 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 367 val |= g4x_infoframe_index(type); 368 369 /* The DIP control register spec says that we need to update the AVI 370 * infoframe without clearing its enable bit */ 371 if (type != HDMI_INFOFRAME_TYPE_AVI) 372 val &= ~g4x_infoframe_enable(type); 373 374 I915_WRITE(reg, val); 375 376 for (i = 0; i < len; i += 4) { 377 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 378 data++; 379 } 380 /* Write every possible data byte to force correct ECC calculation. */ 381 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 382 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 383 384 val |= g4x_infoframe_enable(type); 385 val &= ~VIDEO_DIP_FREQ_MASK; 386 val |= VIDEO_DIP_FREQ_VSYNC; 387 388 I915_WRITE(reg, val); 389 POSTING_READ(reg); 390 } 391 392 static void cpt_read_infoframe(struct intel_encoder *encoder, 393 const struct intel_crtc_state *crtc_state, 394 unsigned int type, 395 void *frame, ssize_t len) 396 { 397 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 398 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 399 u32 val, *data = frame; 400 int i; 401 402 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); 403 404 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 405 val |= g4x_infoframe_index(type); 406 407 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); 408 409 for (i = 0; i < len; i += 4) 410 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); 411 } 412 413 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 414 const struct intel_crtc_state *pipe_config) 415 { 416 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 417 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 418 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); 419 420 if ((val & VIDEO_DIP_ENABLE) == 0) 421 return 0; 422 423 return val & (VIDEO_DIP_ENABLE_AVI | 424 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 425 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 426 } 427 428 static void vlv_write_infoframe(struct intel_encoder *encoder, 429 const struct intel_crtc_state *crtc_state, 430 unsigned int type, 431 const void *frame, ssize_t len) 432 { 433 const u32 *data = frame; 434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 436 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 437 u32 val = I915_READ(reg); 438 int i; 439 440 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 441 442 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 443 val |= g4x_infoframe_index(type); 444 445 val &= ~g4x_infoframe_enable(type); 446 447 I915_WRITE(reg, val); 448 449 for (i = 0; i < len; i += 4) { 450 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 451 data++; 452 } 453 /* Write every possible data byte to force correct ECC calculation. */ 454 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 455 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 456 457 val |= g4x_infoframe_enable(type); 458 val &= ~VIDEO_DIP_FREQ_MASK; 459 val |= VIDEO_DIP_FREQ_VSYNC; 460 461 I915_WRITE(reg, val); 462 POSTING_READ(reg); 463 } 464 465 static void vlv_read_infoframe(struct intel_encoder *encoder, 466 const struct intel_crtc_state *crtc_state, 467 unsigned int type, 468 void *frame, ssize_t len) 469 { 470 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 471 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 472 u32 val, *data = frame; 473 int i; 474 475 val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe)); 476 477 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 478 val |= g4x_infoframe_index(type); 479 480 I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 481 482 for (i = 0; i < len; i += 4) 483 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe)); 484 } 485 486 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 487 const struct intel_crtc_state *pipe_config) 488 { 489 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 490 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 491 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); 492 493 if ((val & VIDEO_DIP_ENABLE) == 0) 494 return 0; 495 496 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 497 return 0; 498 499 return val & (VIDEO_DIP_ENABLE_AVI | 500 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 501 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 502 } 503 504 static void hsw_write_infoframe(struct intel_encoder *encoder, 505 const struct intel_crtc_state *crtc_state, 506 unsigned int type, 507 const void *frame, ssize_t len) 508 { 509 const u32 *data = frame; 510 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 511 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 512 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 513 int data_size; 514 int i; 515 u32 val = I915_READ(ctl_reg); 516 517 data_size = hsw_dip_data_size(type); 518 519 val &= ~hsw_infoframe_enable(type); 520 I915_WRITE(ctl_reg, val); 521 522 for (i = 0; i < len; i += 4) { 523 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 524 type, i >> 2), *data); 525 data++; 526 } 527 /* Write every possible data byte to force correct ECC calculation. */ 528 for (; i < data_size; i += 4) 529 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 530 type, i >> 2), 0); 531 532 val |= hsw_infoframe_enable(type); 533 I915_WRITE(ctl_reg, val); 534 POSTING_READ(ctl_reg); 535 } 536 537 static void hsw_read_infoframe(struct intel_encoder *encoder, 538 const struct intel_crtc_state *crtc_state, 539 unsigned int type, 540 void *frame, ssize_t len) 541 { 542 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 543 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 544 u32 val, *data = frame; 545 int i; 546 547 val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder)); 548 549 for (i = 0; i < len; i += 4) 550 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder, 551 type, i >> 2)); 552 } 553 554 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 555 const struct intel_crtc_state *pipe_config) 556 { 557 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 558 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 559 u32 mask; 560 561 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 562 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 563 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 564 565 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 566 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 567 568 return val & mask; 569 } 570 571 static const u8 infoframe_type_to_idx[] = { 572 HDMI_PACKET_TYPE_GENERAL_CONTROL, 573 HDMI_PACKET_TYPE_GAMUT_METADATA, 574 DP_SDP_VSC, 575 HDMI_INFOFRAME_TYPE_AVI, 576 HDMI_INFOFRAME_TYPE_SPD, 577 HDMI_INFOFRAME_TYPE_VENDOR, 578 HDMI_INFOFRAME_TYPE_DRM, 579 }; 580 581 u32 intel_hdmi_infoframe_enable(unsigned int type) 582 { 583 int i; 584 585 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 586 if (infoframe_type_to_idx[i] == type) 587 return BIT(i); 588 } 589 590 return 0; 591 } 592 593 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 594 const struct intel_crtc_state *crtc_state) 595 { 596 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 597 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 598 u32 val, ret = 0; 599 int i; 600 601 val = dig_port->infoframes_enabled(encoder, crtc_state); 602 603 /* map from hardware bits to dip idx */ 604 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 605 unsigned int type = infoframe_type_to_idx[i]; 606 607 if (HAS_DDI(dev_priv)) { 608 if (val & hsw_infoframe_enable(type)) 609 ret |= BIT(i); 610 } else { 611 if (val & g4x_infoframe_enable(type)) 612 ret |= BIT(i); 613 } 614 } 615 616 return ret; 617 } 618 619 /* 620 * The data we write to the DIP data buffer registers is 1 byte bigger than the 621 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 622 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 623 * used for both technologies. 624 * 625 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 626 * DW1: DB3 | DB2 | DB1 | DB0 627 * DW2: DB7 | DB6 | DB5 | DB4 628 * DW3: ... 629 * 630 * (HB is Header Byte, DB is Data Byte) 631 * 632 * The hdmi pack() functions don't know about that hardware specific hole so we 633 * trick them by giving an offset into the buffer and moving back the header 634 * bytes by one. 635 */ 636 static void intel_write_infoframe(struct intel_encoder *encoder, 637 const struct intel_crtc_state *crtc_state, 638 enum hdmi_infoframe_type type, 639 const union hdmi_infoframe *frame) 640 { 641 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 642 u8 buffer[VIDEO_DIP_DATA_SIZE]; 643 ssize_t len; 644 645 if ((crtc_state->infoframes.enable & 646 intel_hdmi_infoframe_enable(type)) == 0) 647 return; 648 649 if (WARN_ON(frame->any.type != type)) 650 return; 651 652 /* see comment above for the reason for this offset */ 653 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 654 if (WARN_ON(len < 0)) 655 return; 656 657 /* Insert the 'hole' (see big comment above) at position 3 */ 658 memmove(&buffer[0], &buffer[1], 3); 659 buffer[3] = 0; 660 len++; 661 662 intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 663 } 664 665 void intel_read_infoframe(struct intel_encoder *encoder, 666 const struct intel_crtc_state *crtc_state, 667 enum hdmi_infoframe_type type, 668 union hdmi_infoframe *frame) 669 { 670 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 671 u8 buffer[VIDEO_DIP_DATA_SIZE]; 672 int ret; 673 674 if ((crtc_state->infoframes.enable & 675 intel_hdmi_infoframe_enable(type)) == 0) 676 return; 677 678 intel_dig_port->read_infoframe(encoder, crtc_state, 679 type, buffer, sizeof(buffer)); 680 681 /* Fill the 'hole' (see big comment above) at position 3 */ 682 memmove(&buffer[1], &buffer[0], 3); 683 684 /* see comment above for the reason for this offset */ 685 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 686 if (ret) { 687 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type); 688 return; 689 } 690 691 if (frame->any.type != type) 692 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 693 frame->any.type, type); 694 } 695 696 static bool 697 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 698 struct intel_crtc_state *crtc_state, 699 struct drm_connector_state *conn_state) 700 { 701 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 702 const struct drm_display_mode *adjusted_mode = 703 &crtc_state->base.adjusted_mode; 704 struct drm_connector *connector = conn_state->connector; 705 int ret; 706 707 if (!crtc_state->has_infoframe) 708 return true; 709 710 crtc_state->infoframes.enable |= 711 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 712 713 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 714 adjusted_mode); 715 if (ret) 716 return false; 717 718 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 719 frame->colorspace = HDMI_COLORSPACE_YUV420; 720 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 721 frame->colorspace = HDMI_COLORSPACE_YUV444; 722 else 723 frame->colorspace = HDMI_COLORSPACE_RGB; 724 725 drm_hdmi_avi_infoframe_colorspace(frame, conn_state); 726 727 drm_hdmi_avi_infoframe_quant_range(frame, connector, 728 adjusted_mode, 729 crtc_state->limited_color_range ? 730 HDMI_QUANTIZATION_RANGE_LIMITED : 731 HDMI_QUANTIZATION_RANGE_FULL); 732 733 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 734 735 /* TODO: handle pixel repetition for YCBCR420 outputs */ 736 737 ret = hdmi_avi_infoframe_check(frame); 738 if (WARN_ON(ret)) 739 return false; 740 741 return true; 742 } 743 744 static bool 745 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 746 struct intel_crtc_state *crtc_state, 747 struct drm_connector_state *conn_state) 748 { 749 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 750 int ret; 751 752 if (!crtc_state->has_infoframe) 753 return true; 754 755 crtc_state->infoframes.enable |= 756 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 757 758 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 759 if (WARN_ON(ret)) 760 return false; 761 762 frame->sdi = HDMI_SPD_SDI_PC; 763 764 ret = hdmi_spd_infoframe_check(frame); 765 if (WARN_ON(ret)) 766 return false; 767 768 return true; 769 } 770 771 static bool 772 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 773 struct intel_crtc_state *crtc_state, 774 struct drm_connector_state *conn_state) 775 { 776 struct hdmi_vendor_infoframe *frame = 777 &crtc_state->infoframes.hdmi.vendor.hdmi; 778 const struct drm_display_info *info = 779 &conn_state->connector->display_info; 780 int ret; 781 782 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 783 return true; 784 785 crtc_state->infoframes.enable |= 786 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 787 788 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 789 conn_state->connector, 790 &crtc_state->base.adjusted_mode); 791 if (WARN_ON(ret)) 792 return false; 793 794 ret = hdmi_vendor_infoframe_check(frame); 795 if (WARN_ON(ret)) 796 return false; 797 798 return true; 799 } 800 801 static bool 802 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 803 struct intel_crtc_state *crtc_state, 804 struct drm_connector_state *conn_state) 805 { 806 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 807 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 808 int ret; 809 810 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) 811 return true; 812 813 if (!crtc_state->has_infoframe) 814 return true; 815 816 if (!conn_state->hdr_output_metadata) 817 return true; 818 819 crtc_state->infoframes.enable |= 820 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 821 822 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 823 if (ret < 0) { 824 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); 825 return false; 826 } 827 828 ret = hdmi_drm_infoframe_check(frame); 829 if (WARN_ON(ret)) 830 return false; 831 832 return true; 833 } 834 835 static void g4x_set_infoframes(struct intel_encoder *encoder, 836 bool enable, 837 const struct intel_crtc_state *crtc_state, 838 const struct drm_connector_state *conn_state) 839 { 840 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 841 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 842 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 843 i915_reg_t reg = VIDEO_DIP_CTL; 844 u32 val = I915_READ(reg); 845 u32 port = VIDEO_DIP_PORT(encoder->port); 846 847 assert_hdmi_port_disabled(intel_hdmi); 848 849 /* If the registers were not initialized yet, they might be zeroes, 850 * which means we're selecting the AVI DIP and we're setting its 851 * frequency to once. This seems to really confuse the HW and make 852 * things stop working (the register spec says the AVI always needs to 853 * be sent every VSync). So here we avoid writing to the register more 854 * than we need and also explicitly select the AVI DIP and explicitly 855 * set its frequency to every VSync. Avoiding to write it twice seems to 856 * be enough to solve the problem, but being defensive shouldn't hurt us 857 * either. */ 858 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 859 860 if (!enable) { 861 if (!(val & VIDEO_DIP_ENABLE)) 862 return; 863 if (port != (val & VIDEO_DIP_PORT_MASK)) { 864 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 865 (val & VIDEO_DIP_PORT_MASK) >> 29); 866 return; 867 } 868 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 869 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 870 I915_WRITE(reg, val); 871 POSTING_READ(reg); 872 return; 873 } 874 875 if (port != (val & VIDEO_DIP_PORT_MASK)) { 876 if (val & VIDEO_DIP_ENABLE) { 877 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 878 (val & VIDEO_DIP_PORT_MASK) >> 29); 879 return; 880 } 881 val &= ~VIDEO_DIP_PORT_MASK; 882 val |= port; 883 } 884 885 val |= VIDEO_DIP_ENABLE; 886 val &= ~(VIDEO_DIP_ENABLE_AVI | 887 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 888 889 I915_WRITE(reg, val); 890 POSTING_READ(reg); 891 892 intel_write_infoframe(encoder, crtc_state, 893 HDMI_INFOFRAME_TYPE_AVI, 894 &crtc_state->infoframes.avi); 895 intel_write_infoframe(encoder, crtc_state, 896 HDMI_INFOFRAME_TYPE_SPD, 897 &crtc_state->infoframes.spd); 898 intel_write_infoframe(encoder, crtc_state, 899 HDMI_INFOFRAME_TYPE_VENDOR, 900 &crtc_state->infoframes.hdmi); 901 } 902 903 /* 904 * Determine if default_phase=1 can be indicated in the GCP infoframe. 905 * 906 * From HDMI specification 1.4a: 907 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 908 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 909 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 910 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 911 * phase of 0 912 */ 913 static bool gcp_default_phase_possible(int pipe_bpp, 914 const struct drm_display_mode *mode) 915 { 916 unsigned int pixels_per_group; 917 918 switch (pipe_bpp) { 919 case 30: 920 /* 4 pixels in 5 clocks */ 921 pixels_per_group = 4; 922 break; 923 case 36: 924 /* 2 pixels in 3 clocks */ 925 pixels_per_group = 2; 926 break; 927 case 48: 928 /* 1 pixel in 2 clocks */ 929 pixels_per_group = 1; 930 break; 931 default: 932 /* phase information not relevant for 8bpc */ 933 return false; 934 } 935 936 return mode->crtc_hdisplay % pixels_per_group == 0 && 937 mode->crtc_htotal % pixels_per_group == 0 && 938 mode->crtc_hblank_start % pixels_per_group == 0 && 939 mode->crtc_hblank_end % pixels_per_group == 0 && 940 mode->crtc_hsync_start % pixels_per_group == 0 && 941 mode->crtc_hsync_end % pixels_per_group == 0 && 942 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 943 mode->crtc_htotal/2 % pixels_per_group == 0); 944 } 945 946 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 947 const struct intel_crtc_state *crtc_state, 948 const struct drm_connector_state *conn_state) 949 { 950 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 952 i915_reg_t reg; 953 954 if ((crtc_state->infoframes.enable & 955 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 956 return false; 957 958 if (HAS_DDI(dev_priv)) 959 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 960 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 961 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 962 else if (HAS_PCH_SPLIT(dev_priv)) 963 reg = TVIDEO_DIP_GCP(crtc->pipe); 964 else 965 return false; 966 967 I915_WRITE(reg, crtc_state->infoframes.gcp); 968 969 return true; 970 } 971 972 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 973 struct intel_crtc_state *crtc_state) 974 { 975 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 976 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 977 i915_reg_t reg; 978 979 if ((crtc_state->infoframes.enable & 980 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 981 return; 982 983 if (HAS_DDI(dev_priv)) 984 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 985 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 986 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 987 else if (HAS_PCH_SPLIT(dev_priv)) 988 reg = TVIDEO_DIP_GCP(crtc->pipe); 989 else 990 return; 991 992 crtc_state->infoframes.gcp = I915_READ(reg); 993 } 994 995 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 996 struct intel_crtc_state *crtc_state, 997 struct drm_connector_state *conn_state) 998 { 999 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1000 1001 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1002 return; 1003 1004 crtc_state->infoframes.enable |= 1005 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1006 1007 /* Indicate color indication for deep color mode */ 1008 if (crtc_state->pipe_bpp > 24) 1009 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1010 1011 /* Enable default_phase whenever the display mode is suitably aligned */ 1012 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1013 &crtc_state->base.adjusted_mode)) 1014 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1015 } 1016 1017 static void ibx_set_infoframes(struct intel_encoder *encoder, 1018 bool enable, 1019 const struct intel_crtc_state *crtc_state, 1020 const struct drm_connector_state *conn_state) 1021 { 1022 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 1024 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 1025 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1026 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1027 u32 val = I915_READ(reg); 1028 u32 port = VIDEO_DIP_PORT(encoder->port); 1029 1030 assert_hdmi_port_disabled(intel_hdmi); 1031 1032 /* See the big comment in g4x_set_infoframes() */ 1033 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1034 1035 if (!enable) { 1036 if (!(val & VIDEO_DIP_ENABLE)) 1037 return; 1038 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1039 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1040 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1041 I915_WRITE(reg, val); 1042 POSTING_READ(reg); 1043 return; 1044 } 1045 1046 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1047 WARN(val & VIDEO_DIP_ENABLE, 1048 "DIP already enabled on port %c\n", 1049 (val & VIDEO_DIP_PORT_MASK) >> 29); 1050 val &= ~VIDEO_DIP_PORT_MASK; 1051 val |= port; 1052 } 1053 1054 val |= VIDEO_DIP_ENABLE; 1055 val &= ~(VIDEO_DIP_ENABLE_AVI | 1056 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1057 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1058 1059 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1060 val |= VIDEO_DIP_ENABLE_GCP; 1061 1062 I915_WRITE(reg, val); 1063 POSTING_READ(reg); 1064 1065 intel_write_infoframe(encoder, crtc_state, 1066 HDMI_INFOFRAME_TYPE_AVI, 1067 &crtc_state->infoframes.avi); 1068 intel_write_infoframe(encoder, crtc_state, 1069 HDMI_INFOFRAME_TYPE_SPD, 1070 &crtc_state->infoframes.spd); 1071 intel_write_infoframe(encoder, crtc_state, 1072 HDMI_INFOFRAME_TYPE_VENDOR, 1073 &crtc_state->infoframes.hdmi); 1074 } 1075 1076 static void cpt_set_infoframes(struct intel_encoder *encoder, 1077 bool enable, 1078 const struct intel_crtc_state *crtc_state, 1079 const struct drm_connector_state *conn_state) 1080 { 1081 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 1083 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1084 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1085 u32 val = I915_READ(reg); 1086 1087 assert_hdmi_port_disabled(intel_hdmi); 1088 1089 /* See the big comment in g4x_set_infoframes() */ 1090 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1091 1092 if (!enable) { 1093 if (!(val & VIDEO_DIP_ENABLE)) 1094 return; 1095 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1096 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1097 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1098 I915_WRITE(reg, val); 1099 POSTING_READ(reg); 1100 return; 1101 } 1102 1103 /* Set both together, unset both together: see the spec. */ 1104 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1105 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1106 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1107 1108 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1109 val |= VIDEO_DIP_ENABLE_GCP; 1110 1111 I915_WRITE(reg, val); 1112 POSTING_READ(reg); 1113 1114 intel_write_infoframe(encoder, crtc_state, 1115 HDMI_INFOFRAME_TYPE_AVI, 1116 &crtc_state->infoframes.avi); 1117 intel_write_infoframe(encoder, crtc_state, 1118 HDMI_INFOFRAME_TYPE_SPD, 1119 &crtc_state->infoframes.spd); 1120 intel_write_infoframe(encoder, crtc_state, 1121 HDMI_INFOFRAME_TYPE_VENDOR, 1122 &crtc_state->infoframes.hdmi); 1123 } 1124 1125 static void vlv_set_infoframes(struct intel_encoder *encoder, 1126 bool enable, 1127 const struct intel_crtc_state *crtc_state, 1128 const struct drm_connector_state *conn_state) 1129 { 1130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 1132 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1133 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 1134 u32 val = I915_READ(reg); 1135 u32 port = VIDEO_DIP_PORT(encoder->port); 1136 1137 assert_hdmi_port_disabled(intel_hdmi); 1138 1139 /* See the big comment in g4x_set_infoframes() */ 1140 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1141 1142 if (!enable) { 1143 if (!(val & VIDEO_DIP_ENABLE)) 1144 return; 1145 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1146 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1147 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1148 I915_WRITE(reg, val); 1149 POSTING_READ(reg); 1150 return; 1151 } 1152 1153 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1154 WARN(val & VIDEO_DIP_ENABLE, 1155 "DIP already enabled on port %c\n", 1156 (val & VIDEO_DIP_PORT_MASK) >> 29); 1157 val &= ~VIDEO_DIP_PORT_MASK; 1158 val |= port; 1159 } 1160 1161 val |= VIDEO_DIP_ENABLE; 1162 val &= ~(VIDEO_DIP_ENABLE_AVI | 1163 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1164 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1165 1166 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1167 val |= VIDEO_DIP_ENABLE_GCP; 1168 1169 I915_WRITE(reg, val); 1170 POSTING_READ(reg); 1171 1172 intel_write_infoframe(encoder, crtc_state, 1173 HDMI_INFOFRAME_TYPE_AVI, 1174 &crtc_state->infoframes.avi); 1175 intel_write_infoframe(encoder, crtc_state, 1176 HDMI_INFOFRAME_TYPE_SPD, 1177 &crtc_state->infoframes.spd); 1178 intel_write_infoframe(encoder, crtc_state, 1179 HDMI_INFOFRAME_TYPE_VENDOR, 1180 &crtc_state->infoframes.hdmi); 1181 } 1182 1183 static void hsw_set_infoframes(struct intel_encoder *encoder, 1184 bool enable, 1185 const struct intel_crtc_state *crtc_state, 1186 const struct drm_connector_state *conn_state) 1187 { 1188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1189 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1190 u32 val = I915_READ(reg); 1191 1192 assert_hdmi_transcoder_func_disabled(dev_priv, 1193 crtc_state->cpu_transcoder); 1194 1195 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1196 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1197 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1198 VIDEO_DIP_ENABLE_DRM_GLK); 1199 1200 if (!enable) { 1201 I915_WRITE(reg, val); 1202 POSTING_READ(reg); 1203 return; 1204 } 1205 1206 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1207 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1208 1209 I915_WRITE(reg, val); 1210 POSTING_READ(reg); 1211 1212 intel_write_infoframe(encoder, crtc_state, 1213 HDMI_INFOFRAME_TYPE_AVI, 1214 &crtc_state->infoframes.avi); 1215 intel_write_infoframe(encoder, crtc_state, 1216 HDMI_INFOFRAME_TYPE_SPD, 1217 &crtc_state->infoframes.spd); 1218 intel_write_infoframe(encoder, crtc_state, 1219 HDMI_INFOFRAME_TYPE_VENDOR, 1220 &crtc_state->infoframes.hdmi); 1221 intel_write_infoframe(encoder, crtc_state, 1222 HDMI_INFOFRAME_TYPE_DRM, 1223 &crtc_state->infoframes.drm); 1224 } 1225 1226 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1227 { 1228 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1229 struct i2c_adapter *adapter = 1230 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1231 1232 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1233 return; 1234 1235 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", 1236 enable ? "Enabling" : "Disabling"); 1237 1238 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, 1239 adapter, enable); 1240 } 1241 1242 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, 1243 unsigned int offset, void *buffer, size_t size) 1244 { 1245 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1246 struct drm_i915_private *dev_priv = 1247 intel_dig_port->base.base.dev->dev_private; 1248 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, 1249 hdmi->ddc_bus); 1250 int ret; 1251 u8 start = offset & 0xff; 1252 struct i2c_msg msgs[] = { 1253 { 1254 .addr = DRM_HDCP_DDC_ADDR, 1255 .flags = 0, 1256 .len = 1, 1257 .buf = &start, 1258 }, 1259 { 1260 .addr = DRM_HDCP_DDC_ADDR, 1261 .flags = I2C_M_RD, 1262 .len = size, 1263 .buf = buffer 1264 } 1265 }; 1266 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1267 if (ret == ARRAY_SIZE(msgs)) 1268 return 0; 1269 return ret >= 0 ? -EIO : ret; 1270 } 1271 1272 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, 1273 unsigned int offset, void *buffer, size_t size) 1274 { 1275 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1276 struct drm_i915_private *dev_priv = 1277 intel_dig_port->base.base.dev->dev_private; 1278 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, 1279 hdmi->ddc_bus); 1280 int ret; 1281 u8 *write_buf; 1282 struct i2c_msg msg; 1283 1284 write_buf = kzalloc(size + 1, GFP_KERNEL); 1285 if (!write_buf) 1286 return -ENOMEM; 1287 1288 write_buf[0] = offset & 0xff; 1289 memcpy(&write_buf[1], buffer, size); 1290 1291 msg.addr = DRM_HDCP_DDC_ADDR; 1292 msg.flags = 0, 1293 msg.len = size + 1, 1294 msg.buf = write_buf; 1295 1296 ret = i2c_transfer(adapter, &msg, 1); 1297 if (ret == 1) 1298 ret = 0; 1299 else if (ret >= 0) 1300 ret = -EIO; 1301 1302 kfree(write_buf); 1303 return ret; 1304 } 1305 1306 static 1307 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, 1308 u8 *an) 1309 { 1310 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1311 struct drm_i915_private *dev_priv = 1312 intel_dig_port->base.base.dev->dev_private; 1313 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, 1314 hdmi->ddc_bus); 1315 int ret; 1316 1317 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, 1318 DRM_HDCP_AN_LEN); 1319 if (ret) { 1320 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret); 1321 return ret; 1322 } 1323 1324 ret = intel_gmbus_output_aksv(adapter); 1325 if (ret < 0) { 1326 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret); 1327 return ret; 1328 } 1329 return 0; 1330 } 1331 1332 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, 1333 u8 *bksv) 1334 { 1335 int ret; 1336 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, 1337 DRM_HDCP_KSV_LEN); 1338 if (ret) 1339 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret); 1340 return ret; 1341 } 1342 1343 static 1344 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, 1345 u8 *bstatus) 1346 { 1347 int ret; 1348 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, 1349 bstatus, DRM_HDCP_BSTATUS_LEN); 1350 if (ret) 1351 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret); 1352 return ret; 1353 } 1354 1355 static 1356 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, 1357 bool *repeater_present) 1358 { 1359 int ret; 1360 u8 val; 1361 1362 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1363 if (ret) { 1364 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); 1365 return ret; 1366 } 1367 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1368 return 0; 1369 } 1370 1371 static 1372 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, 1373 u8 *ri_prime) 1374 { 1375 int ret; 1376 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, 1377 ri_prime, DRM_HDCP_RI_LEN); 1378 if (ret) 1379 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret); 1380 return ret; 1381 } 1382 1383 static 1384 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, 1385 bool *ksv_ready) 1386 { 1387 int ret; 1388 u8 val; 1389 1390 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1391 if (ret) { 1392 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); 1393 return ret; 1394 } 1395 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1396 return 0; 1397 } 1398 1399 static 1400 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, 1401 int num_downstream, u8 *ksv_fifo) 1402 { 1403 int ret; 1404 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, 1405 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1406 if (ret) { 1407 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret); 1408 return ret; 1409 } 1410 return 0; 1411 } 1412 1413 static 1414 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, 1415 int i, u32 *part) 1416 { 1417 int ret; 1418 1419 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1420 return -EINVAL; 1421 1422 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), 1423 part, DRM_HDCP_V_PRIME_PART_LEN); 1424 if (ret) 1425 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret); 1426 return ret; 1427 } 1428 1429 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) 1430 { 1431 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1432 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1433 struct drm_crtc *crtc = connector->base.state->crtc; 1434 struct intel_crtc *intel_crtc = container_of(crtc, 1435 struct intel_crtc, base); 1436 u32 scanline; 1437 int ret; 1438 1439 for (;;) { 1440 scanline = I915_READ(PIPEDSL(intel_crtc->pipe)); 1441 if (scanline > 100 && scanline < 200) 1442 break; 1443 usleep_range(25, 50); 1444 } 1445 1446 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); 1447 if (ret) { 1448 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret); 1449 return ret; 1450 } 1451 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); 1452 if (ret) { 1453 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret); 1454 return ret; 1455 } 1456 1457 return 0; 1458 } 1459 1460 static 1461 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, 1462 bool enable) 1463 { 1464 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1465 struct intel_connector *connector = hdmi->attached_connector; 1466 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1467 int ret; 1468 1469 if (!enable) 1470 usleep_range(6, 60); /* Bspec says >= 6us */ 1471 1472 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); 1473 if (ret) { 1474 DRM_ERROR("%s HDCP signalling failed (%d)\n", 1475 enable ? "Enable" : "Disable", ret); 1476 return ret; 1477 } 1478 1479 /* 1480 * WA: To fix incorrect positioning of the window of 1481 * opportunity and enc_en signalling in KABYLAKE. 1482 */ 1483 if (IS_KABYLAKE(dev_priv) && enable) 1484 return kbl_repositioning_enc_en_signal(connector); 1485 1486 return 0; 1487 } 1488 1489 static 1490 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) 1491 { 1492 struct drm_i915_private *dev_priv = 1493 intel_dig_port->base.base.dev->dev_private; 1494 enum port port = intel_dig_port->base.port; 1495 int ret; 1496 union { 1497 u32 reg; 1498 u8 shim[DRM_HDCP_RI_LEN]; 1499 } ri; 1500 1501 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); 1502 if (ret) 1503 return false; 1504 1505 I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); 1506 1507 /* Wait for Ri prime match */ 1508 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & 1509 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1510 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", 1511 I915_READ(PORT_HDCP_STATUS(port))); 1512 return false; 1513 } 1514 return true; 1515 } 1516 1517 static struct hdcp2_hdmi_msg_data { 1518 u8 msg_id; 1519 u32 timeout; 1520 u32 timeout2; 1521 } hdcp2_msg_data[] = { 1522 {HDCP_2_2_AKE_INIT, 0, 0}, 1523 {HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0}, 1524 {HDCP_2_2_AKE_NO_STORED_KM, 0, 0}, 1525 {HDCP_2_2_AKE_STORED_KM, 0, 0}, 1526 {HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, 1527 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS}, 1528 {HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, 1529 0}, 1530 {HDCP_2_2_LC_INIT, 0, 0}, 1531 {HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0}, 1532 {HDCP_2_2_SKE_SEND_EKS, 0, 0}, 1533 {HDCP_2_2_REP_SEND_RECVID_LIST, 1534 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0}, 1535 {HDCP_2_2_REP_SEND_ACK, 0, 0}, 1536 {HDCP_2_2_REP_STREAM_MANAGE, 0, 0}, 1537 {HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 1538 0}, 1539 }; 1540 1541 static 1542 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, 1543 u8 *rx_status) 1544 { 1545 return intel_hdmi_hdcp_read(intel_dig_port, 1546 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1547 rx_status, 1548 HDCP_2_2_HDMI_RXSTATUS_LEN); 1549 } 1550 1551 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1552 { 1553 int i; 1554 1555 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++) 1556 if (hdcp2_msg_data[i].msg_id == msg_id && 1557 (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired)) 1558 return hdcp2_msg_data[i].timeout; 1559 else if (hdcp2_msg_data[i].msg_id == msg_id) 1560 return hdcp2_msg_data[i].timeout2; 1561 1562 return -EINVAL; 1563 } 1564 1565 static inline 1566 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port, 1567 u8 msg_id, bool *msg_ready, 1568 ssize_t *msg_sz) 1569 { 1570 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1571 int ret; 1572 1573 ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status); 1574 if (ret < 0) { 1575 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret); 1576 return ret; 1577 } 1578 1579 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1580 rx_status[0]); 1581 1582 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1583 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1584 *msg_sz); 1585 else 1586 *msg_ready = *msg_sz; 1587 1588 return 0; 1589 } 1590 1591 static ssize_t 1592 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, 1593 u8 msg_id, bool paired) 1594 { 1595 bool msg_ready = false; 1596 int timeout, ret; 1597 ssize_t msg_sz = 0; 1598 1599 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1600 if (timeout < 0) 1601 return timeout; 1602 1603 ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, 1604 msg_id, &msg_ready, 1605 &msg_sz), 1606 !ret && msg_ready && msg_sz, timeout * 1000, 1607 1000, 5 * 1000); 1608 if (ret) 1609 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n", 1610 msg_id, ret, timeout); 1611 1612 return ret ? ret : msg_sz; 1613 } 1614 1615 static 1616 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, 1617 void *buf, size_t size) 1618 { 1619 unsigned int offset; 1620 1621 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1622 return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); 1623 } 1624 1625 static 1626 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, 1627 u8 msg_id, void *buf, size_t size) 1628 { 1629 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1630 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1631 unsigned int offset; 1632 ssize_t ret; 1633 1634 ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, 1635 hdcp->is_paired); 1636 if (ret < 0) 1637 return ret; 1638 1639 /* 1640 * Available msg size should be equal to or lesser than the 1641 * available buffer. 1642 */ 1643 if (ret > size) { 1644 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n", 1645 ret, size); 1646 return -1; 1647 } 1648 1649 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1650 ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); 1651 if (ret) 1652 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret); 1653 1654 return ret; 1655 } 1656 1657 static 1658 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) 1659 { 1660 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1661 int ret; 1662 1663 ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); 1664 if (ret) 1665 return ret; 1666 1667 /* 1668 * Re-auth request and Link Integrity Failures are represented by 1669 * same bit. i.e reauth_req. 1670 */ 1671 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1672 ret = HDCP_REAUTH_REQUEST; 1673 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1674 ret = HDCP_TOPOLOGY_CHANGE; 1675 1676 return ret; 1677 } 1678 1679 static 1680 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, 1681 bool *capable) 1682 { 1683 u8 hdcp2_version; 1684 int ret; 1685 1686 *capable = false; 1687 ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1688 &hdcp2_version, sizeof(hdcp2_version)); 1689 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1690 *capable = true; 1691 1692 return ret; 1693 } 1694 1695 static inline 1696 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void) 1697 { 1698 return HDCP_PROTOCOL_HDMI; 1699 } 1700 1701 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1702 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1703 .read_bksv = intel_hdmi_hdcp_read_bksv, 1704 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1705 .repeater_present = intel_hdmi_hdcp_repeater_present, 1706 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1707 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1708 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1709 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1710 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1711 .check_link = intel_hdmi_hdcp_check_link, 1712 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1713 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1714 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1715 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1716 .protocol = HDCP_PROTOCOL_HDMI, 1717 }; 1718 1719 static void intel_hdmi_prepare(struct intel_encoder *encoder, 1720 const struct intel_crtc_state *crtc_state) 1721 { 1722 struct drm_device *dev = encoder->base.dev; 1723 struct drm_i915_private *dev_priv = to_i915(dev); 1724 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1725 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1726 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; 1727 u32 hdmi_val; 1728 1729 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 1730 1731 hdmi_val = SDVO_ENCODING_HDMI; 1732 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 1733 hdmi_val |= HDMI_COLOR_RANGE_16_235; 1734 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1735 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 1736 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1737 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 1738 1739 if (crtc_state->pipe_bpp > 24) 1740 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 1741 else 1742 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 1743 1744 if (crtc_state->has_hdmi_sink) 1745 hdmi_val |= HDMI_MODE_SELECT_HDMI; 1746 1747 if (HAS_PCH_CPT(dev_priv)) 1748 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1749 else if (IS_CHERRYVIEW(dev_priv)) 1750 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 1751 else 1752 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 1753 1754 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 1755 POSTING_READ(intel_hdmi->hdmi_reg); 1756 } 1757 1758 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 1759 enum pipe *pipe) 1760 { 1761 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1762 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1763 intel_wakeref_t wakeref; 1764 bool ret; 1765 1766 wakeref = intel_display_power_get_if_enabled(dev_priv, 1767 encoder->power_domain); 1768 if (!wakeref) 1769 return false; 1770 1771 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 1772 1773 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1774 1775 return ret; 1776 } 1777 1778 static void intel_hdmi_get_config(struct intel_encoder *encoder, 1779 struct intel_crtc_state *pipe_config) 1780 { 1781 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1782 struct drm_device *dev = encoder->base.dev; 1783 struct drm_i915_private *dev_priv = to_i915(dev); 1784 u32 tmp, flags = 0; 1785 int dotclock; 1786 1787 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 1788 1789 tmp = I915_READ(intel_hdmi->hdmi_reg); 1790 1791 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 1792 flags |= DRM_MODE_FLAG_PHSYNC; 1793 else 1794 flags |= DRM_MODE_FLAG_NHSYNC; 1795 1796 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 1797 flags |= DRM_MODE_FLAG_PVSYNC; 1798 else 1799 flags |= DRM_MODE_FLAG_NVSYNC; 1800 1801 if (tmp & HDMI_MODE_SELECT_HDMI) 1802 pipe_config->has_hdmi_sink = true; 1803 1804 pipe_config->infoframes.enable |= 1805 intel_hdmi_infoframes_enabled(encoder, pipe_config); 1806 1807 if (pipe_config->infoframes.enable) 1808 pipe_config->has_infoframe = true; 1809 1810 if (tmp & HDMI_AUDIO_ENABLE) 1811 pipe_config->has_audio = true; 1812 1813 if (!HAS_PCH_SPLIT(dev_priv) && 1814 tmp & HDMI_COLOR_RANGE_16_235) 1815 pipe_config->limited_color_range = true; 1816 1817 pipe_config->base.adjusted_mode.flags |= flags; 1818 1819 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 1820 dotclock = pipe_config->port_clock * 2 / 3; 1821 else 1822 dotclock = pipe_config->port_clock; 1823 1824 if (pipe_config->pixel_multiplier) 1825 dotclock /= pipe_config->pixel_multiplier; 1826 1827 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1828 1829 pipe_config->lane_count = 4; 1830 1831 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 1832 1833 intel_read_infoframe(encoder, pipe_config, 1834 HDMI_INFOFRAME_TYPE_AVI, 1835 &pipe_config->infoframes.avi); 1836 intel_read_infoframe(encoder, pipe_config, 1837 HDMI_INFOFRAME_TYPE_SPD, 1838 &pipe_config->infoframes.spd); 1839 intel_read_infoframe(encoder, pipe_config, 1840 HDMI_INFOFRAME_TYPE_VENDOR, 1841 &pipe_config->infoframes.hdmi); 1842 } 1843 1844 static void intel_enable_hdmi_audio(struct intel_encoder *encoder, 1845 const struct intel_crtc_state *pipe_config, 1846 const struct drm_connector_state *conn_state) 1847 { 1848 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 1849 1850 WARN_ON(!pipe_config->has_hdmi_sink); 1851 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 1852 pipe_name(crtc->pipe)); 1853 intel_audio_codec_enable(encoder, pipe_config, conn_state); 1854 } 1855 1856 static void g4x_enable_hdmi(struct intel_encoder *encoder, 1857 const struct intel_crtc_state *pipe_config, 1858 const struct drm_connector_state *conn_state) 1859 { 1860 struct drm_device *dev = encoder->base.dev; 1861 struct drm_i915_private *dev_priv = to_i915(dev); 1862 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1863 u32 temp; 1864 1865 temp = I915_READ(intel_hdmi->hdmi_reg); 1866 1867 temp |= SDVO_ENABLE; 1868 if (pipe_config->has_audio) 1869 temp |= HDMI_AUDIO_ENABLE; 1870 1871 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1872 POSTING_READ(intel_hdmi->hdmi_reg); 1873 1874 if (pipe_config->has_audio) 1875 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1876 } 1877 1878 static void ibx_enable_hdmi(struct intel_encoder *encoder, 1879 const struct intel_crtc_state *pipe_config, 1880 const struct drm_connector_state *conn_state) 1881 { 1882 struct drm_device *dev = encoder->base.dev; 1883 struct drm_i915_private *dev_priv = to_i915(dev); 1884 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1885 u32 temp; 1886 1887 temp = I915_READ(intel_hdmi->hdmi_reg); 1888 1889 temp |= SDVO_ENABLE; 1890 if (pipe_config->has_audio) 1891 temp |= HDMI_AUDIO_ENABLE; 1892 1893 /* 1894 * HW workaround, need to write this twice for issue 1895 * that may result in first write getting masked. 1896 */ 1897 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1898 POSTING_READ(intel_hdmi->hdmi_reg); 1899 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1900 POSTING_READ(intel_hdmi->hdmi_reg); 1901 1902 /* 1903 * HW workaround, need to toggle enable bit off and on 1904 * for 12bpc with pixel repeat. 1905 * 1906 * FIXME: BSpec says this should be done at the end of 1907 * of the modeset sequence, so not sure if this isn't too soon. 1908 */ 1909 if (pipe_config->pipe_bpp > 24 && 1910 pipe_config->pixel_multiplier > 1) { 1911 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 1912 POSTING_READ(intel_hdmi->hdmi_reg); 1913 1914 /* 1915 * HW workaround, need to write this twice for issue 1916 * that may result in first write getting masked. 1917 */ 1918 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1919 POSTING_READ(intel_hdmi->hdmi_reg); 1920 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1921 POSTING_READ(intel_hdmi->hdmi_reg); 1922 } 1923 1924 if (pipe_config->has_audio) 1925 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1926 } 1927 1928 static void cpt_enable_hdmi(struct intel_encoder *encoder, 1929 const struct intel_crtc_state *pipe_config, 1930 const struct drm_connector_state *conn_state) 1931 { 1932 struct drm_device *dev = encoder->base.dev; 1933 struct drm_i915_private *dev_priv = to_i915(dev); 1934 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 1935 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1936 enum pipe pipe = crtc->pipe; 1937 u32 temp; 1938 1939 temp = I915_READ(intel_hdmi->hdmi_reg); 1940 1941 temp |= SDVO_ENABLE; 1942 if (pipe_config->has_audio) 1943 temp |= HDMI_AUDIO_ENABLE; 1944 1945 /* 1946 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1947 * 1948 * The procedure for 12bpc is as follows: 1949 * 1. disable HDMI clock gating 1950 * 2. enable HDMI with 8bpc 1951 * 3. enable HDMI with 12bpc 1952 * 4. enable HDMI clock gating 1953 */ 1954 1955 if (pipe_config->pipe_bpp > 24) { 1956 I915_WRITE(TRANS_CHICKEN1(pipe), 1957 I915_READ(TRANS_CHICKEN1(pipe)) | 1958 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1959 1960 temp &= ~SDVO_COLOR_FORMAT_MASK; 1961 temp |= SDVO_COLOR_FORMAT_8bpc; 1962 } 1963 1964 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1965 POSTING_READ(intel_hdmi->hdmi_reg); 1966 1967 if (pipe_config->pipe_bpp > 24) { 1968 temp &= ~SDVO_COLOR_FORMAT_MASK; 1969 temp |= HDMI_COLOR_FORMAT_12bpc; 1970 1971 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1972 POSTING_READ(intel_hdmi->hdmi_reg); 1973 1974 I915_WRITE(TRANS_CHICKEN1(pipe), 1975 I915_READ(TRANS_CHICKEN1(pipe)) & 1976 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1977 } 1978 1979 if (pipe_config->has_audio) 1980 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1981 } 1982 1983 static void vlv_enable_hdmi(struct intel_encoder *encoder, 1984 const struct intel_crtc_state *pipe_config, 1985 const struct drm_connector_state *conn_state) 1986 { 1987 } 1988 1989 static void intel_disable_hdmi(struct intel_encoder *encoder, 1990 const struct intel_crtc_state *old_crtc_state, 1991 const struct drm_connector_state *old_conn_state) 1992 { 1993 struct drm_device *dev = encoder->base.dev; 1994 struct drm_i915_private *dev_priv = to_i915(dev); 1995 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1996 struct intel_digital_port *intel_dig_port = 1997 hdmi_to_dig_port(intel_hdmi); 1998 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 1999 u32 temp; 2000 2001 temp = I915_READ(intel_hdmi->hdmi_reg); 2002 2003 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 2004 I915_WRITE(intel_hdmi->hdmi_reg, temp); 2005 POSTING_READ(intel_hdmi->hdmi_reg); 2006 2007 /* 2008 * HW workaround for IBX, we need to move the port 2009 * to transcoder A after disabling it to allow the 2010 * matching DP port to be enabled on transcoder A. 2011 */ 2012 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 2013 /* 2014 * We get CPU/PCH FIFO underruns on the other pipe when 2015 * doing the workaround. Sweep them under the rug. 2016 */ 2017 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2018 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2019 2020 temp &= ~SDVO_PIPE_SEL_MASK; 2021 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 2022 /* 2023 * HW workaround, need to write this twice for issue 2024 * that may result in first write getting masked. 2025 */ 2026 I915_WRITE(intel_hdmi->hdmi_reg, temp); 2027 POSTING_READ(intel_hdmi->hdmi_reg); 2028 I915_WRITE(intel_hdmi->hdmi_reg, temp); 2029 POSTING_READ(intel_hdmi->hdmi_reg); 2030 2031 temp &= ~SDVO_ENABLE; 2032 I915_WRITE(intel_hdmi->hdmi_reg, temp); 2033 POSTING_READ(intel_hdmi->hdmi_reg); 2034 2035 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 2036 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2037 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2038 } 2039 2040 intel_dig_port->set_infoframes(encoder, 2041 false, 2042 old_crtc_state, old_conn_state); 2043 2044 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2045 } 2046 2047 static void g4x_disable_hdmi(struct intel_encoder *encoder, 2048 const struct intel_crtc_state *old_crtc_state, 2049 const struct drm_connector_state *old_conn_state) 2050 { 2051 if (old_crtc_state->has_audio) 2052 intel_audio_codec_disable(encoder, 2053 old_crtc_state, old_conn_state); 2054 2055 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 2056 } 2057 2058 static void pch_disable_hdmi(struct intel_encoder *encoder, 2059 const struct intel_crtc_state *old_crtc_state, 2060 const struct drm_connector_state *old_conn_state) 2061 { 2062 if (old_crtc_state->has_audio) 2063 intel_audio_codec_disable(encoder, 2064 old_crtc_state, old_conn_state); 2065 } 2066 2067 static void pch_post_disable_hdmi(struct intel_encoder *encoder, 2068 const struct intel_crtc_state *old_crtc_state, 2069 const struct drm_connector_state *old_conn_state) 2070 { 2071 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 2072 } 2073 2074 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 2075 { 2076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2077 const struct ddi_vbt_port_info *info = 2078 &dev_priv->vbt.ddi_port_info[encoder->port]; 2079 int max_tmds_clock; 2080 2081 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2082 max_tmds_clock = 594000; 2083 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 2084 max_tmds_clock = 300000; 2085 else if (INTEL_GEN(dev_priv) >= 5) 2086 max_tmds_clock = 225000; 2087 else 2088 max_tmds_clock = 165000; 2089 2090 if (info->max_tmds_clock) 2091 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); 2092 2093 return max_tmds_clock; 2094 } 2095 2096 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 2097 bool respect_downstream_limits, 2098 bool force_dvi) 2099 { 2100 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2101 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 2102 2103 if (respect_downstream_limits) { 2104 struct intel_connector *connector = hdmi->attached_connector; 2105 const struct drm_display_info *info = &connector->base.display_info; 2106 2107 if (hdmi->dp_dual_mode.max_tmds_clock) 2108 max_tmds_clock = min(max_tmds_clock, 2109 hdmi->dp_dual_mode.max_tmds_clock); 2110 2111 if (info->max_tmds_clock) 2112 max_tmds_clock = min(max_tmds_clock, 2113 info->max_tmds_clock); 2114 else if (!hdmi->has_hdmi_sink || force_dvi) 2115 max_tmds_clock = min(max_tmds_clock, 165000); 2116 } 2117 2118 return max_tmds_clock; 2119 } 2120 2121 static enum drm_mode_status 2122 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 2123 int clock, bool respect_downstream_limits, 2124 bool force_dvi) 2125 { 2126 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 2127 2128 if (clock < 25000) 2129 return MODE_CLOCK_LOW; 2130 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) 2131 return MODE_CLOCK_HIGH; 2132 2133 /* BXT DPLL can't generate 223-240 MHz */ 2134 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) 2135 return MODE_CLOCK_RANGE; 2136 2137 /* CHV DPLL can't generate 216-240 MHz */ 2138 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 2139 return MODE_CLOCK_RANGE; 2140 2141 return MODE_OK; 2142 } 2143 2144 static enum drm_mode_status 2145 intel_hdmi_mode_valid(struct drm_connector *connector, 2146 struct drm_display_mode *mode) 2147 { 2148 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 2149 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 2150 struct drm_i915_private *dev_priv = to_i915(dev); 2151 enum drm_mode_status status; 2152 int clock; 2153 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 2154 bool force_dvi = 2155 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; 2156 2157 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 2158 return MODE_NO_DBLESCAN; 2159 2160 clock = mode->clock; 2161 2162 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2163 clock *= 2; 2164 2165 if (clock > max_dotclk) 2166 return MODE_CLOCK_HIGH; 2167 2168 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2169 clock *= 2; 2170 2171 if (drm_mode_is_420_only(&connector->display_info, mode)) 2172 clock /= 2; 2173 2174 /* check if we can do 8bpc */ 2175 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); 2176 2177 if (hdmi->has_hdmi_sink && !force_dvi) { 2178 /* if we can't do 8bpc we may still be able to do 12bpc */ 2179 if (status != MODE_OK && !HAS_GMCH(dev_priv)) 2180 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, 2181 true, force_dvi); 2182 2183 /* if we can't do 8,12bpc we may still be able to do 10bpc */ 2184 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) 2185 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, 2186 true, force_dvi); 2187 } 2188 2189 return status; 2190 } 2191 2192 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 2193 int bpc) 2194 { 2195 struct drm_i915_private *dev_priv = 2196 to_i915(crtc_state->base.crtc->dev); 2197 struct drm_atomic_state *state = crtc_state->base.state; 2198 struct drm_connector_state *connector_state; 2199 struct drm_connector *connector; 2200 const struct drm_display_mode *adjusted_mode = 2201 &crtc_state->base.adjusted_mode; 2202 int i; 2203 2204 if (HAS_GMCH(dev_priv)) 2205 return false; 2206 2207 if (bpc == 10 && INTEL_GEN(dev_priv) < 11) 2208 return false; 2209 2210 if (crtc_state->pipe_bpp < bpc * 3) 2211 return false; 2212 2213 if (!crtc_state->has_hdmi_sink) 2214 return false; 2215 2216 /* 2217 * HDMI deep color affects the clocks, so it's only possible 2218 * when not cloning with other encoder types. 2219 */ 2220 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) 2221 return false; 2222 2223 for_each_new_connector_in_state(state, connector, connector_state, i) { 2224 const struct drm_display_info *info = &connector->display_info; 2225 2226 if (connector_state->crtc != crtc_state->base.crtc) 2227 continue; 2228 2229 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 2230 const struct drm_hdmi_info *hdmi = &info->hdmi; 2231 2232 if (bpc == 12 && !(hdmi->y420_dc_modes & 2233 DRM_EDID_YCBCR420_DC_36)) 2234 return false; 2235 else if (bpc == 10 && !(hdmi->y420_dc_modes & 2236 DRM_EDID_YCBCR420_DC_30)) 2237 return false; 2238 } else { 2239 if (bpc == 12 && !(info->edid_hdmi_dc_modes & 2240 DRM_EDID_HDMI_DC_36)) 2241 return false; 2242 else if (bpc == 10 && !(info->edid_hdmi_dc_modes & 2243 DRM_EDID_HDMI_DC_30)) 2244 return false; 2245 } 2246 } 2247 2248 /* Display WA #1139: glk */ 2249 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && 2250 adjusted_mode->htotal > 5460) 2251 return false; 2252 2253 /* Display Wa_1405510057:icl */ 2254 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 2255 bpc == 10 && INTEL_GEN(dev_priv) >= 11 && 2256 (adjusted_mode->crtc_hblank_end - 2257 adjusted_mode->crtc_hblank_start) % 8 == 2) 2258 return false; 2259 2260 return true; 2261 } 2262 2263 static bool 2264 intel_hdmi_ycbcr420_config(struct drm_connector *connector, 2265 struct intel_crtc_state *config, 2266 int *clock_12bpc, int *clock_10bpc, 2267 int *clock_8bpc) 2268 { 2269 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); 2270 2271 if (!connector->ycbcr_420_allowed) { 2272 DRM_ERROR("Platform doesn't support YCBCR420 output\n"); 2273 return false; 2274 } 2275 2276 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 2277 config->port_clock /= 2; 2278 *clock_12bpc /= 2; 2279 *clock_10bpc /= 2; 2280 *clock_8bpc /= 2; 2281 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2282 2283 /* YCBCR 420 output conversion needs a scaler */ 2284 if (skl_update_scaler_crtc(config)) { 2285 DRM_DEBUG_KMS("Scaler allocation for output failed\n"); 2286 return false; 2287 } 2288 2289 intel_pch_panel_fitting(intel_crtc, config, 2290 DRM_MODE_SCALE_FULLSCREEN); 2291 2292 return true; 2293 } 2294 2295 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2296 struct intel_crtc_state *pipe_config, 2297 struct drm_connector_state *conn_state) 2298 { 2299 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 2300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2301 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 2302 struct drm_connector *connector = conn_state->connector; 2303 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2304 struct intel_digital_connector_state *intel_conn_state = 2305 to_intel_digital_connector_state(conn_state); 2306 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; 2307 int clock_10bpc = clock_8bpc * 5 / 4; 2308 int clock_12bpc = clock_8bpc * 3 / 2; 2309 int desired_bpp; 2310 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; 2311 2312 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2313 return -EINVAL; 2314 2315 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2316 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; 2317 2318 if (pipe_config->has_hdmi_sink) 2319 pipe_config->has_infoframe = true; 2320 2321 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2322 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2323 pipe_config->limited_color_range = 2324 pipe_config->has_hdmi_sink && 2325 drm_default_rgb_quant_range(adjusted_mode) == 2326 HDMI_QUANTIZATION_RANGE_LIMITED; 2327 } else { 2328 pipe_config->limited_color_range = 2329 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2330 } 2331 2332 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { 2333 pipe_config->pixel_multiplier = 2; 2334 clock_8bpc *= 2; 2335 clock_10bpc *= 2; 2336 clock_12bpc *= 2; 2337 } 2338 2339 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { 2340 if (!intel_hdmi_ycbcr420_config(connector, pipe_config, 2341 &clock_12bpc, &clock_10bpc, 2342 &clock_8bpc)) { 2343 DRM_ERROR("Can't support YCBCR420 output\n"); 2344 return -EINVAL; 2345 } 2346 } 2347 2348 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 2349 pipe_config->has_pch_encoder = true; 2350 2351 if (pipe_config->has_hdmi_sink) { 2352 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2353 pipe_config->has_audio = intel_hdmi->has_audio; 2354 else 2355 pipe_config->has_audio = 2356 intel_conn_state->force_audio == HDMI_AUDIO_ON; 2357 } 2358 2359 /* 2360 * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need 2361 * to check that the higher clock still fits within limits. 2362 */ 2363 if (hdmi_deep_color_possible(pipe_config, 12) && 2364 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, 2365 true, force_dvi) == MODE_OK) { 2366 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 2367 desired_bpp = 12*3; 2368 2369 /* Need to adjust the port link by 1.5x for 12bpc. */ 2370 pipe_config->port_clock = clock_12bpc; 2371 } else if (hdmi_deep_color_possible(pipe_config, 10) && 2372 hdmi_port_clock_valid(intel_hdmi, clock_10bpc, 2373 true, force_dvi) == MODE_OK) { 2374 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n"); 2375 desired_bpp = 10 * 3; 2376 2377 /* Need to adjust the port link by 1.25x for 10bpc. */ 2378 pipe_config->port_clock = clock_10bpc; 2379 } else { 2380 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 2381 desired_bpp = 8*3; 2382 2383 pipe_config->port_clock = clock_8bpc; 2384 } 2385 2386 if (!pipe_config->bw_constrained) { 2387 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp); 2388 pipe_config->pipe_bpp = desired_bpp; 2389 } 2390 2391 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, 2392 false, force_dvi) != MODE_OK) { 2393 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); 2394 return -EINVAL; 2395 } 2396 2397 /* Set user selected PAR to incoming mode's member */ 2398 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; 2399 2400 pipe_config->lane_count = 4; 2401 2402 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || 2403 IS_GEMINILAKE(dev_priv))) { 2404 if (scdc->scrambling.low_rates) 2405 pipe_config->hdmi_scrambling = true; 2406 2407 if (pipe_config->port_clock > 340000) { 2408 pipe_config->hdmi_scrambling = true; 2409 pipe_config->hdmi_high_tmds_clock_ratio = true; 2410 } 2411 } 2412 2413 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); 2414 2415 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2416 DRM_DEBUG_KMS("bad AVI infoframe\n"); 2417 return -EINVAL; 2418 } 2419 2420 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2421 DRM_DEBUG_KMS("bad SPD infoframe\n"); 2422 return -EINVAL; 2423 } 2424 2425 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2426 DRM_DEBUG_KMS("bad HDMI infoframe\n"); 2427 return -EINVAL; 2428 } 2429 2430 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2431 DRM_DEBUG_KMS("bad DRM infoframe\n"); 2432 return -EINVAL; 2433 } 2434 2435 return 0; 2436 } 2437 2438 static void 2439 intel_hdmi_unset_edid(struct drm_connector *connector) 2440 { 2441 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2442 2443 intel_hdmi->has_hdmi_sink = false; 2444 intel_hdmi->has_audio = false; 2445 2446 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2447 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2448 2449 kfree(to_intel_connector(connector)->detect_edid); 2450 to_intel_connector(connector)->detect_edid = NULL; 2451 } 2452 2453 static void 2454 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 2455 { 2456 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2457 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 2458 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2459 struct i2c_adapter *adapter = 2460 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2461 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); 2462 2463 /* 2464 * Type 1 DVI adaptors are not required to implement any 2465 * registers, so we can't always detect their presence. 2466 * Ideally we should be able to check the state of the 2467 * CONFIG1 pin, but no such luck on our hardware. 2468 * 2469 * The only method left to us is to check the VBT to see 2470 * if the port is a dual mode capable DP port. But let's 2471 * only do that when we sucesfully read the EDID, to avoid 2472 * confusing log messages about DP dual mode adaptors when 2473 * there's nothing connected to the port. 2474 */ 2475 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2476 /* An overridden EDID imply that we want this port for testing. 2477 * Make sure not to set limits for that port. 2478 */ 2479 if (has_edid && !connector->override_edid && 2480 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2481 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); 2482 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2483 } else { 2484 type = DRM_DP_DUAL_MODE_NONE; 2485 } 2486 } 2487 2488 if (type == DRM_DP_DUAL_MODE_NONE) 2489 return; 2490 2491 hdmi->dp_dual_mode.type = type; 2492 hdmi->dp_dual_mode.max_tmds_clock = 2493 drm_dp_dual_mode_max_tmds_clock(type, adapter); 2494 2495 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2496 drm_dp_get_dual_mode_type_name(type), 2497 hdmi->dp_dual_mode.max_tmds_clock); 2498 } 2499 2500 static bool 2501 intel_hdmi_set_edid(struct drm_connector *connector) 2502 { 2503 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2504 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2505 intel_wakeref_t wakeref; 2506 struct edid *edid; 2507 bool connected = false; 2508 struct i2c_adapter *i2c; 2509 2510 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2511 2512 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2513 2514 edid = drm_get_edid(connector, i2c); 2515 2516 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2517 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2518 intel_gmbus_force_bit(i2c, true); 2519 edid = drm_get_edid(connector, i2c); 2520 intel_gmbus_force_bit(i2c, false); 2521 } 2522 2523 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 2524 2525 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2526 2527 to_intel_connector(connector)->detect_edid = edid; 2528 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2529 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2530 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2531 2532 connected = true; 2533 } 2534 2535 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2536 2537 return connected; 2538 } 2539 2540 static enum drm_connector_status 2541 intel_hdmi_detect(struct drm_connector *connector, bool force) 2542 { 2543 enum drm_connector_status status = connector_status_disconnected; 2544 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2545 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2546 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2547 intel_wakeref_t wakeref; 2548 2549 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2550 connector->base.id, connector->name); 2551 2552 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2553 2554 if (INTEL_GEN(dev_priv) >= 11 && 2555 !intel_digital_port_connected(encoder)) 2556 goto out; 2557 2558 intel_hdmi_unset_edid(connector); 2559 2560 if (intel_hdmi_set_edid(connector)) 2561 status = connector_status_connected; 2562 2563 out: 2564 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2565 2566 if (status != connector_status_connected) 2567 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2568 2569 return status; 2570 } 2571 2572 static void 2573 intel_hdmi_force(struct drm_connector *connector) 2574 { 2575 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2576 connector->base.id, connector->name); 2577 2578 intel_hdmi_unset_edid(connector); 2579 2580 if (connector->status != connector_status_connected) 2581 return; 2582 2583 intel_hdmi_set_edid(connector); 2584 } 2585 2586 static int intel_hdmi_get_modes(struct drm_connector *connector) 2587 { 2588 struct edid *edid; 2589 2590 edid = to_intel_connector(connector)->detect_edid; 2591 if (edid == NULL) 2592 return 0; 2593 2594 return intel_connector_update_modes(connector, edid); 2595 } 2596 2597 static void intel_hdmi_pre_enable(struct intel_encoder *encoder, 2598 const struct intel_crtc_state *pipe_config, 2599 const struct drm_connector_state *conn_state) 2600 { 2601 struct intel_digital_port *intel_dig_port = 2602 enc_to_dig_port(&encoder->base); 2603 2604 intel_hdmi_prepare(encoder, pipe_config); 2605 2606 intel_dig_port->set_infoframes(encoder, 2607 pipe_config->has_infoframe, 2608 pipe_config, conn_state); 2609 } 2610 2611 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, 2612 const struct intel_crtc_state *pipe_config, 2613 const struct drm_connector_state *conn_state) 2614 { 2615 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 2616 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2617 2618 vlv_phy_pre_encoder_enable(encoder, pipe_config); 2619 2620 /* HDMI 1.0V-2dB */ 2621 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 2622 0x2b247878); 2623 2624 dport->set_infoframes(encoder, 2625 pipe_config->has_infoframe, 2626 pipe_config, conn_state); 2627 2628 g4x_enable_hdmi(encoder, pipe_config, conn_state); 2629 2630 vlv_wait_port_ready(dev_priv, dport, 0x0); 2631 } 2632 2633 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 2634 const struct intel_crtc_state *pipe_config, 2635 const struct drm_connector_state *conn_state) 2636 { 2637 intel_hdmi_prepare(encoder, pipe_config); 2638 2639 vlv_phy_pre_pll_enable(encoder, pipe_config); 2640 } 2641 2642 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 2643 const struct intel_crtc_state *pipe_config, 2644 const struct drm_connector_state *conn_state) 2645 { 2646 intel_hdmi_prepare(encoder, pipe_config); 2647 2648 chv_phy_pre_pll_enable(encoder, pipe_config); 2649 } 2650 2651 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, 2652 const struct intel_crtc_state *old_crtc_state, 2653 const struct drm_connector_state *old_conn_state) 2654 { 2655 chv_phy_post_pll_disable(encoder, old_crtc_state); 2656 } 2657 2658 static void vlv_hdmi_post_disable(struct intel_encoder *encoder, 2659 const struct intel_crtc_state *old_crtc_state, 2660 const struct drm_connector_state *old_conn_state) 2661 { 2662 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 2663 vlv_phy_reset_lanes(encoder, old_crtc_state); 2664 } 2665 2666 static void chv_hdmi_post_disable(struct intel_encoder *encoder, 2667 const struct intel_crtc_state *old_crtc_state, 2668 const struct drm_connector_state *old_conn_state) 2669 { 2670 struct drm_device *dev = encoder->base.dev; 2671 struct drm_i915_private *dev_priv = to_i915(dev); 2672 2673 vlv_dpio_get(dev_priv); 2674 2675 /* Assert data lane reset */ 2676 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 2677 2678 vlv_dpio_put(dev_priv); 2679 } 2680 2681 static void chv_hdmi_pre_enable(struct intel_encoder *encoder, 2682 const struct intel_crtc_state *pipe_config, 2683 const struct drm_connector_state *conn_state) 2684 { 2685 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 2686 struct drm_device *dev = encoder->base.dev; 2687 struct drm_i915_private *dev_priv = to_i915(dev); 2688 2689 chv_phy_pre_encoder_enable(encoder, pipe_config); 2690 2691 /* FIXME: Program the support xxx V-dB */ 2692 /* Use 800mV-0dB */ 2693 chv_set_phy_signal_level(encoder, 128, 102, false); 2694 2695 dport->set_infoframes(encoder, 2696 pipe_config->has_infoframe, 2697 pipe_config, conn_state); 2698 2699 g4x_enable_hdmi(encoder, pipe_config, conn_state); 2700 2701 vlv_wait_port_ready(dev_priv, dport, 0x0); 2702 2703 /* Second common lane will stay alive on its own now */ 2704 chv_phy_release_cl2_override(encoder); 2705 } 2706 2707 static struct i2c_adapter * 2708 intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2709 { 2710 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2711 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2712 2713 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2714 } 2715 2716 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2717 { 2718 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2719 struct kobject *i2c_kobj = &adapter->dev.kobj; 2720 struct kobject *connector_kobj = &connector->kdev->kobj; 2721 int ret; 2722 2723 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2724 if (ret) 2725 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret); 2726 } 2727 2728 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2729 { 2730 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2731 struct kobject *i2c_kobj = &adapter->dev.kobj; 2732 struct kobject *connector_kobj = &connector->kdev->kobj; 2733 2734 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2735 } 2736 2737 static int 2738 intel_hdmi_connector_register(struct drm_connector *connector) 2739 { 2740 int ret; 2741 2742 ret = intel_connector_register(connector); 2743 if (ret) 2744 return ret; 2745 2746 i915_debugfs_connector_add(connector); 2747 2748 intel_hdmi_create_i2c_symlink(connector); 2749 2750 return ret; 2751 } 2752 2753 static void intel_hdmi_destroy(struct drm_connector *connector) 2754 { 2755 if (intel_attached_hdmi(connector)->cec_notifier) 2756 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier); 2757 2758 intel_connector_destroy(connector); 2759 } 2760 2761 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2762 { 2763 intel_hdmi_remove_i2c_symlink(connector); 2764 2765 intel_connector_unregister(connector); 2766 } 2767 2768 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2769 .detect = intel_hdmi_detect, 2770 .force = intel_hdmi_force, 2771 .fill_modes = drm_helper_probe_single_connector_modes, 2772 .atomic_get_property = intel_digital_connector_atomic_get_property, 2773 .atomic_set_property = intel_digital_connector_atomic_set_property, 2774 .late_register = intel_hdmi_connector_register, 2775 .early_unregister = intel_hdmi_connector_unregister, 2776 .destroy = intel_hdmi_destroy, 2777 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2778 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2779 }; 2780 2781 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2782 .get_modes = intel_hdmi_get_modes, 2783 .mode_valid = intel_hdmi_mode_valid, 2784 .atomic_check = intel_digital_connector_atomic_check, 2785 }; 2786 2787 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 2788 .destroy = intel_encoder_destroy, 2789 }; 2790 2791 static void 2792 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2793 { 2794 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2795 struct intel_digital_port *intel_dig_port = 2796 hdmi_to_dig_port(intel_hdmi); 2797 2798 intel_attach_force_audio_property(connector); 2799 intel_attach_broadcast_rgb_property(connector); 2800 intel_attach_aspect_ratio_property(connector); 2801 2802 /* 2803 * Attach Colorspace property for Non LSPCON based device 2804 * ToDo: This needs to be extended for LSPCON implementation 2805 * as well. Will be implemented separately. 2806 */ 2807 if (!intel_dig_port->lspcon.active) 2808 intel_attach_colorspace_property(connector); 2809 2810 drm_connector_attach_content_type_property(connector); 2811 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2812 2813 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2814 drm_object_attach_property(&connector->base, 2815 connector->dev->mode_config.hdr_output_metadata_property, 0); 2816 2817 if (!HAS_GMCH(dev_priv)) 2818 drm_connector_attach_max_bpc_property(connector, 8, 12); 2819 } 2820 2821 /* 2822 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2823 * @encoder: intel_encoder 2824 * @connector: drm_connector 2825 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2826 * or reset the high tmds clock ratio for scrambling 2827 * @scrambling: bool to Indicate if the function needs to set or reset 2828 * sink scrambling 2829 * 2830 * This function handles scrambling on HDMI 2.0 capable sinks. 2831 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2832 * it enables scrambling. This should be called before enabling the HDMI 2833 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2834 * detect a scrambled clock within 100 ms. 2835 * 2836 * Returns: 2837 * True on success, false on failure. 2838 */ 2839 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2840 struct drm_connector *connector, 2841 bool high_tmds_clock_ratio, 2842 bool scrambling) 2843 { 2844 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2845 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 2846 struct drm_scrambling *sink_scrambling = 2847 &connector->display_info.hdmi.scdc.scrambling; 2848 struct i2c_adapter *adapter = 2849 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2850 2851 if (!sink_scrambling->supported) 2852 return true; 2853 2854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2855 connector->base.id, connector->name, 2856 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); 2857 2858 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2859 return drm_scdc_set_high_tmds_clock_ratio(adapter, 2860 high_tmds_clock_ratio) && 2861 drm_scdc_set_scrambling(adapter, scrambling); 2862 } 2863 2864 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2865 { 2866 u8 ddc_pin; 2867 2868 switch (port) { 2869 case PORT_B: 2870 ddc_pin = GMBUS_PIN_DPB; 2871 break; 2872 case PORT_C: 2873 ddc_pin = GMBUS_PIN_DPC; 2874 break; 2875 case PORT_D: 2876 ddc_pin = GMBUS_PIN_DPD_CHV; 2877 break; 2878 default: 2879 MISSING_CASE(port); 2880 ddc_pin = GMBUS_PIN_DPB; 2881 break; 2882 } 2883 return ddc_pin; 2884 } 2885 2886 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2887 { 2888 u8 ddc_pin; 2889 2890 switch (port) { 2891 case PORT_B: 2892 ddc_pin = GMBUS_PIN_1_BXT; 2893 break; 2894 case PORT_C: 2895 ddc_pin = GMBUS_PIN_2_BXT; 2896 break; 2897 default: 2898 MISSING_CASE(port); 2899 ddc_pin = GMBUS_PIN_1_BXT; 2900 break; 2901 } 2902 return ddc_pin; 2903 } 2904 2905 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2906 enum port port) 2907 { 2908 u8 ddc_pin; 2909 2910 switch (port) { 2911 case PORT_B: 2912 ddc_pin = GMBUS_PIN_1_BXT; 2913 break; 2914 case PORT_C: 2915 ddc_pin = GMBUS_PIN_2_BXT; 2916 break; 2917 case PORT_D: 2918 ddc_pin = GMBUS_PIN_4_CNP; 2919 break; 2920 case PORT_F: 2921 ddc_pin = GMBUS_PIN_3_BXT; 2922 break; 2923 default: 2924 MISSING_CASE(port); 2925 ddc_pin = GMBUS_PIN_1_BXT; 2926 break; 2927 } 2928 return ddc_pin; 2929 } 2930 2931 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2932 { 2933 u8 ddc_pin; 2934 2935 switch (port) { 2936 case PORT_A: 2937 ddc_pin = GMBUS_PIN_1_BXT; 2938 break; 2939 case PORT_B: 2940 ddc_pin = GMBUS_PIN_2_BXT; 2941 break; 2942 case PORT_C: 2943 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2944 break; 2945 case PORT_D: 2946 ddc_pin = GMBUS_PIN_10_TC2_ICP; 2947 break; 2948 case PORT_E: 2949 ddc_pin = GMBUS_PIN_11_TC3_ICP; 2950 break; 2951 case PORT_F: 2952 ddc_pin = GMBUS_PIN_12_TC4_ICP; 2953 break; 2954 default: 2955 MISSING_CASE(port); 2956 ddc_pin = GMBUS_PIN_2_BXT; 2957 break; 2958 } 2959 return ddc_pin; 2960 } 2961 2962 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2963 { 2964 u8 ddc_pin; 2965 2966 switch (port) { 2967 case PORT_A: 2968 ddc_pin = GMBUS_PIN_1_BXT; 2969 break; 2970 case PORT_B: 2971 ddc_pin = GMBUS_PIN_2_BXT; 2972 break; 2973 case PORT_C: 2974 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2975 break; 2976 default: 2977 MISSING_CASE(port); 2978 ddc_pin = GMBUS_PIN_1_BXT; 2979 break; 2980 } 2981 return ddc_pin; 2982 } 2983 2984 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2985 enum port port) 2986 { 2987 u8 ddc_pin; 2988 2989 switch (port) { 2990 case PORT_B: 2991 ddc_pin = GMBUS_PIN_DPB; 2992 break; 2993 case PORT_C: 2994 ddc_pin = GMBUS_PIN_DPC; 2995 break; 2996 case PORT_D: 2997 ddc_pin = GMBUS_PIN_DPD; 2998 break; 2999 default: 3000 MISSING_CASE(port); 3001 ddc_pin = GMBUS_PIN_DPB; 3002 break; 3003 } 3004 return ddc_pin; 3005 } 3006 3007 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, 3008 enum port port) 3009 { 3010 const struct ddi_vbt_port_info *info = 3011 &dev_priv->vbt.ddi_port_info[port]; 3012 u8 ddc_pin; 3013 3014 if (info->alternate_ddc_pin) { 3015 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", 3016 info->alternate_ddc_pin, port_name(port)); 3017 return info->alternate_ddc_pin; 3018 } 3019 3020 if (HAS_PCH_MCC(dev_priv)) 3021 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 3022 else if (HAS_PCH_ICP(dev_priv)) 3023 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 3024 else if (HAS_PCH_CNP(dev_priv)) 3025 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 3026 else if (IS_GEN9_LP(dev_priv)) 3027 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 3028 else if (IS_CHERRYVIEW(dev_priv)) 3029 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 3030 else 3031 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 3032 3033 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", 3034 ddc_pin, port_name(port)); 3035 3036 return ddc_pin; 3037 } 3038 3039 void intel_infoframe_init(struct intel_digital_port *intel_dig_port) 3040 { 3041 struct drm_i915_private *dev_priv = 3042 to_i915(intel_dig_port->base.base.dev); 3043 3044 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3045 intel_dig_port->write_infoframe = vlv_write_infoframe; 3046 intel_dig_port->read_infoframe = vlv_read_infoframe; 3047 intel_dig_port->set_infoframes = vlv_set_infoframes; 3048 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; 3049 } else if (IS_G4X(dev_priv)) { 3050 intel_dig_port->write_infoframe = g4x_write_infoframe; 3051 intel_dig_port->read_infoframe = g4x_read_infoframe; 3052 intel_dig_port->set_infoframes = g4x_set_infoframes; 3053 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; 3054 } else if (HAS_DDI(dev_priv)) { 3055 if (intel_dig_port->lspcon.active) { 3056 intel_dig_port->write_infoframe = lspcon_write_infoframe; 3057 intel_dig_port->read_infoframe = lspcon_read_infoframe; 3058 intel_dig_port->set_infoframes = lspcon_set_infoframes; 3059 intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3060 } else { 3061 intel_dig_port->write_infoframe = hsw_write_infoframe; 3062 intel_dig_port->read_infoframe = hsw_read_infoframe; 3063 intel_dig_port->set_infoframes = hsw_set_infoframes; 3064 intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; 3065 } 3066 } else if (HAS_PCH_IBX(dev_priv)) { 3067 intel_dig_port->write_infoframe = ibx_write_infoframe; 3068 intel_dig_port->read_infoframe = ibx_read_infoframe; 3069 intel_dig_port->set_infoframes = ibx_set_infoframes; 3070 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; 3071 } else { 3072 intel_dig_port->write_infoframe = cpt_write_infoframe; 3073 intel_dig_port->read_infoframe = cpt_read_infoframe; 3074 intel_dig_port->set_infoframes = cpt_set_infoframes; 3075 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; 3076 } 3077 } 3078 3079 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 3080 struct intel_connector *intel_connector) 3081 { 3082 struct drm_connector *connector = &intel_connector->base; 3083 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3084 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3085 struct drm_device *dev = intel_encoder->base.dev; 3086 struct drm_i915_private *dev_priv = to_i915(dev); 3087 enum port port = intel_encoder->port; 3088 3089 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", 3090 port_name(port)); 3091 3092 if (WARN(intel_dig_port->max_lanes < 4, 3093 "Not enough lanes (%d) for HDMI on port %c\n", 3094 intel_dig_port->max_lanes, port_name(port))) 3095 return; 3096 3097 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 3098 DRM_MODE_CONNECTOR_HDMIA); 3099 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3100 3101 connector->interlace_allowed = 1; 3102 connector->doublescan_allowed = 0; 3103 connector->stereo_allowed = 1; 3104 3105 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 3106 connector->ycbcr_420_allowed = true; 3107 3108 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); 3109 3110 if (WARN_ON(port == PORT_A)) 3111 return; 3112 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 3113 3114 if (HAS_DDI(dev_priv)) 3115 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3116 else 3117 intel_connector->get_hw_state = intel_connector_get_hw_state; 3118 3119 intel_hdmi_add_properties(intel_hdmi, connector); 3120 3121 intel_connector_attach_encoder(intel_connector, intel_encoder); 3122 intel_hdmi->attached_connector = intel_connector; 3123 3124 if (is_hdcp_supported(dev_priv, port)) { 3125 int ret = intel_hdcp_init(intel_connector, 3126 &intel_hdmi_hdcp_shim); 3127 if (ret) 3128 DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); 3129 } 3130 3131 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3132 * 0xd. Failure to do so will result in spurious interrupts being 3133 * generated on the port when a cable is not attached. 3134 */ 3135 if (IS_G45(dev_priv)) { 3136 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 3137 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 3138 } 3139 3140 intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev, 3141 port_identifier(port)); 3142 if (!intel_hdmi->cec_notifier) 3143 DRM_DEBUG_KMS("CEC notifier get failed\n"); 3144 } 3145 3146 void intel_hdmi_init(struct drm_i915_private *dev_priv, 3147 i915_reg_t hdmi_reg, enum port port) 3148 { 3149 struct intel_digital_port *intel_dig_port; 3150 struct intel_encoder *intel_encoder; 3151 struct intel_connector *intel_connector; 3152 3153 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3154 if (!intel_dig_port) 3155 return; 3156 3157 intel_connector = intel_connector_alloc(); 3158 if (!intel_connector) { 3159 kfree(intel_dig_port); 3160 return; 3161 } 3162 3163 intel_encoder = &intel_dig_port->base; 3164 3165 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3166 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 3167 "HDMI %c", port_name(port)); 3168 3169 intel_encoder->hotplug = intel_encoder_hotplug; 3170 intel_encoder->compute_config = intel_hdmi_compute_config; 3171 if (HAS_PCH_SPLIT(dev_priv)) { 3172 intel_encoder->disable = pch_disable_hdmi; 3173 intel_encoder->post_disable = pch_post_disable_hdmi; 3174 } else { 3175 intel_encoder->disable = g4x_disable_hdmi; 3176 } 3177 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 3178 intel_encoder->get_config = intel_hdmi_get_config; 3179 if (IS_CHERRYVIEW(dev_priv)) { 3180 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 3181 intel_encoder->pre_enable = chv_hdmi_pre_enable; 3182 intel_encoder->enable = vlv_enable_hdmi; 3183 intel_encoder->post_disable = chv_hdmi_post_disable; 3184 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 3185 } else if (IS_VALLEYVIEW(dev_priv)) { 3186 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 3187 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 3188 intel_encoder->enable = vlv_enable_hdmi; 3189 intel_encoder->post_disable = vlv_hdmi_post_disable; 3190 } else { 3191 intel_encoder->pre_enable = intel_hdmi_pre_enable; 3192 if (HAS_PCH_CPT(dev_priv)) 3193 intel_encoder->enable = cpt_enable_hdmi; 3194 else if (HAS_PCH_IBX(dev_priv)) 3195 intel_encoder->enable = ibx_enable_hdmi; 3196 else 3197 intel_encoder->enable = g4x_enable_hdmi; 3198 } 3199 3200 intel_encoder->type = INTEL_OUTPUT_HDMI; 3201 intel_encoder->power_domain = intel_port_to_power_domain(port); 3202 intel_encoder->port = port; 3203 if (IS_CHERRYVIEW(dev_priv)) { 3204 if (port == PORT_D) 3205 intel_encoder->crtc_mask = 1 << 2; 3206 else 3207 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 3208 } else { 3209 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3210 } 3211 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 3212 /* 3213 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 3214 * to work on real hardware. And since g4x can send infoframes to 3215 * only one port anyway, nothing is lost by allowing it. 3216 */ 3217 if (IS_G4X(dev_priv)) 3218 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 3219 3220 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 3221 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 3222 intel_dig_port->max_lanes = 4; 3223 3224 intel_infoframe_init(intel_dig_port); 3225 3226 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 3227 intel_hdmi_init_connector(intel_dig_port, intel_connector); 3228 } 3229