1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_hdcp.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <drm/intel_lpe_audio.h> 40 41 #include "i915_debugfs.h" 42 #include "i915_drv.h" 43 #include "intel_atomic.h" 44 #include "intel_connector.h" 45 #include "intel_ddi.h" 46 #include "intel_de.h" 47 #include "intel_display_types.h" 48 #include "intel_dp.h" 49 #include "intel_gmbus.h" 50 #include "intel_hdcp.h" 51 #include "intel_hdmi.h" 52 #include "intel_lspcon.h" 53 #include "intel_panel.h" 54 55 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 56 { 57 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 58 } 59 60 static void 61 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 62 { 63 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 64 struct drm_i915_private *dev_priv = to_i915(dev); 65 u32 enabled_bits; 66 67 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 68 69 drm_WARN(dev, 70 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 71 "HDMI port enabled, expecting disabled\n"); 72 } 73 74 static void 75 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 76 enum transcoder cpu_transcoder) 77 { 78 drm_WARN(&dev_priv->drm, 79 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 80 TRANS_DDI_FUNC_ENABLE, 81 "HDMI transcoder function enabled, expecting disabled\n"); 82 } 83 84 static u32 g4x_infoframe_index(unsigned int type) 85 { 86 switch (type) { 87 case HDMI_PACKET_TYPE_GAMUT_METADATA: 88 return VIDEO_DIP_SELECT_GAMUT; 89 case HDMI_INFOFRAME_TYPE_AVI: 90 return VIDEO_DIP_SELECT_AVI; 91 case HDMI_INFOFRAME_TYPE_SPD: 92 return VIDEO_DIP_SELECT_SPD; 93 case HDMI_INFOFRAME_TYPE_VENDOR: 94 return VIDEO_DIP_SELECT_VENDOR; 95 default: 96 MISSING_CASE(type); 97 return 0; 98 } 99 } 100 101 static u32 g4x_infoframe_enable(unsigned int type) 102 { 103 switch (type) { 104 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 105 return VIDEO_DIP_ENABLE_GCP; 106 case HDMI_PACKET_TYPE_GAMUT_METADATA: 107 return VIDEO_DIP_ENABLE_GAMUT; 108 case DP_SDP_VSC: 109 return 0; 110 case HDMI_INFOFRAME_TYPE_AVI: 111 return VIDEO_DIP_ENABLE_AVI; 112 case HDMI_INFOFRAME_TYPE_SPD: 113 return VIDEO_DIP_ENABLE_SPD; 114 case HDMI_INFOFRAME_TYPE_VENDOR: 115 return VIDEO_DIP_ENABLE_VENDOR; 116 case HDMI_INFOFRAME_TYPE_DRM: 117 return 0; 118 default: 119 MISSING_CASE(type); 120 return 0; 121 } 122 } 123 124 static u32 hsw_infoframe_enable(unsigned int type) 125 { 126 switch (type) { 127 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 128 return VIDEO_DIP_ENABLE_GCP_HSW; 129 case HDMI_PACKET_TYPE_GAMUT_METADATA: 130 return VIDEO_DIP_ENABLE_GMP_HSW; 131 case DP_SDP_VSC: 132 return VIDEO_DIP_ENABLE_VSC_HSW; 133 case DP_SDP_PPS: 134 return VDIP_ENABLE_PPS; 135 case HDMI_INFOFRAME_TYPE_AVI: 136 return VIDEO_DIP_ENABLE_AVI_HSW; 137 case HDMI_INFOFRAME_TYPE_SPD: 138 return VIDEO_DIP_ENABLE_SPD_HSW; 139 case HDMI_INFOFRAME_TYPE_VENDOR: 140 return VIDEO_DIP_ENABLE_VS_HSW; 141 case HDMI_INFOFRAME_TYPE_DRM: 142 return VIDEO_DIP_ENABLE_DRM_GLK; 143 default: 144 MISSING_CASE(type); 145 return 0; 146 } 147 } 148 149 static i915_reg_t 150 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 151 enum transcoder cpu_transcoder, 152 unsigned int type, 153 int i) 154 { 155 switch (type) { 156 case HDMI_PACKET_TYPE_GAMUT_METADATA: 157 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 158 case DP_SDP_VSC: 159 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 160 case DP_SDP_PPS: 161 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 162 case HDMI_INFOFRAME_TYPE_AVI: 163 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 164 case HDMI_INFOFRAME_TYPE_SPD: 165 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 166 case HDMI_INFOFRAME_TYPE_VENDOR: 167 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 168 case HDMI_INFOFRAME_TYPE_DRM: 169 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 170 default: 171 MISSING_CASE(type); 172 return INVALID_MMIO_REG; 173 } 174 } 175 176 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 177 unsigned int type) 178 { 179 switch (type) { 180 case DP_SDP_VSC: 181 return VIDEO_DIP_VSC_DATA_SIZE; 182 case DP_SDP_PPS: 183 return VIDEO_DIP_PPS_DATA_SIZE; 184 case HDMI_PACKET_TYPE_GAMUT_METADATA: 185 if (DISPLAY_VER(dev_priv) >= 11) 186 return VIDEO_DIP_GMP_DATA_SIZE; 187 else 188 return VIDEO_DIP_DATA_SIZE; 189 default: 190 return VIDEO_DIP_DATA_SIZE; 191 } 192 } 193 194 static void g4x_write_infoframe(struct intel_encoder *encoder, 195 const struct intel_crtc_state *crtc_state, 196 unsigned int type, 197 const void *frame, ssize_t len) 198 { 199 const u32 *data = frame; 200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 201 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 202 int i; 203 204 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 205 "Writing DIP with CTL reg disabled\n"); 206 207 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 208 val |= g4x_infoframe_index(type); 209 210 val &= ~g4x_infoframe_enable(type); 211 212 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 213 214 for (i = 0; i < len; i += 4) { 215 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 216 data++; 217 } 218 /* Write every possible data byte to force correct ECC calculation. */ 219 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 220 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 221 222 val |= g4x_infoframe_enable(type); 223 val &= ~VIDEO_DIP_FREQ_MASK; 224 val |= VIDEO_DIP_FREQ_VSYNC; 225 226 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 227 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 228 } 229 230 static void g4x_read_infoframe(struct intel_encoder *encoder, 231 const struct intel_crtc_state *crtc_state, 232 unsigned int type, 233 void *frame, ssize_t len) 234 { 235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 236 u32 val, *data = frame; 237 int i; 238 239 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 240 241 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 242 val |= g4x_infoframe_index(type); 243 244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 245 246 for (i = 0; i < len; i += 4) 247 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 248 } 249 250 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 251 const struct intel_crtc_state *pipe_config) 252 { 253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 254 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 255 256 if ((val & VIDEO_DIP_ENABLE) == 0) 257 return 0; 258 259 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 260 return 0; 261 262 return val & (VIDEO_DIP_ENABLE_AVI | 263 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 264 } 265 266 static void ibx_write_infoframe(struct intel_encoder *encoder, 267 const struct intel_crtc_state *crtc_state, 268 unsigned int type, 269 const void *frame, ssize_t len) 270 { 271 const u32 *data = frame; 272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 274 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 275 u32 val = intel_de_read(dev_priv, reg); 276 int i; 277 278 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 279 "Writing DIP with CTL reg disabled\n"); 280 281 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 282 val |= g4x_infoframe_index(type); 283 284 val &= ~g4x_infoframe_enable(type); 285 286 intel_de_write(dev_priv, reg, val); 287 288 for (i = 0; i < len; i += 4) { 289 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 290 *data); 291 data++; 292 } 293 /* Write every possible data byte to force correct ECC calculation. */ 294 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 295 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 296 297 val |= g4x_infoframe_enable(type); 298 val &= ~VIDEO_DIP_FREQ_MASK; 299 val |= VIDEO_DIP_FREQ_VSYNC; 300 301 intel_de_write(dev_priv, reg, val); 302 intel_de_posting_read(dev_priv, reg); 303 } 304 305 static void ibx_read_infoframe(struct intel_encoder *encoder, 306 const struct intel_crtc_state *crtc_state, 307 unsigned int type, 308 void *frame, ssize_t len) 309 { 310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 311 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 312 u32 val, *data = frame; 313 int i; 314 315 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 316 317 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 318 val |= g4x_infoframe_index(type); 319 320 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 321 322 for (i = 0; i < len; i += 4) 323 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 324 } 325 326 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 327 const struct intel_crtc_state *pipe_config) 328 { 329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 330 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 331 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 332 u32 val = intel_de_read(dev_priv, reg); 333 334 if ((val & VIDEO_DIP_ENABLE) == 0) 335 return 0; 336 337 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 338 return 0; 339 340 return val & (VIDEO_DIP_ENABLE_AVI | 341 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 342 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 343 } 344 345 static void cpt_write_infoframe(struct intel_encoder *encoder, 346 const struct intel_crtc_state *crtc_state, 347 unsigned int type, 348 const void *frame, ssize_t len) 349 { 350 const u32 *data = frame; 351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 353 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 354 u32 val = intel_de_read(dev_priv, reg); 355 int i; 356 357 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 358 "Writing DIP with CTL reg disabled\n"); 359 360 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 361 val |= g4x_infoframe_index(type); 362 363 /* The DIP control register spec says that we need to update the AVI 364 * infoframe without clearing its enable bit */ 365 if (type != HDMI_INFOFRAME_TYPE_AVI) 366 val &= ~g4x_infoframe_enable(type); 367 368 intel_de_write(dev_priv, reg, val); 369 370 for (i = 0; i < len; i += 4) { 371 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 372 *data); 373 data++; 374 } 375 /* Write every possible data byte to force correct ECC calculation. */ 376 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 377 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 378 379 val |= g4x_infoframe_enable(type); 380 val &= ~VIDEO_DIP_FREQ_MASK; 381 val |= VIDEO_DIP_FREQ_VSYNC; 382 383 intel_de_write(dev_priv, reg, val); 384 intel_de_posting_read(dev_priv, reg); 385 } 386 387 static void cpt_read_infoframe(struct intel_encoder *encoder, 388 const struct intel_crtc_state *crtc_state, 389 unsigned int type, 390 void *frame, ssize_t len) 391 { 392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 394 u32 val, *data = frame; 395 int i; 396 397 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 398 399 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 400 val |= g4x_infoframe_index(type); 401 402 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 403 404 for (i = 0; i < len; i += 4) 405 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 406 } 407 408 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 409 const struct intel_crtc_state *pipe_config) 410 { 411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 412 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 413 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 414 415 if ((val & VIDEO_DIP_ENABLE) == 0) 416 return 0; 417 418 return val & (VIDEO_DIP_ENABLE_AVI | 419 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 420 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 421 } 422 423 static void vlv_write_infoframe(struct intel_encoder *encoder, 424 const struct intel_crtc_state *crtc_state, 425 unsigned int type, 426 const void *frame, ssize_t len) 427 { 428 const u32 *data = frame; 429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 431 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 432 u32 val = intel_de_read(dev_priv, reg); 433 int i; 434 435 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 436 "Writing DIP with CTL reg disabled\n"); 437 438 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 439 val |= g4x_infoframe_index(type); 440 441 val &= ~g4x_infoframe_enable(type); 442 443 intel_de_write(dev_priv, reg, val); 444 445 for (i = 0; i < len; i += 4) { 446 intel_de_write(dev_priv, 447 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 448 data++; 449 } 450 /* Write every possible data byte to force correct ECC calculation. */ 451 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 452 intel_de_write(dev_priv, 453 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 454 455 val |= g4x_infoframe_enable(type); 456 val &= ~VIDEO_DIP_FREQ_MASK; 457 val |= VIDEO_DIP_FREQ_VSYNC; 458 459 intel_de_write(dev_priv, reg, val); 460 intel_de_posting_read(dev_priv, reg); 461 } 462 463 static void vlv_read_infoframe(struct intel_encoder *encoder, 464 const struct intel_crtc_state *crtc_state, 465 unsigned int type, 466 void *frame, ssize_t len) 467 { 468 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 469 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 470 u32 val, *data = frame; 471 int i; 472 473 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); 474 475 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 476 val |= g4x_infoframe_index(type); 477 478 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 479 480 for (i = 0; i < len; i += 4) 481 *data++ = intel_de_read(dev_priv, 482 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 483 } 484 485 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 486 const struct intel_crtc_state *pipe_config) 487 { 488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 489 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 490 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 491 492 if ((val & VIDEO_DIP_ENABLE) == 0) 493 return 0; 494 495 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 496 return 0; 497 498 return val & (VIDEO_DIP_ENABLE_AVI | 499 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 500 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 501 } 502 503 void hsw_write_infoframe(struct intel_encoder *encoder, 504 const struct intel_crtc_state *crtc_state, 505 unsigned int type, 506 const void *frame, ssize_t len) 507 { 508 const u32 *data = frame; 509 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 511 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 512 int data_size; 513 int i; 514 u32 val = intel_de_read(dev_priv, ctl_reg); 515 516 data_size = hsw_dip_data_size(dev_priv, type); 517 518 drm_WARN_ON(&dev_priv->drm, len > data_size); 519 520 val &= ~hsw_infoframe_enable(type); 521 intel_de_write(dev_priv, ctl_reg, val); 522 523 for (i = 0; i < len; i += 4) { 524 intel_de_write(dev_priv, 525 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 526 *data); 527 data++; 528 } 529 /* Write every possible data byte to force correct ECC calculation. */ 530 for (; i < data_size; i += 4) 531 intel_de_write(dev_priv, 532 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 533 0); 534 535 /* Wa_14013475917 */ 536 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr && 537 type == DP_SDP_VSC) 538 return; 539 540 val |= hsw_infoframe_enable(type); 541 intel_de_write(dev_priv, ctl_reg, val); 542 intel_de_posting_read(dev_priv, ctl_reg); 543 } 544 545 void hsw_read_infoframe(struct intel_encoder *encoder, 546 const struct intel_crtc_state *crtc_state, 547 unsigned int type, void *frame, ssize_t len) 548 { 549 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 551 u32 *data = frame; 552 int i; 553 554 for (i = 0; i < len; i += 4) 555 *data++ = intel_de_read(dev_priv, 556 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 557 } 558 559 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 560 const struct intel_crtc_state *pipe_config) 561 { 562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 563 u32 val = intel_de_read(dev_priv, 564 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 565 u32 mask; 566 567 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 568 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 569 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 570 571 if (DISPLAY_VER(dev_priv) >= 10) 572 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 573 574 return val & mask; 575 } 576 577 static const u8 infoframe_type_to_idx[] = { 578 HDMI_PACKET_TYPE_GENERAL_CONTROL, 579 HDMI_PACKET_TYPE_GAMUT_METADATA, 580 DP_SDP_VSC, 581 HDMI_INFOFRAME_TYPE_AVI, 582 HDMI_INFOFRAME_TYPE_SPD, 583 HDMI_INFOFRAME_TYPE_VENDOR, 584 HDMI_INFOFRAME_TYPE_DRM, 585 }; 586 587 u32 intel_hdmi_infoframe_enable(unsigned int type) 588 { 589 int i; 590 591 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 592 if (infoframe_type_to_idx[i] == type) 593 return BIT(i); 594 } 595 596 return 0; 597 } 598 599 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 600 const struct intel_crtc_state *crtc_state) 601 { 602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 603 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 604 u32 val, ret = 0; 605 int i; 606 607 val = dig_port->infoframes_enabled(encoder, crtc_state); 608 609 /* map from hardware bits to dip idx */ 610 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 611 unsigned int type = infoframe_type_to_idx[i]; 612 613 if (HAS_DDI(dev_priv)) { 614 if (val & hsw_infoframe_enable(type)) 615 ret |= BIT(i); 616 } else { 617 if (val & g4x_infoframe_enable(type)) 618 ret |= BIT(i); 619 } 620 } 621 622 return ret; 623 } 624 625 /* 626 * The data we write to the DIP data buffer registers is 1 byte bigger than the 627 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 628 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 629 * used for both technologies. 630 * 631 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 632 * DW1: DB3 | DB2 | DB1 | DB0 633 * DW2: DB7 | DB6 | DB5 | DB4 634 * DW3: ... 635 * 636 * (HB is Header Byte, DB is Data Byte) 637 * 638 * The hdmi pack() functions don't know about that hardware specific hole so we 639 * trick them by giving an offset into the buffer and moving back the header 640 * bytes by one. 641 */ 642 static void intel_write_infoframe(struct intel_encoder *encoder, 643 const struct intel_crtc_state *crtc_state, 644 enum hdmi_infoframe_type type, 645 const union hdmi_infoframe *frame) 646 { 647 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 648 u8 buffer[VIDEO_DIP_DATA_SIZE]; 649 ssize_t len; 650 651 if ((crtc_state->infoframes.enable & 652 intel_hdmi_infoframe_enable(type)) == 0) 653 return; 654 655 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 656 return; 657 658 /* see comment above for the reason for this offset */ 659 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 660 if (drm_WARN_ON(encoder->base.dev, len < 0)) 661 return; 662 663 /* Insert the 'hole' (see big comment above) at position 3 */ 664 memmove(&buffer[0], &buffer[1], 3); 665 buffer[3] = 0; 666 len++; 667 668 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 669 } 670 671 void intel_read_infoframe(struct intel_encoder *encoder, 672 const struct intel_crtc_state *crtc_state, 673 enum hdmi_infoframe_type type, 674 union hdmi_infoframe *frame) 675 { 676 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 677 u8 buffer[VIDEO_DIP_DATA_SIZE]; 678 int ret; 679 680 if ((crtc_state->infoframes.enable & 681 intel_hdmi_infoframe_enable(type)) == 0) 682 return; 683 684 dig_port->read_infoframe(encoder, crtc_state, 685 type, buffer, sizeof(buffer)); 686 687 /* Fill the 'hole' (see big comment above) at position 3 */ 688 memmove(&buffer[1], &buffer[0], 3); 689 690 /* see comment above for the reason for this offset */ 691 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 692 if (ret) { 693 drm_dbg_kms(encoder->base.dev, 694 "Failed to unpack infoframe type 0x%02x\n", type); 695 return; 696 } 697 698 if (frame->any.type != type) 699 drm_dbg_kms(encoder->base.dev, 700 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 701 frame->any.type, type); 702 } 703 704 static bool 705 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 706 struct intel_crtc_state *crtc_state, 707 struct drm_connector_state *conn_state) 708 { 709 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 710 const struct drm_display_mode *adjusted_mode = 711 &crtc_state->hw.adjusted_mode; 712 struct drm_connector *connector = conn_state->connector; 713 int ret; 714 715 if (!crtc_state->has_infoframe) 716 return true; 717 718 crtc_state->infoframes.enable |= 719 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 720 721 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 722 adjusted_mode); 723 if (ret) 724 return false; 725 726 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 727 frame->colorspace = HDMI_COLORSPACE_YUV420; 728 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 729 frame->colorspace = HDMI_COLORSPACE_YUV444; 730 else 731 frame->colorspace = HDMI_COLORSPACE_RGB; 732 733 drm_hdmi_avi_infoframe_colorspace(frame, conn_state); 734 735 /* nonsense combination */ 736 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 737 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 738 739 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 740 drm_hdmi_avi_infoframe_quant_range(frame, connector, 741 adjusted_mode, 742 crtc_state->limited_color_range ? 743 HDMI_QUANTIZATION_RANGE_LIMITED : 744 HDMI_QUANTIZATION_RANGE_FULL); 745 } else { 746 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 747 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 748 } 749 750 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 751 752 /* TODO: handle pixel repetition for YCBCR420 outputs */ 753 754 ret = hdmi_avi_infoframe_check(frame); 755 if (drm_WARN_ON(encoder->base.dev, ret)) 756 return false; 757 758 return true; 759 } 760 761 static bool 762 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 763 struct intel_crtc_state *crtc_state, 764 struct drm_connector_state *conn_state) 765 { 766 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 767 int ret; 768 769 if (!crtc_state->has_infoframe) 770 return true; 771 772 crtc_state->infoframes.enable |= 773 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 774 775 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 776 if (drm_WARN_ON(encoder->base.dev, ret)) 777 return false; 778 779 frame->sdi = HDMI_SPD_SDI_PC; 780 781 ret = hdmi_spd_infoframe_check(frame); 782 if (drm_WARN_ON(encoder->base.dev, ret)) 783 return false; 784 785 return true; 786 } 787 788 static bool 789 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 790 struct intel_crtc_state *crtc_state, 791 struct drm_connector_state *conn_state) 792 { 793 struct hdmi_vendor_infoframe *frame = 794 &crtc_state->infoframes.hdmi.vendor.hdmi; 795 const struct drm_display_info *info = 796 &conn_state->connector->display_info; 797 int ret; 798 799 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 800 return true; 801 802 crtc_state->infoframes.enable |= 803 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 804 805 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 806 conn_state->connector, 807 &crtc_state->hw.adjusted_mode); 808 if (drm_WARN_ON(encoder->base.dev, ret)) 809 return false; 810 811 ret = hdmi_vendor_infoframe_check(frame); 812 if (drm_WARN_ON(encoder->base.dev, ret)) 813 return false; 814 815 return true; 816 } 817 818 static bool 819 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 820 struct intel_crtc_state *crtc_state, 821 struct drm_connector_state *conn_state) 822 { 823 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 825 int ret; 826 827 if (DISPLAY_VER(dev_priv) < 10) 828 return true; 829 830 if (!crtc_state->has_infoframe) 831 return true; 832 833 if (!conn_state->hdr_output_metadata) 834 return true; 835 836 crtc_state->infoframes.enable |= 837 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 838 839 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 840 if (ret < 0) { 841 drm_dbg_kms(&dev_priv->drm, 842 "couldn't set HDR metadata in infoframe\n"); 843 return false; 844 } 845 846 ret = hdmi_drm_infoframe_check(frame); 847 if (drm_WARN_ON(&dev_priv->drm, ret)) 848 return false; 849 850 return true; 851 } 852 853 static void g4x_set_infoframes(struct intel_encoder *encoder, 854 bool enable, 855 const struct intel_crtc_state *crtc_state, 856 const struct drm_connector_state *conn_state) 857 { 858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 860 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 861 i915_reg_t reg = VIDEO_DIP_CTL; 862 u32 val = intel_de_read(dev_priv, reg); 863 u32 port = VIDEO_DIP_PORT(encoder->port); 864 865 assert_hdmi_port_disabled(intel_hdmi); 866 867 /* If the registers were not initialized yet, they might be zeroes, 868 * which means we're selecting the AVI DIP and we're setting its 869 * frequency to once. This seems to really confuse the HW and make 870 * things stop working (the register spec says the AVI always needs to 871 * be sent every VSync). So here we avoid writing to the register more 872 * than we need and also explicitly select the AVI DIP and explicitly 873 * set its frequency to every VSync. Avoiding to write it twice seems to 874 * be enough to solve the problem, but being defensive shouldn't hurt us 875 * either. */ 876 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 877 878 if (!enable) { 879 if (!(val & VIDEO_DIP_ENABLE)) 880 return; 881 if (port != (val & VIDEO_DIP_PORT_MASK)) { 882 drm_dbg_kms(&dev_priv->drm, 883 "video DIP still enabled on port %c\n", 884 (val & VIDEO_DIP_PORT_MASK) >> 29); 885 return; 886 } 887 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 888 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 889 intel_de_write(dev_priv, reg, val); 890 intel_de_posting_read(dev_priv, reg); 891 return; 892 } 893 894 if (port != (val & VIDEO_DIP_PORT_MASK)) { 895 if (val & VIDEO_DIP_ENABLE) { 896 drm_dbg_kms(&dev_priv->drm, 897 "video DIP already enabled on port %c\n", 898 (val & VIDEO_DIP_PORT_MASK) >> 29); 899 return; 900 } 901 val &= ~VIDEO_DIP_PORT_MASK; 902 val |= port; 903 } 904 905 val |= VIDEO_DIP_ENABLE; 906 val &= ~(VIDEO_DIP_ENABLE_AVI | 907 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 908 909 intel_de_write(dev_priv, reg, val); 910 intel_de_posting_read(dev_priv, reg); 911 912 intel_write_infoframe(encoder, crtc_state, 913 HDMI_INFOFRAME_TYPE_AVI, 914 &crtc_state->infoframes.avi); 915 intel_write_infoframe(encoder, crtc_state, 916 HDMI_INFOFRAME_TYPE_SPD, 917 &crtc_state->infoframes.spd); 918 intel_write_infoframe(encoder, crtc_state, 919 HDMI_INFOFRAME_TYPE_VENDOR, 920 &crtc_state->infoframes.hdmi); 921 } 922 923 /* 924 * Determine if default_phase=1 can be indicated in the GCP infoframe. 925 * 926 * From HDMI specification 1.4a: 927 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 928 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 929 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 930 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 931 * phase of 0 932 */ 933 static bool gcp_default_phase_possible(int pipe_bpp, 934 const struct drm_display_mode *mode) 935 { 936 unsigned int pixels_per_group; 937 938 switch (pipe_bpp) { 939 case 30: 940 /* 4 pixels in 5 clocks */ 941 pixels_per_group = 4; 942 break; 943 case 36: 944 /* 2 pixels in 3 clocks */ 945 pixels_per_group = 2; 946 break; 947 case 48: 948 /* 1 pixel in 2 clocks */ 949 pixels_per_group = 1; 950 break; 951 default: 952 /* phase information not relevant for 8bpc */ 953 return false; 954 } 955 956 return mode->crtc_hdisplay % pixels_per_group == 0 && 957 mode->crtc_htotal % pixels_per_group == 0 && 958 mode->crtc_hblank_start % pixels_per_group == 0 && 959 mode->crtc_hblank_end % pixels_per_group == 0 && 960 mode->crtc_hsync_start % pixels_per_group == 0 && 961 mode->crtc_hsync_end % pixels_per_group == 0 && 962 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 963 mode->crtc_htotal/2 % pixels_per_group == 0); 964 } 965 966 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 967 const struct intel_crtc_state *crtc_state, 968 const struct drm_connector_state *conn_state) 969 { 970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 972 i915_reg_t reg; 973 974 if ((crtc_state->infoframes.enable & 975 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 976 return false; 977 978 if (HAS_DDI(dev_priv)) 979 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 980 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 981 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 982 else if (HAS_PCH_SPLIT(dev_priv)) 983 reg = TVIDEO_DIP_GCP(crtc->pipe); 984 else 985 return false; 986 987 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 988 989 return true; 990 } 991 992 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 993 struct intel_crtc_state *crtc_state) 994 { 995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 996 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 997 i915_reg_t reg; 998 999 if ((crtc_state->infoframes.enable & 1000 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1001 return; 1002 1003 if (HAS_DDI(dev_priv)) 1004 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1005 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1006 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1007 else if (HAS_PCH_SPLIT(dev_priv)) 1008 reg = TVIDEO_DIP_GCP(crtc->pipe); 1009 else 1010 return; 1011 1012 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1013 } 1014 1015 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1016 struct intel_crtc_state *crtc_state, 1017 struct drm_connector_state *conn_state) 1018 { 1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1020 1021 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1022 return; 1023 1024 crtc_state->infoframes.enable |= 1025 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1026 1027 /* Indicate color indication for deep color mode */ 1028 if (crtc_state->pipe_bpp > 24) 1029 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1030 1031 /* Enable default_phase whenever the display mode is suitably aligned */ 1032 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1033 &crtc_state->hw.adjusted_mode)) 1034 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1035 } 1036 1037 static void ibx_set_infoframes(struct intel_encoder *encoder, 1038 bool enable, 1039 const struct intel_crtc_state *crtc_state, 1040 const struct drm_connector_state *conn_state) 1041 { 1042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1045 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1046 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1047 u32 val = intel_de_read(dev_priv, reg); 1048 u32 port = VIDEO_DIP_PORT(encoder->port); 1049 1050 assert_hdmi_port_disabled(intel_hdmi); 1051 1052 /* See the big comment in g4x_set_infoframes() */ 1053 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1054 1055 if (!enable) { 1056 if (!(val & VIDEO_DIP_ENABLE)) 1057 return; 1058 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1059 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1060 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1061 intel_de_write(dev_priv, reg, val); 1062 intel_de_posting_read(dev_priv, reg); 1063 return; 1064 } 1065 1066 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1067 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1068 "DIP already enabled on port %c\n", 1069 (val & VIDEO_DIP_PORT_MASK) >> 29); 1070 val &= ~VIDEO_DIP_PORT_MASK; 1071 val |= port; 1072 } 1073 1074 val |= VIDEO_DIP_ENABLE; 1075 val &= ~(VIDEO_DIP_ENABLE_AVI | 1076 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1077 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1078 1079 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1080 val |= VIDEO_DIP_ENABLE_GCP; 1081 1082 intel_de_write(dev_priv, reg, val); 1083 intel_de_posting_read(dev_priv, reg); 1084 1085 intel_write_infoframe(encoder, crtc_state, 1086 HDMI_INFOFRAME_TYPE_AVI, 1087 &crtc_state->infoframes.avi); 1088 intel_write_infoframe(encoder, crtc_state, 1089 HDMI_INFOFRAME_TYPE_SPD, 1090 &crtc_state->infoframes.spd); 1091 intel_write_infoframe(encoder, crtc_state, 1092 HDMI_INFOFRAME_TYPE_VENDOR, 1093 &crtc_state->infoframes.hdmi); 1094 } 1095 1096 static void cpt_set_infoframes(struct intel_encoder *encoder, 1097 bool enable, 1098 const struct intel_crtc_state *crtc_state, 1099 const struct drm_connector_state *conn_state) 1100 { 1101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1103 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1104 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1105 u32 val = intel_de_read(dev_priv, reg); 1106 1107 assert_hdmi_port_disabled(intel_hdmi); 1108 1109 /* See the big comment in g4x_set_infoframes() */ 1110 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1111 1112 if (!enable) { 1113 if (!(val & VIDEO_DIP_ENABLE)) 1114 return; 1115 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1116 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1117 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1118 intel_de_write(dev_priv, reg, val); 1119 intel_de_posting_read(dev_priv, reg); 1120 return; 1121 } 1122 1123 /* Set both together, unset both together: see the spec. */ 1124 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1125 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1126 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1127 1128 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1129 val |= VIDEO_DIP_ENABLE_GCP; 1130 1131 intel_de_write(dev_priv, reg, val); 1132 intel_de_posting_read(dev_priv, reg); 1133 1134 intel_write_infoframe(encoder, crtc_state, 1135 HDMI_INFOFRAME_TYPE_AVI, 1136 &crtc_state->infoframes.avi); 1137 intel_write_infoframe(encoder, crtc_state, 1138 HDMI_INFOFRAME_TYPE_SPD, 1139 &crtc_state->infoframes.spd); 1140 intel_write_infoframe(encoder, crtc_state, 1141 HDMI_INFOFRAME_TYPE_VENDOR, 1142 &crtc_state->infoframes.hdmi); 1143 } 1144 1145 static void vlv_set_infoframes(struct intel_encoder *encoder, 1146 bool enable, 1147 const struct intel_crtc_state *crtc_state, 1148 const struct drm_connector_state *conn_state) 1149 { 1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1152 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1153 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 1154 u32 val = intel_de_read(dev_priv, reg); 1155 u32 port = VIDEO_DIP_PORT(encoder->port); 1156 1157 assert_hdmi_port_disabled(intel_hdmi); 1158 1159 /* See the big comment in g4x_set_infoframes() */ 1160 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1161 1162 if (!enable) { 1163 if (!(val & VIDEO_DIP_ENABLE)) 1164 return; 1165 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1166 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1167 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1168 intel_de_write(dev_priv, reg, val); 1169 intel_de_posting_read(dev_priv, reg); 1170 return; 1171 } 1172 1173 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1174 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1175 "DIP already enabled on port %c\n", 1176 (val & VIDEO_DIP_PORT_MASK) >> 29); 1177 val &= ~VIDEO_DIP_PORT_MASK; 1178 val |= port; 1179 } 1180 1181 val |= VIDEO_DIP_ENABLE; 1182 val &= ~(VIDEO_DIP_ENABLE_AVI | 1183 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1184 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1185 1186 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1187 val |= VIDEO_DIP_ENABLE_GCP; 1188 1189 intel_de_write(dev_priv, reg, val); 1190 intel_de_posting_read(dev_priv, reg); 1191 1192 intel_write_infoframe(encoder, crtc_state, 1193 HDMI_INFOFRAME_TYPE_AVI, 1194 &crtc_state->infoframes.avi); 1195 intel_write_infoframe(encoder, crtc_state, 1196 HDMI_INFOFRAME_TYPE_SPD, 1197 &crtc_state->infoframes.spd); 1198 intel_write_infoframe(encoder, crtc_state, 1199 HDMI_INFOFRAME_TYPE_VENDOR, 1200 &crtc_state->infoframes.hdmi); 1201 } 1202 1203 static void hsw_set_infoframes(struct intel_encoder *encoder, 1204 bool enable, 1205 const struct intel_crtc_state *crtc_state, 1206 const struct drm_connector_state *conn_state) 1207 { 1208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1209 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1210 u32 val = intel_de_read(dev_priv, reg); 1211 1212 assert_hdmi_transcoder_func_disabled(dev_priv, 1213 crtc_state->cpu_transcoder); 1214 1215 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1216 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1217 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1218 VIDEO_DIP_ENABLE_DRM_GLK); 1219 1220 if (!enable) { 1221 intel_de_write(dev_priv, reg, val); 1222 intel_de_posting_read(dev_priv, reg); 1223 return; 1224 } 1225 1226 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1227 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1228 1229 intel_de_write(dev_priv, reg, val); 1230 intel_de_posting_read(dev_priv, reg); 1231 1232 intel_write_infoframe(encoder, crtc_state, 1233 HDMI_INFOFRAME_TYPE_AVI, 1234 &crtc_state->infoframes.avi); 1235 intel_write_infoframe(encoder, crtc_state, 1236 HDMI_INFOFRAME_TYPE_SPD, 1237 &crtc_state->infoframes.spd); 1238 intel_write_infoframe(encoder, crtc_state, 1239 HDMI_INFOFRAME_TYPE_VENDOR, 1240 &crtc_state->infoframes.hdmi); 1241 intel_write_infoframe(encoder, crtc_state, 1242 HDMI_INFOFRAME_TYPE_DRM, 1243 &crtc_state->infoframes.drm); 1244 } 1245 1246 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1247 { 1248 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1249 struct i2c_adapter *adapter = 1250 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1251 1252 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1253 return; 1254 1255 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", 1256 enable ? "Enabling" : "Disabling"); 1257 1258 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable); 1259 } 1260 1261 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1262 unsigned int offset, void *buffer, size_t size) 1263 { 1264 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1265 struct intel_hdmi *hdmi = &dig_port->hdmi; 1266 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1267 hdmi->ddc_bus); 1268 int ret; 1269 u8 start = offset & 0xff; 1270 struct i2c_msg msgs[] = { 1271 { 1272 .addr = DRM_HDCP_DDC_ADDR, 1273 .flags = 0, 1274 .len = 1, 1275 .buf = &start, 1276 }, 1277 { 1278 .addr = DRM_HDCP_DDC_ADDR, 1279 .flags = I2C_M_RD, 1280 .len = size, 1281 .buf = buffer 1282 } 1283 }; 1284 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1285 if (ret == ARRAY_SIZE(msgs)) 1286 return 0; 1287 return ret >= 0 ? -EIO : ret; 1288 } 1289 1290 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1291 unsigned int offset, void *buffer, size_t size) 1292 { 1293 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1294 struct intel_hdmi *hdmi = &dig_port->hdmi; 1295 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1296 hdmi->ddc_bus); 1297 int ret; 1298 u8 *write_buf; 1299 struct i2c_msg msg; 1300 1301 write_buf = kzalloc(size + 1, GFP_KERNEL); 1302 if (!write_buf) 1303 return -ENOMEM; 1304 1305 write_buf[0] = offset & 0xff; 1306 memcpy(&write_buf[1], buffer, size); 1307 1308 msg.addr = DRM_HDCP_DDC_ADDR; 1309 msg.flags = 0, 1310 msg.len = size + 1, 1311 msg.buf = write_buf; 1312 1313 ret = i2c_transfer(adapter, &msg, 1); 1314 if (ret == 1) 1315 ret = 0; 1316 else if (ret >= 0) 1317 ret = -EIO; 1318 1319 kfree(write_buf); 1320 return ret; 1321 } 1322 1323 static 1324 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1325 u8 *an) 1326 { 1327 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1328 struct intel_hdmi *hdmi = &dig_port->hdmi; 1329 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1330 hdmi->ddc_bus); 1331 int ret; 1332 1333 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1334 DRM_HDCP_AN_LEN); 1335 if (ret) { 1336 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", 1337 ret); 1338 return ret; 1339 } 1340 1341 ret = intel_gmbus_output_aksv(adapter); 1342 if (ret < 0) { 1343 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); 1344 return ret; 1345 } 1346 return 0; 1347 } 1348 1349 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1350 u8 *bksv) 1351 { 1352 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1353 1354 int ret; 1355 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1356 DRM_HDCP_KSV_LEN); 1357 if (ret) 1358 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", 1359 ret); 1360 return ret; 1361 } 1362 1363 static 1364 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1365 u8 *bstatus) 1366 { 1367 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1368 1369 int ret; 1370 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1371 bstatus, DRM_HDCP_BSTATUS_LEN); 1372 if (ret) 1373 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", 1374 ret); 1375 return ret; 1376 } 1377 1378 static 1379 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1380 bool *repeater_present) 1381 { 1382 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1383 int ret; 1384 u8 val; 1385 1386 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1387 if (ret) { 1388 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1389 ret); 1390 return ret; 1391 } 1392 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1393 return 0; 1394 } 1395 1396 static 1397 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1398 u8 *ri_prime) 1399 { 1400 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1401 1402 int ret; 1403 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1404 ri_prime, DRM_HDCP_RI_LEN); 1405 if (ret) 1406 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", 1407 ret); 1408 return ret; 1409 } 1410 1411 static 1412 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1413 bool *ksv_ready) 1414 { 1415 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1416 int ret; 1417 u8 val; 1418 1419 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1420 if (ret) { 1421 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1422 ret); 1423 return ret; 1424 } 1425 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1426 return 0; 1427 } 1428 1429 static 1430 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1431 int num_downstream, u8 *ksv_fifo) 1432 { 1433 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1434 int ret; 1435 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1436 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1437 if (ret) { 1438 drm_dbg_kms(&i915->drm, 1439 "Read ksv fifo over DDC failed (%d)\n", ret); 1440 return ret; 1441 } 1442 return 0; 1443 } 1444 1445 static 1446 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1447 int i, u32 *part) 1448 { 1449 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1450 int ret; 1451 1452 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1453 return -EINVAL; 1454 1455 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1456 part, DRM_HDCP_V_PRIME_PART_LEN); 1457 if (ret) 1458 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", 1459 i, ret); 1460 return ret; 1461 } 1462 1463 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1464 enum transcoder cpu_transcoder) 1465 { 1466 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1467 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1468 struct drm_crtc *crtc = connector->base.state->crtc; 1469 struct intel_crtc *intel_crtc = container_of(crtc, 1470 struct intel_crtc, base); 1471 u32 scanline; 1472 int ret; 1473 1474 for (;;) { 1475 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe)); 1476 if (scanline > 100 && scanline < 200) 1477 break; 1478 usleep_range(25, 50); 1479 } 1480 1481 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1482 false, TRANS_DDI_HDCP_SIGNALLING); 1483 if (ret) { 1484 drm_err(&dev_priv->drm, 1485 "Disable HDCP signalling failed (%d)\n", ret); 1486 return ret; 1487 } 1488 1489 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1490 true, TRANS_DDI_HDCP_SIGNALLING); 1491 if (ret) { 1492 drm_err(&dev_priv->drm, 1493 "Enable HDCP signalling failed (%d)\n", ret); 1494 return ret; 1495 } 1496 1497 return 0; 1498 } 1499 1500 static 1501 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1502 enum transcoder cpu_transcoder, 1503 bool enable) 1504 { 1505 struct intel_hdmi *hdmi = &dig_port->hdmi; 1506 struct intel_connector *connector = hdmi->attached_connector; 1507 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1508 int ret; 1509 1510 if (!enable) 1511 usleep_range(6, 60); /* Bspec says >= 6us */ 1512 1513 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1514 cpu_transcoder, enable, 1515 TRANS_DDI_HDCP_SIGNALLING); 1516 if (ret) { 1517 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", 1518 enable ? "Enable" : "Disable", ret); 1519 return ret; 1520 } 1521 1522 /* 1523 * WA: To fix incorrect positioning of the window of 1524 * opportunity and enc_en signalling in KABYLAKE. 1525 */ 1526 if (IS_KABYLAKE(dev_priv) && enable) 1527 return kbl_repositioning_enc_en_signal(connector, 1528 cpu_transcoder); 1529 1530 return 0; 1531 } 1532 1533 static 1534 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1535 struct intel_connector *connector) 1536 { 1537 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1538 enum port port = dig_port->base.port; 1539 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1540 int ret; 1541 union { 1542 u32 reg; 1543 u8 shim[DRM_HDCP_RI_LEN]; 1544 } ri; 1545 1546 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1547 if (ret) 1548 return false; 1549 1550 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1551 1552 /* Wait for Ri prime match */ 1553 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1554 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1555 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1556 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", 1557 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1558 port))); 1559 return false; 1560 } 1561 return true; 1562 } 1563 1564 static 1565 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1566 struct intel_connector *connector) 1567 { 1568 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1569 int retry; 1570 1571 for (retry = 0; retry < 3; retry++) 1572 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1573 return true; 1574 1575 drm_err(&i915->drm, "Link check failed\n"); 1576 return false; 1577 } 1578 1579 struct hdcp2_hdmi_msg_timeout { 1580 u8 msg_id; 1581 u16 timeout; 1582 }; 1583 1584 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1585 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1586 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1587 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1588 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1589 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1590 }; 1591 1592 static 1593 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1594 u8 *rx_status) 1595 { 1596 return intel_hdmi_hdcp_read(dig_port, 1597 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1598 rx_status, 1599 HDCP_2_2_HDMI_RXSTATUS_LEN); 1600 } 1601 1602 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1603 { 1604 int i; 1605 1606 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1607 if (is_paired) 1608 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1609 else 1610 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1611 } 1612 1613 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1614 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1615 return hdcp2_msg_timeout[i].timeout; 1616 } 1617 1618 return -EINVAL; 1619 } 1620 1621 static int 1622 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1623 u8 msg_id, bool *msg_ready, 1624 ssize_t *msg_sz) 1625 { 1626 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1627 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1628 int ret; 1629 1630 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1631 if (ret < 0) { 1632 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", 1633 ret); 1634 return ret; 1635 } 1636 1637 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1638 rx_status[0]); 1639 1640 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1641 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1642 *msg_sz); 1643 else 1644 *msg_ready = *msg_sz; 1645 1646 return 0; 1647 } 1648 1649 static ssize_t 1650 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1651 u8 msg_id, bool paired) 1652 { 1653 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1654 bool msg_ready = false; 1655 int timeout, ret; 1656 ssize_t msg_sz = 0; 1657 1658 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1659 if (timeout < 0) 1660 return timeout; 1661 1662 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1663 msg_id, &msg_ready, 1664 &msg_sz), 1665 !ret && msg_ready && msg_sz, timeout * 1000, 1666 1000, 5 * 1000); 1667 if (ret) 1668 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", 1669 msg_id, ret, timeout); 1670 1671 return ret ? ret : msg_sz; 1672 } 1673 1674 static 1675 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, 1676 void *buf, size_t size) 1677 { 1678 unsigned int offset; 1679 1680 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1681 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1682 } 1683 1684 static 1685 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, 1686 u8 msg_id, void *buf, size_t size) 1687 { 1688 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1689 struct intel_hdmi *hdmi = &dig_port->hdmi; 1690 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1691 unsigned int offset; 1692 ssize_t ret; 1693 1694 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1695 hdcp->is_paired); 1696 if (ret < 0) 1697 return ret; 1698 1699 /* 1700 * Available msg size should be equal to or lesser than the 1701 * available buffer. 1702 */ 1703 if (ret > size) { 1704 drm_dbg_kms(&i915->drm, 1705 "msg_sz(%zd) is more than exp size(%zu)\n", 1706 ret, size); 1707 return -1; 1708 } 1709 1710 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1711 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1712 if (ret) 1713 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", 1714 msg_id, ret); 1715 1716 return ret; 1717 } 1718 1719 static 1720 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1721 struct intel_connector *connector) 1722 { 1723 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1724 int ret; 1725 1726 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1727 if (ret) 1728 return ret; 1729 1730 /* 1731 * Re-auth request and Link Integrity Failures are represented by 1732 * same bit. i.e reauth_req. 1733 */ 1734 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1735 ret = HDCP_REAUTH_REQUEST; 1736 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1737 ret = HDCP_TOPOLOGY_CHANGE; 1738 1739 return ret; 1740 } 1741 1742 static 1743 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, 1744 bool *capable) 1745 { 1746 u8 hdcp2_version; 1747 int ret; 1748 1749 *capable = false; 1750 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1751 &hdcp2_version, sizeof(hdcp2_version)); 1752 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1753 *capable = true; 1754 1755 return ret; 1756 } 1757 1758 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1759 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1760 .read_bksv = intel_hdmi_hdcp_read_bksv, 1761 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1762 .repeater_present = intel_hdmi_hdcp_repeater_present, 1763 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1764 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1765 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1766 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1767 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1768 .check_link = intel_hdmi_hdcp_check_link, 1769 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1770 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1771 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1772 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1773 .protocol = HDCP_PROTOCOL_HDMI, 1774 }; 1775 1776 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1777 { 1778 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1779 int max_tmds_clock, vbt_max_tmds_clock; 1780 1781 if (DISPLAY_VER(dev_priv) >= 10) 1782 max_tmds_clock = 594000; 1783 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 1784 max_tmds_clock = 300000; 1785 else if (DISPLAY_VER(dev_priv) >= 5) 1786 max_tmds_clock = 225000; 1787 else 1788 max_tmds_clock = 165000; 1789 1790 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); 1791 if (vbt_max_tmds_clock) 1792 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1793 1794 return max_tmds_clock; 1795 } 1796 1797 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1798 const struct drm_connector_state *conn_state) 1799 { 1800 return hdmi->has_hdmi_sink && 1801 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1802 } 1803 1804 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1805 bool respect_downstream_limits, 1806 bool has_hdmi_sink) 1807 { 1808 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1809 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1810 1811 if (respect_downstream_limits) { 1812 struct intel_connector *connector = hdmi->attached_connector; 1813 const struct drm_display_info *info = &connector->base.display_info; 1814 1815 if (hdmi->dp_dual_mode.max_tmds_clock) 1816 max_tmds_clock = min(max_tmds_clock, 1817 hdmi->dp_dual_mode.max_tmds_clock); 1818 1819 if (info->max_tmds_clock) 1820 max_tmds_clock = min(max_tmds_clock, 1821 info->max_tmds_clock); 1822 else if (!has_hdmi_sink) 1823 max_tmds_clock = min(max_tmds_clock, 165000); 1824 } 1825 1826 return max_tmds_clock; 1827 } 1828 1829 static enum drm_mode_status 1830 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1831 int clock, bool respect_downstream_limits, 1832 bool has_hdmi_sink) 1833 { 1834 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1835 1836 if (clock < 25000) 1837 return MODE_CLOCK_LOW; 1838 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1839 has_hdmi_sink)) 1840 return MODE_CLOCK_HIGH; 1841 1842 /* GLK DPLL can't generate 446-480 MHz */ 1843 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1844 return MODE_CLOCK_RANGE; 1845 1846 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1847 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1848 clock > 223333 && clock < 240000) 1849 return MODE_CLOCK_RANGE; 1850 1851 /* CHV DPLL can't generate 216-240 MHz */ 1852 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1853 return MODE_CLOCK_RANGE; 1854 1855 return MODE_OK; 1856 } 1857 1858 static int intel_hdmi_port_clock(int clock, int bpc) 1859 { 1860 /* 1861 * Need to adjust the port link by: 1862 * 1.5x for 12bpc 1863 * 1.25x for 10bpc 1864 */ 1865 return clock * bpc / 8; 1866 } 1867 1868 static enum drm_mode_status 1869 intel_hdmi_mode_clock_valid(struct intel_hdmi *hdmi, int clock, bool has_hdmi_sink) 1870 { 1871 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1872 struct drm_i915_private *dev_priv = to_i915(dev); 1873 enum drm_mode_status status; 1874 1875 /* check if we can do 8bpc */ 1876 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8), 1877 true, has_hdmi_sink); 1878 1879 if (has_hdmi_sink) { 1880 /* if we can't do 8bpc we may still be able to do 12bpc */ 1881 if (status != MODE_OK && !HAS_GMCH(dev_priv)) 1882 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12), 1883 true, has_hdmi_sink); 1884 1885 /* if we can't do 8,12bpc we may still be able to do 10bpc */ 1886 if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11) 1887 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10), 1888 true, has_hdmi_sink); 1889 } 1890 1891 return status; 1892 } 1893 1894 static enum drm_mode_status 1895 intel_hdmi_mode_valid(struct drm_connector *connector, 1896 struct drm_display_mode *mode) 1897 { 1898 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1899 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1900 struct drm_i915_private *dev_priv = to_i915(dev); 1901 enum drm_mode_status status; 1902 int clock = mode->clock; 1903 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1904 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 1905 bool ycbcr_420_only; 1906 1907 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1908 return MODE_NO_DBLESCAN; 1909 1910 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1911 clock *= 2; 1912 1913 if (clock > max_dotclk) 1914 return MODE_CLOCK_HIGH; 1915 1916 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1917 if (!has_hdmi_sink) 1918 return MODE_CLOCK_LOW; 1919 clock *= 2; 1920 } 1921 1922 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 1923 if (ycbcr_420_only) 1924 clock /= 2; 1925 1926 status = intel_hdmi_mode_clock_valid(hdmi, clock, has_hdmi_sink); 1927 if (status != MODE_OK) { 1928 if (ycbcr_420_only || 1929 !connector->ycbcr_420_allowed || 1930 !drm_mode_is_420_also(&connector->display_info, mode)) 1931 return status; 1932 1933 clock /= 2; 1934 status = intel_hdmi_mode_clock_valid(hdmi, clock, has_hdmi_sink); 1935 if (status != MODE_OK) 1936 return status; 1937 } 1938 1939 return intel_mode_valid_max_plane_size(dev_priv, mode, false); 1940 } 1941 1942 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 1943 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 1944 { 1945 struct drm_atomic_state *state = crtc_state->uapi.state; 1946 struct drm_connector_state *connector_state; 1947 struct drm_connector *connector; 1948 int i; 1949 1950 if (crtc_state->pipe_bpp < bpc * 3) 1951 return false; 1952 1953 if (!has_hdmi_sink) 1954 return false; 1955 1956 for_each_new_connector_in_state(state, connector, connector_state, i) { 1957 const struct drm_display_info *info = &connector->display_info; 1958 1959 if (connector_state->crtc != crtc_state->uapi.crtc) 1960 continue; 1961 1962 if (ycbcr420_output) { 1963 const struct drm_hdmi_info *hdmi = &info->hdmi; 1964 1965 if (bpc == 12 && !(hdmi->y420_dc_modes & 1966 DRM_EDID_YCBCR420_DC_36)) 1967 return false; 1968 else if (bpc == 10 && !(hdmi->y420_dc_modes & 1969 DRM_EDID_YCBCR420_DC_30)) 1970 return false; 1971 } else { 1972 if (bpc == 12 && !(info->edid_hdmi_dc_modes & 1973 DRM_EDID_HDMI_DC_36)) 1974 return false; 1975 else if (bpc == 10 && !(info->edid_hdmi_dc_modes & 1976 DRM_EDID_HDMI_DC_30)) 1977 return false; 1978 } 1979 } 1980 1981 return true; 1982 } 1983 1984 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 1985 int bpc) 1986 { 1987 struct drm_i915_private *dev_priv = 1988 to_i915(crtc_state->uapi.crtc->dev); 1989 const struct drm_display_mode *adjusted_mode = 1990 &crtc_state->hw.adjusted_mode; 1991 1992 if (HAS_GMCH(dev_priv)) 1993 return false; 1994 1995 if (bpc == 10 && DISPLAY_VER(dev_priv) < 11) 1996 return false; 1997 1998 /* 1999 * HDMI deep color affects the clocks, so it's only possible 2000 * when not cloning with other encoder types. 2001 */ 2002 if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI)) 2003 return false; 2004 2005 /* Display Wa_1405510057:icl,ehl */ 2006 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 2007 bpc == 10 && DISPLAY_VER(dev_priv) == 11 && 2008 (adjusted_mode->crtc_hblank_end - 2009 adjusted_mode->crtc_hblank_start) % 8 == 2) 2010 return false; 2011 2012 return intel_hdmi_deep_color_possible(crtc_state, bpc, 2013 crtc_state->has_hdmi_sink, 2014 crtc_state->output_format == 2015 INTEL_OUTPUT_FORMAT_YCBCR420); 2016 } 2017 2018 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2019 struct intel_crtc_state *crtc_state, 2020 int clock) 2021 { 2022 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2023 int bpc; 2024 2025 for (bpc = 12; bpc >= 10; bpc -= 2) { 2026 if (hdmi_deep_color_possible(crtc_state, bpc) && 2027 hdmi_port_clock_valid(intel_hdmi, 2028 intel_hdmi_port_clock(clock, bpc), 2029 true, crtc_state->has_hdmi_sink) == MODE_OK) 2030 return bpc; 2031 } 2032 2033 return 8; 2034 } 2035 2036 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2037 struct intel_crtc_state *crtc_state) 2038 { 2039 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2040 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2041 const struct drm_display_mode *adjusted_mode = 2042 &crtc_state->hw.adjusted_mode; 2043 int bpc, clock = adjusted_mode->crtc_clock; 2044 2045 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2046 clock *= 2; 2047 2048 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 2049 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2050 clock /= 2; 2051 2052 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock); 2053 2054 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); 2055 2056 /* 2057 * pipe_bpp could already be below 8bpc due to 2058 * FDI bandwidth constraints. We shouldn't bump it 2059 * back up to 8bpc in that case. 2060 */ 2061 if (crtc_state->pipe_bpp > bpc * 3) 2062 crtc_state->pipe_bpp = bpc * 3; 2063 2064 drm_dbg_kms(&i915->drm, 2065 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2066 bpc, crtc_state->pipe_bpp); 2067 2068 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, 2069 false, crtc_state->has_hdmi_sink) != MODE_OK) { 2070 drm_dbg_kms(&i915->drm, 2071 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2072 crtc_state->port_clock); 2073 return -EINVAL; 2074 } 2075 2076 return 0; 2077 } 2078 2079 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2080 const struct drm_connector_state *conn_state) 2081 { 2082 const struct intel_digital_connector_state *intel_conn_state = 2083 to_intel_digital_connector_state(conn_state); 2084 const struct drm_display_mode *adjusted_mode = 2085 &crtc_state->hw.adjusted_mode; 2086 2087 /* 2088 * Our YCbCr output is always limited range. 2089 * crtc_state->limited_color_range only applies to RGB, 2090 * and it must never be set for YCbCr or we risk setting 2091 * some conflicting bits in PIPECONF which will mess up 2092 * the colors on the monitor. 2093 */ 2094 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2095 return false; 2096 2097 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2098 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2099 return crtc_state->has_hdmi_sink && 2100 drm_default_rgb_quant_range(adjusted_mode) == 2101 HDMI_QUANTIZATION_RANGE_LIMITED; 2102 } else { 2103 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2104 } 2105 } 2106 2107 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2108 const struct intel_crtc_state *crtc_state, 2109 const struct drm_connector_state *conn_state) 2110 { 2111 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2112 const struct intel_digital_connector_state *intel_conn_state = 2113 to_intel_digital_connector_state(conn_state); 2114 2115 if (!crtc_state->has_hdmi_sink) 2116 return false; 2117 2118 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2119 return intel_hdmi->has_audio; 2120 else 2121 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2122 } 2123 2124 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2125 struct intel_crtc_state *crtc_state, 2126 const struct drm_connector_state *conn_state) 2127 { 2128 struct drm_connector *connector = conn_state->connector; 2129 struct drm_i915_private *i915 = to_i915(connector->dev); 2130 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2131 int ret; 2132 bool ycbcr_420_only; 2133 2134 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, adjusted_mode); 2135 if (connector->ycbcr_420_allowed && ycbcr_420_only) { 2136 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2137 } else { 2138 if (!connector->ycbcr_420_allowed && ycbcr_420_only) 2139 drm_dbg_kms(&i915->drm, 2140 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2141 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 2142 } 2143 2144 ret = intel_hdmi_compute_clock(encoder, crtc_state); 2145 if (ret) { 2146 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 && 2147 connector->ycbcr_420_allowed && 2148 drm_mode_is_420_also(&connector->display_info, adjusted_mode)) { 2149 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2150 ret = intel_hdmi_compute_clock(encoder, crtc_state); 2151 } 2152 } 2153 2154 return ret; 2155 } 2156 2157 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2158 struct intel_crtc_state *pipe_config, 2159 struct drm_connector_state *conn_state) 2160 { 2161 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2162 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2163 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2164 struct drm_connector *connector = conn_state->connector; 2165 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2166 int ret; 2167 2168 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2169 return -EINVAL; 2170 2171 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2172 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, 2173 conn_state); 2174 2175 if (pipe_config->has_hdmi_sink) 2176 pipe_config->has_infoframe = true; 2177 2178 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2179 pipe_config->pixel_multiplier = 2; 2180 2181 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 2182 pipe_config->has_pch_encoder = true; 2183 2184 pipe_config->has_audio = 2185 intel_hdmi_has_audio(encoder, pipe_config, conn_state); 2186 2187 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state); 2188 if (ret) 2189 return ret; 2190 2191 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 2192 ret = intel_pch_panel_fitting(pipe_config, conn_state); 2193 if (ret) 2194 return ret; 2195 } 2196 2197 pipe_config->limited_color_range = 2198 intel_hdmi_limited_color_range(pipe_config, conn_state); 2199 2200 if (conn_state->picture_aspect_ratio) 2201 adjusted_mode->picture_aspect_ratio = 2202 conn_state->picture_aspect_ratio; 2203 2204 pipe_config->lane_count = 4; 2205 2206 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) { 2207 if (scdc->scrambling.low_rates) 2208 pipe_config->hdmi_scrambling = true; 2209 2210 if (pipe_config->port_clock > 340000) { 2211 pipe_config->hdmi_scrambling = true; 2212 pipe_config->hdmi_high_tmds_clock_ratio = true; 2213 } 2214 } 2215 2216 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2217 conn_state); 2218 2219 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2220 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); 2221 return -EINVAL; 2222 } 2223 2224 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2225 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); 2226 return -EINVAL; 2227 } 2228 2229 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2230 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); 2231 return -EINVAL; 2232 } 2233 2234 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2235 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); 2236 return -EINVAL; 2237 } 2238 2239 return 0; 2240 } 2241 2242 static void 2243 intel_hdmi_unset_edid(struct drm_connector *connector) 2244 { 2245 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2246 2247 intel_hdmi->has_hdmi_sink = false; 2248 intel_hdmi->has_audio = false; 2249 2250 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2251 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2252 2253 kfree(to_intel_connector(connector)->detect_edid); 2254 to_intel_connector(connector)->detect_edid = NULL; 2255 } 2256 2257 static void 2258 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 2259 { 2260 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2261 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2262 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2263 struct i2c_adapter *adapter = 2264 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2265 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter); 2266 2267 /* 2268 * Type 1 DVI adaptors are not required to implement any 2269 * registers, so we can't always detect their presence. 2270 * Ideally we should be able to check the state of the 2271 * CONFIG1 pin, but no such luck on our hardware. 2272 * 2273 * The only method left to us is to check the VBT to see 2274 * if the port is a dual mode capable DP port. But let's 2275 * only do that when we sucesfully read the EDID, to avoid 2276 * confusing log messages about DP dual mode adaptors when 2277 * there's nothing connected to the port. 2278 */ 2279 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2280 /* An overridden EDID imply that we want this port for testing. 2281 * Make sure not to set limits for that port. 2282 */ 2283 if (has_edid && !connector->override_edid && 2284 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2285 drm_dbg_kms(&dev_priv->drm, 2286 "Assuming DP dual mode adaptor presence based on VBT\n"); 2287 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2288 } else { 2289 type = DRM_DP_DUAL_MODE_NONE; 2290 } 2291 } 2292 2293 if (type == DRM_DP_DUAL_MODE_NONE) 2294 return; 2295 2296 hdmi->dp_dual_mode.type = type; 2297 hdmi->dp_dual_mode.max_tmds_clock = 2298 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter); 2299 2300 drm_dbg_kms(&dev_priv->drm, 2301 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2302 drm_dp_get_dual_mode_type_name(type), 2303 hdmi->dp_dual_mode.max_tmds_clock); 2304 } 2305 2306 static bool 2307 intel_hdmi_set_edid(struct drm_connector *connector) 2308 { 2309 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2310 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2311 intel_wakeref_t wakeref; 2312 struct edid *edid; 2313 bool connected = false; 2314 struct i2c_adapter *i2c; 2315 2316 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2317 2318 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2319 2320 edid = drm_get_edid(connector, i2c); 2321 2322 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2323 drm_dbg_kms(&dev_priv->drm, 2324 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2325 intel_gmbus_force_bit(i2c, true); 2326 edid = drm_get_edid(connector, i2c); 2327 intel_gmbus_force_bit(i2c, false); 2328 } 2329 2330 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 2331 2332 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2333 2334 to_intel_connector(connector)->detect_edid = edid; 2335 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2336 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2337 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2338 2339 connected = true; 2340 } 2341 2342 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2343 2344 return connected; 2345 } 2346 2347 static enum drm_connector_status 2348 intel_hdmi_detect(struct drm_connector *connector, bool force) 2349 { 2350 enum drm_connector_status status = connector_status_disconnected; 2351 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2352 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2353 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2354 intel_wakeref_t wakeref; 2355 2356 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2357 connector->base.id, connector->name); 2358 2359 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 2360 return connector_status_disconnected; 2361 2362 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2363 2364 if (DISPLAY_VER(dev_priv) >= 11 && 2365 !intel_digital_port_connected(encoder)) 2366 goto out; 2367 2368 intel_hdmi_unset_edid(connector); 2369 2370 if (intel_hdmi_set_edid(connector)) 2371 status = connector_status_connected; 2372 2373 out: 2374 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2375 2376 if (status != connector_status_connected) 2377 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2378 2379 /* 2380 * Make sure the refs for power wells enabled during detect are 2381 * dropped to avoid a new detect cycle triggered by HPD polling. 2382 */ 2383 intel_display_power_flush_work(dev_priv); 2384 2385 return status; 2386 } 2387 2388 static void 2389 intel_hdmi_force(struct drm_connector *connector) 2390 { 2391 struct drm_i915_private *i915 = to_i915(connector->dev); 2392 2393 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2394 connector->base.id, connector->name); 2395 2396 intel_hdmi_unset_edid(connector); 2397 2398 if (connector->status != connector_status_connected) 2399 return; 2400 2401 intel_hdmi_set_edid(connector); 2402 } 2403 2404 static int intel_hdmi_get_modes(struct drm_connector *connector) 2405 { 2406 struct edid *edid; 2407 2408 edid = to_intel_connector(connector)->detect_edid; 2409 if (edid == NULL) 2410 return 0; 2411 2412 return intel_connector_update_modes(connector, edid); 2413 } 2414 2415 static struct i2c_adapter * 2416 intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2417 { 2418 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2419 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2420 2421 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2422 } 2423 2424 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2425 { 2426 struct drm_i915_private *i915 = to_i915(connector->dev); 2427 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2428 struct kobject *i2c_kobj = &adapter->dev.kobj; 2429 struct kobject *connector_kobj = &connector->kdev->kobj; 2430 int ret; 2431 2432 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2433 if (ret) 2434 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret); 2435 } 2436 2437 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2438 { 2439 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2440 struct kobject *i2c_kobj = &adapter->dev.kobj; 2441 struct kobject *connector_kobj = &connector->kdev->kobj; 2442 2443 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2444 } 2445 2446 static int 2447 intel_hdmi_connector_register(struct drm_connector *connector) 2448 { 2449 int ret; 2450 2451 ret = intel_connector_register(connector); 2452 if (ret) 2453 return ret; 2454 2455 intel_hdmi_create_i2c_symlink(connector); 2456 2457 return ret; 2458 } 2459 2460 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2461 { 2462 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2463 2464 cec_notifier_conn_unregister(n); 2465 2466 intel_hdmi_remove_i2c_symlink(connector); 2467 intel_connector_unregister(connector); 2468 } 2469 2470 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2471 .detect = intel_hdmi_detect, 2472 .force = intel_hdmi_force, 2473 .fill_modes = drm_helper_probe_single_connector_modes, 2474 .atomic_get_property = intel_digital_connector_atomic_get_property, 2475 .atomic_set_property = intel_digital_connector_atomic_set_property, 2476 .late_register = intel_hdmi_connector_register, 2477 .early_unregister = intel_hdmi_connector_unregister, 2478 .destroy = intel_connector_destroy, 2479 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2480 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2481 }; 2482 2483 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2484 .get_modes = intel_hdmi_get_modes, 2485 .mode_valid = intel_hdmi_mode_valid, 2486 .atomic_check = intel_digital_connector_atomic_check, 2487 }; 2488 2489 static void 2490 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2491 { 2492 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2493 2494 intel_attach_force_audio_property(connector); 2495 intel_attach_broadcast_rgb_property(connector); 2496 intel_attach_aspect_ratio_property(connector); 2497 2498 intel_attach_hdmi_colorspace_property(connector); 2499 drm_connector_attach_content_type_property(connector); 2500 2501 if (DISPLAY_VER(dev_priv) >= 10) 2502 drm_connector_attach_hdr_output_metadata_property(connector); 2503 2504 if (!HAS_GMCH(dev_priv)) 2505 drm_connector_attach_max_bpc_property(connector, 8, 12); 2506 } 2507 2508 /* 2509 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2510 * @encoder: intel_encoder 2511 * @connector: drm_connector 2512 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2513 * or reset the high tmds clock ratio for scrambling 2514 * @scrambling: bool to Indicate if the function needs to set or reset 2515 * sink scrambling 2516 * 2517 * This function handles scrambling on HDMI 2.0 capable sinks. 2518 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2519 * it enables scrambling. This should be called before enabling the HDMI 2520 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2521 * detect a scrambled clock within 100 ms. 2522 * 2523 * Returns: 2524 * True on success, false on failure. 2525 */ 2526 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2527 struct drm_connector *connector, 2528 bool high_tmds_clock_ratio, 2529 bool scrambling) 2530 { 2531 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2532 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2533 struct drm_scrambling *sink_scrambling = 2534 &connector->display_info.hdmi.scdc.scrambling; 2535 struct i2c_adapter *adapter = 2536 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2537 2538 if (!sink_scrambling->supported) 2539 return true; 2540 2541 drm_dbg_kms(&dev_priv->drm, 2542 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2543 connector->base.id, connector->name, 2544 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); 2545 2546 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2547 return drm_scdc_set_high_tmds_clock_ratio(adapter, 2548 high_tmds_clock_ratio) && 2549 drm_scdc_set_scrambling(adapter, scrambling); 2550 } 2551 2552 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2553 { 2554 u8 ddc_pin; 2555 2556 switch (port) { 2557 case PORT_B: 2558 ddc_pin = GMBUS_PIN_DPB; 2559 break; 2560 case PORT_C: 2561 ddc_pin = GMBUS_PIN_DPC; 2562 break; 2563 case PORT_D: 2564 ddc_pin = GMBUS_PIN_DPD_CHV; 2565 break; 2566 default: 2567 MISSING_CASE(port); 2568 ddc_pin = GMBUS_PIN_DPB; 2569 break; 2570 } 2571 return ddc_pin; 2572 } 2573 2574 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2575 { 2576 u8 ddc_pin; 2577 2578 switch (port) { 2579 case PORT_B: 2580 ddc_pin = GMBUS_PIN_1_BXT; 2581 break; 2582 case PORT_C: 2583 ddc_pin = GMBUS_PIN_2_BXT; 2584 break; 2585 default: 2586 MISSING_CASE(port); 2587 ddc_pin = GMBUS_PIN_1_BXT; 2588 break; 2589 } 2590 return ddc_pin; 2591 } 2592 2593 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2594 enum port port) 2595 { 2596 u8 ddc_pin; 2597 2598 switch (port) { 2599 case PORT_B: 2600 ddc_pin = GMBUS_PIN_1_BXT; 2601 break; 2602 case PORT_C: 2603 ddc_pin = GMBUS_PIN_2_BXT; 2604 break; 2605 case PORT_D: 2606 ddc_pin = GMBUS_PIN_4_CNP; 2607 break; 2608 case PORT_F: 2609 ddc_pin = GMBUS_PIN_3_BXT; 2610 break; 2611 default: 2612 MISSING_CASE(port); 2613 ddc_pin = GMBUS_PIN_1_BXT; 2614 break; 2615 } 2616 return ddc_pin; 2617 } 2618 2619 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2620 { 2621 enum phy phy = intel_port_to_phy(dev_priv, port); 2622 2623 if (intel_phy_is_combo(dev_priv, phy)) 2624 return GMBUS_PIN_1_BXT + port; 2625 else if (intel_phy_is_tc(dev_priv, phy)) 2626 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 2627 2628 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 2629 return GMBUS_PIN_2_BXT; 2630 } 2631 2632 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2633 { 2634 enum phy phy = intel_port_to_phy(dev_priv, port); 2635 u8 ddc_pin; 2636 2637 switch (phy) { 2638 case PHY_A: 2639 ddc_pin = GMBUS_PIN_1_BXT; 2640 break; 2641 case PHY_B: 2642 ddc_pin = GMBUS_PIN_2_BXT; 2643 break; 2644 case PHY_C: 2645 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2646 break; 2647 default: 2648 MISSING_CASE(phy); 2649 ddc_pin = GMBUS_PIN_1_BXT; 2650 break; 2651 } 2652 return ddc_pin; 2653 } 2654 2655 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2656 { 2657 enum phy phy = intel_port_to_phy(dev_priv, port); 2658 2659 WARN_ON(port == PORT_C); 2660 2661 /* 2662 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2663 * final two outputs use type-c pins, even though they're actually 2664 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2665 * all outputs. 2666 */ 2667 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2668 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2669 2670 return GMBUS_PIN_1_BXT + phy; 2671 } 2672 2673 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) 2674 { 2675 enum phy phy = intel_port_to_phy(i915, port); 2676 2677 drm_WARN_ON(&i915->drm, port == PORT_A); 2678 2679 /* 2680 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2681 * final two outputs use type-c pins, even though they're actually 2682 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2683 * all outputs. 2684 */ 2685 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2686 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2687 2688 return GMBUS_PIN_1_BXT + phy; 2689 } 2690 2691 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2692 { 2693 return intel_port_to_phy(dev_priv, port) + 1; 2694 } 2695 2696 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2697 { 2698 enum phy phy = intel_port_to_phy(dev_priv, port); 2699 2700 WARN_ON(port == PORT_B || port == PORT_C); 2701 2702 /* 2703 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2704 * except first combo output. 2705 */ 2706 if (phy == PHY_A) 2707 return GMBUS_PIN_1_BXT; 2708 2709 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2710 } 2711 2712 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2713 enum port port) 2714 { 2715 u8 ddc_pin; 2716 2717 switch (port) { 2718 case PORT_B: 2719 ddc_pin = GMBUS_PIN_DPB; 2720 break; 2721 case PORT_C: 2722 ddc_pin = GMBUS_PIN_DPC; 2723 break; 2724 case PORT_D: 2725 ddc_pin = GMBUS_PIN_DPD; 2726 break; 2727 default: 2728 MISSING_CASE(port); 2729 ddc_pin = GMBUS_PIN_DPB; 2730 break; 2731 } 2732 return ddc_pin; 2733 } 2734 2735 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2736 { 2737 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2738 enum port port = encoder->port; 2739 u8 ddc_pin; 2740 2741 ddc_pin = intel_bios_alternate_ddc_pin(encoder); 2742 if (ddc_pin) { 2743 drm_dbg_kms(&dev_priv->drm, 2744 "Using DDC pin 0x%x for port %c (VBT)\n", 2745 ddc_pin, port_name(port)); 2746 return ddc_pin; 2747 } 2748 2749 if (IS_ALDERLAKE_S(dev_priv)) 2750 ddc_pin = adls_port_to_ddc_pin(dev_priv, port); 2751 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2752 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); 2753 else if (IS_ROCKETLAKE(dev_priv)) 2754 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); 2755 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv)) 2756 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port); 2757 else if (HAS_PCH_MCC(dev_priv)) 2758 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 2759 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2760 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 2761 else if (HAS_PCH_CNP(dev_priv)) 2762 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 2763 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2764 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 2765 else if (IS_CHERRYVIEW(dev_priv)) 2766 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 2767 else 2768 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 2769 2770 drm_dbg_kms(&dev_priv->drm, 2771 "Using DDC pin 0x%x for port %c (platform default)\n", 2772 ddc_pin, port_name(port)); 2773 2774 return ddc_pin; 2775 } 2776 2777 void intel_infoframe_init(struct intel_digital_port *dig_port) 2778 { 2779 struct drm_i915_private *dev_priv = 2780 to_i915(dig_port->base.base.dev); 2781 2782 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2783 dig_port->write_infoframe = vlv_write_infoframe; 2784 dig_port->read_infoframe = vlv_read_infoframe; 2785 dig_port->set_infoframes = vlv_set_infoframes; 2786 dig_port->infoframes_enabled = vlv_infoframes_enabled; 2787 } else if (IS_G4X(dev_priv)) { 2788 dig_port->write_infoframe = g4x_write_infoframe; 2789 dig_port->read_infoframe = g4x_read_infoframe; 2790 dig_port->set_infoframes = g4x_set_infoframes; 2791 dig_port->infoframes_enabled = g4x_infoframes_enabled; 2792 } else if (HAS_DDI(dev_priv)) { 2793 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) { 2794 dig_port->write_infoframe = lspcon_write_infoframe; 2795 dig_port->read_infoframe = lspcon_read_infoframe; 2796 dig_port->set_infoframes = lspcon_set_infoframes; 2797 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 2798 } else { 2799 dig_port->write_infoframe = hsw_write_infoframe; 2800 dig_port->read_infoframe = hsw_read_infoframe; 2801 dig_port->set_infoframes = hsw_set_infoframes; 2802 dig_port->infoframes_enabled = hsw_infoframes_enabled; 2803 } 2804 } else if (HAS_PCH_IBX(dev_priv)) { 2805 dig_port->write_infoframe = ibx_write_infoframe; 2806 dig_port->read_infoframe = ibx_read_infoframe; 2807 dig_port->set_infoframes = ibx_set_infoframes; 2808 dig_port->infoframes_enabled = ibx_infoframes_enabled; 2809 } else { 2810 dig_port->write_infoframe = cpt_write_infoframe; 2811 dig_port->read_infoframe = cpt_read_infoframe; 2812 dig_port->set_infoframes = cpt_set_infoframes; 2813 dig_port->infoframes_enabled = cpt_infoframes_enabled; 2814 } 2815 } 2816 2817 void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 2818 struct intel_connector *intel_connector) 2819 { 2820 struct drm_connector *connector = &intel_connector->base; 2821 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2822 struct intel_encoder *intel_encoder = &dig_port->base; 2823 struct drm_device *dev = intel_encoder->base.dev; 2824 struct drm_i915_private *dev_priv = to_i915(dev); 2825 struct i2c_adapter *ddc; 2826 enum port port = intel_encoder->port; 2827 struct cec_connector_info conn_info; 2828 2829 drm_dbg_kms(&dev_priv->drm, 2830 "Adding HDMI connector on [ENCODER:%d:%s]\n", 2831 intel_encoder->base.base.id, intel_encoder->base.name); 2832 2833 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 2834 return; 2835 2836 if (drm_WARN(dev, dig_port->max_lanes < 4, 2837 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 2838 dig_port->max_lanes, intel_encoder->base.base.id, 2839 intel_encoder->base.name)) 2840 return; 2841 2842 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); 2843 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2844 2845 drm_connector_init_with_ddc(dev, connector, 2846 &intel_hdmi_connector_funcs, 2847 DRM_MODE_CONNECTOR_HDMIA, 2848 ddc); 2849 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 2850 2851 connector->interlace_allowed = 1; 2852 connector->doublescan_allowed = 0; 2853 connector->stereo_allowed = 1; 2854 2855 if (DISPLAY_VER(dev_priv) >= 10) 2856 connector->ycbcr_420_allowed = true; 2857 2858 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2859 2860 if (HAS_DDI(dev_priv)) 2861 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2862 else 2863 intel_connector->get_hw_state = intel_connector_get_hw_state; 2864 2865 intel_hdmi_add_properties(intel_hdmi, connector); 2866 2867 intel_connector_attach_encoder(intel_connector, intel_encoder); 2868 intel_hdmi->attached_connector = intel_connector; 2869 2870 if (is_hdcp_supported(dev_priv, port)) { 2871 int ret = intel_hdcp_init(intel_connector, dig_port, 2872 &intel_hdmi_hdcp_shim); 2873 if (ret) 2874 drm_dbg_kms(&dev_priv->drm, 2875 "HDCP init failed, skipping.\n"); 2876 } 2877 2878 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2879 * 0xd. Failure to do so will result in spurious interrupts being 2880 * generated on the port when a cable is not attached. 2881 */ 2882 if (IS_G45(dev_priv)) { 2883 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 2884 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 2885 (temp & ~0xf) | 0xd); 2886 } 2887 2888 cec_fill_conn_info_from_drm(&conn_info, connector); 2889 2890 intel_hdmi->cec_notifier = 2891 cec_notifier_conn_register(dev->dev, port_identifier(port), 2892 &conn_info); 2893 if (!intel_hdmi->cec_notifier) 2894 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); 2895 } 2896 2897 /* 2898 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 2899 * @vactive: Vactive of a display mode 2900 * 2901 * @return: appropriate dsc slice height for a given mode. 2902 */ 2903 int intel_hdmi_dsc_get_slice_height(int vactive) 2904 { 2905 int slice_height; 2906 2907 /* 2908 * Slice Height determination : HDMI2.1 Section 7.7.5.2 2909 * Select smallest slice height >=96, that results in a valid PPS and 2910 * requires minimum padding lines required for final slice. 2911 * 2912 * Assumption : Vactive is even. 2913 */ 2914 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 2915 if (vactive % slice_height == 0) 2916 return slice_height; 2917 2918 return 0; 2919 } 2920 2921 /* 2922 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 2923 * and dsc decoder capabilities 2924 * 2925 * @crtc_state: intel crtc_state 2926 * @src_max_slices: maximum slices supported by the DSC encoder 2927 * @src_max_slice_width: maximum slice width supported by DSC encoder 2928 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 2929 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 2930 * 2931 * @return: num of dsc slices that can be supported by the dsc encoder 2932 * and decoder. 2933 */ 2934 int 2935 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 2936 int src_max_slices, int src_max_slice_width, 2937 int hdmi_max_slices, int hdmi_throughput) 2938 { 2939 /* Pixel rates in KPixels/sec */ 2940 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 2941 /* 2942 * Rates at which the source and sink are required to process pixels in each 2943 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 2944 */ 2945 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 2946 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 2947 2948 /* Spec limits the slice width to 2720 pixels */ 2949 #define MAX_HDMI_SLICE_WIDTH 2720 2950 int kslice_adjust; 2951 int adjusted_clk_khz; 2952 int min_slices; 2953 int target_slices; 2954 int max_throughput; /* max clock freq. in khz per slice */ 2955 int max_slice_width; 2956 int slice_width; 2957 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 2958 2959 if (!hdmi_throughput) 2960 return 0; 2961 2962 /* 2963 * Slice Width determination : HDMI2.1 Section 7.7.5.1 2964 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 2965 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 2966 * dividing adjusted clock value by 10. 2967 */ 2968 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 2969 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 2970 kslice_adjust = 10; 2971 else 2972 kslice_adjust = 5; 2973 2974 /* 2975 * As per spec, the rate at which the source and the sink process 2976 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 2977 * This depends upon the pixel clock rate and output formats 2978 * (kslice adjust). 2979 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 2980 * at max 340MHz, otherwise they can be processed at max 400MHz. 2981 */ 2982 2983 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 2984 2985 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 2986 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 2987 else 2988 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 2989 2990 /* 2991 * Taking into account the sink's capability for maximum 2992 * clock per slice (in MHz) as read from HF-VSDB. 2993 */ 2994 max_throughput = min(max_throughput, hdmi_throughput * 1000); 2995 2996 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 2997 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 2998 2999 /* 3000 * Keep on increasing the num of slices/line, starting from min_slices 3001 * per line till we get such a number, for which the slice_width is 3002 * just less than max_slice_width. The slices/line selected should be 3003 * less than or equal to the max horizontal slices that the combination 3004 * of PCON encoder and HDMI decoder can support. 3005 */ 3006 slice_width = max_slice_width; 3007 3008 do { 3009 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3010 target_slices = 1; 3011 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3012 target_slices = 2; 3013 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3014 target_slices = 4; 3015 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3016 target_slices = 8; 3017 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3018 target_slices = 12; 3019 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3020 target_slices = 16; 3021 else 3022 return 0; 3023 3024 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3025 if (slice_width >= max_slice_width) 3026 min_slices = target_slices + 1; 3027 } while (slice_width >= max_slice_width); 3028 3029 return target_slices; 3030 } 3031 3032 /* 3033 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3034 * source and sink capabilities. 3035 * 3036 * @src_fraction_bpp: fractional bpp supported by the source 3037 * @slice_width: dsc slice width supported by the source and sink 3038 * @num_slices: num of slices supported by the source and sink 3039 * @output_format: video output format 3040 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3041 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3042 * 3043 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3044 */ 3045 int 3046 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3047 int output_format, bool hdmi_all_bpp, 3048 int hdmi_max_chunk_bytes) 3049 { 3050 int max_dsc_bpp, min_dsc_bpp; 3051 int target_bytes; 3052 bool bpp_found = false; 3053 int bpp_decrement_x16; 3054 int bpp_target; 3055 int bpp_target_x16; 3056 3057 /* 3058 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3059 * Start with the max bpp and keep on decrementing with 3060 * fractional bpp, if supported by PCON DSC encoder 3061 * 3062 * for each bpp we check if no of bytes can be supported by HDMI sink 3063 */ 3064 3065 /* Assuming: bpc as 8*/ 3066 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3067 min_dsc_bpp = 6; 3068 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3069 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3070 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3071 min_dsc_bpp = 8; 3072 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3073 } else { 3074 /* Assuming 4:2:2 encoding */ 3075 min_dsc_bpp = 7; 3076 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3077 } 3078 3079 /* 3080 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3081 * Section 7.7.34 : Source shall not enable compressed Video 3082 * Transport with bpp_target settings above 12 bpp unless 3083 * DSC_all_bpp is set to 1. 3084 */ 3085 if (!hdmi_all_bpp) 3086 max_dsc_bpp = min(max_dsc_bpp, 12); 3087 3088 /* 3089 * The Sink has a limit of compressed data in bytes for a scanline, 3090 * as described in max_chunk_bytes field in HFVSDB block of edid. 3091 * The no. of bytes depend on the target bits per pixel that the 3092 * source configures. So we start with the max_bpp and calculate 3093 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3094 * till we get the target_chunk_bytes just less than what the sink's 3095 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3096 * 3097 * The decrement is according to the fractional support from PCON DSC 3098 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3099 * 3100 * bpp_target_x16 = bpp_target * 16 3101 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3102 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3103 */ 3104 3105 bpp_target = max_dsc_bpp; 3106 3107 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3108 if (!src_fractional_bpp) 3109 src_fractional_bpp = 1; 3110 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3111 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3112 3113 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3114 int bpp; 3115 3116 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3117 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3118 if (target_bytes <= hdmi_max_chunk_bytes) { 3119 bpp_found = true; 3120 break; 3121 } 3122 bpp_target_x16 -= bpp_decrement_x16; 3123 } 3124 if (bpp_found) 3125 return bpp_target_x16; 3126 3127 return 0; 3128 } 3129