1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_hdcp_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_edid.h> 41 #include <drm/intel_lpe_audio.h> 42 43 #include "i915_debugfs.h" 44 #include "i915_drv.h" 45 #include "i915_reg.h" 46 #include "intel_atomic.h" 47 #include "intel_connector.h" 48 #include "intel_ddi.h" 49 #include "intel_de.h" 50 #include "intel_display_types.h" 51 #include "intel_dp.h" 52 #include "intel_gmbus.h" 53 #include "intel_hdcp.h" 54 #include "intel_hdcp_regs.h" 55 #include "intel_hdmi.h" 56 #include "intel_lspcon.h" 57 #include "intel_panel.h" 58 #include "intel_snps_phy.h" 59 60 static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi) 61 { 62 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev); 63 } 64 65 static void 66 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 67 { 68 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi); 69 u32 enabled_bits; 70 71 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 72 73 drm_WARN(&dev_priv->drm, 74 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 75 "HDMI port enabled, expecting disabled\n"); 76 } 77 78 static void 79 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 80 enum transcoder cpu_transcoder) 81 { 82 drm_WARN(&dev_priv->drm, 83 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 84 TRANS_DDI_FUNC_ENABLE, 85 "HDMI transcoder function enabled, expecting disabled\n"); 86 } 87 88 static u32 g4x_infoframe_index(unsigned int type) 89 { 90 switch (type) { 91 case HDMI_PACKET_TYPE_GAMUT_METADATA: 92 return VIDEO_DIP_SELECT_GAMUT; 93 case HDMI_INFOFRAME_TYPE_AVI: 94 return VIDEO_DIP_SELECT_AVI; 95 case HDMI_INFOFRAME_TYPE_SPD: 96 return VIDEO_DIP_SELECT_SPD; 97 case HDMI_INFOFRAME_TYPE_VENDOR: 98 return VIDEO_DIP_SELECT_VENDOR; 99 default: 100 MISSING_CASE(type); 101 return 0; 102 } 103 } 104 105 static u32 g4x_infoframe_enable(unsigned int type) 106 { 107 switch (type) { 108 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 109 return VIDEO_DIP_ENABLE_GCP; 110 case HDMI_PACKET_TYPE_GAMUT_METADATA: 111 return VIDEO_DIP_ENABLE_GAMUT; 112 case DP_SDP_VSC: 113 return 0; 114 case HDMI_INFOFRAME_TYPE_AVI: 115 return VIDEO_DIP_ENABLE_AVI; 116 case HDMI_INFOFRAME_TYPE_SPD: 117 return VIDEO_DIP_ENABLE_SPD; 118 case HDMI_INFOFRAME_TYPE_VENDOR: 119 return VIDEO_DIP_ENABLE_VENDOR; 120 case HDMI_INFOFRAME_TYPE_DRM: 121 return 0; 122 default: 123 MISSING_CASE(type); 124 return 0; 125 } 126 } 127 128 static u32 hsw_infoframe_enable(unsigned int type) 129 { 130 switch (type) { 131 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 132 return VIDEO_DIP_ENABLE_GCP_HSW; 133 case HDMI_PACKET_TYPE_GAMUT_METADATA: 134 return VIDEO_DIP_ENABLE_GMP_HSW; 135 case DP_SDP_VSC: 136 return VIDEO_DIP_ENABLE_VSC_HSW; 137 case DP_SDP_PPS: 138 return VDIP_ENABLE_PPS; 139 case HDMI_INFOFRAME_TYPE_AVI: 140 return VIDEO_DIP_ENABLE_AVI_HSW; 141 case HDMI_INFOFRAME_TYPE_SPD: 142 return VIDEO_DIP_ENABLE_SPD_HSW; 143 case HDMI_INFOFRAME_TYPE_VENDOR: 144 return VIDEO_DIP_ENABLE_VS_HSW; 145 case HDMI_INFOFRAME_TYPE_DRM: 146 return VIDEO_DIP_ENABLE_DRM_GLK; 147 default: 148 MISSING_CASE(type); 149 return 0; 150 } 151 } 152 153 static i915_reg_t 154 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 155 enum transcoder cpu_transcoder, 156 unsigned int type, 157 int i) 158 { 159 switch (type) { 160 case HDMI_PACKET_TYPE_GAMUT_METADATA: 161 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 162 case DP_SDP_VSC: 163 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 164 case DP_SDP_PPS: 165 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 166 case HDMI_INFOFRAME_TYPE_AVI: 167 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 168 case HDMI_INFOFRAME_TYPE_SPD: 169 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 170 case HDMI_INFOFRAME_TYPE_VENDOR: 171 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 172 case HDMI_INFOFRAME_TYPE_DRM: 173 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 174 default: 175 MISSING_CASE(type); 176 return INVALID_MMIO_REG; 177 } 178 } 179 180 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 181 unsigned int type) 182 { 183 switch (type) { 184 case DP_SDP_VSC: 185 return VIDEO_DIP_VSC_DATA_SIZE; 186 case DP_SDP_PPS: 187 return VIDEO_DIP_PPS_DATA_SIZE; 188 case HDMI_PACKET_TYPE_GAMUT_METADATA: 189 if (DISPLAY_VER(dev_priv) >= 11) 190 return VIDEO_DIP_GMP_DATA_SIZE; 191 else 192 return VIDEO_DIP_DATA_SIZE; 193 default: 194 return VIDEO_DIP_DATA_SIZE; 195 } 196 } 197 198 static void g4x_write_infoframe(struct intel_encoder *encoder, 199 const struct intel_crtc_state *crtc_state, 200 unsigned int type, 201 const void *frame, ssize_t len) 202 { 203 const u32 *data = frame; 204 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 205 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 206 int i; 207 208 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 209 "Writing DIP with CTL reg disabled\n"); 210 211 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 212 val |= g4x_infoframe_index(type); 213 214 val &= ~g4x_infoframe_enable(type); 215 216 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 217 218 for (i = 0; i < len; i += 4) { 219 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 220 data++; 221 } 222 /* Write every possible data byte to force correct ECC calculation. */ 223 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 224 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 225 226 val |= g4x_infoframe_enable(type); 227 val &= ~VIDEO_DIP_FREQ_MASK; 228 val |= VIDEO_DIP_FREQ_VSYNC; 229 230 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 231 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 232 } 233 234 static void g4x_read_infoframe(struct intel_encoder *encoder, 235 const struct intel_crtc_state *crtc_state, 236 unsigned int type, 237 void *frame, ssize_t len) 238 { 239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 240 u32 val, *data = frame; 241 int i; 242 243 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 244 245 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 246 val |= g4x_infoframe_index(type); 247 248 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 249 250 for (i = 0; i < len; i += 4) 251 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 252 } 253 254 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 255 const struct intel_crtc_state *pipe_config) 256 { 257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 258 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 259 260 if ((val & VIDEO_DIP_ENABLE) == 0) 261 return 0; 262 263 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 264 return 0; 265 266 return val & (VIDEO_DIP_ENABLE_AVI | 267 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 268 } 269 270 static void ibx_write_infoframe(struct intel_encoder *encoder, 271 const struct intel_crtc_state *crtc_state, 272 unsigned int type, 273 const void *frame, ssize_t len) 274 { 275 const u32 *data = frame; 276 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 277 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 278 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 279 u32 val = intel_de_read(dev_priv, reg); 280 int i; 281 282 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 283 "Writing DIP with CTL reg disabled\n"); 284 285 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 286 val |= g4x_infoframe_index(type); 287 288 val &= ~g4x_infoframe_enable(type); 289 290 intel_de_write(dev_priv, reg, val); 291 292 for (i = 0; i < len; i += 4) { 293 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 294 *data); 295 data++; 296 } 297 /* Write every possible data byte to force correct ECC calculation. */ 298 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 299 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 300 301 val |= g4x_infoframe_enable(type); 302 val &= ~VIDEO_DIP_FREQ_MASK; 303 val |= VIDEO_DIP_FREQ_VSYNC; 304 305 intel_de_write(dev_priv, reg, val); 306 intel_de_posting_read(dev_priv, reg); 307 } 308 309 static void ibx_read_infoframe(struct intel_encoder *encoder, 310 const struct intel_crtc_state *crtc_state, 311 unsigned int type, 312 void *frame, ssize_t len) 313 { 314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 316 u32 val, *data = frame; 317 int i; 318 319 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 320 321 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 322 val |= g4x_infoframe_index(type); 323 324 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 325 326 for (i = 0; i < len; i += 4) 327 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 328 } 329 330 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 331 const struct intel_crtc_state *pipe_config) 332 { 333 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 334 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 335 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 336 u32 val = intel_de_read(dev_priv, reg); 337 338 if ((val & VIDEO_DIP_ENABLE) == 0) 339 return 0; 340 341 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 342 return 0; 343 344 return val & (VIDEO_DIP_ENABLE_AVI | 345 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 346 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 347 } 348 349 static void cpt_write_infoframe(struct intel_encoder *encoder, 350 const struct intel_crtc_state *crtc_state, 351 unsigned int type, 352 const void *frame, ssize_t len) 353 { 354 const u32 *data = frame; 355 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 356 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 357 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 358 u32 val = intel_de_read(dev_priv, reg); 359 int i; 360 361 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 362 "Writing DIP with CTL reg disabled\n"); 363 364 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 365 val |= g4x_infoframe_index(type); 366 367 /* The DIP control register spec says that we need to update the AVI 368 * infoframe without clearing its enable bit */ 369 if (type != HDMI_INFOFRAME_TYPE_AVI) 370 val &= ~g4x_infoframe_enable(type); 371 372 intel_de_write(dev_priv, reg, val); 373 374 for (i = 0; i < len; i += 4) { 375 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 376 *data); 377 data++; 378 } 379 /* Write every possible data byte to force correct ECC calculation. */ 380 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 381 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 382 383 val |= g4x_infoframe_enable(type); 384 val &= ~VIDEO_DIP_FREQ_MASK; 385 val |= VIDEO_DIP_FREQ_VSYNC; 386 387 intel_de_write(dev_priv, reg, val); 388 intel_de_posting_read(dev_priv, reg); 389 } 390 391 static void cpt_read_infoframe(struct intel_encoder *encoder, 392 const struct intel_crtc_state *crtc_state, 393 unsigned int type, 394 void *frame, ssize_t len) 395 { 396 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 397 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 398 u32 val, *data = frame; 399 int i; 400 401 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 402 403 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 404 val |= g4x_infoframe_index(type); 405 406 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 407 408 for (i = 0; i < len; i += 4) 409 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 410 } 411 412 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 413 const struct intel_crtc_state *pipe_config) 414 { 415 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 416 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 417 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 418 419 if ((val & VIDEO_DIP_ENABLE) == 0) 420 return 0; 421 422 return val & (VIDEO_DIP_ENABLE_AVI | 423 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 424 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 425 } 426 427 static void vlv_write_infoframe(struct intel_encoder *encoder, 428 const struct intel_crtc_state *crtc_state, 429 unsigned int type, 430 const void *frame, ssize_t len) 431 { 432 const u32 *data = frame; 433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 435 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 436 u32 val = intel_de_read(dev_priv, reg); 437 int i; 438 439 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 440 "Writing DIP with CTL reg disabled\n"); 441 442 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 443 val |= g4x_infoframe_index(type); 444 445 val &= ~g4x_infoframe_enable(type); 446 447 intel_de_write(dev_priv, reg, val); 448 449 for (i = 0; i < len; i += 4) { 450 intel_de_write(dev_priv, 451 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 452 data++; 453 } 454 /* Write every possible data byte to force correct ECC calculation. */ 455 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 456 intel_de_write(dev_priv, 457 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 458 459 val |= g4x_infoframe_enable(type); 460 val &= ~VIDEO_DIP_FREQ_MASK; 461 val |= VIDEO_DIP_FREQ_VSYNC; 462 463 intel_de_write(dev_priv, reg, val); 464 intel_de_posting_read(dev_priv, reg); 465 } 466 467 static void vlv_read_infoframe(struct intel_encoder *encoder, 468 const struct intel_crtc_state *crtc_state, 469 unsigned int type, 470 void *frame, ssize_t len) 471 { 472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 474 u32 val, *data = frame; 475 int i; 476 477 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); 478 479 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 480 val |= g4x_infoframe_index(type); 481 482 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 483 484 for (i = 0; i < len; i += 4) 485 *data++ = intel_de_read(dev_priv, 486 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 487 } 488 489 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 490 const struct intel_crtc_state *pipe_config) 491 { 492 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 493 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 494 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 495 496 if ((val & VIDEO_DIP_ENABLE) == 0) 497 return 0; 498 499 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 500 return 0; 501 502 return val & (VIDEO_DIP_ENABLE_AVI | 503 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 504 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 505 } 506 507 void hsw_write_infoframe(struct intel_encoder *encoder, 508 const struct intel_crtc_state *crtc_state, 509 unsigned int type, 510 const void *frame, ssize_t len) 511 { 512 const u32 *data = frame; 513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 514 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 515 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 516 int data_size; 517 int i; 518 u32 val = intel_de_read(dev_priv, ctl_reg); 519 520 data_size = hsw_dip_data_size(dev_priv, type); 521 522 drm_WARN_ON(&dev_priv->drm, len > data_size); 523 524 val &= ~hsw_infoframe_enable(type); 525 intel_de_write(dev_priv, ctl_reg, val); 526 527 for (i = 0; i < len; i += 4) { 528 intel_de_write(dev_priv, 529 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 530 *data); 531 data++; 532 } 533 /* Write every possible data byte to force correct ECC calculation. */ 534 for (; i < data_size; i += 4) 535 intel_de_write(dev_priv, 536 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 537 0); 538 539 /* Wa_14013475917 */ 540 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr && 541 type == DP_SDP_VSC) 542 return; 543 544 val |= hsw_infoframe_enable(type); 545 intel_de_write(dev_priv, ctl_reg, val); 546 intel_de_posting_read(dev_priv, ctl_reg); 547 } 548 549 void hsw_read_infoframe(struct intel_encoder *encoder, 550 const struct intel_crtc_state *crtc_state, 551 unsigned int type, void *frame, ssize_t len) 552 { 553 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 554 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 555 u32 *data = frame; 556 int i; 557 558 for (i = 0; i < len; i += 4) 559 *data++ = intel_de_read(dev_priv, 560 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 561 } 562 563 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 564 const struct intel_crtc_state *pipe_config) 565 { 566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 567 u32 val = intel_de_read(dev_priv, 568 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 569 u32 mask; 570 571 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 572 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 573 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 574 575 if (DISPLAY_VER(dev_priv) >= 10) 576 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 577 578 return val & mask; 579 } 580 581 static const u8 infoframe_type_to_idx[] = { 582 HDMI_PACKET_TYPE_GENERAL_CONTROL, 583 HDMI_PACKET_TYPE_GAMUT_METADATA, 584 DP_SDP_VSC, 585 HDMI_INFOFRAME_TYPE_AVI, 586 HDMI_INFOFRAME_TYPE_SPD, 587 HDMI_INFOFRAME_TYPE_VENDOR, 588 HDMI_INFOFRAME_TYPE_DRM, 589 }; 590 591 u32 intel_hdmi_infoframe_enable(unsigned int type) 592 { 593 int i; 594 595 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 596 if (infoframe_type_to_idx[i] == type) 597 return BIT(i); 598 } 599 600 return 0; 601 } 602 603 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 604 const struct intel_crtc_state *crtc_state) 605 { 606 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 607 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 608 u32 val, ret = 0; 609 int i; 610 611 val = dig_port->infoframes_enabled(encoder, crtc_state); 612 613 /* map from hardware bits to dip idx */ 614 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 615 unsigned int type = infoframe_type_to_idx[i]; 616 617 if (HAS_DDI(dev_priv)) { 618 if (val & hsw_infoframe_enable(type)) 619 ret |= BIT(i); 620 } else { 621 if (val & g4x_infoframe_enable(type)) 622 ret |= BIT(i); 623 } 624 } 625 626 return ret; 627 } 628 629 /* 630 * The data we write to the DIP data buffer registers is 1 byte bigger than the 631 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 632 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 633 * used for both technologies. 634 * 635 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 636 * DW1: DB3 | DB2 | DB1 | DB0 637 * DW2: DB7 | DB6 | DB5 | DB4 638 * DW3: ... 639 * 640 * (HB is Header Byte, DB is Data Byte) 641 * 642 * The hdmi pack() functions don't know about that hardware specific hole so we 643 * trick them by giving an offset into the buffer and moving back the header 644 * bytes by one. 645 */ 646 static void intel_write_infoframe(struct intel_encoder *encoder, 647 const struct intel_crtc_state *crtc_state, 648 enum hdmi_infoframe_type type, 649 const union hdmi_infoframe *frame) 650 { 651 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 652 u8 buffer[VIDEO_DIP_DATA_SIZE]; 653 ssize_t len; 654 655 if ((crtc_state->infoframes.enable & 656 intel_hdmi_infoframe_enable(type)) == 0) 657 return; 658 659 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 660 return; 661 662 /* see comment above for the reason for this offset */ 663 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 664 if (drm_WARN_ON(encoder->base.dev, len < 0)) 665 return; 666 667 /* Insert the 'hole' (see big comment above) at position 3 */ 668 memmove(&buffer[0], &buffer[1], 3); 669 buffer[3] = 0; 670 len++; 671 672 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 673 } 674 675 void intel_read_infoframe(struct intel_encoder *encoder, 676 const struct intel_crtc_state *crtc_state, 677 enum hdmi_infoframe_type type, 678 union hdmi_infoframe *frame) 679 { 680 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 681 u8 buffer[VIDEO_DIP_DATA_SIZE]; 682 int ret; 683 684 if ((crtc_state->infoframes.enable & 685 intel_hdmi_infoframe_enable(type)) == 0) 686 return; 687 688 dig_port->read_infoframe(encoder, crtc_state, 689 type, buffer, sizeof(buffer)); 690 691 /* Fill the 'hole' (see big comment above) at position 3 */ 692 memmove(&buffer[1], &buffer[0], 3); 693 694 /* see comment above for the reason for this offset */ 695 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 696 if (ret) { 697 drm_dbg_kms(encoder->base.dev, 698 "Failed to unpack infoframe type 0x%02x\n", type); 699 return; 700 } 701 702 if (frame->any.type != type) 703 drm_dbg_kms(encoder->base.dev, 704 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 705 frame->any.type, type); 706 } 707 708 static bool 709 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 710 struct intel_crtc_state *crtc_state, 711 struct drm_connector_state *conn_state) 712 { 713 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 714 const struct drm_display_mode *adjusted_mode = 715 &crtc_state->hw.adjusted_mode; 716 struct drm_connector *connector = conn_state->connector; 717 int ret; 718 719 if (!crtc_state->has_infoframe) 720 return true; 721 722 crtc_state->infoframes.enable |= 723 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 724 725 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 726 adjusted_mode); 727 if (ret) 728 return false; 729 730 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 731 frame->colorspace = HDMI_COLORSPACE_YUV420; 732 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 733 frame->colorspace = HDMI_COLORSPACE_YUV444; 734 else 735 frame->colorspace = HDMI_COLORSPACE_RGB; 736 737 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 738 739 /* nonsense combination */ 740 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 741 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 742 743 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 744 drm_hdmi_avi_infoframe_quant_range(frame, connector, 745 adjusted_mode, 746 crtc_state->limited_color_range ? 747 HDMI_QUANTIZATION_RANGE_LIMITED : 748 HDMI_QUANTIZATION_RANGE_FULL); 749 } else { 750 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 751 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 752 } 753 754 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 755 756 /* TODO: handle pixel repetition for YCBCR420 outputs */ 757 758 ret = hdmi_avi_infoframe_check(frame); 759 if (drm_WARN_ON(encoder->base.dev, ret)) 760 return false; 761 762 return true; 763 } 764 765 static bool 766 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 767 struct intel_crtc_state *crtc_state, 768 struct drm_connector_state *conn_state) 769 { 770 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 771 int ret; 772 773 if (!crtc_state->has_infoframe) 774 return true; 775 776 crtc_state->infoframes.enable |= 777 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 778 779 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 780 if (drm_WARN_ON(encoder->base.dev, ret)) 781 return false; 782 783 frame->sdi = HDMI_SPD_SDI_PC; 784 785 ret = hdmi_spd_infoframe_check(frame); 786 if (drm_WARN_ON(encoder->base.dev, ret)) 787 return false; 788 789 return true; 790 } 791 792 static bool 793 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 794 struct intel_crtc_state *crtc_state, 795 struct drm_connector_state *conn_state) 796 { 797 struct hdmi_vendor_infoframe *frame = 798 &crtc_state->infoframes.hdmi.vendor.hdmi; 799 const struct drm_display_info *info = 800 &conn_state->connector->display_info; 801 int ret; 802 803 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 804 return true; 805 806 crtc_state->infoframes.enable |= 807 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 808 809 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 810 conn_state->connector, 811 &crtc_state->hw.adjusted_mode); 812 if (drm_WARN_ON(encoder->base.dev, ret)) 813 return false; 814 815 ret = hdmi_vendor_infoframe_check(frame); 816 if (drm_WARN_ON(encoder->base.dev, ret)) 817 return false; 818 819 return true; 820 } 821 822 static bool 823 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 824 struct intel_crtc_state *crtc_state, 825 struct drm_connector_state *conn_state) 826 { 827 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 828 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 829 int ret; 830 831 if (DISPLAY_VER(dev_priv) < 10) 832 return true; 833 834 if (!crtc_state->has_infoframe) 835 return true; 836 837 if (!conn_state->hdr_output_metadata) 838 return true; 839 840 crtc_state->infoframes.enable |= 841 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 842 843 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 844 if (ret < 0) { 845 drm_dbg_kms(&dev_priv->drm, 846 "couldn't set HDR metadata in infoframe\n"); 847 return false; 848 } 849 850 ret = hdmi_drm_infoframe_check(frame); 851 if (drm_WARN_ON(&dev_priv->drm, ret)) 852 return false; 853 854 return true; 855 } 856 857 static void g4x_set_infoframes(struct intel_encoder *encoder, 858 bool enable, 859 const struct intel_crtc_state *crtc_state, 860 const struct drm_connector_state *conn_state) 861 { 862 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 863 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 864 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 865 i915_reg_t reg = VIDEO_DIP_CTL; 866 u32 val = intel_de_read(dev_priv, reg); 867 u32 port = VIDEO_DIP_PORT(encoder->port); 868 869 assert_hdmi_port_disabled(intel_hdmi); 870 871 /* If the registers were not initialized yet, they might be zeroes, 872 * which means we're selecting the AVI DIP and we're setting its 873 * frequency to once. This seems to really confuse the HW and make 874 * things stop working (the register spec says the AVI always needs to 875 * be sent every VSync). So here we avoid writing to the register more 876 * than we need and also explicitly select the AVI DIP and explicitly 877 * set its frequency to every VSync. Avoiding to write it twice seems to 878 * be enough to solve the problem, but being defensive shouldn't hurt us 879 * either. */ 880 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 881 882 if (!enable) { 883 if (!(val & VIDEO_DIP_ENABLE)) 884 return; 885 if (port != (val & VIDEO_DIP_PORT_MASK)) { 886 drm_dbg_kms(&dev_priv->drm, 887 "video DIP still enabled on port %c\n", 888 (val & VIDEO_DIP_PORT_MASK) >> 29); 889 return; 890 } 891 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 892 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 893 intel_de_write(dev_priv, reg, val); 894 intel_de_posting_read(dev_priv, reg); 895 return; 896 } 897 898 if (port != (val & VIDEO_DIP_PORT_MASK)) { 899 if (val & VIDEO_DIP_ENABLE) { 900 drm_dbg_kms(&dev_priv->drm, 901 "video DIP already enabled on port %c\n", 902 (val & VIDEO_DIP_PORT_MASK) >> 29); 903 return; 904 } 905 val &= ~VIDEO_DIP_PORT_MASK; 906 val |= port; 907 } 908 909 val |= VIDEO_DIP_ENABLE; 910 val &= ~(VIDEO_DIP_ENABLE_AVI | 911 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 912 913 intel_de_write(dev_priv, reg, val); 914 intel_de_posting_read(dev_priv, reg); 915 916 intel_write_infoframe(encoder, crtc_state, 917 HDMI_INFOFRAME_TYPE_AVI, 918 &crtc_state->infoframes.avi); 919 intel_write_infoframe(encoder, crtc_state, 920 HDMI_INFOFRAME_TYPE_SPD, 921 &crtc_state->infoframes.spd); 922 intel_write_infoframe(encoder, crtc_state, 923 HDMI_INFOFRAME_TYPE_VENDOR, 924 &crtc_state->infoframes.hdmi); 925 } 926 927 /* 928 * Determine if default_phase=1 can be indicated in the GCP infoframe. 929 * 930 * From HDMI specification 1.4a: 931 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 932 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 933 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 934 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 935 * phase of 0 936 */ 937 static bool gcp_default_phase_possible(int pipe_bpp, 938 const struct drm_display_mode *mode) 939 { 940 unsigned int pixels_per_group; 941 942 switch (pipe_bpp) { 943 case 30: 944 /* 4 pixels in 5 clocks */ 945 pixels_per_group = 4; 946 break; 947 case 36: 948 /* 2 pixels in 3 clocks */ 949 pixels_per_group = 2; 950 break; 951 case 48: 952 /* 1 pixel in 2 clocks */ 953 pixels_per_group = 1; 954 break; 955 default: 956 /* phase information not relevant for 8bpc */ 957 return false; 958 } 959 960 return mode->crtc_hdisplay % pixels_per_group == 0 && 961 mode->crtc_htotal % pixels_per_group == 0 && 962 mode->crtc_hblank_start % pixels_per_group == 0 && 963 mode->crtc_hblank_end % pixels_per_group == 0 && 964 mode->crtc_hsync_start % pixels_per_group == 0 && 965 mode->crtc_hsync_end % pixels_per_group == 0 && 966 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 967 mode->crtc_htotal/2 % pixels_per_group == 0); 968 } 969 970 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 971 const struct intel_crtc_state *crtc_state, 972 const struct drm_connector_state *conn_state) 973 { 974 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 975 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 976 i915_reg_t reg; 977 978 if ((crtc_state->infoframes.enable & 979 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 980 return false; 981 982 if (HAS_DDI(dev_priv)) 983 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 984 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 985 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 986 else if (HAS_PCH_SPLIT(dev_priv)) 987 reg = TVIDEO_DIP_GCP(crtc->pipe); 988 else 989 return false; 990 991 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 992 993 return true; 994 } 995 996 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 997 struct intel_crtc_state *crtc_state) 998 { 999 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1000 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1001 i915_reg_t reg; 1002 1003 if ((crtc_state->infoframes.enable & 1004 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1005 return; 1006 1007 if (HAS_DDI(dev_priv)) 1008 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1009 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1010 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1011 else if (HAS_PCH_SPLIT(dev_priv)) 1012 reg = TVIDEO_DIP_GCP(crtc->pipe); 1013 else 1014 return; 1015 1016 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1017 } 1018 1019 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1020 struct intel_crtc_state *crtc_state, 1021 struct drm_connector_state *conn_state) 1022 { 1023 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1024 1025 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1026 return; 1027 1028 crtc_state->infoframes.enable |= 1029 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1030 1031 /* Indicate color indication for deep color mode */ 1032 if (crtc_state->pipe_bpp > 24) 1033 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1034 1035 /* Enable default_phase whenever the display mode is suitably aligned */ 1036 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1037 &crtc_state->hw.adjusted_mode)) 1038 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1039 } 1040 1041 static void ibx_set_infoframes(struct intel_encoder *encoder, 1042 bool enable, 1043 const struct intel_crtc_state *crtc_state, 1044 const struct drm_connector_state *conn_state) 1045 { 1046 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1047 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1048 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1049 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1050 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1051 u32 val = intel_de_read(dev_priv, reg); 1052 u32 port = VIDEO_DIP_PORT(encoder->port); 1053 1054 assert_hdmi_port_disabled(intel_hdmi); 1055 1056 /* See the big comment in g4x_set_infoframes() */ 1057 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1058 1059 if (!enable) { 1060 if (!(val & VIDEO_DIP_ENABLE)) 1061 return; 1062 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1063 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1064 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1065 intel_de_write(dev_priv, reg, val); 1066 intel_de_posting_read(dev_priv, reg); 1067 return; 1068 } 1069 1070 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1071 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1072 "DIP already enabled on port %c\n", 1073 (val & VIDEO_DIP_PORT_MASK) >> 29); 1074 val &= ~VIDEO_DIP_PORT_MASK; 1075 val |= port; 1076 } 1077 1078 val |= VIDEO_DIP_ENABLE; 1079 val &= ~(VIDEO_DIP_ENABLE_AVI | 1080 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1081 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1082 1083 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1084 val |= VIDEO_DIP_ENABLE_GCP; 1085 1086 intel_de_write(dev_priv, reg, val); 1087 intel_de_posting_read(dev_priv, reg); 1088 1089 intel_write_infoframe(encoder, crtc_state, 1090 HDMI_INFOFRAME_TYPE_AVI, 1091 &crtc_state->infoframes.avi); 1092 intel_write_infoframe(encoder, crtc_state, 1093 HDMI_INFOFRAME_TYPE_SPD, 1094 &crtc_state->infoframes.spd); 1095 intel_write_infoframe(encoder, crtc_state, 1096 HDMI_INFOFRAME_TYPE_VENDOR, 1097 &crtc_state->infoframes.hdmi); 1098 } 1099 1100 static void cpt_set_infoframes(struct intel_encoder *encoder, 1101 bool enable, 1102 const struct intel_crtc_state *crtc_state, 1103 const struct drm_connector_state *conn_state) 1104 { 1105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1106 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1107 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1108 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1109 u32 val = intel_de_read(dev_priv, reg); 1110 1111 assert_hdmi_port_disabled(intel_hdmi); 1112 1113 /* See the big comment in g4x_set_infoframes() */ 1114 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1115 1116 if (!enable) { 1117 if (!(val & VIDEO_DIP_ENABLE)) 1118 return; 1119 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1120 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1121 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1122 intel_de_write(dev_priv, reg, val); 1123 intel_de_posting_read(dev_priv, reg); 1124 return; 1125 } 1126 1127 /* Set both together, unset both together: see the spec. */ 1128 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1129 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1130 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1131 1132 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1133 val |= VIDEO_DIP_ENABLE_GCP; 1134 1135 intel_de_write(dev_priv, reg, val); 1136 intel_de_posting_read(dev_priv, reg); 1137 1138 intel_write_infoframe(encoder, crtc_state, 1139 HDMI_INFOFRAME_TYPE_AVI, 1140 &crtc_state->infoframes.avi); 1141 intel_write_infoframe(encoder, crtc_state, 1142 HDMI_INFOFRAME_TYPE_SPD, 1143 &crtc_state->infoframes.spd); 1144 intel_write_infoframe(encoder, crtc_state, 1145 HDMI_INFOFRAME_TYPE_VENDOR, 1146 &crtc_state->infoframes.hdmi); 1147 } 1148 1149 static void vlv_set_infoframes(struct intel_encoder *encoder, 1150 bool enable, 1151 const struct intel_crtc_state *crtc_state, 1152 const struct drm_connector_state *conn_state) 1153 { 1154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1155 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1156 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1157 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1158 u32 val = intel_de_read(dev_priv, reg); 1159 u32 port = VIDEO_DIP_PORT(encoder->port); 1160 1161 assert_hdmi_port_disabled(intel_hdmi); 1162 1163 /* See the big comment in g4x_set_infoframes() */ 1164 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1165 1166 if (!enable) { 1167 if (!(val & VIDEO_DIP_ENABLE)) 1168 return; 1169 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1170 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1171 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1172 intel_de_write(dev_priv, reg, val); 1173 intel_de_posting_read(dev_priv, reg); 1174 return; 1175 } 1176 1177 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1178 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1179 "DIP already enabled on port %c\n", 1180 (val & VIDEO_DIP_PORT_MASK) >> 29); 1181 val &= ~VIDEO_DIP_PORT_MASK; 1182 val |= port; 1183 } 1184 1185 val |= VIDEO_DIP_ENABLE; 1186 val &= ~(VIDEO_DIP_ENABLE_AVI | 1187 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1188 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1189 1190 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1191 val |= VIDEO_DIP_ENABLE_GCP; 1192 1193 intel_de_write(dev_priv, reg, val); 1194 intel_de_posting_read(dev_priv, reg); 1195 1196 intel_write_infoframe(encoder, crtc_state, 1197 HDMI_INFOFRAME_TYPE_AVI, 1198 &crtc_state->infoframes.avi); 1199 intel_write_infoframe(encoder, crtc_state, 1200 HDMI_INFOFRAME_TYPE_SPD, 1201 &crtc_state->infoframes.spd); 1202 intel_write_infoframe(encoder, crtc_state, 1203 HDMI_INFOFRAME_TYPE_VENDOR, 1204 &crtc_state->infoframes.hdmi); 1205 } 1206 1207 static void hsw_set_infoframes(struct intel_encoder *encoder, 1208 bool enable, 1209 const struct intel_crtc_state *crtc_state, 1210 const struct drm_connector_state *conn_state) 1211 { 1212 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1213 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1214 u32 val = intel_de_read(dev_priv, reg); 1215 1216 assert_hdmi_transcoder_func_disabled(dev_priv, 1217 crtc_state->cpu_transcoder); 1218 1219 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1220 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1221 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1222 VIDEO_DIP_ENABLE_DRM_GLK); 1223 1224 if (!enable) { 1225 intel_de_write(dev_priv, reg, val); 1226 intel_de_posting_read(dev_priv, reg); 1227 return; 1228 } 1229 1230 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1231 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1232 1233 intel_de_write(dev_priv, reg, val); 1234 intel_de_posting_read(dev_priv, reg); 1235 1236 intel_write_infoframe(encoder, crtc_state, 1237 HDMI_INFOFRAME_TYPE_AVI, 1238 &crtc_state->infoframes.avi); 1239 intel_write_infoframe(encoder, crtc_state, 1240 HDMI_INFOFRAME_TYPE_SPD, 1241 &crtc_state->infoframes.spd); 1242 intel_write_infoframe(encoder, crtc_state, 1243 HDMI_INFOFRAME_TYPE_VENDOR, 1244 &crtc_state->infoframes.hdmi); 1245 intel_write_infoframe(encoder, crtc_state, 1246 HDMI_INFOFRAME_TYPE_DRM, 1247 &crtc_state->infoframes.drm); 1248 } 1249 1250 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1251 { 1252 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1253 struct i2c_adapter *adapter; 1254 1255 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1256 return; 1257 1258 adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1259 1260 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", 1261 enable ? "Enabling" : "Disabling"); 1262 1263 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable); 1264 } 1265 1266 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1267 unsigned int offset, void *buffer, size_t size) 1268 { 1269 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1270 struct intel_hdmi *hdmi = &dig_port->hdmi; 1271 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1272 hdmi->ddc_bus); 1273 int ret; 1274 u8 start = offset & 0xff; 1275 struct i2c_msg msgs[] = { 1276 { 1277 .addr = DRM_HDCP_DDC_ADDR, 1278 .flags = 0, 1279 .len = 1, 1280 .buf = &start, 1281 }, 1282 { 1283 .addr = DRM_HDCP_DDC_ADDR, 1284 .flags = I2C_M_RD, 1285 .len = size, 1286 .buf = buffer 1287 } 1288 }; 1289 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1290 if (ret == ARRAY_SIZE(msgs)) 1291 return 0; 1292 return ret >= 0 ? -EIO : ret; 1293 } 1294 1295 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1296 unsigned int offset, void *buffer, size_t size) 1297 { 1298 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1299 struct intel_hdmi *hdmi = &dig_port->hdmi; 1300 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1301 hdmi->ddc_bus); 1302 int ret; 1303 u8 *write_buf; 1304 struct i2c_msg msg; 1305 1306 write_buf = kzalloc(size + 1, GFP_KERNEL); 1307 if (!write_buf) 1308 return -ENOMEM; 1309 1310 write_buf[0] = offset & 0xff; 1311 memcpy(&write_buf[1], buffer, size); 1312 1313 msg.addr = DRM_HDCP_DDC_ADDR; 1314 msg.flags = 0, 1315 msg.len = size + 1, 1316 msg.buf = write_buf; 1317 1318 ret = i2c_transfer(adapter, &msg, 1); 1319 if (ret == 1) 1320 ret = 0; 1321 else if (ret >= 0) 1322 ret = -EIO; 1323 1324 kfree(write_buf); 1325 return ret; 1326 } 1327 1328 static 1329 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1330 u8 *an) 1331 { 1332 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1333 struct intel_hdmi *hdmi = &dig_port->hdmi; 1334 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1335 hdmi->ddc_bus); 1336 int ret; 1337 1338 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1339 DRM_HDCP_AN_LEN); 1340 if (ret) { 1341 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", 1342 ret); 1343 return ret; 1344 } 1345 1346 ret = intel_gmbus_output_aksv(adapter); 1347 if (ret < 0) { 1348 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); 1349 return ret; 1350 } 1351 return 0; 1352 } 1353 1354 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1355 u8 *bksv) 1356 { 1357 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1358 1359 int ret; 1360 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1361 DRM_HDCP_KSV_LEN); 1362 if (ret) 1363 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", 1364 ret); 1365 return ret; 1366 } 1367 1368 static 1369 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1370 u8 *bstatus) 1371 { 1372 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1373 1374 int ret; 1375 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1376 bstatus, DRM_HDCP_BSTATUS_LEN); 1377 if (ret) 1378 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", 1379 ret); 1380 return ret; 1381 } 1382 1383 static 1384 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1385 bool *repeater_present) 1386 { 1387 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1388 int ret; 1389 u8 val; 1390 1391 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1392 if (ret) { 1393 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1394 ret); 1395 return ret; 1396 } 1397 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1398 return 0; 1399 } 1400 1401 static 1402 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1403 u8 *ri_prime) 1404 { 1405 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1406 1407 int ret; 1408 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1409 ri_prime, DRM_HDCP_RI_LEN); 1410 if (ret) 1411 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", 1412 ret); 1413 return ret; 1414 } 1415 1416 static 1417 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1418 bool *ksv_ready) 1419 { 1420 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1421 int ret; 1422 u8 val; 1423 1424 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1425 if (ret) { 1426 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1427 ret); 1428 return ret; 1429 } 1430 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1431 return 0; 1432 } 1433 1434 static 1435 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1436 int num_downstream, u8 *ksv_fifo) 1437 { 1438 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1439 int ret; 1440 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1441 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1442 if (ret) { 1443 drm_dbg_kms(&i915->drm, 1444 "Read ksv fifo over DDC failed (%d)\n", ret); 1445 return ret; 1446 } 1447 return 0; 1448 } 1449 1450 static 1451 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1452 int i, u32 *part) 1453 { 1454 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1455 int ret; 1456 1457 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1458 return -EINVAL; 1459 1460 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1461 part, DRM_HDCP_V_PRIME_PART_LEN); 1462 if (ret) 1463 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", 1464 i, ret); 1465 return ret; 1466 } 1467 1468 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1469 enum transcoder cpu_transcoder) 1470 { 1471 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1472 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1473 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1474 u32 scanline; 1475 int ret; 1476 1477 for (;;) { 1478 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe)); 1479 if (scanline > 100 && scanline < 200) 1480 break; 1481 usleep_range(25, 50); 1482 } 1483 1484 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1485 false, TRANS_DDI_HDCP_SIGNALLING); 1486 if (ret) { 1487 drm_err(&dev_priv->drm, 1488 "Disable HDCP signalling failed (%d)\n", ret); 1489 return ret; 1490 } 1491 1492 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1493 true, TRANS_DDI_HDCP_SIGNALLING); 1494 if (ret) { 1495 drm_err(&dev_priv->drm, 1496 "Enable HDCP signalling failed (%d)\n", ret); 1497 return ret; 1498 } 1499 1500 return 0; 1501 } 1502 1503 static 1504 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1505 enum transcoder cpu_transcoder, 1506 bool enable) 1507 { 1508 struct intel_hdmi *hdmi = &dig_port->hdmi; 1509 struct intel_connector *connector = hdmi->attached_connector; 1510 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1511 int ret; 1512 1513 if (!enable) 1514 usleep_range(6, 60); /* Bspec says >= 6us */ 1515 1516 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1517 cpu_transcoder, enable, 1518 TRANS_DDI_HDCP_SIGNALLING); 1519 if (ret) { 1520 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", 1521 enable ? "Enable" : "Disable", ret); 1522 return ret; 1523 } 1524 1525 /* 1526 * WA: To fix incorrect positioning of the window of 1527 * opportunity and enc_en signalling in KABYLAKE. 1528 */ 1529 if (IS_KABYLAKE(dev_priv) && enable) 1530 return kbl_repositioning_enc_en_signal(connector, 1531 cpu_transcoder); 1532 1533 return 0; 1534 } 1535 1536 static 1537 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1538 struct intel_connector *connector) 1539 { 1540 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1541 enum port port = dig_port->base.port; 1542 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1543 int ret; 1544 union { 1545 u32 reg; 1546 u8 shim[DRM_HDCP_RI_LEN]; 1547 } ri; 1548 1549 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1550 if (ret) 1551 return false; 1552 1553 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1554 1555 /* Wait for Ri prime match */ 1556 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1557 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1558 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1559 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", 1560 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1561 port))); 1562 return false; 1563 } 1564 return true; 1565 } 1566 1567 static 1568 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1569 struct intel_connector *connector) 1570 { 1571 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1572 int retry; 1573 1574 for (retry = 0; retry < 3; retry++) 1575 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1576 return true; 1577 1578 drm_err(&i915->drm, "Link check failed\n"); 1579 return false; 1580 } 1581 1582 struct hdcp2_hdmi_msg_timeout { 1583 u8 msg_id; 1584 u16 timeout; 1585 }; 1586 1587 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1588 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1589 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1590 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1591 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1592 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1593 }; 1594 1595 static 1596 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1597 u8 *rx_status) 1598 { 1599 return intel_hdmi_hdcp_read(dig_port, 1600 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1601 rx_status, 1602 HDCP_2_2_HDMI_RXSTATUS_LEN); 1603 } 1604 1605 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1606 { 1607 int i; 1608 1609 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1610 if (is_paired) 1611 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1612 else 1613 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1614 } 1615 1616 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1617 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1618 return hdcp2_msg_timeout[i].timeout; 1619 } 1620 1621 return -EINVAL; 1622 } 1623 1624 static int 1625 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1626 u8 msg_id, bool *msg_ready, 1627 ssize_t *msg_sz) 1628 { 1629 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1630 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1631 int ret; 1632 1633 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1634 if (ret < 0) { 1635 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", 1636 ret); 1637 return ret; 1638 } 1639 1640 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1641 rx_status[0]); 1642 1643 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1644 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1645 *msg_sz); 1646 else 1647 *msg_ready = *msg_sz; 1648 1649 return 0; 1650 } 1651 1652 static ssize_t 1653 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1654 u8 msg_id, bool paired) 1655 { 1656 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1657 bool msg_ready = false; 1658 int timeout, ret; 1659 ssize_t msg_sz = 0; 1660 1661 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1662 if (timeout < 0) 1663 return timeout; 1664 1665 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1666 msg_id, &msg_ready, 1667 &msg_sz), 1668 !ret && msg_ready && msg_sz, timeout * 1000, 1669 1000, 5 * 1000); 1670 if (ret) 1671 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", 1672 msg_id, ret, timeout); 1673 1674 return ret ? ret : msg_sz; 1675 } 1676 1677 static 1678 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, 1679 void *buf, size_t size) 1680 { 1681 unsigned int offset; 1682 1683 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1684 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1685 } 1686 1687 static 1688 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, 1689 u8 msg_id, void *buf, size_t size) 1690 { 1691 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1692 struct intel_hdmi *hdmi = &dig_port->hdmi; 1693 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1694 unsigned int offset; 1695 ssize_t ret; 1696 1697 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1698 hdcp->is_paired); 1699 if (ret < 0) 1700 return ret; 1701 1702 /* 1703 * Available msg size should be equal to or lesser than the 1704 * available buffer. 1705 */ 1706 if (ret > size) { 1707 drm_dbg_kms(&i915->drm, 1708 "msg_sz(%zd) is more than exp size(%zu)\n", 1709 ret, size); 1710 return -EINVAL; 1711 } 1712 1713 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1714 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1715 if (ret) 1716 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", 1717 msg_id, ret); 1718 1719 return ret; 1720 } 1721 1722 static 1723 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1724 struct intel_connector *connector) 1725 { 1726 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1727 int ret; 1728 1729 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1730 if (ret) 1731 return ret; 1732 1733 /* 1734 * Re-auth request and Link Integrity Failures are represented by 1735 * same bit. i.e reauth_req. 1736 */ 1737 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1738 ret = HDCP_REAUTH_REQUEST; 1739 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1740 ret = HDCP_TOPOLOGY_CHANGE; 1741 1742 return ret; 1743 } 1744 1745 static 1746 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, 1747 bool *capable) 1748 { 1749 u8 hdcp2_version; 1750 int ret; 1751 1752 *capable = false; 1753 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1754 &hdcp2_version, sizeof(hdcp2_version)); 1755 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1756 *capable = true; 1757 1758 return ret; 1759 } 1760 1761 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1762 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1763 .read_bksv = intel_hdmi_hdcp_read_bksv, 1764 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1765 .repeater_present = intel_hdmi_hdcp_repeater_present, 1766 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1767 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1768 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1769 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1770 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1771 .check_link = intel_hdmi_hdcp_check_link, 1772 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1773 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1774 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1775 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1776 .protocol = HDCP_PROTOCOL_HDMI, 1777 }; 1778 1779 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1780 { 1781 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1782 int max_tmds_clock, vbt_max_tmds_clock; 1783 1784 if (DISPLAY_VER(dev_priv) >= 10) 1785 max_tmds_clock = 594000; 1786 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 1787 max_tmds_clock = 300000; 1788 else if (DISPLAY_VER(dev_priv) >= 5) 1789 max_tmds_clock = 225000; 1790 else 1791 max_tmds_clock = 165000; 1792 1793 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); 1794 if (vbt_max_tmds_clock) 1795 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1796 1797 return max_tmds_clock; 1798 } 1799 1800 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1801 const struct drm_connector_state *conn_state) 1802 { 1803 return hdmi->has_hdmi_sink && 1804 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1805 } 1806 1807 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1808 { 1809 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1810 } 1811 1812 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1813 bool respect_downstream_limits, 1814 bool has_hdmi_sink) 1815 { 1816 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1817 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1818 1819 if (respect_downstream_limits) { 1820 struct intel_connector *connector = hdmi->attached_connector; 1821 const struct drm_display_info *info = &connector->base.display_info; 1822 1823 if (hdmi->dp_dual_mode.max_tmds_clock) 1824 max_tmds_clock = min(max_tmds_clock, 1825 hdmi->dp_dual_mode.max_tmds_clock); 1826 1827 if (info->max_tmds_clock) 1828 max_tmds_clock = min(max_tmds_clock, 1829 info->max_tmds_clock); 1830 else if (!has_hdmi_sink) 1831 max_tmds_clock = min(max_tmds_clock, 165000); 1832 } 1833 1834 return max_tmds_clock; 1835 } 1836 1837 static enum drm_mode_status 1838 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1839 int clock, bool respect_downstream_limits, 1840 bool has_hdmi_sink) 1841 { 1842 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1843 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port); 1844 1845 if (clock < 25000) 1846 return MODE_CLOCK_LOW; 1847 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1848 has_hdmi_sink)) 1849 return MODE_CLOCK_HIGH; 1850 1851 /* GLK DPLL can't generate 446-480 MHz */ 1852 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1853 return MODE_CLOCK_RANGE; 1854 1855 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1856 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1857 clock > 223333 && clock < 240000) 1858 return MODE_CLOCK_RANGE; 1859 1860 /* CHV DPLL can't generate 216-240 MHz */ 1861 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1862 return MODE_CLOCK_RANGE; 1863 1864 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1865 if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200) 1866 return MODE_CLOCK_RANGE; 1867 1868 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1869 if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800) 1870 return MODE_CLOCK_RANGE; 1871 1872 /* 1873 * SNPS PHYs' MPLLB table-based programming can only handle a fixed 1874 * set of link rates. 1875 * 1876 * FIXME: We will hopefully get an algorithmic way of programming 1877 * the MPLLB for HDMI in the future. 1878 */ 1879 if (IS_DG2(dev_priv)) 1880 return intel_snps_phy_check_hdmi_link_rate(clock); 1881 1882 return MODE_OK; 1883 } 1884 1885 int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output) 1886 { 1887 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1888 if (ycbcr420_output) 1889 clock /= 2; 1890 1891 /* 1892 * Need to adjust the port link by: 1893 * 1.5x for 12bpc 1894 * 1.25x for 10bpc 1895 */ 1896 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1897 } 1898 1899 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc) 1900 { 1901 switch (bpc) { 1902 case 12: 1903 return !HAS_GMCH(i915); 1904 case 10: 1905 return DISPLAY_VER(i915) >= 11; 1906 case 8: 1907 return true; 1908 default: 1909 MISSING_CASE(bpc); 1910 return false; 1911 } 1912 } 1913 1914 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, 1915 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 1916 { 1917 const struct drm_display_info *info = &connector->display_info; 1918 const struct drm_hdmi_info *hdmi = &info->hdmi; 1919 1920 switch (bpc) { 1921 case 12: 1922 if (!has_hdmi_sink) 1923 return false; 1924 1925 if (ycbcr420_output) 1926 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1927 else 1928 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1929 case 10: 1930 if (!has_hdmi_sink) 1931 return false; 1932 1933 if (ycbcr420_output) 1934 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1935 else 1936 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1937 case 8: 1938 return true; 1939 default: 1940 MISSING_CASE(bpc); 1941 return false; 1942 } 1943 } 1944 1945 static enum drm_mode_status 1946 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, 1947 bool has_hdmi_sink, bool ycbcr420_output) 1948 { 1949 struct drm_i915_private *i915 = to_i915(connector->dev); 1950 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1951 enum drm_mode_status status = MODE_OK; 1952 int bpc; 1953 1954 /* 1955 * Try all color depths since valid port clock range 1956 * can have holes. Any mode that can be used with at 1957 * least one color depth is accepted. 1958 */ 1959 for (bpc = 12; bpc >= 8; bpc -= 2) { 1960 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output); 1961 1962 if (!intel_hdmi_source_bpc_possible(i915, bpc)) 1963 continue; 1964 1965 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output)) 1966 continue; 1967 1968 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 1969 if (status == MODE_OK) 1970 return MODE_OK; 1971 } 1972 1973 /* can never happen */ 1974 drm_WARN_ON(&i915->drm, status == MODE_OK); 1975 1976 return status; 1977 } 1978 1979 static enum drm_mode_status 1980 intel_hdmi_mode_valid(struct drm_connector *connector, 1981 struct drm_display_mode *mode) 1982 { 1983 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1984 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1985 enum drm_mode_status status; 1986 int clock = mode->clock; 1987 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1988 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 1989 bool ycbcr_420_only; 1990 1991 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1992 return MODE_NO_DBLESCAN; 1993 1994 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1995 clock *= 2; 1996 1997 if (clock > max_dotclk) 1998 return MODE_CLOCK_HIGH; 1999 2000 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2001 if (!has_hdmi_sink) 2002 return MODE_CLOCK_LOW; 2003 clock *= 2; 2004 } 2005 2006 /* 2007 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2008 * enumerated only if FRL is supported. Current platforms do not support 2009 * FRL so prune the higher resolution modes that require doctclock more 2010 * than 600MHz. 2011 */ 2012 if (clock > 600000) 2013 return MODE_CLOCK_HIGH; 2014 2015 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 2016 2017 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only); 2018 if (status != MODE_OK) { 2019 if (ycbcr_420_only || 2020 !connector->ycbcr_420_allowed || 2021 !drm_mode_is_420_also(&connector->display_info, mode)) 2022 return status; 2023 2024 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true); 2025 if (status != MODE_OK) 2026 return status; 2027 } 2028 2029 return intel_mode_valid_max_plane_size(dev_priv, mode, false); 2030 } 2031 2032 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2033 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 2034 { 2035 struct drm_atomic_state *state = crtc_state->uapi.state; 2036 struct drm_connector_state *connector_state; 2037 struct drm_connector *connector; 2038 int i; 2039 2040 for_each_new_connector_in_state(state, connector, connector_state, i) { 2041 if (connector_state->crtc != crtc_state->uapi.crtc) 2042 continue; 2043 2044 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output)) 2045 return false; 2046 } 2047 2048 return true; 2049 } 2050 2051 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2052 { 2053 struct drm_i915_private *dev_priv = 2054 to_i915(crtc_state->uapi.crtc->dev); 2055 const struct drm_display_mode *adjusted_mode = 2056 &crtc_state->hw.adjusted_mode; 2057 2058 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc)) 2059 return false; 2060 2061 /* Display Wa_1405510057:icl,ehl */ 2062 if (intel_hdmi_is_ycbcr420(crtc_state) && 2063 bpc == 10 && DISPLAY_VER(dev_priv) == 11 && 2064 (adjusted_mode->crtc_hblank_end - 2065 adjusted_mode->crtc_hblank_start) % 8 == 2) 2066 return false; 2067 2068 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink, 2069 intel_hdmi_is_ycbcr420(crtc_state)); 2070 } 2071 2072 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2073 struct intel_crtc_state *crtc_state, 2074 int clock, bool respect_downstream_limits) 2075 { 2076 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2077 bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state); 2078 int bpc; 2079 2080 /* 2081 * pipe_bpp could already be below 8bpc due to FDI 2082 * bandwidth constraints. HDMI minimum is 8bpc however. 2083 */ 2084 bpc = max(crtc_state->pipe_bpp / 3, 8); 2085 2086 /* 2087 * We will never exceed downstream TMDS clock limits while 2088 * attempting deep color. If the user insists on forcing an 2089 * out of spec mode they will have to be satisfied with 8bpc. 2090 */ 2091 if (!respect_downstream_limits) 2092 bpc = 8; 2093 2094 for (; bpc >= 8; bpc -= 2) { 2095 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output); 2096 2097 if (hdmi_bpc_possible(crtc_state, bpc) && 2098 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2099 respect_downstream_limits, 2100 crtc_state->has_hdmi_sink) == MODE_OK) 2101 return bpc; 2102 } 2103 2104 return -EINVAL; 2105 } 2106 2107 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2108 struct intel_crtc_state *crtc_state, 2109 bool respect_downstream_limits) 2110 { 2111 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2112 const struct drm_display_mode *adjusted_mode = 2113 &crtc_state->hw.adjusted_mode; 2114 int bpc, clock = adjusted_mode->crtc_clock; 2115 2116 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2117 clock *= 2; 2118 2119 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2120 respect_downstream_limits); 2121 if (bpc < 0) 2122 return bpc; 2123 2124 crtc_state->port_clock = 2125 intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state)); 2126 2127 /* 2128 * pipe_bpp could already be below 8bpc due to 2129 * FDI bandwidth constraints. We shouldn't bump it 2130 * back up to the HDMI minimum 8bpc in that case. 2131 */ 2132 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2133 2134 drm_dbg_kms(&i915->drm, 2135 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2136 bpc, crtc_state->pipe_bpp); 2137 2138 return 0; 2139 } 2140 2141 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2142 const struct drm_connector_state *conn_state) 2143 { 2144 const struct intel_digital_connector_state *intel_conn_state = 2145 to_intel_digital_connector_state(conn_state); 2146 const struct drm_display_mode *adjusted_mode = 2147 &crtc_state->hw.adjusted_mode; 2148 2149 /* 2150 * Our YCbCr output is always limited range. 2151 * crtc_state->limited_color_range only applies to RGB, 2152 * and it must never be set for YCbCr or we risk setting 2153 * some conflicting bits in PIPECONF which will mess up 2154 * the colors on the monitor. 2155 */ 2156 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2157 return false; 2158 2159 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2160 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2161 return crtc_state->has_hdmi_sink && 2162 drm_default_rgb_quant_range(adjusted_mode) == 2163 HDMI_QUANTIZATION_RANGE_LIMITED; 2164 } else { 2165 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2166 } 2167 } 2168 2169 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2170 const struct intel_crtc_state *crtc_state, 2171 const struct drm_connector_state *conn_state) 2172 { 2173 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2174 const struct intel_digital_connector_state *intel_conn_state = 2175 to_intel_digital_connector_state(conn_state); 2176 2177 if (!crtc_state->has_hdmi_sink) 2178 return false; 2179 2180 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2181 return intel_hdmi->has_audio; 2182 else 2183 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2184 } 2185 2186 static enum intel_output_format 2187 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state, 2188 struct intel_connector *connector, 2189 bool ycbcr_420_output) 2190 { 2191 if (!crtc_state->has_hdmi_sink) 2192 return INTEL_OUTPUT_FORMAT_RGB; 2193 2194 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2195 return INTEL_OUTPUT_FORMAT_YCBCR420; 2196 else 2197 return INTEL_OUTPUT_FORMAT_RGB; 2198 } 2199 2200 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2201 struct intel_crtc_state *crtc_state, 2202 const struct drm_connector_state *conn_state, 2203 bool respect_downstream_limits) 2204 { 2205 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2206 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2207 const struct drm_display_info *info = &connector->base.display_info; 2208 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2209 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2210 int ret; 2211 2212 crtc_state->output_format = 2213 intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only); 2214 2215 if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) { 2216 drm_dbg_kms(&i915->drm, 2217 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2218 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 2219 } 2220 2221 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2222 if (ret) { 2223 if (intel_hdmi_is_ycbcr420(crtc_state) || 2224 !connector->base.ycbcr_420_allowed || 2225 !drm_mode_is_420_also(info, adjusted_mode)) 2226 return ret; 2227 2228 crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true); 2229 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2230 } 2231 2232 return ret; 2233 } 2234 2235 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2236 { 2237 return crtc_state->uapi.encoder_mask && 2238 !is_power_of_2(crtc_state->uapi.encoder_mask); 2239 } 2240 2241 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2242 struct intel_crtc_state *pipe_config, 2243 struct drm_connector_state *conn_state) 2244 { 2245 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2246 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2247 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2248 struct drm_connector *connector = conn_state->connector; 2249 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2250 int ret; 2251 2252 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2253 return -EINVAL; 2254 2255 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2256 pipe_config->has_hdmi_sink = 2257 intel_has_hdmi_sink(intel_hdmi, conn_state) && 2258 !intel_hdmi_is_cloned(pipe_config); 2259 2260 if (pipe_config->has_hdmi_sink) 2261 pipe_config->has_infoframe = true; 2262 2263 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2264 pipe_config->pixel_multiplier = 2; 2265 2266 pipe_config->has_audio = 2267 intel_hdmi_has_audio(encoder, pipe_config, conn_state); 2268 2269 /* 2270 * Try to respect downstream TMDS clock limits first, if 2271 * that fails assume the user might know something we don't. 2272 */ 2273 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2274 if (ret) 2275 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2276 if (ret) { 2277 drm_dbg_kms(&dev_priv->drm, 2278 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2279 pipe_config->hw.adjusted_mode.crtc_clock); 2280 return ret; 2281 } 2282 2283 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2284 ret = intel_panel_fitting(pipe_config, conn_state); 2285 if (ret) 2286 return ret; 2287 } 2288 2289 pipe_config->limited_color_range = 2290 intel_hdmi_limited_color_range(pipe_config, conn_state); 2291 2292 if (conn_state->picture_aspect_ratio) 2293 adjusted_mode->picture_aspect_ratio = 2294 conn_state->picture_aspect_ratio; 2295 2296 pipe_config->lane_count = 4; 2297 2298 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) { 2299 if (scdc->scrambling.low_rates) 2300 pipe_config->hdmi_scrambling = true; 2301 2302 if (pipe_config->port_clock > 340000) { 2303 pipe_config->hdmi_scrambling = true; 2304 pipe_config->hdmi_high_tmds_clock_ratio = true; 2305 } 2306 } 2307 2308 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2309 conn_state); 2310 2311 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2312 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); 2313 return -EINVAL; 2314 } 2315 2316 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2317 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); 2318 return -EINVAL; 2319 } 2320 2321 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2322 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); 2323 return -EINVAL; 2324 } 2325 2326 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2327 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); 2328 return -EINVAL; 2329 } 2330 2331 return 0; 2332 } 2333 2334 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2335 { 2336 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2337 2338 /* 2339 * Give a hand to buggy BIOSen which forget to turn 2340 * the TMDS output buffers back on after a reboot. 2341 */ 2342 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2343 } 2344 2345 static void 2346 intel_hdmi_unset_edid(struct drm_connector *connector) 2347 { 2348 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2349 2350 intel_hdmi->has_hdmi_sink = false; 2351 intel_hdmi->has_audio = false; 2352 2353 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2354 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2355 2356 kfree(to_intel_connector(connector)->detect_edid); 2357 to_intel_connector(connector)->detect_edid = NULL; 2358 } 2359 2360 static void 2361 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) 2362 { 2363 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2364 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2365 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2366 struct i2c_adapter *adapter = 2367 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2368 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter); 2369 2370 /* 2371 * Type 1 DVI adaptors are not required to implement any 2372 * registers, so we can't always detect their presence. 2373 * Ideally we should be able to check the state of the 2374 * CONFIG1 pin, but no such luck on our hardware. 2375 * 2376 * The only method left to us is to check the VBT to see 2377 * if the port is a dual mode capable DP port. 2378 */ 2379 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2380 if (!connector->force && 2381 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2382 drm_dbg_kms(&dev_priv->drm, 2383 "Assuming DP dual mode adaptor presence based on VBT\n"); 2384 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2385 } else { 2386 type = DRM_DP_DUAL_MODE_NONE; 2387 } 2388 } 2389 2390 if (type == DRM_DP_DUAL_MODE_NONE) 2391 return; 2392 2393 hdmi->dp_dual_mode.type = type; 2394 hdmi->dp_dual_mode.max_tmds_clock = 2395 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter); 2396 2397 drm_dbg_kms(&dev_priv->drm, 2398 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2399 drm_dp_get_dual_mode_type_name(type), 2400 hdmi->dp_dual_mode.max_tmds_clock); 2401 2402 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2403 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) && 2404 !intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2405 drm_dbg_kms(&dev_priv->drm, 2406 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2407 hdmi->dp_dual_mode.max_tmds_clock = 0; 2408 } 2409 } 2410 2411 static bool 2412 intel_hdmi_set_edid(struct drm_connector *connector) 2413 { 2414 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2415 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2416 intel_wakeref_t wakeref; 2417 struct edid *edid; 2418 bool connected = false; 2419 struct i2c_adapter *i2c; 2420 2421 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2422 2423 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2424 2425 edid = drm_get_edid(connector, i2c); 2426 2427 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2428 drm_dbg_kms(&dev_priv->drm, 2429 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2430 intel_gmbus_force_bit(i2c, true); 2431 edid = drm_get_edid(connector, i2c); 2432 intel_gmbus_force_bit(i2c, false); 2433 } 2434 2435 to_intel_connector(connector)->detect_edid = edid; 2436 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2437 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2438 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2439 2440 intel_hdmi_dp_dual_mode_detect(connector); 2441 2442 connected = true; 2443 } 2444 2445 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2446 2447 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2448 2449 return connected; 2450 } 2451 2452 static enum drm_connector_status 2453 intel_hdmi_detect(struct drm_connector *connector, bool force) 2454 { 2455 enum drm_connector_status status = connector_status_disconnected; 2456 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2457 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2458 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2459 intel_wakeref_t wakeref; 2460 2461 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2462 connector->base.id, connector->name); 2463 2464 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 2465 return connector_status_disconnected; 2466 2467 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2468 2469 if (DISPLAY_VER(dev_priv) >= 11 && 2470 !intel_digital_port_connected(encoder)) 2471 goto out; 2472 2473 intel_hdmi_unset_edid(connector); 2474 2475 if (intel_hdmi_set_edid(connector)) 2476 status = connector_status_connected; 2477 2478 out: 2479 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2480 2481 if (status != connector_status_connected) 2482 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2483 2484 /* 2485 * Make sure the refs for power wells enabled during detect are 2486 * dropped to avoid a new detect cycle triggered by HPD polling. 2487 */ 2488 intel_display_power_flush_work(dev_priv); 2489 2490 return status; 2491 } 2492 2493 static void 2494 intel_hdmi_force(struct drm_connector *connector) 2495 { 2496 struct drm_i915_private *i915 = to_i915(connector->dev); 2497 2498 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2499 connector->base.id, connector->name); 2500 2501 intel_hdmi_unset_edid(connector); 2502 2503 if (connector->status != connector_status_connected) 2504 return; 2505 2506 intel_hdmi_set_edid(connector); 2507 } 2508 2509 static int intel_hdmi_get_modes(struct drm_connector *connector) 2510 { 2511 struct edid *edid; 2512 2513 edid = to_intel_connector(connector)->detect_edid; 2514 if (edid == NULL) 2515 return 0; 2516 2517 return intel_connector_update_modes(connector, edid); 2518 } 2519 2520 static struct i2c_adapter * 2521 intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2522 { 2523 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2524 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2525 2526 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2527 } 2528 2529 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2530 { 2531 struct drm_i915_private *i915 = to_i915(connector->dev); 2532 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2533 struct kobject *i2c_kobj = &adapter->dev.kobj; 2534 struct kobject *connector_kobj = &connector->kdev->kobj; 2535 int ret; 2536 2537 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2538 if (ret) 2539 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret); 2540 } 2541 2542 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2543 { 2544 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2545 struct kobject *i2c_kobj = &adapter->dev.kobj; 2546 struct kobject *connector_kobj = &connector->kdev->kobj; 2547 2548 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2549 } 2550 2551 static int 2552 intel_hdmi_connector_register(struct drm_connector *connector) 2553 { 2554 int ret; 2555 2556 ret = intel_connector_register(connector); 2557 if (ret) 2558 return ret; 2559 2560 intel_hdmi_create_i2c_symlink(connector); 2561 2562 return ret; 2563 } 2564 2565 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2566 { 2567 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2568 2569 cec_notifier_conn_unregister(n); 2570 2571 intel_hdmi_remove_i2c_symlink(connector); 2572 intel_connector_unregister(connector); 2573 } 2574 2575 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2576 .detect = intel_hdmi_detect, 2577 .force = intel_hdmi_force, 2578 .fill_modes = drm_helper_probe_single_connector_modes, 2579 .atomic_get_property = intel_digital_connector_atomic_get_property, 2580 .atomic_set_property = intel_digital_connector_atomic_set_property, 2581 .late_register = intel_hdmi_connector_register, 2582 .early_unregister = intel_hdmi_connector_unregister, 2583 .destroy = intel_connector_destroy, 2584 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2585 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2586 }; 2587 2588 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2589 .get_modes = intel_hdmi_get_modes, 2590 .mode_valid = intel_hdmi_mode_valid, 2591 .atomic_check = intel_digital_connector_atomic_check, 2592 }; 2593 2594 static void 2595 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2596 { 2597 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2598 2599 intel_attach_force_audio_property(connector); 2600 intel_attach_broadcast_rgb_property(connector); 2601 intel_attach_aspect_ratio_property(connector); 2602 2603 intel_attach_hdmi_colorspace_property(connector); 2604 drm_connector_attach_content_type_property(connector); 2605 2606 if (DISPLAY_VER(dev_priv) >= 10) 2607 drm_connector_attach_hdr_output_metadata_property(connector); 2608 2609 if (!HAS_GMCH(dev_priv)) 2610 drm_connector_attach_max_bpc_property(connector, 8, 12); 2611 } 2612 2613 /* 2614 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2615 * @encoder: intel_encoder 2616 * @connector: drm_connector 2617 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2618 * or reset the high tmds clock ratio for scrambling 2619 * @scrambling: bool to Indicate if the function needs to set or reset 2620 * sink scrambling 2621 * 2622 * This function handles scrambling on HDMI 2.0 capable sinks. 2623 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2624 * it enables scrambling. This should be called before enabling the HDMI 2625 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2626 * detect a scrambled clock within 100 ms. 2627 * 2628 * Returns: 2629 * True on success, false on failure. 2630 */ 2631 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2632 struct drm_connector *connector, 2633 bool high_tmds_clock_ratio, 2634 bool scrambling) 2635 { 2636 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2637 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2638 struct drm_scrambling *sink_scrambling = 2639 &connector->display_info.hdmi.scdc.scrambling; 2640 struct i2c_adapter *adapter = 2641 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2642 2643 if (!sink_scrambling->supported) 2644 return true; 2645 2646 drm_dbg_kms(&dev_priv->drm, 2647 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2648 connector->base.id, connector->name, 2649 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2650 2651 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2652 return drm_scdc_set_high_tmds_clock_ratio(adapter, 2653 high_tmds_clock_ratio) && 2654 drm_scdc_set_scrambling(adapter, scrambling); 2655 } 2656 2657 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2658 { 2659 u8 ddc_pin; 2660 2661 switch (port) { 2662 case PORT_B: 2663 ddc_pin = GMBUS_PIN_DPB; 2664 break; 2665 case PORT_C: 2666 ddc_pin = GMBUS_PIN_DPC; 2667 break; 2668 case PORT_D: 2669 ddc_pin = GMBUS_PIN_DPD_CHV; 2670 break; 2671 default: 2672 MISSING_CASE(port); 2673 ddc_pin = GMBUS_PIN_DPB; 2674 break; 2675 } 2676 return ddc_pin; 2677 } 2678 2679 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2680 { 2681 u8 ddc_pin; 2682 2683 switch (port) { 2684 case PORT_B: 2685 ddc_pin = GMBUS_PIN_1_BXT; 2686 break; 2687 case PORT_C: 2688 ddc_pin = GMBUS_PIN_2_BXT; 2689 break; 2690 default: 2691 MISSING_CASE(port); 2692 ddc_pin = GMBUS_PIN_1_BXT; 2693 break; 2694 } 2695 return ddc_pin; 2696 } 2697 2698 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2699 enum port port) 2700 { 2701 u8 ddc_pin; 2702 2703 switch (port) { 2704 case PORT_B: 2705 ddc_pin = GMBUS_PIN_1_BXT; 2706 break; 2707 case PORT_C: 2708 ddc_pin = GMBUS_PIN_2_BXT; 2709 break; 2710 case PORT_D: 2711 ddc_pin = GMBUS_PIN_4_CNP; 2712 break; 2713 case PORT_F: 2714 ddc_pin = GMBUS_PIN_3_BXT; 2715 break; 2716 default: 2717 MISSING_CASE(port); 2718 ddc_pin = GMBUS_PIN_1_BXT; 2719 break; 2720 } 2721 return ddc_pin; 2722 } 2723 2724 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2725 { 2726 enum phy phy = intel_port_to_phy(dev_priv, port); 2727 2728 if (intel_phy_is_combo(dev_priv, phy)) 2729 return GMBUS_PIN_1_BXT + port; 2730 else if (intel_phy_is_tc(dev_priv, phy)) 2731 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 2732 2733 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 2734 return GMBUS_PIN_2_BXT; 2735 } 2736 2737 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2738 { 2739 enum phy phy = intel_port_to_phy(dev_priv, port); 2740 u8 ddc_pin; 2741 2742 switch (phy) { 2743 case PHY_A: 2744 ddc_pin = GMBUS_PIN_1_BXT; 2745 break; 2746 case PHY_B: 2747 ddc_pin = GMBUS_PIN_2_BXT; 2748 break; 2749 case PHY_C: 2750 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2751 break; 2752 default: 2753 MISSING_CASE(phy); 2754 ddc_pin = GMBUS_PIN_1_BXT; 2755 break; 2756 } 2757 return ddc_pin; 2758 } 2759 2760 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2761 { 2762 enum phy phy = intel_port_to_phy(dev_priv, port); 2763 2764 WARN_ON(port == PORT_C); 2765 2766 /* 2767 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2768 * final two outputs use type-c pins, even though they're actually 2769 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2770 * all outputs. 2771 */ 2772 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2773 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2774 2775 return GMBUS_PIN_1_BXT + phy; 2776 } 2777 2778 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) 2779 { 2780 enum phy phy = intel_port_to_phy(i915, port); 2781 2782 drm_WARN_ON(&i915->drm, port == PORT_A); 2783 2784 /* 2785 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2786 * final two outputs use type-c pins, even though they're actually 2787 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2788 * all outputs. 2789 */ 2790 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2791 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2792 2793 return GMBUS_PIN_1_BXT + phy; 2794 } 2795 2796 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2797 { 2798 return intel_port_to_phy(dev_priv, port) + 1; 2799 } 2800 2801 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2802 { 2803 enum phy phy = intel_port_to_phy(dev_priv, port); 2804 2805 WARN_ON(port == PORT_B || port == PORT_C); 2806 2807 /* 2808 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2809 * except first combo output. 2810 */ 2811 if (phy == PHY_A) 2812 return GMBUS_PIN_1_BXT; 2813 2814 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2815 } 2816 2817 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2818 enum port port) 2819 { 2820 u8 ddc_pin; 2821 2822 switch (port) { 2823 case PORT_B: 2824 ddc_pin = GMBUS_PIN_DPB; 2825 break; 2826 case PORT_C: 2827 ddc_pin = GMBUS_PIN_DPC; 2828 break; 2829 case PORT_D: 2830 ddc_pin = GMBUS_PIN_DPD; 2831 break; 2832 default: 2833 MISSING_CASE(port); 2834 ddc_pin = GMBUS_PIN_DPB; 2835 break; 2836 } 2837 return ddc_pin; 2838 } 2839 2840 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2841 { 2842 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2843 enum port port = encoder->port; 2844 u8 ddc_pin; 2845 2846 ddc_pin = intel_bios_alternate_ddc_pin(encoder); 2847 if (ddc_pin) { 2848 drm_dbg_kms(&dev_priv->drm, 2849 "Using DDC pin 0x%x for port %c (VBT)\n", 2850 ddc_pin, port_name(port)); 2851 return ddc_pin; 2852 } 2853 2854 if (IS_ALDERLAKE_S(dev_priv)) 2855 ddc_pin = adls_port_to_ddc_pin(dev_priv, port); 2856 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2857 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); 2858 else if (IS_ROCKETLAKE(dev_priv)) 2859 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); 2860 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv)) 2861 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port); 2862 else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv)) 2863 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 2864 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2865 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 2866 else if (HAS_PCH_CNP(dev_priv)) 2867 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 2868 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2869 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 2870 else if (IS_CHERRYVIEW(dev_priv)) 2871 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 2872 else 2873 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 2874 2875 drm_dbg_kms(&dev_priv->drm, 2876 "Using DDC pin 0x%x for port %c (platform default)\n", 2877 ddc_pin, port_name(port)); 2878 2879 return ddc_pin; 2880 } 2881 2882 void intel_infoframe_init(struct intel_digital_port *dig_port) 2883 { 2884 struct drm_i915_private *dev_priv = 2885 to_i915(dig_port->base.base.dev); 2886 2887 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2888 dig_port->write_infoframe = vlv_write_infoframe; 2889 dig_port->read_infoframe = vlv_read_infoframe; 2890 dig_port->set_infoframes = vlv_set_infoframes; 2891 dig_port->infoframes_enabled = vlv_infoframes_enabled; 2892 } else if (IS_G4X(dev_priv)) { 2893 dig_port->write_infoframe = g4x_write_infoframe; 2894 dig_port->read_infoframe = g4x_read_infoframe; 2895 dig_port->set_infoframes = g4x_set_infoframes; 2896 dig_port->infoframes_enabled = g4x_infoframes_enabled; 2897 } else if (HAS_DDI(dev_priv)) { 2898 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) { 2899 dig_port->write_infoframe = lspcon_write_infoframe; 2900 dig_port->read_infoframe = lspcon_read_infoframe; 2901 dig_port->set_infoframes = lspcon_set_infoframes; 2902 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 2903 } else { 2904 dig_port->write_infoframe = hsw_write_infoframe; 2905 dig_port->read_infoframe = hsw_read_infoframe; 2906 dig_port->set_infoframes = hsw_set_infoframes; 2907 dig_port->infoframes_enabled = hsw_infoframes_enabled; 2908 } 2909 } else if (HAS_PCH_IBX(dev_priv)) { 2910 dig_port->write_infoframe = ibx_write_infoframe; 2911 dig_port->read_infoframe = ibx_read_infoframe; 2912 dig_port->set_infoframes = ibx_set_infoframes; 2913 dig_port->infoframes_enabled = ibx_infoframes_enabled; 2914 } else { 2915 dig_port->write_infoframe = cpt_write_infoframe; 2916 dig_port->read_infoframe = cpt_read_infoframe; 2917 dig_port->set_infoframes = cpt_set_infoframes; 2918 dig_port->infoframes_enabled = cpt_infoframes_enabled; 2919 } 2920 } 2921 2922 void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 2923 struct intel_connector *intel_connector) 2924 { 2925 struct drm_connector *connector = &intel_connector->base; 2926 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2927 struct intel_encoder *intel_encoder = &dig_port->base; 2928 struct drm_device *dev = intel_encoder->base.dev; 2929 struct drm_i915_private *dev_priv = to_i915(dev); 2930 struct i2c_adapter *ddc; 2931 enum port port = intel_encoder->port; 2932 struct cec_connector_info conn_info; 2933 2934 drm_dbg_kms(&dev_priv->drm, 2935 "Adding HDMI connector on [ENCODER:%d:%s]\n", 2936 intel_encoder->base.base.id, intel_encoder->base.name); 2937 2938 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 2939 return; 2940 2941 if (drm_WARN(dev, dig_port->max_lanes < 4, 2942 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 2943 dig_port->max_lanes, intel_encoder->base.base.id, 2944 intel_encoder->base.name)) 2945 return; 2946 2947 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); 2948 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2949 2950 drm_connector_init_with_ddc(dev, connector, 2951 &intel_hdmi_connector_funcs, 2952 DRM_MODE_CONNECTOR_HDMIA, 2953 ddc); 2954 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 2955 2956 connector->interlace_allowed = true; 2957 connector->stereo_allowed = true; 2958 2959 if (DISPLAY_VER(dev_priv) >= 10) 2960 connector->ycbcr_420_allowed = true; 2961 2962 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2963 2964 if (HAS_DDI(dev_priv)) 2965 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2966 else 2967 intel_connector->get_hw_state = intel_connector_get_hw_state; 2968 2969 intel_hdmi_add_properties(intel_hdmi, connector); 2970 2971 intel_connector_attach_encoder(intel_connector, intel_encoder); 2972 intel_hdmi->attached_connector = intel_connector; 2973 2974 if (is_hdcp_supported(dev_priv, port)) { 2975 int ret = intel_hdcp_init(intel_connector, dig_port, 2976 &intel_hdmi_hdcp_shim); 2977 if (ret) 2978 drm_dbg_kms(&dev_priv->drm, 2979 "HDCP init failed, skipping.\n"); 2980 } 2981 2982 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2983 * 0xd. Failure to do so will result in spurious interrupts being 2984 * generated on the port when a cable is not attached. 2985 */ 2986 if (IS_G45(dev_priv)) { 2987 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 2988 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 2989 (temp & ~0xf) | 0xd); 2990 } 2991 2992 cec_fill_conn_info_from_drm(&conn_info, connector); 2993 2994 intel_hdmi->cec_notifier = 2995 cec_notifier_conn_register(dev->dev, port_identifier(port), 2996 &conn_info); 2997 if (!intel_hdmi->cec_notifier) 2998 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); 2999 } 3000 3001 /* 3002 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3003 * @vactive: Vactive of a display mode 3004 * 3005 * @return: appropriate dsc slice height for a given mode. 3006 */ 3007 int intel_hdmi_dsc_get_slice_height(int vactive) 3008 { 3009 int slice_height; 3010 3011 /* 3012 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3013 * Select smallest slice height >=96, that results in a valid PPS and 3014 * requires minimum padding lines required for final slice. 3015 * 3016 * Assumption : Vactive is even. 3017 */ 3018 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3019 if (vactive % slice_height == 0) 3020 return slice_height; 3021 3022 return 0; 3023 } 3024 3025 /* 3026 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3027 * and dsc decoder capabilities 3028 * 3029 * @crtc_state: intel crtc_state 3030 * @src_max_slices: maximum slices supported by the DSC encoder 3031 * @src_max_slice_width: maximum slice width supported by DSC encoder 3032 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3033 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3034 * 3035 * @return: num of dsc slices that can be supported by the dsc encoder 3036 * and decoder. 3037 */ 3038 int 3039 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3040 int src_max_slices, int src_max_slice_width, 3041 int hdmi_max_slices, int hdmi_throughput) 3042 { 3043 /* Pixel rates in KPixels/sec */ 3044 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3045 /* 3046 * Rates at which the source and sink are required to process pixels in each 3047 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3048 */ 3049 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3050 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3051 3052 /* Spec limits the slice width to 2720 pixels */ 3053 #define MAX_HDMI_SLICE_WIDTH 2720 3054 int kslice_adjust; 3055 int adjusted_clk_khz; 3056 int min_slices; 3057 int target_slices; 3058 int max_throughput; /* max clock freq. in khz per slice */ 3059 int max_slice_width; 3060 int slice_width; 3061 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3062 3063 if (!hdmi_throughput) 3064 return 0; 3065 3066 /* 3067 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3068 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3069 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3070 * dividing adjusted clock value by 10. 3071 */ 3072 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3073 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3074 kslice_adjust = 10; 3075 else 3076 kslice_adjust = 5; 3077 3078 /* 3079 * As per spec, the rate at which the source and the sink process 3080 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3081 * This depends upon the pixel clock rate and output formats 3082 * (kslice adjust). 3083 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3084 * at max 340MHz, otherwise they can be processed at max 400MHz. 3085 */ 3086 3087 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3088 3089 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3090 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3091 else 3092 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3093 3094 /* 3095 * Taking into account the sink's capability for maximum 3096 * clock per slice (in MHz) as read from HF-VSDB. 3097 */ 3098 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3099 3100 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3101 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3102 3103 /* 3104 * Keep on increasing the num of slices/line, starting from min_slices 3105 * per line till we get such a number, for which the slice_width is 3106 * just less than max_slice_width. The slices/line selected should be 3107 * less than or equal to the max horizontal slices that the combination 3108 * of PCON encoder and HDMI decoder can support. 3109 */ 3110 slice_width = max_slice_width; 3111 3112 do { 3113 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3114 target_slices = 1; 3115 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3116 target_slices = 2; 3117 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3118 target_slices = 4; 3119 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3120 target_slices = 8; 3121 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3122 target_slices = 12; 3123 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3124 target_slices = 16; 3125 else 3126 return 0; 3127 3128 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3129 if (slice_width >= max_slice_width) 3130 min_slices = target_slices + 1; 3131 } while (slice_width >= max_slice_width); 3132 3133 return target_slices; 3134 } 3135 3136 /* 3137 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3138 * source and sink capabilities. 3139 * 3140 * @src_fraction_bpp: fractional bpp supported by the source 3141 * @slice_width: dsc slice width supported by the source and sink 3142 * @num_slices: num of slices supported by the source and sink 3143 * @output_format: video output format 3144 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3145 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3146 * 3147 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3148 */ 3149 int 3150 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3151 int output_format, bool hdmi_all_bpp, 3152 int hdmi_max_chunk_bytes) 3153 { 3154 int max_dsc_bpp, min_dsc_bpp; 3155 int target_bytes; 3156 bool bpp_found = false; 3157 int bpp_decrement_x16; 3158 int bpp_target; 3159 int bpp_target_x16; 3160 3161 /* 3162 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3163 * Start with the max bpp and keep on decrementing with 3164 * fractional bpp, if supported by PCON DSC encoder 3165 * 3166 * for each bpp we check if no of bytes can be supported by HDMI sink 3167 */ 3168 3169 /* Assuming: bpc as 8*/ 3170 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3171 min_dsc_bpp = 6; 3172 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3173 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3174 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3175 min_dsc_bpp = 8; 3176 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3177 } else { 3178 /* Assuming 4:2:2 encoding */ 3179 min_dsc_bpp = 7; 3180 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3181 } 3182 3183 /* 3184 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3185 * Section 7.7.34 : Source shall not enable compressed Video 3186 * Transport with bpp_target settings above 12 bpp unless 3187 * DSC_all_bpp is set to 1. 3188 */ 3189 if (!hdmi_all_bpp) 3190 max_dsc_bpp = min(max_dsc_bpp, 12); 3191 3192 /* 3193 * The Sink has a limit of compressed data in bytes for a scanline, 3194 * as described in max_chunk_bytes field in HFVSDB block of edid. 3195 * The no. of bytes depend on the target bits per pixel that the 3196 * source configures. So we start with the max_bpp and calculate 3197 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3198 * till we get the target_chunk_bytes just less than what the sink's 3199 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3200 * 3201 * The decrement is according to the fractional support from PCON DSC 3202 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3203 * 3204 * bpp_target_x16 = bpp_target * 16 3205 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3206 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3207 */ 3208 3209 bpp_target = max_dsc_bpp; 3210 3211 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3212 if (!src_fractional_bpp) 3213 src_fractional_bpp = 1; 3214 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3215 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3216 3217 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3218 int bpp; 3219 3220 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3221 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3222 if (target_bytes <= hdmi_max_chunk_bytes) { 3223 bpp_found = true; 3224 break; 3225 } 3226 bpp_target_x16 -= bpp_decrement_x16; 3227 } 3228 if (bpp_found) 3229 return bpp_target_x16; 3230 3231 return 0; 3232 } 3233