1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_hdcp.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <drm/i915_drm.h> 40 #include <drm/intel_lpe_audio.h> 41 42 #include "i915_debugfs.h" 43 #include "i915_drv.h" 44 #include "intel_atomic.h" 45 #include "intel_audio.h" 46 #include "intel_connector.h" 47 #include "intel_ddi.h" 48 #include "intel_display_debugfs.h" 49 #include "intel_display_types.h" 50 #include "intel_dp.h" 51 #include "intel_dpio_phy.h" 52 #include "intel_fifo_underrun.h" 53 #include "intel_gmbus.h" 54 #include "intel_hdcp.h" 55 #include "intel_hdmi.h" 56 #include "intel_hotplug.h" 57 #include "intel_lspcon.h" 58 #include "intel_panel.h" 59 #include "intel_sdvo.h" 60 #include "intel_sideband.h" 61 62 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 63 { 64 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 65 } 66 67 static void 68 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 69 { 70 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 71 struct drm_i915_private *dev_priv = to_i915(dev); 72 u32 enabled_bits; 73 74 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 75 76 drm_WARN(dev, 77 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 78 "HDMI port enabled, expecting disabled\n"); 79 } 80 81 static void 82 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 83 enum transcoder cpu_transcoder) 84 { 85 drm_WARN(&dev_priv->drm, 86 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 87 TRANS_DDI_FUNC_ENABLE, 88 "HDMI transcoder function enabled, expecting disabled\n"); 89 } 90 91 struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) 92 { 93 struct intel_digital_port *intel_dig_port = 94 container_of(&encoder->base, struct intel_digital_port, 95 base.base); 96 return &intel_dig_port->hdmi; 97 } 98 99 static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector) 100 { 101 return enc_to_intel_hdmi(intel_attached_encoder(connector)); 102 } 103 104 static u32 g4x_infoframe_index(unsigned int type) 105 { 106 switch (type) { 107 case HDMI_PACKET_TYPE_GAMUT_METADATA: 108 return VIDEO_DIP_SELECT_GAMUT; 109 case HDMI_INFOFRAME_TYPE_AVI: 110 return VIDEO_DIP_SELECT_AVI; 111 case HDMI_INFOFRAME_TYPE_SPD: 112 return VIDEO_DIP_SELECT_SPD; 113 case HDMI_INFOFRAME_TYPE_VENDOR: 114 return VIDEO_DIP_SELECT_VENDOR; 115 default: 116 MISSING_CASE(type); 117 return 0; 118 } 119 } 120 121 static u32 g4x_infoframe_enable(unsigned int type) 122 { 123 switch (type) { 124 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 125 return VIDEO_DIP_ENABLE_GCP; 126 case HDMI_PACKET_TYPE_GAMUT_METADATA: 127 return VIDEO_DIP_ENABLE_GAMUT; 128 case DP_SDP_VSC: 129 return 0; 130 case HDMI_INFOFRAME_TYPE_AVI: 131 return VIDEO_DIP_ENABLE_AVI; 132 case HDMI_INFOFRAME_TYPE_SPD: 133 return VIDEO_DIP_ENABLE_SPD; 134 case HDMI_INFOFRAME_TYPE_VENDOR: 135 return VIDEO_DIP_ENABLE_VENDOR; 136 case HDMI_INFOFRAME_TYPE_DRM: 137 return 0; 138 default: 139 MISSING_CASE(type); 140 return 0; 141 } 142 } 143 144 static u32 hsw_infoframe_enable(unsigned int type) 145 { 146 switch (type) { 147 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 148 return VIDEO_DIP_ENABLE_GCP_HSW; 149 case HDMI_PACKET_TYPE_GAMUT_METADATA: 150 return VIDEO_DIP_ENABLE_GMP_HSW; 151 case DP_SDP_VSC: 152 return VIDEO_DIP_ENABLE_VSC_HSW; 153 case DP_SDP_PPS: 154 return VDIP_ENABLE_PPS; 155 case HDMI_INFOFRAME_TYPE_AVI: 156 return VIDEO_DIP_ENABLE_AVI_HSW; 157 case HDMI_INFOFRAME_TYPE_SPD: 158 return VIDEO_DIP_ENABLE_SPD_HSW; 159 case HDMI_INFOFRAME_TYPE_VENDOR: 160 return VIDEO_DIP_ENABLE_VS_HSW; 161 case HDMI_INFOFRAME_TYPE_DRM: 162 return VIDEO_DIP_ENABLE_DRM_GLK; 163 default: 164 MISSING_CASE(type); 165 return 0; 166 } 167 } 168 169 static i915_reg_t 170 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 171 enum transcoder cpu_transcoder, 172 unsigned int type, 173 int i) 174 { 175 switch (type) { 176 case HDMI_PACKET_TYPE_GAMUT_METADATA: 177 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 178 case DP_SDP_VSC: 179 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 180 case DP_SDP_PPS: 181 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 182 case HDMI_INFOFRAME_TYPE_AVI: 183 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 184 case HDMI_INFOFRAME_TYPE_SPD: 185 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 186 case HDMI_INFOFRAME_TYPE_VENDOR: 187 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 188 case HDMI_INFOFRAME_TYPE_DRM: 189 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 190 default: 191 MISSING_CASE(type); 192 return INVALID_MMIO_REG; 193 } 194 } 195 196 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 197 unsigned int type) 198 { 199 switch (type) { 200 case DP_SDP_VSC: 201 return VIDEO_DIP_VSC_DATA_SIZE; 202 case DP_SDP_PPS: 203 return VIDEO_DIP_PPS_DATA_SIZE; 204 case HDMI_PACKET_TYPE_GAMUT_METADATA: 205 if (INTEL_GEN(dev_priv) >= 11) 206 return VIDEO_DIP_GMP_DATA_SIZE; 207 else 208 return VIDEO_DIP_DATA_SIZE; 209 default: 210 return VIDEO_DIP_DATA_SIZE; 211 } 212 } 213 214 static void g4x_write_infoframe(struct intel_encoder *encoder, 215 const struct intel_crtc_state *crtc_state, 216 unsigned int type, 217 const void *frame, ssize_t len) 218 { 219 const u32 *data = frame; 220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 221 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 222 int i; 223 224 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 225 "Writing DIP with CTL reg disabled\n"); 226 227 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 228 val |= g4x_infoframe_index(type); 229 230 val &= ~g4x_infoframe_enable(type); 231 232 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 233 234 for (i = 0; i < len; i += 4) { 235 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 236 data++; 237 } 238 /* Write every possible data byte to force correct ECC calculation. */ 239 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 240 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 241 242 val |= g4x_infoframe_enable(type); 243 val &= ~VIDEO_DIP_FREQ_MASK; 244 val |= VIDEO_DIP_FREQ_VSYNC; 245 246 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 247 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 248 } 249 250 static void g4x_read_infoframe(struct intel_encoder *encoder, 251 const struct intel_crtc_state *crtc_state, 252 unsigned int type, 253 void *frame, ssize_t len) 254 { 255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 256 u32 val, *data = frame; 257 int i; 258 259 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 260 261 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 262 val |= g4x_infoframe_index(type); 263 264 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 265 266 for (i = 0; i < len; i += 4) 267 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 268 } 269 270 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 271 const struct intel_crtc_state *pipe_config) 272 { 273 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 274 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 275 276 if ((val & VIDEO_DIP_ENABLE) == 0) 277 return 0; 278 279 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 280 return 0; 281 282 return val & (VIDEO_DIP_ENABLE_AVI | 283 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 284 } 285 286 static void ibx_write_infoframe(struct intel_encoder *encoder, 287 const struct intel_crtc_state *crtc_state, 288 unsigned int type, 289 const void *frame, ssize_t len) 290 { 291 const u32 *data = frame; 292 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 294 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 295 u32 val = intel_de_read(dev_priv, reg); 296 int i; 297 298 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 299 "Writing DIP with CTL reg disabled\n"); 300 301 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 302 val |= g4x_infoframe_index(type); 303 304 val &= ~g4x_infoframe_enable(type); 305 306 intel_de_write(dev_priv, reg, val); 307 308 for (i = 0; i < len; i += 4) { 309 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 310 *data); 311 data++; 312 } 313 /* Write every possible data byte to force correct ECC calculation. */ 314 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 315 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 316 317 val |= g4x_infoframe_enable(type); 318 val &= ~VIDEO_DIP_FREQ_MASK; 319 val |= VIDEO_DIP_FREQ_VSYNC; 320 321 intel_de_write(dev_priv, reg, val); 322 intel_de_posting_read(dev_priv, reg); 323 } 324 325 static void ibx_read_infoframe(struct intel_encoder *encoder, 326 const struct intel_crtc_state *crtc_state, 327 unsigned int type, 328 void *frame, ssize_t len) 329 { 330 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 331 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 332 u32 val, *data = frame; 333 int i; 334 335 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 336 337 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 338 val |= g4x_infoframe_index(type); 339 340 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 341 342 for (i = 0; i < len; i += 4) 343 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 344 } 345 346 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 347 const struct intel_crtc_state *pipe_config) 348 { 349 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 350 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 351 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 352 u32 val = intel_de_read(dev_priv, reg); 353 354 if ((val & VIDEO_DIP_ENABLE) == 0) 355 return 0; 356 357 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 358 return 0; 359 360 return val & (VIDEO_DIP_ENABLE_AVI | 361 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 362 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 363 } 364 365 static void cpt_write_infoframe(struct intel_encoder *encoder, 366 const struct intel_crtc_state *crtc_state, 367 unsigned int type, 368 const void *frame, ssize_t len) 369 { 370 const u32 *data = frame; 371 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 373 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 374 u32 val = intel_de_read(dev_priv, reg); 375 int i; 376 377 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 378 "Writing DIP with CTL reg disabled\n"); 379 380 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 381 val |= g4x_infoframe_index(type); 382 383 /* The DIP control register spec says that we need to update the AVI 384 * infoframe without clearing its enable bit */ 385 if (type != HDMI_INFOFRAME_TYPE_AVI) 386 val &= ~g4x_infoframe_enable(type); 387 388 intel_de_write(dev_priv, reg, val); 389 390 for (i = 0; i < len; i += 4) { 391 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 392 *data); 393 data++; 394 } 395 /* Write every possible data byte to force correct ECC calculation. */ 396 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 397 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 398 399 val |= g4x_infoframe_enable(type); 400 val &= ~VIDEO_DIP_FREQ_MASK; 401 val |= VIDEO_DIP_FREQ_VSYNC; 402 403 intel_de_write(dev_priv, reg, val); 404 intel_de_posting_read(dev_priv, reg); 405 } 406 407 static void cpt_read_infoframe(struct intel_encoder *encoder, 408 const struct intel_crtc_state *crtc_state, 409 unsigned int type, 410 void *frame, ssize_t len) 411 { 412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 413 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 414 u32 val, *data = frame; 415 int i; 416 417 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 418 419 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 420 val |= g4x_infoframe_index(type); 421 422 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 423 424 for (i = 0; i < len; i += 4) 425 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 426 } 427 428 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 429 const struct intel_crtc_state *pipe_config) 430 { 431 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 432 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 433 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 434 435 if ((val & VIDEO_DIP_ENABLE) == 0) 436 return 0; 437 438 return val & (VIDEO_DIP_ENABLE_AVI | 439 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 440 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 441 } 442 443 static void vlv_write_infoframe(struct intel_encoder *encoder, 444 const struct intel_crtc_state *crtc_state, 445 unsigned int type, 446 const void *frame, ssize_t len) 447 { 448 const u32 *data = frame; 449 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 451 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 452 u32 val = intel_de_read(dev_priv, reg); 453 int i; 454 455 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 456 "Writing DIP with CTL reg disabled\n"); 457 458 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 459 val |= g4x_infoframe_index(type); 460 461 val &= ~g4x_infoframe_enable(type); 462 463 intel_de_write(dev_priv, reg, val); 464 465 for (i = 0; i < len; i += 4) { 466 intel_de_write(dev_priv, 467 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 468 data++; 469 } 470 /* Write every possible data byte to force correct ECC calculation. */ 471 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 472 intel_de_write(dev_priv, 473 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 474 475 val |= g4x_infoframe_enable(type); 476 val &= ~VIDEO_DIP_FREQ_MASK; 477 val |= VIDEO_DIP_FREQ_VSYNC; 478 479 intel_de_write(dev_priv, reg, val); 480 intel_de_posting_read(dev_priv, reg); 481 } 482 483 static void vlv_read_infoframe(struct intel_encoder *encoder, 484 const struct intel_crtc_state *crtc_state, 485 unsigned int type, 486 void *frame, ssize_t len) 487 { 488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 490 u32 val, *data = frame; 491 int i; 492 493 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); 494 495 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 496 val |= g4x_infoframe_index(type); 497 498 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 499 500 for (i = 0; i < len; i += 4) 501 *data++ = intel_de_read(dev_priv, 502 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 503 } 504 505 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 506 const struct intel_crtc_state *pipe_config) 507 { 508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 509 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 510 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 511 512 if ((val & VIDEO_DIP_ENABLE) == 0) 513 return 0; 514 515 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 516 return 0; 517 518 return val & (VIDEO_DIP_ENABLE_AVI | 519 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 520 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 521 } 522 523 static void hsw_write_infoframe(struct intel_encoder *encoder, 524 const struct intel_crtc_state *crtc_state, 525 unsigned int type, 526 const void *frame, ssize_t len) 527 { 528 const u32 *data = frame; 529 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 530 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 531 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 532 int data_size; 533 int i; 534 u32 val = intel_de_read(dev_priv, ctl_reg); 535 536 data_size = hsw_dip_data_size(dev_priv, type); 537 538 drm_WARN_ON(&dev_priv->drm, len > data_size); 539 540 val &= ~hsw_infoframe_enable(type); 541 intel_de_write(dev_priv, ctl_reg, val); 542 543 for (i = 0; i < len; i += 4) { 544 intel_de_write(dev_priv, 545 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 546 *data); 547 data++; 548 } 549 /* Write every possible data byte to force correct ECC calculation. */ 550 for (; i < data_size; i += 4) 551 intel_de_write(dev_priv, 552 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 553 0); 554 555 val |= hsw_infoframe_enable(type); 556 intel_de_write(dev_priv, ctl_reg, val); 557 intel_de_posting_read(dev_priv, ctl_reg); 558 } 559 560 static void hsw_read_infoframe(struct intel_encoder *encoder, 561 const struct intel_crtc_state *crtc_state, 562 unsigned int type, 563 void *frame, ssize_t len) 564 { 565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 566 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 567 u32 val, *data = frame; 568 int i; 569 570 val = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(cpu_transcoder)); 571 572 for (i = 0; i < len; i += 4) 573 *data++ = intel_de_read(dev_priv, 574 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 575 } 576 577 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 578 const struct intel_crtc_state *pipe_config) 579 { 580 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 581 u32 val = intel_de_read(dev_priv, 582 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 583 u32 mask; 584 585 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 586 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 587 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 588 589 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 590 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 591 592 return val & mask; 593 } 594 595 static const u8 infoframe_type_to_idx[] = { 596 HDMI_PACKET_TYPE_GENERAL_CONTROL, 597 HDMI_PACKET_TYPE_GAMUT_METADATA, 598 DP_SDP_VSC, 599 HDMI_INFOFRAME_TYPE_AVI, 600 HDMI_INFOFRAME_TYPE_SPD, 601 HDMI_INFOFRAME_TYPE_VENDOR, 602 HDMI_INFOFRAME_TYPE_DRM, 603 }; 604 605 u32 intel_hdmi_infoframe_enable(unsigned int type) 606 { 607 int i; 608 609 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 610 if (infoframe_type_to_idx[i] == type) 611 return BIT(i); 612 } 613 614 return 0; 615 } 616 617 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 618 const struct intel_crtc_state *crtc_state) 619 { 620 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 621 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 622 u32 val, ret = 0; 623 int i; 624 625 val = dig_port->infoframes_enabled(encoder, crtc_state); 626 627 /* map from hardware bits to dip idx */ 628 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 629 unsigned int type = infoframe_type_to_idx[i]; 630 631 if (HAS_DDI(dev_priv)) { 632 if (val & hsw_infoframe_enable(type)) 633 ret |= BIT(i); 634 } else { 635 if (val & g4x_infoframe_enable(type)) 636 ret |= BIT(i); 637 } 638 } 639 640 return ret; 641 } 642 643 /* 644 * The data we write to the DIP data buffer registers is 1 byte bigger than the 645 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 646 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 647 * used for both technologies. 648 * 649 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 650 * DW1: DB3 | DB2 | DB1 | DB0 651 * DW2: DB7 | DB6 | DB5 | DB4 652 * DW3: ... 653 * 654 * (HB is Header Byte, DB is Data Byte) 655 * 656 * The hdmi pack() functions don't know about that hardware specific hole so we 657 * trick them by giving an offset into the buffer and moving back the header 658 * bytes by one. 659 */ 660 static void intel_write_infoframe(struct intel_encoder *encoder, 661 const struct intel_crtc_state *crtc_state, 662 enum hdmi_infoframe_type type, 663 const union hdmi_infoframe *frame) 664 { 665 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 666 u8 buffer[VIDEO_DIP_DATA_SIZE]; 667 ssize_t len; 668 669 if ((crtc_state->infoframes.enable & 670 intel_hdmi_infoframe_enable(type)) == 0) 671 return; 672 673 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 674 return; 675 676 /* see comment above for the reason for this offset */ 677 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 678 if (drm_WARN_ON(encoder->base.dev, len < 0)) 679 return; 680 681 /* Insert the 'hole' (see big comment above) at position 3 */ 682 memmove(&buffer[0], &buffer[1], 3); 683 buffer[3] = 0; 684 len++; 685 686 intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 687 } 688 689 void intel_read_infoframe(struct intel_encoder *encoder, 690 const struct intel_crtc_state *crtc_state, 691 enum hdmi_infoframe_type type, 692 union hdmi_infoframe *frame) 693 { 694 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 695 u8 buffer[VIDEO_DIP_DATA_SIZE]; 696 int ret; 697 698 if ((crtc_state->infoframes.enable & 699 intel_hdmi_infoframe_enable(type)) == 0) 700 return; 701 702 intel_dig_port->read_infoframe(encoder, crtc_state, 703 type, buffer, sizeof(buffer)); 704 705 /* Fill the 'hole' (see big comment above) at position 3 */ 706 memmove(&buffer[1], &buffer[0], 3); 707 708 /* see comment above for the reason for this offset */ 709 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 710 if (ret) { 711 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type); 712 return; 713 } 714 715 if (frame->any.type != type) 716 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 717 frame->any.type, type); 718 } 719 720 static bool 721 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 722 struct intel_crtc_state *crtc_state, 723 struct drm_connector_state *conn_state) 724 { 725 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 726 const struct drm_display_mode *adjusted_mode = 727 &crtc_state->hw.adjusted_mode; 728 struct drm_connector *connector = conn_state->connector; 729 int ret; 730 731 if (!crtc_state->has_infoframe) 732 return true; 733 734 crtc_state->infoframes.enable |= 735 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 736 737 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 738 adjusted_mode); 739 if (ret) 740 return false; 741 742 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 743 frame->colorspace = HDMI_COLORSPACE_YUV420; 744 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 745 frame->colorspace = HDMI_COLORSPACE_YUV444; 746 else 747 frame->colorspace = HDMI_COLORSPACE_RGB; 748 749 drm_hdmi_avi_infoframe_colorspace(frame, conn_state); 750 751 /* nonsense combination */ 752 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 753 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 754 755 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 756 drm_hdmi_avi_infoframe_quant_range(frame, connector, 757 adjusted_mode, 758 crtc_state->limited_color_range ? 759 HDMI_QUANTIZATION_RANGE_LIMITED : 760 HDMI_QUANTIZATION_RANGE_FULL); 761 } else { 762 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 763 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 764 } 765 766 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 767 768 /* TODO: handle pixel repetition for YCBCR420 outputs */ 769 770 ret = hdmi_avi_infoframe_check(frame); 771 if (drm_WARN_ON(encoder->base.dev, ret)) 772 return false; 773 774 return true; 775 } 776 777 static bool 778 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 779 struct intel_crtc_state *crtc_state, 780 struct drm_connector_state *conn_state) 781 { 782 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 783 int ret; 784 785 if (!crtc_state->has_infoframe) 786 return true; 787 788 crtc_state->infoframes.enable |= 789 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 790 791 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 792 if (drm_WARN_ON(encoder->base.dev, ret)) 793 return false; 794 795 frame->sdi = HDMI_SPD_SDI_PC; 796 797 ret = hdmi_spd_infoframe_check(frame); 798 if (drm_WARN_ON(encoder->base.dev, ret)) 799 return false; 800 801 return true; 802 } 803 804 static bool 805 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 806 struct intel_crtc_state *crtc_state, 807 struct drm_connector_state *conn_state) 808 { 809 struct hdmi_vendor_infoframe *frame = 810 &crtc_state->infoframes.hdmi.vendor.hdmi; 811 const struct drm_display_info *info = 812 &conn_state->connector->display_info; 813 int ret; 814 815 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 816 return true; 817 818 crtc_state->infoframes.enable |= 819 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 820 821 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 822 conn_state->connector, 823 &crtc_state->hw.adjusted_mode); 824 if (drm_WARN_ON(encoder->base.dev, ret)) 825 return false; 826 827 ret = hdmi_vendor_infoframe_check(frame); 828 if (drm_WARN_ON(encoder->base.dev, ret)) 829 return false; 830 831 return true; 832 } 833 834 static bool 835 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 836 struct intel_crtc_state *crtc_state, 837 struct drm_connector_state *conn_state) 838 { 839 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 840 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 841 int ret; 842 843 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) 844 return true; 845 846 if (!crtc_state->has_infoframe) 847 return true; 848 849 if (!conn_state->hdr_output_metadata) 850 return true; 851 852 crtc_state->infoframes.enable |= 853 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 854 855 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 856 if (ret < 0) { 857 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); 858 return false; 859 } 860 861 ret = hdmi_drm_infoframe_check(frame); 862 if (drm_WARN_ON(&dev_priv->drm, ret)) 863 return false; 864 865 return true; 866 } 867 868 static void g4x_set_infoframes(struct intel_encoder *encoder, 869 bool enable, 870 const struct intel_crtc_state *crtc_state, 871 const struct drm_connector_state *conn_state) 872 { 873 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 874 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 875 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 876 i915_reg_t reg = VIDEO_DIP_CTL; 877 u32 val = intel_de_read(dev_priv, reg); 878 u32 port = VIDEO_DIP_PORT(encoder->port); 879 880 assert_hdmi_port_disabled(intel_hdmi); 881 882 /* If the registers were not initialized yet, they might be zeroes, 883 * which means we're selecting the AVI DIP and we're setting its 884 * frequency to once. This seems to really confuse the HW and make 885 * things stop working (the register spec says the AVI always needs to 886 * be sent every VSync). So here we avoid writing to the register more 887 * than we need and also explicitly select the AVI DIP and explicitly 888 * set its frequency to every VSync. Avoiding to write it twice seems to 889 * be enough to solve the problem, but being defensive shouldn't hurt us 890 * either. */ 891 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 892 893 if (!enable) { 894 if (!(val & VIDEO_DIP_ENABLE)) 895 return; 896 if (port != (val & VIDEO_DIP_PORT_MASK)) { 897 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 898 (val & VIDEO_DIP_PORT_MASK) >> 29); 899 return; 900 } 901 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 902 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 903 intel_de_write(dev_priv, reg, val); 904 intel_de_posting_read(dev_priv, reg); 905 return; 906 } 907 908 if (port != (val & VIDEO_DIP_PORT_MASK)) { 909 if (val & VIDEO_DIP_ENABLE) { 910 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 911 (val & VIDEO_DIP_PORT_MASK) >> 29); 912 return; 913 } 914 val &= ~VIDEO_DIP_PORT_MASK; 915 val |= port; 916 } 917 918 val |= VIDEO_DIP_ENABLE; 919 val &= ~(VIDEO_DIP_ENABLE_AVI | 920 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 921 922 intel_de_write(dev_priv, reg, val); 923 intel_de_posting_read(dev_priv, reg); 924 925 intel_write_infoframe(encoder, crtc_state, 926 HDMI_INFOFRAME_TYPE_AVI, 927 &crtc_state->infoframes.avi); 928 intel_write_infoframe(encoder, crtc_state, 929 HDMI_INFOFRAME_TYPE_SPD, 930 &crtc_state->infoframes.spd); 931 intel_write_infoframe(encoder, crtc_state, 932 HDMI_INFOFRAME_TYPE_VENDOR, 933 &crtc_state->infoframes.hdmi); 934 } 935 936 /* 937 * Determine if default_phase=1 can be indicated in the GCP infoframe. 938 * 939 * From HDMI specification 1.4a: 940 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 941 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 942 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 943 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 944 * phase of 0 945 */ 946 static bool gcp_default_phase_possible(int pipe_bpp, 947 const struct drm_display_mode *mode) 948 { 949 unsigned int pixels_per_group; 950 951 switch (pipe_bpp) { 952 case 30: 953 /* 4 pixels in 5 clocks */ 954 pixels_per_group = 4; 955 break; 956 case 36: 957 /* 2 pixels in 3 clocks */ 958 pixels_per_group = 2; 959 break; 960 case 48: 961 /* 1 pixel in 2 clocks */ 962 pixels_per_group = 1; 963 break; 964 default: 965 /* phase information not relevant for 8bpc */ 966 return false; 967 } 968 969 return mode->crtc_hdisplay % pixels_per_group == 0 && 970 mode->crtc_htotal % pixels_per_group == 0 && 971 mode->crtc_hblank_start % pixels_per_group == 0 && 972 mode->crtc_hblank_end % pixels_per_group == 0 && 973 mode->crtc_hsync_start % pixels_per_group == 0 && 974 mode->crtc_hsync_end % pixels_per_group == 0 && 975 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 976 mode->crtc_htotal/2 % pixels_per_group == 0); 977 } 978 979 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 980 const struct intel_crtc_state *crtc_state, 981 const struct drm_connector_state *conn_state) 982 { 983 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 984 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 985 i915_reg_t reg; 986 987 if ((crtc_state->infoframes.enable & 988 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 989 return false; 990 991 if (HAS_DDI(dev_priv)) 992 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 993 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 994 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 995 else if (HAS_PCH_SPLIT(dev_priv)) 996 reg = TVIDEO_DIP_GCP(crtc->pipe); 997 else 998 return false; 999 1000 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 1001 1002 return true; 1003 } 1004 1005 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1006 struct intel_crtc_state *crtc_state) 1007 { 1008 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1009 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1010 i915_reg_t reg; 1011 1012 if ((crtc_state->infoframes.enable & 1013 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1014 return; 1015 1016 if (HAS_DDI(dev_priv)) 1017 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1018 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1019 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1020 else if (HAS_PCH_SPLIT(dev_priv)) 1021 reg = TVIDEO_DIP_GCP(crtc->pipe); 1022 else 1023 return; 1024 1025 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1026 } 1027 1028 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1029 struct intel_crtc_state *crtc_state, 1030 struct drm_connector_state *conn_state) 1031 { 1032 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1033 1034 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1035 return; 1036 1037 crtc_state->infoframes.enable |= 1038 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1039 1040 /* Indicate color indication for deep color mode */ 1041 if (crtc_state->pipe_bpp > 24) 1042 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1043 1044 /* Enable default_phase whenever the display mode is suitably aligned */ 1045 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1046 &crtc_state->hw.adjusted_mode)) 1047 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1048 } 1049 1050 static void ibx_set_infoframes(struct intel_encoder *encoder, 1051 bool enable, 1052 const struct intel_crtc_state *crtc_state, 1053 const struct drm_connector_state *conn_state) 1054 { 1055 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1057 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 1058 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1059 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1060 u32 val = intel_de_read(dev_priv, reg); 1061 u32 port = VIDEO_DIP_PORT(encoder->port); 1062 1063 assert_hdmi_port_disabled(intel_hdmi); 1064 1065 /* See the big comment in g4x_set_infoframes() */ 1066 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1067 1068 if (!enable) { 1069 if (!(val & VIDEO_DIP_ENABLE)) 1070 return; 1071 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1072 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1073 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1074 intel_de_write(dev_priv, reg, val); 1075 intel_de_posting_read(dev_priv, reg); 1076 return; 1077 } 1078 1079 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1080 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1081 "DIP already enabled on port %c\n", 1082 (val & VIDEO_DIP_PORT_MASK) >> 29); 1083 val &= ~VIDEO_DIP_PORT_MASK; 1084 val |= port; 1085 } 1086 1087 val |= VIDEO_DIP_ENABLE; 1088 val &= ~(VIDEO_DIP_ENABLE_AVI | 1089 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1090 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1091 1092 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1093 val |= VIDEO_DIP_ENABLE_GCP; 1094 1095 intel_de_write(dev_priv, reg, val); 1096 intel_de_posting_read(dev_priv, reg); 1097 1098 intel_write_infoframe(encoder, crtc_state, 1099 HDMI_INFOFRAME_TYPE_AVI, 1100 &crtc_state->infoframes.avi); 1101 intel_write_infoframe(encoder, crtc_state, 1102 HDMI_INFOFRAME_TYPE_SPD, 1103 &crtc_state->infoframes.spd); 1104 intel_write_infoframe(encoder, crtc_state, 1105 HDMI_INFOFRAME_TYPE_VENDOR, 1106 &crtc_state->infoframes.hdmi); 1107 } 1108 1109 static void cpt_set_infoframes(struct intel_encoder *encoder, 1110 bool enable, 1111 const struct intel_crtc_state *crtc_state, 1112 const struct drm_connector_state *conn_state) 1113 { 1114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1116 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1117 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1118 u32 val = intel_de_read(dev_priv, reg); 1119 1120 assert_hdmi_port_disabled(intel_hdmi); 1121 1122 /* See the big comment in g4x_set_infoframes() */ 1123 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1124 1125 if (!enable) { 1126 if (!(val & VIDEO_DIP_ENABLE)) 1127 return; 1128 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1129 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1130 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1131 intel_de_write(dev_priv, reg, val); 1132 intel_de_posting_read(dev_priv, reg); 1133 return; 1134 } 1135 1136 /* Set both together, unset both together: see the spec. */ 1137 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1138 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1139 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1140 1141 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1142 val |= VIDEO_DIP_ENABLE_GCP; 1143 1144 intel_de_write(dev_priv, reg, val); 1145 intel_de_posting_read(dev_priv, reg); 1146 1147 intel_write_infoframe(encoder, crtc_state, 1148 HDMI_INFOFRAME_TYPE_AVI, 1149 &crtc_state->infoframes.avi); 1150 intel_write_infoframe(encoder, crtc_state, 1151 HDMI_INFOFRAME_TYPE_SPD, 1152 &crtc_state->infoframes.spd); 1153 intel_write_infoframe(encoder, crtc_state, 1154 HDMI_INFOFRAME_TYPE_VENDOR, 1155 &crtc_state->infoframes.hdmi); 1156 } 1157 1158 static void vlv_set_infoframes(struct intel_encoder *encoder, 1159 bool enable, 1160 const struct intel_crtc_state *crtc_state, 1161 const struct drm_connector_state *conn_state) 1162 { 1163 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1165 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1166 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 1167 u32 val = intel_de_read(dev_priv, reg); 1168 u32 port = VIDEO_DIP_PORT(encoder->port); 1169 1170 assert_hdmi_port_disabled(intel_hdmi); 1171 1172 /* See the big comment in g4x_set_infoframes() */ 1173 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1174 1175 if (!enable) { 1176 if (!(val & VIDEO_DIP_ENABLE)) 1177 return; 1178 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1179 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1180 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1181 intel_de_write(dev_priv, reg, val); 1182 intel_de_posting_read(dev_priv, reg); 1183 return; 1184 } 1185 1186 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1187 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1188 "DIP already enabled on port %c\n", 1189 (val & VIDEO_DIP_PORT_MASK) >> 29); 1190 val &= ~VIDEO_DIP_PORT_MASK; 1191 val |= port; 1192 } 1193 1194 val |= VIDEO_DIP_ENABLE; 1195 val &= ~(VIDEO_DIP_ENABLE_AVI | 1196 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1197 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1198 1199 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1200 val |= VIDEO_DIP_ENABLE_GCP; 1201 1202 intel_de_write(dev_priv, reg, val); 1203 intel_de_posting_read(dev_priv, reg); 1204 1205 intel_write_infoframe(encoder, crtc_state, 1206 HDMI_INFOFRAME_TYPE_AVI, 1207 &crtc_state->infoframes.avi); 1208 intel_write_infoframe(encoder, crtc_state, 1209 HDMI_INFOFRAME_TYPE_SPD, 1210 &crtc_state->infoframes.spd); 1211 intel_write_infoframe(encoder, crtc_state, 1212 HDMI_INFOFRAME_TYPE_VENDOR, 1213 &crtc_state->infoframes.hdmi); 1214 } 1215 1216 static void hsw_set_infoframes(struct intel_encoder *encoder, 1217 bool enable, 1218 const struct intel_crtc_state *crtc_state, 1219 const struct drm_connector_state *conn_state) 1220 { 1221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1222 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1223 u32 val = intel_de_read(dev_priv, reg); 1224 1225 assert_hdmi_transcoder_func_disabled(dev_priv, 1226 crtc_state->cpu_transcoder); 1227 1228 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1229 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1230 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1231 VIDEO_DIP_ENABLE_DRM_GLK); 1232 1233 if (!enable) { 1234 intel_de_write(dev_priv, reg, val); 1235 intel_de_posting_read(dev_priv, reg); 1236 return; 1237 } 1238 1239 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1240 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1241 1242 intel_de_write(dev_priv, reg, val); 1243 intel_de_posting_read(dev_priv, reg); 1244 1245 intel_write_infoframe(encoder, crtc_state, 1246 HDMI_INFOFRAME_TYPE_AVI, 1247 &crtc_state->infoframes.avi); 1248 intel_write_infoframe(encoder, crtc_state, 1249 HDMI_INFOFRAME_TYPE_SPD, 1250 &crtc_state->infoframes.spd); 1251 intel_write_infoframe(encoder, crtc_state, 1252 HDMI_INFOFRAME_TYPE_VENDOR, 1253 &crtc_state->infoframes.hdmi); 1254 intel_write_infoframe(encoder, crtc_state, 1255 HDMI_INFOFRAME_TYPE_DRM, 1256 &crtc_state->infoframes.drm); 1257 } 1258 1259 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1260 { 1261 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1262 struct i2c_adapter *adapter = 1263 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1264 1265 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1266 return; 1267 1268 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", 1269 enable ? "Enabling" : "Disabling"); 1270 1271 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, 1272 adapter, enable); 1273 } 1274 1275 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, 1276 unsigned int offset, void *buffer, size_t size) 1277 { 1278 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); 1279 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1280 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1281 hdmi->ddc_bus); 1282 int ret; 1283 u8 start = offset & 0xff; 1284 struct i2c_msg msgs[] = { 1285 { 1286 .addr = DRM_HDCP_DDC_ADDR, 1287 .flags = 0, 1288 .len = 1, 1289 .buf = &start, 1290 }, 1291 { 1292 .addr = DRM_HDCP_DDC_ADDR, 1293 .flags = I2C_M_RD, 1294 .len = size, 1295 .buf = buffer 1296 } 1297 }; 1298 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1299 if (ret == ARRAY_SIZE(msgs)) 1300 return 0; 1301 return ret >= 0 ? -EIO : ret; 1302 } 1303 1304 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, 1305 unsigned int offset, void *buffer, size_t size) 1306 { 1307 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); 1308 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1309 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1310 hdmi->ddc_bus); 1311 int ret; 1312 u8 *write_buf; 1313 struct i2c_msg msg; 1314 1315 write_buf = kzalloc(size + 1, GFP_KERNEL); 1316 if (!write_buf) 1317 return -ENOMEM; 1318 1319 write_buf[0] = offset & 0xff; 1320 memcpy(&write_buf[1], buffer, size); 1321 1322 msg.addr = DRM_HDCP_DDC_ADDR; 1323 msg.flags = 0, 1324 msg.len = size + 1, 1325 msg.buf = write_buf; 1326 1327 ret = i2c_transfer(adapter, &msg, 1); 1328 if (ret == 1) 1329 ret = 0; 1330 else if (ret >= 0) 1331 ret = -EIO; 1332 1333 kfree(write_buf); 1334 return ret; 1335 } 1336 1337 static 1338 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, 1339 u8 *an) 1340 { 1341 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); 1342 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1343 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1344 hdmi->ddc_bus); 1345 int ret; 1346 1347 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, 1348 DRM_HDCP_AN_LEN); 1349 if (ret) { 1350 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret); 1351 return ret; 1352 } 1353 1354 ret = intel_gmbus_output_aksv(adapter); 1355 if (ret < 0) { 1356 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret); 1357 return ret; 1358 } 1359 return 0; 1360 } 1361 1362 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, 1363 u8 *bksv) 1364 { 1365 int ret; 1366 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, 1367 DRM_HDCP_KSV_LEN); 1368 if (ret) 1369 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret); 1370 return ret; 1371 } 1372 1373 static 1374 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, 1375 u8 *bstatus) 1376 { 1377 int ret; 1378 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, 1379 bstatus, DRM_HDCP_BSTATUS_LEN); 1380 if (ret) 1381 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret); 1382 return ret; 1383 } 1384 1385 static 1386 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, 1387 bool *repeater_present) 1388 { 1389 int ret; 1390 u8 val; 1391 1392 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1393 if (ret) { 1394 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); 1395 return ret; 1396 } 1397 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1398 return 0; 1399 } 1400 1401 static 1402 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, 1403 u8 *ri_prime) 1404 { 1405 int ret; 1406 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, 1407 ri_prime, DRM_HDCP_RI_LEN); 1408 if (ret) 1409 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret); 1410 return ret; 1411 } 1412 1413 static 1414 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, 1415 bool *ksv_ready) 1416 { 1417 int ret; 1418 u8 val; 1419 1420 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1421 if (ret) { 1422 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); 1423 return ret; 1424 } 1425 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1426 return 0; 1427 } 1428 1429 static 1430 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, 1431 int num_downstream, u8 *ksv_fifo) 1432 { 1433 int ret; 1434 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, 1435 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1436 if (ret) { 1437 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret); 1438 return ret; 1439 } 1440 return 0; 1441 } 1442 1443 static 1444 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, 1445 int i, u32 *part) 1446 { 1447 int ret; 1448 1449 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1450 return -EINVAL; 1451 1452 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), 1453 part, DRM_HDCP_V_PRIME_PART_LEN); 1454 if (ret) 1455 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret); 1456 return ret; 1457 } 1458 1459 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) 1460 { 1461 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1462 struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); 1463 struct drm_crtc *crtc = connector->base.state->crtc; 1464 struct intel_crtc *intel_crtc = container_of(crtc, 1465 struct intel_crtc, base); 1466 u32 scanline; 1467 int ret; 1468 1469 for (;;) { 1470 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe)); 1471 if (scanline > 100 && scanline < 200) 1472 break; 1473 usleep_range(25, 50); 1474 } 1475 1476 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); 1477 if (ret) { 1478 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret); 1479 return ret; 1480 } 1481 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); 1482 if (ret) { 1483 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret); 1484 return ret; 1485 } 1486 1487 return 0; 1488 } 1489 1490 static 1491 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, 1492 bool enable) 1493 { 1494 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1495 struct intel_connector *connector = hdmi->attached_connector; 1496 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1497 int ret; 1498 1499 if (!enable) 1500 usleep_range(6, 60); /* Bspec says >= 6us */ 1501 1502 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); 1503 if (ret) { 1504 DRM_ERROR("%s HDCP signalling failed (%d)\n", 1505 enable ? "Enable" : "Disable", ret); 1506 return ret; 1507 } 1508 1509 /* 1510 * WA: To fix incorrect positioning of the window of 1511 * opportunity and enc_en signalling in KABYLAKE. 1512 */ 1513 if (IS_KABYLAKE(dev_priv) && enable) 1514 return kbl_repositioning_enc_en_signal(connector); 1515 1516 return 0; 1517 } 1518 1519 static 1520 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) 1521 { 1522 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); 1523 struct intel_connector *connector = 1524 intel_dig_port->hdmi.attached_connector; 1525 enum port port = intel_dig_port->base.port; 1526 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1527 int ret; 1528 union { 1529 u32 reg; 1530 u8 shim[DRM_HDCP_RI_LEN]; 1531 } ri; 1532 1533 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); 1534 if (ret) 1535 return false; 1536 1537 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1538 1539 /* Wait for Ri prime match */ 1540 if (wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1541 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1542 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", 1543 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port))); 1544 return false; 1545 } 1546 return true; 1547 } 1548 1549 struct hdcp2_hdmi_msg_timeout { 1550 u8 msg_id; 1551 u16 timeout; 1552 }; 1553 1554 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1555 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1556 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1557 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1558 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1559 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1560 }; 1561 1562 static 1563 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, 1564 u8 *rx_status) 1565 { 1566 return intel_hdmi_hdcp_read(intel_dig_port, 1567 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1568 rx_status, 1569 HDCP_2_2_HDMI_RXSTATUS_LEN); 1570 } 1571 1572 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1573 { 1574 int i; 1575 1576 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1577 if (is_paired) 1578 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1579 else 1580 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1581 } 1582 1583 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1584 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1585 return hdcp2_msg_timeout[i].timeout; 1586 } 1587 1588 return -EINVAL; 1589 } 1590 1591 static inline 1592 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port, 1593 u8 msg_id, bool *msg_ready, 1594 ssize_t *msg_sz) 1595 { 1596 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1597 int ret; 1598 1599 ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status); 1600 if (ret < 0) { 1601 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret); 1602 return ret; 1603 } 1604 1605 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1606 rx_status[0]); 1607 1608 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1609 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1610 *msg_sz); 1611 else 1612 *msg_ready = *msg_sz; 1613 1614 return 0; 1615 } 1616 1617 static ssize_t 1618 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, 1619 u8 msg_id, bool paired) 1620 { 1621 bool msg_ready = false; 1622 int timeout, ret; 1623 ssize_t msg_sz = 0; 1624 1625 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1626 if (timeout < 0) 1627 return timeout; 1628 1629 ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, 1630 msg_id, &msg_ready, 1631 &msg_sz), 1632 !ret && msg_ready && msg_sz, timeout * 1000, 1633 1000, 5 * 1000); 1634 if (ret) 1635 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n", 1636 msg_id, ret, timeout); 1637 1638 return ret ? ret : msg_sz; 1639 } 1640 1641 static 1642 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, 1643 void *buf, size_t size) 1644 { 1645 unsigned int offset; 1646 1647 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1648 return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); 1649 } 1650 1651 static 1652 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, 1653 u8 msg_id, void *buf, size_t size) 1654 { 1655 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1656 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1657 unsigned int offset; 1658 ssize_t ret; 1659 1660 ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, 1661 hdcp->is_paired); 1662 if (ret < 0) 1663 return ret; 1664 1665 /* 1666 * Available msg size should be equal to or lesser than the 1667 * available buffer. 1668 */ 1669 if (ret > size) { 1670 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n", 1671 ret, size); 1672 return -1; 1673 } 1674 1675 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1676 ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); 1677 if (ret) 1678 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret); 1679 1680 return ret; 1681 } 1682 1683 static 1684 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) 1685 { 1686 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1687 int ret; 1688 1689 ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); 1690 if (ret) 1691 return ret; 1692 1693 /* 1694 * Re-auth request and Link Integrity Failures are represented by 1695 * same bit. i.e reauth_req. 1696 */ 1697 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1698 ret = HDCP_REAUTH_REQUEST; 1699 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1700 ret = HDCP_TOPOLOGY_CHANGE; 1701 1702 return ret; 1703 } 1704 1705 static 1706 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, 1707 bool *capable) 1708 { 1709 u8 hdcp2_version; 1710 int ret; 1711 1712 *capable = false; 1713 ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1714 &hdcp2_version, sizeof(hdcp2_version)); 1715 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1716 *capable = true; 1717 1718 return ret; 1719 } 1720 1721 static inline 1722 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void) 1723 { 1724 return HDCP_PROTOCOL_HDMI; 1725 } 1726 1727 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1728 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1729 .read_bksv = intel_hdmi_hdcp_read_bksv, 1730 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1731 .repeater_present = intel_hdmi_hdcp_repeater_present, 1732 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1733 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1734 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1735 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1736 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1737 .check_link = intel_hdmi_hdcp_check_link, 1738 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1739 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1740 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1741 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1742 .protocol = HDCP_PROTOCOL_HDMI, 1743 }; 1744 1745 static void intel_hdmi_prepare(struct intel_encoder *encoder, 1746 const struct intel_crtc_state *crtc_state) 1747 { 1748 struct drm_device *dev = encoder->base.dev; 1749 struct drm_i915_private *dev_priv = to_i915(dev); 1750 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1751 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1752 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1753 u32 hdmi_val; 1754 1755 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 1756 1757 hdmi_val = SDVO_ENCODING_HDMI; 1758 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 1759 hdmi_val |= HDMI_COLOR_RANGE_16_235; 1760 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1761 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 1762 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1763 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 1764 1765 if (crtc_state->pipe_bpp > 24) 1766 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 1767 else 1768 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 1769 1770 if (crtc_state->has_hdmi_sink) 1771 hdmi_val |= HDMI_MODE_SELECT_HDMI; 1772 1773 if (HAS_PCH_CPT(dev_priv)) 1774 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1775 else if (IS_CHERRYVIEW(dev_priv)) 1776 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 1777 else 1778 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 1779 1780 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 1781 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1782 } 1783 1784 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 1785 enum pipe *pipe) 1786 { 1787 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1788 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1789 intel_wakeref_t wakeref; 1790 bool ret; 1791 1792 wakeref = intel_display_power_get_if_enabled(dev_priv, 1793 encoder->power_domain); 1794 if (!wakeref) 1795 return false; 1796 1797 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 1798 1799 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1800 1801 return ret; 1802 } 1803 1804 static void intel_hdmi_get_config(struct intel_encoder *encoder, 1805 struct intel_crtc_state *pipe_config) 1806 { 1807 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1808 struct drm_device *dev = encoder->base.dev; 1809 struct drm_i915_private *dev_priv = to_i915(dev); 1810 u32 tmp, flags = 0; 1811 int dotclock; 1812 1813 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 1814 1815 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1816 1817 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 1818 flags |= DRM_MODE_FLAG_PHSYNC; 1819 else 1820 flags |= DRM_MODE_FLAG_NHSYNC; 1821 1822 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 1823 flags |= DRM_MODE_FLAG_PVSYNC; 1824 else 1825 flags |= DRM_MODE_FLAG_NVSYNC; 1826 1827 if (tmp & HDMI_MODE_SELECT_HDMI) 1828 pipe_config->has_hdmi_sink = true; 1829 1830 pipe_config->infoframes.enable |= 1831 intel_hdmi_infoframes_enabled(encoder, pipe_config); 1832 1833 if (pipe_config->infoframes.enable) 1834 pipe_config->has_infoframe = true; 1835 1836 if (tmp & HDMI_AUDIO_ENABLE) 1837 pipe_config->has_audio = true; 1838 1839 if (!HAS_PCH_SPLIT(dev_priv) && 1840 tmp & HDMI_COLOR_RANGE_16_235) 1841 pipe_config->limited_color_range = true; 1842 1843 pipe_config->hw.adjusted_mode.flags |= flags; 1844 1845 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 1846 dotclock = pipe_config->port_clock * 2 / 3; 1847 else 1848 dotclock = pipe_config->port_clock; 1849 1850 if (pipe_config->pixel_multiplier) 1851 dotclock /= pipe_config->pixel_multiplier; 1852 1853 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1854 1855 pipe_config->lane_count = 4; 1856 1857 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 1858 1859 intel_read_infoframe(encoder, pipe_config, 1860 HDMI_INFOFRAME_TYPE_AVI, 1861 &pipe_config->infoframes.avi); 1862 intel_read_infoframe(encoder, pipe_config, 1863 HDMI_INFOFRAME_TYPE_SPD, 1864 &pipe_config->infoframes.spd); 1865 intel_read_infoframe(encoder, pipe_config, 1866 HDMI_INFOFRAME_TYPE_VENDOR, 1867 &pipe_config->infoframes.hdmi); 1868 } 1869 1870 static void intel_enable_hdmi_audio(struct intel_encoder *encoder, 1871 const struct intel_crtc_state *pipe_config, 1872 const struct drm_connector_state *conn_state) 1873 { 1874 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1875 1876 drm_WARN_ON(encoder->base.dev, !pipe_config->has_hdmi_sink); 1877 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 1878 pipe_name(crtc->pipe)); 1879 intel_audio_codec_enable(encoder, pipe_config, conn_state); 1880 } 1881 1882 static void g4x_enable_hdmi(struct intel_encoder *encoder, 1883 const struct intel_crtc_state *pipe_config, 1884 const struct drm_connector_state *conn_state) 1885 { 1886 struct drm_device *dev = encoder->base.dev; 1887 struct drm_i915_private *dev_priv = to_i915(dev); 1888 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1889 u32 temp; 1890 1891 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1892 1893 temp |= SDVO_ENABLE; 1894 if (pipe_config->has_audio) 1895 temp |= HDMI_AUDIO_ENABLE; 1896 1897 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1898 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1899 1900 if (pipe_config->has_audio) 1901 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1902 } 1903 1904 static void ibx_enable_hdmi(struct intel_encoder *encoder, 1905 const struct intel_crtc_state *pipe_config, 1906 const struct drm_connector_state *conn_state) 1907 { 1908 struct drm_device *dev = encoder->base.dev; 1909 struct drm_i915_private *dev_priv = to_i915(dev); 1910 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1911 u32 temp; 1912 1913 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1914 1915 temp |= SDVO_ENABLE; 1916 if (pipe_config->has_audio) 1917 temp |= HDMI_AUDIO_ENABLE; 1918 1919 /* 1920 * HW workaround, need to write this twice for issue 1921 * that may result in first write getting masked. 1922 */ 1923 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1924 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1925 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1926 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1927 1928 /* 1929 * HW workaround, need to toggle enable bit off and on 1930 * for 12bpc with pixel repeat. 1931 * 1932 * FIXME: BSpec says this should be done at the end of 1933 * of the modeset sequence, so not sure if this isn't too soon. 1934 */ 1935 if (pipe_config->pipe_bpp > 24 && 1936 pipe_config->pixel_multiplier > 1) { 1937 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 1938 temp & ~SDVO_ENABLE); 1939 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1940 1941 /* 1942 * HW workaround, need to write this twice for issue 1943 * that may result in first write getting masked. 1944 */ 1945 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1946 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1947 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1948 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1949 } 1950 1951 if (pipe_config->has_audio) 1952 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1953 } 1954 1955 static void cpt_enable_hdmi(struct intel_encoder *encoder, 1956 const struct intel_crtc_state *pipe_config, 1957 const struct drm_connector_state *conn_state) 1958 { 1959 struct drm_device *dev = encoder->base.dev; 1960 struct drm_i915_private *dev_priv = to_i915(dev); 1961 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1962 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1963 enum pipe pipe = crtc->pipe; 1964 u32 temp; 1965 1966 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1967 1968 temp |= SDVO_ENABLE; 1969 if (pipe_config->has_audio) 1970 temp |= HDMI_AUDIO_ENABLE; 1971 1972 /* 1973 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1974 * 1975 * The procedure for 12bpc is as follows: 1976 * 1. disable HDMI clock gating 1977 * 2. enable HDMI with 8bpc 1978 * 3. enable HDMI with 12bpc 1979 * 4. enable HDMI clock gating 1980 */ 1981 1982 if (pipe_config->pipe_bpp > 24) { 1983 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 1984 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1985 1986 temp &= ~SDVO_COLOR_FORMAT_MASK; 1987 temp |= SDVO_COLOR_FORMAT_8bpc; 1988 } 1989 1990 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1991 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1992 1993 if (pipe_config->pipe_bpp > 24) { 1994 temp &= ~SDVO_COLOR_FORMAT_MASK; 1995 temp |= HDMI_COLOR_FORMAT_12bpc; 1996 1997 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1998 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1999 2000 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 2001 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 2002 } 2003 2004 if (pipe_config->has_audio) 2005 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 2006 } 2007 2008 static void vlv_enable_hdmi(struct intel_encoder *encoder, 2009 const struct intel_crtc_state *pipe_config, 2010 const struct drm_connector_state *conn_state) 2011 { 2012 } 2013 2014 static void intel_disable_hdmi(struct intel_encoder *encoder, 2015 const struct intel_crtc_state *old_crtc_state, 2016 const struct drm_connector_state *old_conn_state) 2017 { 2018 struct drm_device *dev = encoder->base.dev; 2019 struct drm_i915_private *dev_priv = to_i915(dev); 2020 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2021 struct intel_digital_port *intel_dig_port = 2022 hdmi_to_dig_port(intel_hdmi); 2023 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2024 u32 temp; 2025 2026 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 2027 2028 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 2029 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2030 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2031 2032 /* 2033 * HW workaround for IBX, we need to move the port 2034 * to transcoder A after disabling it to allow the 2035 * matching DP port to be enabled on transcoder A. 2036 */ 2037 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 2038 /* 2039 * We get CPU/PCH FIFO underruns on the other pipe when 2040 * doing the workaround. Sweep them under the rug. 2041 */ 2042 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2043 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2044 2045 temp &= ~SDVO_PIPE_SEL_MASK; 2046 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 2047 /* 2048 * HW workaround, need to write this twice for issue 2049 * that may result in first write getting masked. 2050 */ 2051 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2052 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2053 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2054 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2055 2056 temp &= ~SDVO_ENABLE; 2057 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2058 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2059 2060 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 2061 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2062 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2063 } 2064 2065 intel_dig_port->set_infoframes(encoder, 2066 false, 2067 old_crtc_state, old_conn_state); 2068 2069 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2070 } 2071 2072 static void g4x_disable_hdmi(struct intel_encoder *encoder, 2073 const struct intel_crtc_state *old_crtc_state, 2074 const struct drm_connector_state *old_conn_state) 2075 { 2076 if (old_crtc_state->has_audio) 2077 intel_audio_codec_disable(encoder, 2078 old_crtc_state, old_conn_state); 2079 2080 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 2081 } 2082 2083 static void pch_disable_hdmi(struct intel_encoder *encoder, 2084 const struct intel_crtc_state *old_crtc_state, 2085 const struct drm_connector_state *old_conn_state) 2086 { 2087 if (old_crtc_state->has_audio) 2088 intel_audio_codec_disable(encoder, 2089 old_crtc_state, old_conn_state); 2090 } 2091 2092 static void pch_post_disable_hdmi(struct intel_encoder *encoder, 2093 const struct intel_crtc_state *old_crtc_state, 2094 const struct drm_connector_state *old_conn_state) 2095 { 2096 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 2097 } 2098 2099 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 2100 { 2101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2102 int max_tmds_clock, vbt_max_tmds_clock; 2103 2104 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2105 max_tmds_clock = 594000; 2106 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 2107 max_tmds_clock = 300000; 2108 else if (INTEL_GEN(dev_priv) >= 5) 2109 max_tmds_clock = 225000; 2110 else 2111 max_tmds_clock = 165000; 2112 2113 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); 2114 if (vbt_max_tmds_clock) 2115 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 2116 2117 return max_tmds_clock; 2118 } 2119 2120 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 2121 const struct drm_connector_state *conn_state) 2122 { 2123 return hdmi->has_hdmi_sink && 2124 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 2125 } 2126 2127 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 2128 bool respect_downstream_limits, 2129 bool has_hdmi_sink) 2130 { 2131 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2132 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 2133 2134 if (respect_downstream_limits) { 2135 struct intel_connector *connector = hdmi->attached_connector; 2136 const struct drm_display_info *info = &connector->base.display_info; 2137 2138 if (hdmi->dp_dual_mode.max_tmds_clock) 2139 max_tmds_clock = min(max_tmds_clock, 2140 hdmi->dp_dual_mode.max_tmds_clock); 2141 2142 if (info->max_tmds_clock) 2143 max_tmds_clock = min(max_tmds_clock, 2144 info->max_tmds_clock); 2145 else if (!has_hdmi_sink) 2146 max_tmds_clock = min(max_tmds_clock, 165000); 2147 } 2148 2149 return max_tmds_clock; 2150 } 2151 2152 static enum drm_mode_status 2153 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 2154 int clock, bool respect_downstream_limits, 2155 bool has_hdmi_sink) 2156 { 2157 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 2158 2159 if (clock < 25000) 2160 return MODE_CLOCK_LOW; 2161 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 2162 has_hdmi_sink)) 2163 return MODE_CLOCK_HIGH; 2164 2165 /* BXT DPLL can't generate 223-240 MHz */ 2166 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) 2167 return MODE_CLOCK_RANGE; 2168 2169 /* CHV DPLL can't generate 216-240 MHz */ 2170 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 2171 return MODE_CLOCK_RANGE; 2172 2173 return MODE_OK; 2174 } 2175 2176 static enum drm_mode_status 2177 intel_hdmi_mode_valid(struct drm_connector *connector, 2178 struct drm_display_mode *mode) 2179 { 2180 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2181 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 2182 struct drm_i915_private *dev_priv = to_i915(dev); 2183 enum drm_mode_status status; 2184 int clock = mode->clock; 2185 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 2186 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 2187 2188 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 2189 return MODE_NO_DBLESCAN; 2190 2191 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2192 clock *= 2; 2193 2194 if (clock > max_dotclk) 2195 return MODE_CLOCK_HIGH; 2196 2197 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2198 clock *= 2; 2199 2200 if (drm_mode_is_420_only(&connector->display_info, mode)) 2201 clock /= 2; 2202 2203 /* check if we can do 8bpc */ 2204 status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink); 2205 2206 if (has_hdmi_sink) { 2207 /* if we can't do 8bpc we may still be able to do 12bpc */ 2208 if (status != MODE_OK && !HAS_GMCH(dev_priv)) 2209 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, 2210 true, has_hdmi_sink); 2211 2212 /* if we can't do 8,12bpc we may still be able to do 10bpc */ 2213 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) 2214 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, 2215 true, has_hdmi_sink); 2216 } 2217 if (status != MODE_OK) 2218 return status; 2219 2220 return intel_mode_valid_max_plane_size(dev_priv, mode); 2221 } 2222 2223 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 2224 int bpc) 2225 { 2226 struct drm_i915_private *dev_priv = 2227 to_i915(crtc_state->uapi.crtc->dev); 2228 struct drm_atomic_state *state = crtc_state->uapi.state; 2229 struct drm_connector_state *connector_state; 2230 struct drm_connector *connector; 2231 const struct drm_display_mode *adjusted_mode = 2232 &crtc_state->hw.adjusted_mode; 2233 int i; 2234 2235 if (HAS_GMCH(dev_priv)) 2236 return false; 2237 2238 if (bpc == 10 && INTEL_GEN(dev_priv) < 11) 2239 return false; 2240 2241 if (crtc_state->pipe_bpp < bpc * 3) 2242 return false; 2243 2244 if (!crtc_state->has_hdmi_sink) 2245 return false; 2246 2247 /* 2248 * HDMI deep color affects the clocks, so it's only possible 2249 * when not cloning with other encoder types. 2250 */ 2251 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) 2252 return false; 2253 2254 for_each_new_connector_in_state(state, connector, connector_state, i) { 2255 const struct drm_display_info *info = &connector->display_info; 2256 2257 if (connector_state->crtc != crtc_state->uapi.crtc) 2258 continue; 2259 2260 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 2261 const struct drm_hdmi_info *hdmi = &info->hdmi; 2262 2263 if (bpc == 12 && !(hdmi->y420_dc_modes & 2264 DRM_EDID_YCBCR420_DC_36)) 2265 return false; 2266 else if (bpc == 10 && !(hdmi->y420_dc_modes & 2267 DRM_EDID_YCBCR420_DC_30)) 2268 return false; 2269 } else { 2270 if (bpc == 12 && !(info->edid_hdmi_dc_modes & 2271 DRM_EDID_HDMI_DC_36)) 2272 return false; 2273 else if (bpc == 10 && !(info->edid_hdmi_dc_modes & 2274 DRM_EDID_HDMI_DC_30)) 2275 return false; 2276 } 2277 } 2278 2279 /* Display WA #1139: glk */ 2280 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && 2281 adjusted_mode->htotal > 5460) 2282 return false; 2283 2284 /* Display Wa_1405510057:icl */ 2285 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 2286 bpc == 10 && INTEL_GEN(dev_priv) >= 11 && 2287 (adjusted_mode->crtc_hblank_end - 2288 adjusted_mode->crtc_hblank_start) % 8 == 2) 2289 return false; 2290 2291 return true; 2292 } 2293 2294 static bool 2295 intel_hdmi_ycbcr420_config(struct drm_connector *connector, 2296 struct intel_crtc_state *config) 2297 { 2298 struct intel_crtc *intel_crtc = to_intel_crtc(config->uapi.crtc); 2299 2300 if (!connector->ycbcr_420_allowed) { 2301 DRM_ERROR("Platform doesn't support YCBCR420 output\n"); 2302 return false; 2303 } 2304 2305 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2306 2307 /* YCBCR 420 output conversion needs a scaler */ 2308 if (skl_update_scaler_crtc(config)) { 2309 DRM_DEBUG_KMS("Scaler allocation for output failed\n"); 2310 return false; 2311 } 2312 2313 intel_pch_panel_fitting(intel_crtc, config, 2314 DRM_MODE_SCALE_FULLSCREEN); 2315 2316 return true; 2317 } 2318 2319 static int intel_hdmi_port_clock(int clock, int bpc) 2320 { 2321 /* 2322 * Need to adjust the port link by: 2323 * 1.5x for 12bpc 2324 * 1.25x for 10bpc 2325 */ 2326 return clock * bpc / 8; 2327 } 2328 2329 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2330 struct intel_crtc_state *crtc_state, 2331 int clock) 2332 { 2333 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2334 int bpc; 2335 2336 for (bpc = 12; bpc >= 10; bpc -= 2) { 2337 if (hdmi_deep_color_possible(crtc_state, bpc) && 2338 hdmi_port_clock_valid(intel_hdmi, 2339 intel_hdmi_port_clock(clock, bpc), 2340 true, crtc_state->has_hdmi_sink) == MODE_OK) 2341 return bpc; 2342 } 2343 2344 return 8; 2345 } 2346 2347 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2348 struct intel_crtc_state *crtc_state) 2349 { 2350 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2351 const struct drm_display_mode *adjusted_mode = 2352 &crtc_state->hw.adjusted_mode; 2353 int bpc, clock = adjusted_mode->crtc_clock; 2354 2355 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2356 clock *= 2; 2357 2358 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 2359 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2360 clock /= 2; 2361 2362 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock); 2363 2364 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); 2365 2366 /* 2367 * pipe_bpp could already be below 8bpc due to 2368 * FDI bandwidth constraints. We shouldn't bump it 2369 * back up to 8bpc in that case. 2370 */ 2371 if (crtc_state->pipe_bpp > bpc * 3) 2372 crtc_state->pipe_bpp = bpc * 3; 2373 2374 DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n", 2375 bpc, crtc_state->pipe_bpp); 2376 2377 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, 2378 false, crtc_state->has_hdmi_sink) != MODE_OK) { 2379 DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n", 2380 crtc_state->port_clock); 2381 return -EINVAL; 2382 } 2383 2384 return 0; 2385 } 2386 2387 static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2388 const struct drm_connector_state *conn_state) 2389 { 2390 const struct intel_digital_connector_state *intel_conn_state = 2391 to_intel_digital_connector_state(conn_state); 2392 const struct drm_display_mode *adjusted_mode = 2393 &crtc_state->hw.adjusted_mode; 2394 2395 /* 2396 * Our YCbCr output is always limited range. 2397 * crtc_state->limited_color_range only applies to RGB, 2398 * and it must never be set for YCbCr or we risk setting 2399 * some conflicting bits in PIPECONF which will mess up 2400 * the colors on the monitor. 2401 */ 2402 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2403 return false; 2404 2405 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2406 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2407 return crtc_state->has_hdmi_sink && 2408 drm_default_rgb_quant_range(adjusted_mode) == 2409 HDMI_QUANTIZATION_RANGE_LIMITED; 2410 } else { 2411 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2412 } 2413 } 2414 2415 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2416 struct intel_crtc_state *pipe_config, 2417 struct drm_connector_state *conn_state) 2418 { 2419 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2420 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2421 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2422 struct drm_connector *connector = conn_state->connector; 2423 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2424 struct intel_digital_connector_state *intel_conn_state = 2425 to_intel_digital_connector_state(conn_state); 2426 int ret; 2427 2428 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2429 return -EINVAL; 2430 2431 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2432 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, 2433 conn_state); 2434 2435 if (pipe_config->has_hdmi_sink) 2436 pipe_config->has_infoframe = true; 2437 2438 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2439 pipe_config->pixel_multiplier = 2; 2440 2441 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { 2442 if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) { 2443 DRM_ERROR("Can't support YCBCR420 output\n"); 2444 return -EINVAL; 2445 } 2446 } 2447 2448 pipe_config->limited_color_range = 2449 intel_hdmi_limited_color_range(pipe_config, conn_state); 2450 2451 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 2452 pipe_config->has_pch_encoder = true; 2453 2454 if (pipe_config->has_hdmi_sink) { 2455 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2456 pipe_config->has_audio = intel_hdmi->has_audio; 2457 else 2458 pipe_config->has_audio = 2459 intel_conn_state->force_audio == HDMI_AUDIO_ON; 2460 } 2461 2462 ret = intel_hdmi_compute_clock(encoder, pipe_config); 2463 if (ret) 2464 return ret; 2465 2466 if (conn_state->picture_aspect_ratio) 2467 adjusted_mode->picture_aspect_ratio = 2468 conn_state->picture_aspect_ratio; 2469 2470 pipe_config->lane_count = 4; 2471 2472 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || 2473 IS_GEMINILAKE(dev_priv))) { 2474 if (scdc->scrambling.low_rates) 2475 pipe_config->hdmi_scrambling = true; 2476 2477 if (pipe_config->port_clock > 340000) { 2478 pipe_config->hdmi_scrambling = true; 2479 pipe_config->hdmi_high_tmds_clock_ratio = true; 2480 } 2481 } 2482 2483 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); 2484 2485 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2486 DRM_DEBUG_KMS("bad AVI infoframe\n"); 2487 return -EINVAL; 2488 } 2489 2490 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2491 DRM_DEBUG_KMS("bad SPD infoframe\n"); 2492 return -EINVAL; 2493 } 2494 2495 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2496 DRM_DEBUG_KMS("bad HDMI infoframe\n"); 2497 return -EINVAL; 2498 } 2499 2500 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2501 DRM_DEBUG_KMS("bad DRM infoframe\n"); 2502 return -EINVAL; 2503 } 2504 2505 return 0; 2506 } 2507 2508 static void 2509 intel_hdmi_unset_edid(struct drm_connector *connector) 2510 { 2511 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2512 2513 intel_hdmi->has_hdmi_sink = false; 2514 intel_hdmi->has_audio = false; 2515 2516 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2517 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2518 2519 kfree(to_intel_connector(connector)->detect_edid); 2520 to_intel_connector(connector)->detect_edid = NULL; 2521 } 2522 2523 static void 2524 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 2525 { 2526 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2527 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2528 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2529 struct i2c_adapter *adapter = 2530 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2531 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); 2532 2533 /* 2534 * Type 1 DVI adaptors are not required to implement any 2535 * registers, so we can't always detect their presence. 2536 * Ideally we should be able to check the state of the 2537 * CONFIG1 pin, but no such luck on our hardware. 2538 * 2539 * The only method left to us is to check the VBT to see 2540 * if the port is a dual mode capable DP port. But let's 2541 * only do that when we sucesfully read the EDID, to avoid 2542 * confusing log messages about DP dual mode adaptors when 2543 * there's nothing connected to the port. 2544 */ 2545 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2546 /* An overridden EDID imply that we want this port for testing. 2547 * Make sure not to set limits for that port. 2548 */ 2549 if (has_edid && !connector->override_edid && 2550 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2551 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); 2552 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2553 } else { 2554 type = DRM_DP_DUAL_MODE_NONE; 2555 } 2556 } 2557 2558 if (type == DRM_DP_DUAL_MODE_NONE) 2559 return; 2560 2561 hdmi->dp_dual_mode.type = type; 2562 hdmi->dp_dual_mode.max_tmds_clock = 2563 drm_dp_dual_mode_max_tmds_clock(type, adapter); 2564 2565 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2566 drm_dp_get_dual_mode_type_name(type), 2567 hdmi->dp_dual_mode.max_tmds_clock); 2568 } 2569 2570 static bool 2571 intel_hdmi_set_edid(struct drm_connector *connector) 2572 { 2573 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2574 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2575 intel_wakeref_t wakeref; 2576 struct edid *edid; 2577 bool connected = false; 2578 struct i2c_adapter *i2c; 2579 2580 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2581 2582 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2583 2584 edid = drm_get_edid(connector, i2c); 2585 2586 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2587 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2588 intel_gmbus_force_bit(i2c, true); 2589 edid = drm_get_edid(connector, i2c); 2590 intel_gmbus_force_bit(i2c, false); 2591 } 2592 2593 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 2594 2595 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2596 2597 to_intel_connector(connector)->detect_edid = edid; 2598 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2599 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2600 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2601 2602 connected = true; 2603 } 2604 2605 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2606 2607 return connected; 2608 } 2609 2610 static enum drm_connector_status 2611 intel_hdmi_detect(struct drm_connector *connector, bool force) 2612 { 2613 enum drm_connector_status status = connector_status_disconnected; 2614 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2615 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2616 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2617 intel_wakeref_t wakeref; 2618 2619 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2620 connector->base.id, connector->name); 2621 2622 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2623 2624 if (INTEL_GEN(dev_priv) >= 11 && 2625 !intel_digital_port_connected(encoder)) 2626 goto out; 2627 2628 intel_hdmi_unset_edid(connector); 2629 2630 if (intel_hdmi_set_edid(connector)) 2631 status = connector_status_connected; 2632 2633 out: 2634 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2635 2636 if (status != connector_status_connected) 2637 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2638 2639 /* 2640 * Make sure the refs for power wells enabled during detect are 2641 * dropped to avoid a new detect cycle triggered by HPD polling. 2642 */ 2643 intel_display_power_flush_work(dev_priv); 2644 2645 return status; 2646 } 2647 2648 static void 2649 intel_hdmi_force(struct drm_connector *connector) 2650 { 2651 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2652 connector->base.id, connector->name); 2653 2654 intel_hdmi_unset_edid(connector); 2655 2656 if (connector->status != connector_status_connected) 2657 return; 2658 2659 intel_hdmi_set_edid(connector); 2660 } 2661 2662 static int intel_hdmi_get_modes(struct drm_connector *connector) 2663 { 2664 struct edid *edid; 2665 2666 edid = to_intel_connector(connector)->detect_edid; 2667 if (edid == NULL) 2668 return 0; 2669 2670 return intel_connector_update_modes(connector, edid); 2671 } 2672 2673 static void intel_hdmi_pre_enable(struct intel_encoder *encoder, 2674 const struct intel_crtc_state *pipe_config, 2675 const struct drm_connector_state *conn_state) 2676 { 2677 struct intel_digital_port *intel_dig_port = 2678 enc_to_dig_port(encoder); 2679 2680 intel_hdmi_prepare(encoder, pipe_config); 2681 2682 intel_dig_port->set_infoframes(encoder, 2683 pipe_config->has_infoframe, 2684 pipe_config, conn_state); 2685 } 2686 2687 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, 2688 const struct intel_crtc_state *pipe_config, 2689 const struct drm_connector_state *conn_state) 2690 { 2691 struct intel_digital_port *dport = enc_to_dig_port(encoder); 2692 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2693 2694 vlv_phy_pre_encoder_enable(encoder, pipe_config); 2695 2696 /* HDMI 1.0V-2dB */ 2697 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 2698 0x2b247878); 2699 2700 dport->set_infoframes(encoder, 2701 pipe_config->has_infoframe, 2702 pipe_config, conn_state); 2703 2704 g4x_enable_hdmi(encoder, pipe_config, conn_state); 2705 2706 vlv_wait_port_ready(dev_priv, dport, 0x0); 2707 } 2708 2709 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 2710 const struct intel_crtc_state *pipe_config, 2711 const struct drm_connector_state *conn_state) 2712 { 2713 intel_hdmi_prepare(encoder, pipe_config); 2714 2715 vlv_phy_pre_pll_enable(encoder, pipe_config); 2716 } 2717 2718 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 2719 const struct intel_crtc_state *pipe_config, 2720 const struct drm_connector_state *conn_state) 2721 { 2722 intel_hdmi_prepare(encoder, pipe_config); 2723 2724 chv_phy_pre_pll_enable(encoder, pipe_config); 2725 } 2726 2727 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, 2728 const struct intel_crtc_state *old_crtc_state, 2729 const struct drm_connector_state *old_conn_state) 2730 { 2731 chv_phy_post_pll_disable(encoder, old_crtc_state); 2732 } 2733 2734 static void vlv_hdmi_post_disable(struct intel_encoder *encoder, 2735 const struct intel_crtc_state *old_crtc_state, 2736 const struct drm_connector_state *old_conn_state) 2737 { 2738 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 2739 vlv_phy_reset_lanes(encoder, old_crtc_state); 2740 } 2741 2742 static void chv_hdmi_post_disable(struct intel_encoder *encoder, 2743 const struct intel_crtc_state *old_crtc_state, 2744 const struct drm_connector_state *old_conn_state) 2745 { 2746 struct drm_device *dev = encoder->base.dev; 2747 struct drm_i915_private *dev_priv = to_i915(dev); 2748 2749 vlv_dpio_get(dev_priv); 2750 2751 /* Assert data lane reset */ 2752 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 2753 2754 vlv_dpio_put(dev_priv); 2755 } 2756 2757 static void chv_hdmi_pre_enable(struct intel_encoder *encoder, 2758 const struct intel_crtc_state *pipe_config, 2759 const struct drm_connector_state *conn_state) 2760 { 2761 struct intel_digital_port *dport = enc_to_dig_port(encoder); 2762 struct drm_device *dev = encoder->base.dev; 2763 struct drm_i915_private *dev_priv = to_i915(dev); 2764 2765 chv_phy_pre_encoder_enable(encoder, pipe_config); 2766 2767 /* FIXME: Program the support xxx V-dB */ 2768 /* Use 800mV-0dB */ 2769 chv_set_phy_signal_level(encoder, 128, 102, false); 2770 2771 dport->set_infoframes(encoder, 2772 pipe_config->has_infoframe, 2773 pipe_config, conn_state); 2774 2775 g4x_enable_hdmi(encoder, pipe_config, conn_state); 2776 2777 vlv_wait_port_ready(dev_priv, dport, 0x0); 2778 2779 /* Second common lane will stay alive on its own now */ 2780 chv_phy_release_cl2_override(encoder); 2781 } 2782 2783 static struct i2c_adapter * 2784 intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2785 { 2786 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2787 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2788 2789 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2790 } 2791 2792 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2793 { 2794 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2795 struct kobject *i2c_kobj = &adapter->dev.kobj; 2796 struct kobject *connector_kobj = &connector->kdev->kobj; 2797 int ret; 2798 2799 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2800 if (ret) 2801 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret); 2802 } 2803 2804 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2805 { 2806 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2807 struct kobject *i2c_kobj = &adapter->dev.kobj; 2808 struct kobject *connector_kobj = &connector->kdev->kobj; 2809 2810 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2811 } 2812 2813 static int 2814 intel_hdmi_connector_register(struct drm_connector *connector) 2815 { 2816 int ret; 2817 2818 ret = intel_connector_register(connector); 2819 if (ret) 2820 return ret; 2821 2822 intel_connector_debugfs_add(connector); 2823 2824 intel_hdmi_create_i2c_symlink(connector); 2825 2826 return ret; 2827 } 2828 2829 static void intel_hdmi_destroy(struct drm_connector *connector) 2830 { 2831 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2832 2833 cec_notifier_conn_unregister(n); 2834 2835 intel_connector_destroy(connector); 2836 } 2837 2838 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2839 { 2840 intel_hdmi_remove_i2c_symlink(connector); 2841 2842 intel_connector_unregister(connector); 2843 } 2844 2845 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2846 .detect = intel_hdmi_detect, 2847 .force = intel_hdmi_force, 2848 .fill_modes = drm_helper_probe_single_connector_modes, 2849 .atomic_get_property = intel_digital_connector_atomic_get_property, 2850 .atomic_set_property = intel_digital_connector_atomic_set_property, 2851 .late_register = intel_hdmi_connector_register, 2852 .early_unregister = intel_hdmi_connector_unregister, 2853 .destroy = intel_hdmi_destroy, 2854 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2855 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2856 }; 2857 2858 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2859 .get_modes = intel_hdmi_get_modes, 2860 .mode_valid = intel_hdmi_mode_valid, 2861 .atomic_check = intel_digital_connector_atomic_check, 2862 }; 2863 2864 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 2865 .destroy = intel_encoder_destroy, 2866 }; 2867 2868 static void 2869 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2870 { 2871 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2872 struct intel_digital_port *intel_dig_port = 2873 hdmi_to_dig_port(intel_hdmi); 2874 2875 intel_attach_force_audio_property(connector); 2876 intel_attach_broadcast_rgb_property(connector); 2877 intel_attach_aspect_ratio_property(connector); 2878 2879 /* 2880 * Attach Colorspace property for Non LSPCON based device 2881 * ToDo: This needs to be extended for LSPCON implementation 2882 * as well. Will be implemented separately. 2883 */ 2884 if (!intel_dig_port->lspcon.active) 2885 intel_attach_colorspace_property(connector); 2886 2887 drm_connector_attach_content_type_property(connector); 2888 2889 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2890 drm_object_attach_property(&connector->base, 2891 connector->dev->mode_config.hdr_output_metadata_property, 0); 2892 2893 if (!HAS_GMCH(dev_priv)) 2894 drm_connector_attach_max_bpc_property(connector, 8, 12); 2895 } 2896 2897 /* 2898 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2899 * @encoder: intel_encoder 2900 * @connector: drm_connector 2901 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2902 * or reset the high tmds clock ratio for scrambling 2903 * @scrambling: bool to Indicate if the function needs to set or reset 2904 * sink scrambling 2905 * 2906 * This function handles scrambling on HDMI 2.0 capable sinks. 2907 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2908 * it enables scrambling. This should be called before enabling the HDMI 2909 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2910 * detect a scrambled clock within 100 ms. 2911 * 2912 * Returns: 2913 * True on success, false on failure. 2914 */ 2915 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2916 struct drm_connector *connector, 2917 bool high_tmds_clock_ratio, 2918 bool scrambling) 2919 { 2920 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2921 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2922 struct drm_scrambling *sink_scrambling = 2923 &connector->display_info.hdmi.scdc.scrambling; 2924 struct i2c_adapter *adapter = 2925 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2926 2927 if (!sink_scrambling->supported) 2928 return true; 2929 2930 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2931 connector->base.id, connector->name, 2932 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); 2933 2934 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2935 return drm_scdc_set_high_tmds_clock_ratio(adapter, 2936 high_tmds_clock_ratio) && 2937 drm_scdc_set_scrambling(adapter, scrambling); 2938 } 2939 2940 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2941 { 2942 u8 ddc_pin; 2943 2944 switch (port) { 2945 case PORT_B: 2946 ddc_pin = GMBUS_PIN_DPB; 2947 break; 2948 case PORT_C: 2949 ddc_pin = GMBUS_PIN_DPC; 2950 break; 2951 case PORT_D: 2952 ddc_pin = GMBUS_PIN_DPD_CHV; 2953 break; 2954 default: 2955 MISSING_CASE(port); 2956 ddc_pin = GMBUS_PIN_DPB; 2957 break; 2958 } 2959 return ddc_pin; 2960 } 2961 2962 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2963 { 2964 u8 ddc_pin; 2965 2966 switch (port) { 2967 case PORT_B: 2968 ddc_pin = GMBUS_PIN_1_BXT; 2969 break; 2970 case PORT_C: 2971 ddc_pin = GMBUS_PIN_2_BXT; 2972 break; 2973 default: 2974 MISSING_CASE(port); 2975 ddc_pin = GMBUS_PIN_1_BXT; 2976 break; 2977 } 2978 return ddc_pin; 2979 } 2980 2981 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2982 enum port port) 2983 { 2984 u8 ddc_pin; 2985 2986 switch (port) { 2987 case PORT_B: 2988 ddc_pin = GMBUS_PIN_1_BXT; 2989 break; 2990 case PORT_C: 2991 ddc_pin = GMBUS_PIN_2_BXT; 2992 break; 2993 case PORT_D: 2994 ddc_pin = GMBUS_PIN_4_CNP; 2995 break; 2996 case PORT_F: 2997 ddc_pin = GMBUS_PIN_3_BXT; 2998 break; 2999 default: 3000 MISSING_CASE(port); 3001 ddc_pin = GMBUS_PIN_1_BXT; 3002 break; 3003 } 3004 return ddc_pin; 3005 } 3006 3007 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3008 { 3009 enum phy phy = intel_port_to_phy(dev_priv, port); 3010 3011 if (intel_phy_is_combo(dev_priv, phy)) 3012 return GMBUS_PIN_1_BXT + port; 3013 else if (intel_phy_is_tc(dev_priv, phy)) 3014 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 3015 3016 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 3017 return GMBUS_PIN_2_BXT; 3018 } 3019 3020 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3021 { 3022 enum phy phy = intel_port_to_phy(dev_priv, port); 3023 u8 ddc_pin; 3024 3025 switch (phy) { 3026 case PHY_A: 3027 ddc_pin = GMBUS_PIN_1_BXT; 3028 break; 3029 case PHY_B: 3030 ddc_pin = GMBUS_PIN_2_BXT; 3031 break; 3032 case PHY_C: 3033 ddc_pin = GMBUS_PIN_9_TC1_ICP; 3034 break; 3035 default: 3036 MISSING_CASE(phy); 3037 ddc_pin = GMBUS_PIN_1_BXT; 3038 break; 3039 } 3040 return ddc_pin; 3041 } 3042 3043 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 3044 enum port port) 3045 { 3046 u8 ddc_pin; 3047 3048 switch (port) { 3049 case PORT_B: 3050 ddc_pin = GMBUS_PIN_DPB; 3051 break; 3052 case PORT_C: 3053 ddc_pin = GMBUS_PIN_DPC; 3054 break; 3055 case PORT_D: 3056 ddc_pin = GMBUS_PIN_DPD; 3057 break; 3058 default: 3059 MISSING_CASE(port); 3060 ddc_pin = GMBUS_PIN_DPB; 3061 break; 3062 } 3063 return ddc_pin; 3064 } 3065 3066 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 3067 { 3068 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3069 enum port port = encoder->port; 3070 u8 ddc_pin; 3071 3072 ddc_pin = intel_bios_alternate_ddc_pin(encoder); 3073 if (ddc_pin) { 3074 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", 3075 ddc_pin, port_name(port)); 3076 return ddc_pin; 3077 } 3078 3079 if (HAS_PCH_MCC(dev_priv)) 3080 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 3081 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3082 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 3083 else if (HAS_PCH_CNP(dev_priv)) 3084 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 3085 else if (IS_GEN9_LP(dev_priv)) 3086 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 3087 else if (IS_CHERRYVIEW(dev_priv)) 3088 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 3089 else 3090 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 3091 3092 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", 3093 ddc_pin, port_name(port)); 3094 3095 return ddc_pin; 3096 } 3097 3098 void intel_infoframe_init(struct intel_digital_port *intel_dig_port) 3099 { 3100 struct drm_i915_private *dev_priv = 3101 to_i915(intel_dig_port->base.base.dev); 3102 3103 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3104 intel_dig_port->write_infoframe = vlv_write_infoframe; 3105 intel_dig_port->read_infoframe = vlv_read_infoframe; 3106 intel_dig_port->set_infoframes = vlv_set_infoframes; 3107 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; 3108 } else if (IS_G4X(dev_priv)) { 3109 intel_dig_port->write_infoframe = g4x_write_infoframe; 3110 intel_dig_port->read_infoframe = g4x_read_infoframe; 3111 intel_dig_port->set_infoframes = g4x_set_infoframes; 3112 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; 3113 } else if (HAS_DDI(dev_priv)) { 3114 if (intel_dig_port->lspcon.active) { 3115 intel_dig_port->write_infoframe = lspcon_write_infoframe; 3116 intel_dig_port->read_infoframe = lspcon_read_infoframe; 3117 intel_dig_port->set_infoframes = lspcon_set_infoframes; 3118 intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3119 } else { 3120 intel_dig_port->write_infoframe = hsw_write_infoframe; 3121 intel_dig_port->read_infoframe = hsw_read_infoframe; 3122 intel_dig_port->set_infoframes = hsw_set_infoframes; 3123 intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; 3124 } 3125 } else if (HAS_PCH_IBX(dev_priv)) { 3126 intel_dig_port->write_infoframe = ibx_write_infoframe; 3127 intel_dig_port->read_infoframe = ibx_read_infoframe; 3128 intel_dig_port->set_infoframes = ibx_set_infoframes; 3129 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; 3130 } else { 3131 intel_dig_port->write_infoframe = cpt_write_infoframe; 3132 intel_dig_port->read_infoframe = cpt_read_infoframe; 3133 intel_dig_port->set_infoframes = cpt_set_infoframes; 3134 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; 3135 } 3136 } 3137 3138 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 3139 struct intel_connector *intel_connector) 3140 { 3141 struct drm_connector *connector = &intel_connector->base; 3142 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3143 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3144 struct drm_device *dev = intel_encoder->base.dev; 3145 struct drm_i915_private *dev_priv = to_i915(dev); 3146 struct i2c_adapter *ddc; 3147 enum port port = intel_encoder->port; 3148 struct cec_connector_info conn_info; 3149 3150 DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n", 3151 intel_encoder->base.base.id, intel_encoder->base.name); 3152 3153 if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3154 return; 3155 3156 if (drm_WARN(dev, intel_dig_port->max_lanes < 4, 3157 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3158 intel_dig_port->max_lanes, intel_encoder->base.base.id, 3159 intel_encoder->base.name)) 3160 return; 3161 3162 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); 3163 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 3164 3165 drm_connector_init_with_ddc(dev, connector, 3166 &intel_hdmi_connector_funcs, 3167 DRM_MODE_CONNECTOR_HDMIA, 3168 ddc); 3169 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3170 3171 connector->interlace_allowed = 1; 3172 connector->doublescan_allowed = 0; 3173 connector->stereo_allowed = 1; 3174 3175 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 3176 connector->ycbcr_420_allowed = true; 3177 3178 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 3179 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3180 3181 if (HAS_DDI(dev_priv)) 3182 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3183 else 3184 intel_connector->get_hw_state = intel_connector_get_hw_state; 3185 3186 intel_hdmi_add_properties(intel_hdmi, connector); 3187 3188 intel_connector_attach_encoder(intel_connector, intel_encoder); 3189 intel_hdmi->attached_connector = intel_connector; 3190 3191 if (is_hdcp_supported(dev_priv, port)) { 3192 int ret = intel_hdcp_init(intel_connector, 3193 &intel_hdmi_hdcp_shim); 3194 if (ret) 3195 DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); 3196 } 3197 3198 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3199 * 0xd. Failure to do so will result in spurious interrupts being 3200 * generated on the port when a cable is not attached. 3201 */ 3202 if (IS_G45(dev_priv)) { 3203 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 3204 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 3205 (temp & ~0xf) | 0xd); 3206 } 3207 3208 cec_fill_conn_info_from_drm(&conn_info, connector); 3209 3210 intel_hdmi->cec_notifier = 3211 cec_notifier_conn_register(dev->dev, port_identifier(port), 3212 &conn_info); 3213 if (!intel_hdmi->cec_notifier) 3214 DRM_DEBUG_KMS("CEC notifier get failed\n"); 3215 } 3216 3217 static enum intel_hotplug_state 3218 intel_hdmi_hotplug(struct intel_encoder *encoder, 3219 struct intel_connector *connector, bool irq_received) 3220 { 3221 enum intel_hotplug_state state; 3222 3223 state = intel_encoder_hotplug(encoder, connector, irq_received); 3224 3225 /* 3226 * On many platforms the HDMI live state signal is known to be 3227 * unreliable, so we can't use it to detect if a sink is connected or 3228 * not. Instead we detect if it's connected based on whether we can 3229 * read the EDID or not. That in turn has a problem during disconnect, 3230 * since the HPD interrupt may be raised before the DDC lines get 3231 * disconnected (due to how the required length of DDC vs. HPD 3232 * connector pins are specified) and so we'll still be able to get a 3233 * valid EDID. To solve this schedule another detection cycle if this 3234 * time around we didn't detect any change in the sink's connection 3235 * status. 3236 */ 3237 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received) 3238 state = INTEL_HOTPLUG_RETRY; 3239 3240 return state; 3241 } 3242 3243 void intel_hdmi_init(struct drm_i915_private *dev_priv, 3244 i915_reg_t hdmi_reg, enum port port) 3245 { 3246 struct intel_digital_port *intel_dig_port; 3247 struct intel_encoder *intel_encoder; 3248 struct intel_connector *intel_connector; 3249 3250 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3251 if (!intel_dig_port) 3252 return; 3253 3254 intel_connector = intel_connector_alloc(); 3255 if (!intel_connector) { 3256 kfree(intel_dig_port); 3257 return; 3258 } 3259 3260 intel_encoder = &intel_dig_port->base; 3261 3262 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3263 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 3264 "HDMI %c", port_name(port)); 3265 3266 intel_encoder->hotplug = intel_hdmi_hotplug; 3267 intel_encoder->compute_config = intel_hdmi_compute_config; 3268 if (HAS_PCH_SPLIT(dev_priv)) { 3269 intel_encoder->disable = pch_disable_hdmi; 3270 intel_encoder->post_disable = pch_post_disable_hdmi; 3271 } else { 3272 intel_encoder->disable = g4x_disable_hdmi; 3273 } 3274 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 3275 intel_encoder->get_config = intel_hdmi_get_config; 3276 if (IS_CHERRYVIEW(dev_priv)) { 3277 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 3278 intel_encoder->pre_enable = chv_hdmi_pre_enable; 3279 intel_encoder->enable = vlv_enable_hdmi; 3280 intel_encoder->post_disable = chv_hdmi_post_disable; 3281 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 3282 } else if (IS_VALLEYVIEW(dev_priv)) { 3283 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 3284 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 3285 intel_encoder->enable = vlv_enable_hdmi; 3286 intel_encoder->post_disable = vlv_hdmi_post_disable; 3287 } else { 3288 intel_encoder->pre_enable = intel_hdmi_pre_enable; 3289 if (HAS_PCH_CPT(dev_priv)) 3290 intel_encoder->enable = cpt_enable_hdmi; 3291 else if (HAS_PCH_IBX(dev_priv)) 3292 intel_encoder->enable = ibx_enable_hdmi; 3293 else 3294 intel_encoder->enable = g4x_enable_hdmi; 3295 } 3296 3297 intel_encoder->type = INTEL_OUTPUT_HDMI; 3298 intel_encoder->power_domain = intel_port_to_power_domain(port); 3299 intel_encoder->port = port; 3300 if (IS_CHERRYVIEW(dev_priv)) { 3301 if (port == PORT_D) 3302 intel_encoder->pipe_mask = BIT(PIPE_C); 3303 else 3304 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 3305 } else { 3306 intel_encoder->pipe_mask = ~0; 3307 } 3308 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 3309 /* 3310 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 3311 * to work on real hardware. And since g4x can send infoframes to 3312 * only one port anyway, nothing is lost by allowing it. 3313 */ 3314 if (IS_G4X(dev_priv)) 3315 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 3316 3317 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 3318 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 3319 intel_dig_port->max_lanes = 4; 3320 3321 intel_infoframe_init(intel_dig_port); 3322 3323 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 3324 intel_hdmi_init_connector(intel_dig_port, intel_connector); 3325 } 3326