1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_hdcp.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <drm/intel_lpe_audio.h> 40 41 #include "i915_debugfs.h" 42 #include "i915_drv.h" 43 #include "intel_atomic.h" 44 #include "intel_audio.h" 45 #include "intel_connector.h" 46 #include "intel_ddi.h" 47 #include "intel_display_types.h" 48 #include "intel_dp.h" 49 #include "intel_dpio_phy.h" 50 #include "intel_fifo_underrun.h" 51 #include "intel_gmbus.h" 52 #include "intel_hdcp.h" 53 #include "intel_hdmi.h" 54 #include "intel_hotplug.h" 55 #include "intel_lspcon.h" 56 #include "intel_panel.h" 57 #include "intel_sdvo.h" 58 #include "intel_sideband.h" 59 60 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 61 { 62 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 63 } 64 65 static void 66 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 67 { 68 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 69 struct drm_i915_private *dev_priv = to_i915(dev); 70 u32 enabled_bits; 71 72 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 73 74 drm_WARN(dev, 75 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 76 "HDMI port enabled, expecting disabled\n"); 77 } 78 79 static void 80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 81 enum transcoder cpu_transcoder) 82 { 83 drm_WARN(&dev_priv->drm, 84 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 85 TRANS_DDI_FUNC_ENABLE, 86 "HDMI transcoder function enabled, expecting disabled\n"); 87 } 88 89 struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) 90 { 91 struct intel_digital_port *dig_port = 92 container_of(&encoder->base, struct intel_digital_port, 93 base.base); 94 return &dig_port->hdmi; 95 } 96 97 static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector) 98 { 99 return enc_to_intel_hdmi(intel_attached_encoder(connector)); 100 } 101 102 static u32 g4x_infoframe_index(unsigned int type) 103 { 104 switch (type) { 105 case HDMI_PACKET_TYPE_GAMUT_METADATA: 106 return VIDEO_DIP_SELECT_GAMUT; 107 case HDMI_INFOFRAME_TYPE_AVI: 108 return VIDEO_DIP_SELECT_AVI; 109 case HDMI_INFOFRAME_TYPE_SPD: 110 return VIDEO_DIP_SELECT_SPD; 111 case HDMI_INFOFRAME_TYPE_VENDOR: 112 return VIDEO_DIP_SELECT_VENDOR; 113 default: 114 MISSING_CASE(type); 115 return 0; 116 } 117 } 118 119 static u32 g4x_infoframe_enable(unsigned int type) 120 { 121 switch (type) { 122 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 123 return VIDEO_DIP_ENABLE_GCP; 124 case HDMI_PACKET_TYPE_GAMUT_METADATA: 125 return VIDEO_DIP_ENABLE_GAMUT; 126 case DP_SDP_VSC: 127 return 0; 128 case HDMI_INFOFRAME_TYPE_AVI: 129 return VIDEO_DIP_ENABLE_AVI; 130 case HDMI_INFOFRAME_TYPE_SPD: 131 return VIDEO_DIP_ENABLE_SPD; 132 case HDMI_INFOFRAME_TYPE_VENDOR: 133 return VIDEO_DIP_ENABLE_VENDOR; 134 case HDMI_INFOFRAME_TYPE_DRM: 135 return 0; 136 default: 137 MISSING_CASE(type); 138 return 0; 139 } 140 } 141 142 static u32 hsw_infoframe_enable(unsigned int type) 143 { 144 switch (type) { 145 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 146 return VIDEO_DIP_ENABLE_GCP_HSW; 147 case HDMI_PACKET_TYPE_GAMUT_METADATA: 148 return VIDEO_DIP_ENABLE_GMP_HSW; 149 case DP_SDP_VSC: 150 return VIDEO_DIP_ENABLE_VSC_HSW; 151 case DP_SDP_PPS: 152 return VDIP_ENABLE_PPS; 153 case HDMI_INFOFRAME_TYPE_AVI: 154 return VIDEO_DIP_ENABLE_AVI_HSW; 155 case HDMI_INFOFRAME_TYPE_SPD: 156 return VIDEO_DIP_ENABLE_SPD_HSW; 157 case HDMI_INFOFRAME_TYPE_VENDOR: 158 return VIDEO_DIP_ENABLE_VS_HSW; 159 case HDMI_INFOFRAME_TYPE_DRM: 160 return VIDEO_DIP_ENABLE_DRM_GLK; 161 default: 162 MISSING_CASE(type); 163 return 0; 164 } 165 } 166 167 static i915_reg_t 168 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 169 enum transcoder cpu_transcoder, 170 unsigned int type, 171 int i) 172 { 173 switch (type) { 174 case HDMI_PACKET_TYPE_GAMUT_METADATA: 175 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 176 case DP_SDP_VSC: 177 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 178 case DP_SDP_PPS: 179 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 180 case HDMI_INFOFRAME_TYPE_AVI: 181 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 182 case HDMI_INFOFRAME_TYPE_SPD: 183 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 184 case HDMI_INFOFRAME_TYPE_VENDOR: 185 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 186 case HDMI_INFOFRAME_TYPE_DRM: 187 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 188 default: 189 MISSING_CASE(type); 190 return INVALID_MMIO_REG; 191 } 192 } 193 194 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 195 unsigned int type) 196 { 197 switch (type) { 198 case DP_SDP_VSC: 199 return VIDEO_DIP_VSC_DATA_SIZE; 200 case DP_SDP_PPS: 201 return VIDEO_DIP_PPS_DATA_SIZE; 202 case HDMI_PACKET_TYPE_GAMUT_METADATA: 203 if (INTEL_GEN(dev_priv) >= 11) 204 return VIDEO_DIP_GMP_DATA_SIZE; 205 else 206 return VIDEO_DIP_DATA_SIZE; 207 default: 208 return VIDEO_DIP_DATA_SIZE; 209 } 210 } 211 212 static void g4x_write_infoframe(struct intel_encoder *encoder, 213 const struct intel_crtc_state *crtc_state, 214 unsigned int type, 215 const void *frame, ssize_t len) 216 { 217 const u32 *data = frame; 218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 219 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 220 int i; 221 222 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 223 "Writing DIP with CTL reg disabled\n"); 224 225 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 226 val |= g4x_infoframe_index(type); 227 228 val &= ~g4x_infoframe_enable(type); 229 230 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 231 232 for (i = 0; i < len; i += 4) { 233 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 234 data++; 235 } 236 /* Write every possible data byte to force correct ECC calculation. */ 237 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 238 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 239 240 val |= g4x_infoframe_enable(type); 241 val &= ~VIDEO_DIP_FREQ_MASK; 242 val |= VIDEO_DIP_FREQ_VSYNC; 243 244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 245 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 246 } 247 248 static void g4x_read_infoframe(struct intel_encoder *encoder, 249 const struct intel_crtc_state *crtc_state, 250 unsigned int type, 251 void *frame, ssize_t len) 252 { 253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 254 u32 val, *data = frame; 255 int i; 256 257 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 258 259 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 260 val |= g4x_infoframe_index(type); 261 262 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 263 264 for (i = 0; i < len; i += 4) 265 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 266 } 267 268 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 269 const struct intel_crtc_state *pipe_config) 270 { 271 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 272 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 273 274 if ((val & VIDEO_DIP_ENABLE) == 0) 275 return 0; 276 277 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 278 return 0; 279 280 return val & (VIDEO_DIP_ENABLE_AVI | 281 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 282 } 283 284 static void ibx_write_infoframe(struct intel_encoder *encoder, 285 const struct intel_crtc_state *crtc_state, 286 unsigned int type, 287 const void *frame, ssize_t len) 288 { 289 const u32 *data = frame; 290 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 292 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 293 u32 val = intel_de_read(dev_priv, reg); 294 int i; 295 296 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 297 "Writing DIP with CTL reg disabled\n"); 298 299 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 300 val |= g4x_infoframe_index(type); 301 302 val &= ~g4x_infoframe_enable(type); 303 304 intel_de_write(dev_priv, reg, val); 305 306 for (i = 0; i < len; i += 4) { 307 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 308 *data); 309 data++; 310 } 311 /* Write every possible data byte to force correct ECC calculation. */ 312 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 313 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 314 315 val |= g4x_infoframe_enable(type); 316 val &= ~VIDEO_DIP_FREQ_MASK; 317 val |= VIDEO_DIP_FREQ_VSYNC; 318 319 intel_de_write(dev_priv, reg, val); 320 intel_de_posting_read(dev_priv, reg); 321 } 322 323 static void ibx_read_infoframe(struct intel_encoder *encoder, 324 const struct intel_crtc_state *crtc_state, 325 unsigned int type, 326 void *frame, ssize_t len) 327 { 328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 329 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 330 u32 val, *data = frame; 331 int i; 332 333 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 334 335 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 336 val |= g4x_infoframe_index(type); 337 338 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 339 340 for (i = 0; i < len; i += 4) 341 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 342 } 343 344 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 345 const struct intel_crtc_state *pipe_config) 346 { 347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 348 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 349 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 350 u32 val = intel_de_read(dev_priv, reg); 351 352 if ((val & VIDEO_DIP_ENABLE) == 0) 353 return 0; 354 355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 356 return 0; 357 358 return val & (VIDEO_DIP_ENABLE_AVI | 359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 361 } 362 363 static void cpt_write_infoframe(struct intel_encoder *encoder, 364 const struct intel_crtc_state *crtc_state, 365 unsigned int type, 366 const void *frame, ssize_t len) 367 { 368 const u32 *data = frame; 369 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 371 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 372 u32 val = intel_de_read(dev_priv, reg); 373 int i; 374 375 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 376 "Writing DIP with CTL reg disabled\n"); 377 378 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 379 val |= g4x_infoframe_index(type); 380 381 /* The DIP control register spec says that we need to update the AVI 382 * infoframe without clearing its enable bit */ 383 if (type != HDMI_INFOFRAME_TYPE_AVI) 384 val &= ~g4x_infoframe_enable(type); 385 386 intel_de_write(dev_priv, reg, val); 387 388 for (i = 0; i < len; i += 4) { 389 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 390 *data); 391 data++; 392 } 393 /* Write every possible data byte to force correct ECC calculation. */ 394 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 395 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 396 397 val |= g4x_infoframe_enable(type); 398 val &= ~VIDEO_DIP_FREQ_MASK; 399 val |= VIDEO_DIP_FREQ_VSYNC; 400 401 intel_de_write(dev_priv, reg, val); 402 intel_de_posting_read(dev_priv, reg); 403 } 404 405 static void cpt_read_infoframe(struct intel_encoder *encoder, 406 const struct intel_crtc_state *crtc_state, 407 unsigned int type, 408 void *frame, ssize_t len) 409 { 410 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 411 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 412 u32 val, *data = frame; 413 int i; 414 415 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 416 417 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 418 val |= g4x_infoframe_index(type); 419 420 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 421 422 for (i = 0; i < len; i += 4) 423 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 424 } 425 426 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 427 const struct intel_crtc_state *pipe_config) 428 { 429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 430 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 431 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 432 433 if ((val & VIDEO_DIP_ENABLE) == 0) 434 return 0; 435 436 return val & (VIDEO_DIP_ENABLE_AVI | 437 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 438 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 439 } 440 441 static void vlv_write_infoframe(struct intel_encoder *encoder, 442 const struct intel_crtc_state *crtc_state, 443 unsigned int type, 444 const void *frame, ssize_t len) 445 { 446 const u32 *data = frame; 447 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 449 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 450 u32 val = intel_de_read(dev_priv, reg); 451 int i; 452 453 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 454 "Writing DIP with CTL reg disabled\n"); 455 456 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 457 val |= g4x_infoframe_index(type); 458 459 val &= ~g4x_infoframe_enable(type); 460 461 intel_de_write(dev_priv, reg, val); 462 463 for (i = 0; i < len; i += 4) { 464 intel_de_write(dev_priv, 465 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 466 data++; 467 } 468 /* Write every possible data byte to force correct ECC calculation. */ 469 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 470 intel_de_write(dev_priv, 471 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 472 473 val |= g4x_infoframe_enable(type); 474 val &= ~VIDEO_DIP_FREQ_MASK; 475 val |= VIDEO_DIP_FREQ_VSYNC; 476 477 intel_de_write(dev_priv, reg, val); 478 intel_de_posting_read(dev_priv, reg); 479 } 480 481 static void vlv_read_infoframe(struct intel_encoder *encoder, 482 const struct intel_crtc_state *crtc_state, 483 unsigned int type, 484 void *frame, ssize_t len) 485 { 486 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 487 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 488 u32 val, *data = frame; 489 int i; 490 491 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); 492 493 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 494 val |= g4x_infoframe_index(type); 495 496 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 497 498 for (i = 0; i < len; i += 4) 499 *data++ = intel_de_read(dev_priv, 500 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 501 } 502 503 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 504 const struct intel_crtc_state *pipe_config) 505 { 506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 507 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 508 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 509 510 if ((val & VIDEO_DIP_ENABLE) == 0) 511 return 0; 512 513 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 514 return 0; 515 516 return val & (VIDEO_DIP_ENABLE_AVI | 517 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 518 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 519 } 520 521 void hsw_write_infoframe(struct intel_encoder *encoder, 522 const struct intel_crtc_state *crtc_state, 523 unsigned int type, 524 const void *frame, ssize_t len) 525 { 526 const u32 *data = frame; 527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 528 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 529 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 530 int data_size; 531 int i; 532 u32 val = intel_de_read(dev_priv, ctl_reg); 533 534 data_size = hsw_dip_data_size(dev_priv, type); 535 536 drm_WARN_ON(&dev_priv->drm, len > data_size); 537 538 val &= ~hsw_infoframe_enable(type); 539 intel_de_write(dev_priv, ctl_reg, val); 540 541 for (i = 0; i < len; i += 4) { 542 intel_de_write(dev_priv, 543 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 544 *data); 545 data++; 546 } 547 /* Write every possible data byte to force correct ECC calculation. */ 548 for (; i < data_size; i += 4) 549 intel_de_write(dev_priv, 550 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 551 0); 552 553 val |= hsw_infoframe_enable(type); 554 intel_de_write(dev_priv, ctl_reg, val); 555 intel_de_posting_read(dev_priv, ctl_reg); 556 } 557 558 void hsw_read_infoframe(struct intel_encoder *encoder, 559 const struct intel_crtc_state *crtc_state, 560 unsigned int type, void *frame, ssize_t len) 561 { 562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 563 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 564 u32 val, *data = frame; 565 int i; 566 567 val = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(cpu_transcoder)); 568 569 for (i = 0; i < len; i += 4) 570 *data++ = intel_de_read(dev_priv, 571 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 572 } 573 574 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 575 const struct intel_crtc_state *pipe_config) 576 { 577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 578 u32 val = intel_de_read(dev_priv, 579 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 580 u32 mask; 581 582 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 583 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 584 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 585 586 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 587 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 588 589 return val & mask; 590 } 591 592 static const u8 infoframe_type_to_idx[] = { 593 HDMI_PACKET_TYPE_GENERAL_CONTROL, 594 HDMI_PACKET_TYPE_GAMUT_METADATA, 595 DP_SDP_VSC, 596 HDMI_INFOFRAME_TYPE_AVI, 597 HDMI_INFOFRAME_TYPE_SPD, 598 HDMI_INFOFRAME_TYPE_VENDOR, 599 HDMI_INFOFRAME_TYPE_DRM, 600 }; 601 602 u32 intel_hdmi_infoframe_enable(unsigned int type) 603 { 604 int i; 605 606 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 607 if (infoframe_type_to_idx[i] == type) 608 return BIT(i); 609 } 610 611 return 0; 612 } 613 614 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 615 const struct intel_crtc_state *crtc_state) 616 { 617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 618 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 619 u32 val, ret = 0; 620 int i; 621 622 val = dig_port->infoframes_enabled(encoder, crtc_state); 623 624 /* map from hardware bits to dip idx */ 625 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 626 unsigned int type = infoframe_type_to_idx[i]; 627 628 if (HAS_DDI(dev_priv)) { 629 if (val & hsw_infoframe_enable(type)) 630 ret |= BIT(i); 631 } else { 632 if (val & g4x_infoframe_enable(type)) 633 ret |= BIT(i); 634 } 635 } 636 637 return ret; 638 } 639 640 /* 641 * The data we write to the DIP data buffer registers is 1 byte bigger than the 642 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 643 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 644 * used for both technologies. 645 * 646 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 647 * DW1: DB3 | DB2 | DB1 | DB0 648 * DW2: DB7 | DB6 | DB5 | DB4 649 * DW3: ... 650 * 651 * (HB is Header Byte, DB is Data Byte) 652 * 653 * The hdmi pack() functions don't know about that hardware specific hole so we 654 * trick them by giving an offset into the buffer and moving back the header 655 * bytes by one. 656 */ 657 static void intel_write_infoframe(struct intel_encoder *encoder, 658 const struct intel_crtc_state *crtc_state, 659 enum hdmi_infoframe_type type, 660 const union hdmi_infoframe *frame) 661 { 662 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 663 u8 buffer[VIDEO_DIP_DATA_SIZE]; 664 ssize_t len; 665 666 if ((crtc_state->infoframes.enable & 667 intel_hdmi_infoframe_enable(type)) == 0) 668 return; 669 670 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 671 return; 672 673 /* see comment above for the reason for this offset */ 674 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 675 if (drm_WARN_ON(encoder->base.dev, len < 0)) 676 return; 677 678 /* Insert the 'hole' (see big comment above) at position 3 */ 679 memmove(&buffer[0], &buffer[1], 3); 680 buffer[3] = 0; 681 len++; 682 683 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 684 } 685 686 void intel_read_infoframe(struct intel_encoder *encoder, 687 const struct intel_crtc_state *crtc_state, 688 enum hdmi_infoframe_type type, 689 union hdmi_infoframe *frame) 690 { 691 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 692 u8 buffer[VIDEO_DIP_DATA_SIZE]; 693 int ret; 694 695 if ((crtc_state->infoframes.enable & 696 intel_hdmi_infoframe_enable(type)) == 0) 697 return; 698 699 dig_port->read_infoframe(encoder, crtc_state, 700 type, buffer, sizeof(buffer)); 701 702 /* Fill the 'hole' (see big comment above) at position 3 */ 703 memmove(&buffer[1], &buffer[0], 3); 704 705 /* see comment above for the reason for this offset */ 706 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 707 if (ret) { 708 drm_dbg_kms(encoder->base.dev, 709 "Failed to unpack infoframe type 0x%02x\n", type); 710 return; 711 } 712 713 if (frame->any.type != type) 714 drm_dbg_kms(encoder->base.dev, 715 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 716 frame->any.type, type); 717 } 718 719 static bool 720 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 721 struct intel_crtc_state *crtc_state, 722 struct drm_connector_state *conn_state) 723 { 724 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 725 const struct drm_display_mode *adjusted_mode = 726 &crtc_state->hw.adjusted_mode; 727 struct drm_connector *connector = conn_state->connector; 728 int ret; 729 730 if (!crtc_state->has_infoframe) 731 return true; 732 733 crtc_state->infoframes.enable |= 734 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 735 736 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 737 adjusted_mode); 738 if (ret) 739 return false; 740 741 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 742 frame->colorspace = HDMI_COLORSPACE_YUV420; 743 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 744 frame->colorspace = HDMI_COLORSPACE_YUV444; 745 else 746 frame->colorspace = HDMI_COLORSPACE_RGB; 747 748 drm_hdmi_avi_infoframe_colorspace(frame, conn_state); 749 750 /* nonsense combination */ 751 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 752 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 753 754 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 755 drm_hdmi_avi_infoframe_quant_range(frame, connector, 756 adjusted_mode, 757 crtc_state->limited_color_range ? 758 HDMI_QUANTIZATION_RANGE_LIMITED : 759 HDMI_QUANTIZATION_RANGE_FULL); 760 } else { 761 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 762 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 763 } 764 765 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 766 767 /* TODO: handle pixel repetition for YCBCR420 outputs */ 768 769 ret = hdmi_avi_infoframe_check(frame); 770 if (drm_WARN_ON(encoder->base.dev, ret)) 771 return false; 772 773 return true; 774 } 775 776 static bool 777 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 778 struct intel_crtc_state *crtc_state, 779 struct drm_connector_state *conn_state) 780 { 781 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 782 int ret; 783 784 if (!crtc_state->has_infoframe) 785 return true; 786 787 crtc_state->infoframes.enable |= 788 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 789 790 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 791 if (drm_WARN_ON(encoder->base.dev, ret)) 792 return false; 793 794 frame->sdi = HDMI_SPD_SDI_PC; 795 796 ret = hdmi_spd_infoframe_check(frame); 797 if (drm_WARN_ON(encoder->base.dev, ret)) 798 return false; 799 800 return true; 801 } 802 803 static bool 804 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 805 struct intel_crtc_state *crtc_state, 806 struct drm_connector_state *conn_state) 807 { 808 struct hdmi_vendor_infoframe *frame = 809 &crtc_state->infoframes.hdmi.vendor.hdmi; 810 const struct drm_display_info *info = 811 &conn_state->connector->display_info; 812 int ret; 813 814 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 815 return true; 816 817 crtc_state->infoframes.enable |= 818 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 819 820 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 821 conn_state->connector, 822 &crtc_state->hw.adjusted_mode); 823 if (drm_WARN_ON(encoder->base.dev, ret)) 824 return false; 825 826 ret = hdmi_vendor_infoframe_check(frame); 827 if (drm_WARN_ON(encoder->base.dev, ret)) 828 return false; 829 830 return true; 831 } 832 833 static bool 834 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 835 struct intel_crtc_state *crtc_state, 836 struct drm_connector_state *conn_state) 837 { 838 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 839 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 840 int ret; 841 842 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) 843 return true; 844 845 if (!crtc_state->has_infoframe) 846 return true; 847 848 if (!conn_state->hdr_output_metadata) 849 return true; 850 851 crtc_state->infoframes.enable |= 852 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 853 854 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 855 if (ret < 0) { 856 drm_dbg_kms(&dev_priv->drm, 857 "couldn't set HDR metadata in infoframe\n"); 858 return false; 859 } 860 861 ret = hdmi_drm_infoframe_check(frame); 862 if (drm_WARN_ON(&dev_priv->drm, ret)) 863 return false; 864 865 return true; 866 } 867 868 static void g4x_set_infoframes(struct intel_encoder *encoder, 869 bool enable, 870 const struct intel_crtc_state *crtc_state, 871 const struct drm_connector_state *conn_state) 872 { 873 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 874 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 875 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 876 i915_reg_t reg = VIDEO_DIP_CTL; 877 u32 val = intel_de_read(dev_priv, reg); 878 u32 port = VIDEO_DIP_PORT(encoder->port); 879 880 assert_hdmi_port_disabled(intel_hdmi); 881 882 /* If the registers were not initialized yet, they might be zeroes, 883 * which means we're selecting the AVI DIP and we're setting its 884 * frequency to once. This seems to really confuse the HW and make 885 * things stop working (the register spec says the AVI always needs to 886 * be sent every VSync). So here we avoid writing to the register more 887 * than we need and also explicitly select the AVI DIP and explicitly 888 * set its frequency to every VSync. Avoiding to write it twice seems to 889 * be enough to solve the problem, but being defensive shouldn't hurt us 890 * either. */ 891 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 892 893 if (!enable) { 894 if (!(val & VIDEO_DIP_ENABLE)) 895 return; 896 if (port != (val & VIDEO_DIP_PORT_MASK)) { 897 drm_dbg_kms(&dev_priv->drm, 898 "video DIP still enabled on port %c\n", 899 (val & VIDEO_DIP_PORT_MASK) >> 29); 900 return; 901 } 902 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 903 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 904 intel_de_write(dev_priv, reg, val); 905 intel_de_posting_read(dev_priv, reg); 906 return; 907 } 908 909 if (port != (val & VIDEO_DIP_PORT_MASK)) { 910 if (val & VIDEO_DIP_ENABLE) { 911 drm_dbg_kms(&dev_priv->drm, 912 "video DIP already enabled on port %c\n", 913 (val & VIDEO_DIP_PORT_MASK) >> 29); 914 return; 915 } 916 val &= ~VIDEO_DIP_PORT_MASK; 917 val |= port; 918 } 919 920 val |= VIDEO_DIP_ENABLE; 921 val &= ~(VIDEO_DIP_ENABLE_AVI | 922 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 923 924 intel_de_write(dev_priv, reg, val); 925 intel_de_posting_read(dev_priv, reg); 926 927 intel_write_infoframe(encoder, crtc_state, 928 HDMI_INFOFRAME_TYPE_AVI, 929 &crtc_state->infoframes.avi); 930 intel_write_infoframe(encoder, crtc_state, 931 HDMI_INFOFRAME_TYPE_SPD, 932 &crtc_state->infoframes.spd); 933 intel_write_infoframe(encoder, crtc_state, 934 HDMI_INFOFRAME_TYPE_VENDOR, 935 &crtc_state->infoframes.hdmi); 936 } 937 938 /* 939 * Determine if default_phase=1 can be indicated in the GCP infoframe. 940 * 941 * From HDMI specification 1.4a: 942 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 943 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 944 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 945 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 946 * phase of 0 947 */ 948 static bool gcp_default_phase_possible(int pipe_bpp, 949 const struct drm_display_mode *mode) 950 { 951 unsigned int pixels_per_group; 952 953 switch (pipe_bpp) { 954 case 30: 955 /* 4 pixels in 5 clocks */ 956 pixels_per_group = 4; 957 break; 958 case 36: 959 /* 2 pixels in 3 clocks */ 960 pixels_per_group = 2; 961 break; 962 case 48: 963 /* 1 pixel in 2 clocks */ 964 pixels_per_group = 1; 965 break; 966 default: 967 /* phase information not relevant for 8bpc */ 968 return false; 969 } 970 971 return mode->crtc_hdisplay % pixels_per_group == 0 && 972 mode->crtc_htotal % pixels_per_group == 0 && 973 mode->crtc_hblank_start % pixels_per_group == 0 && 974 mode->crtc_hblank_end % pixels_per_group == 0 && 975 mode->crtc_hsync_start % pixels_per_group == 0 && 976 mode->crtc_hsync_end % pixels_per_group == 0 && 977 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 978 mode->crtc_htotal/2 % pixels_per_group == 0); 979 } 980 981 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 982 const struct intel_crtc_state *crtc_state, 983 const struct drm_connector_state *conn_state) 984 { 985 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 986 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 987 i915_reg_t reg; 988 989 if ((crtc_state->infoframes.enable & 990 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 991 return false; 992 993 if (HAS_DDI(dev_priv)) 994 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 995 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 996 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 997 else if (HAS_PCH_SPLIT(dev_priv)) 998 reg = TVIDEO_DIP_GCP(crtc->pipe); 999 else 1000 return false; 1001 1002 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 1003 1004 return true; 1005 } 1006 1007 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1008 struct intel_crtc_state *crtc_state) 1009 { 1010 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1011 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1012 i915_reg_t reg; 1013 1014 if ((crtc_state->infoframes.enable & 1015 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1016 return; 1017 1018 if (HAS_DDI(dev_priv)) 1019 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1020 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1021 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1022 else if (HAS_PCH_SPLIT(dev_priv)) 1023 reg = TVIDEO_DIP_GCP(crtc->pipe); 1024 else 1025 return; 1026 1027 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1028 } 1029 1030 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1031 struct intel_crtc_state *crtc_state, 1032 struct drm_connector_state *conn_state) 1033 { 1034 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1035 1036 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1037 return; 1038 1039 crtc_state->infoframes.enable |= 1040 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1041 1042 /* Indicate color indication for deep color mode */ 1043 if (crtc_state->pipe_bpp > 24) 1044 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1045 1046 /* Enable default_phase whenever the display mode is suitably aligned */ 1047 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1048 &crtc_state->hw.adjusted_mode)) 1049 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1050 } 1051 1052 static void ibx_set_infoframes(struct intel_encoder *encoder, 1053 bool enable, 1054 const struct intel_crtc_state *crtc_state, 1055 const struct drm_connector_state *conn_state) 1056 { 1057 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1059 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1060 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1061 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1062 u32 val = intel_de_read(dev_priv, reg); 1063 u32 port = VIDEO_DIP_PORT(encoder->port); 1064 1065 assert_hdmi_port_disabled(intel_hdmi); 1066 1067 /* See the big comment in g4x_set_infoframes() */ 1068 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1069 1070 if (!enable) { 1071 if (!(val & VIDEO_DIP_ENABLE)) 1072 return; 1073 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1074 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1075 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1076 intel_de_write(dev_priv, reg, val); 1077 intel_de_posting_read(dev_priv, reg); 1078 return; 1079 } 1080 1081 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1082 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1083 "DIP already enabled on port %c\n", 1084 (val & VIDEO_DIP_PORT_MASK) >> 29); 1085 val &= ~VIDEO_DIP_PORT_MASK; 1086 val |= port; 1087 } 1088 1089 val |= VIDEO_DIP_ENABLE; 1090 val &= ~(VIDEO_DIP_ENABLE_AVI | 1091 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1092 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1093 1094 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1095 val |= VIDEO_DIP_ENABLE_GCP; 1096 1097 intel_de_write(dev_priv, reg, val); 1098 intel_de_posting_read(dev_priv, reg); 1099 1100 intel_write_infoframe(encoder, crtc_state, 1101 HDMI_INFOFRAME_TYPE_AVI, 1102 &crtc_state->infoframes.avi); 1103 intel_write_infoframe(encoder, crtc_state, 1104 HDMI_INFOFRAME_TYPE_SPD, 1105 &crtc_state->infoframes.spd); 1106 intel_write_infoframe(encoder, crtc_state, 1107 HDMI_INFOFRAME_TYPE_VENDOR, 1108 &crtc_state->infoframes.hdmi); 1109 } 1110 1111 static void cpt_set_infoframes(struct intel_encoder *encoder, 1112 bool enable, 1113 const struct intel_crtc_state *crtc_state, 1114 const struct drm_connector_state *conn_state) 1115 { 1116 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1118 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1119 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1120 u32 val = intel_de_read(dev_priv, reg); 1121 1122 assert_hdmi_port_disabled(intel_hdmi); 1123 1124 /* See the big comment in g4x_set_infoframes() */ 1125 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1126 1127 if (!enable) { 1128 if (!(val & VIDEO_DIP_ENABLE)) 1129 return; 1130 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1131 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1132 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1133 intel_de_write(dev_priv, reg, val); 1134 intel_de_posting_read(dev_priv, reg); 1135 return; 1136 } 1137 1138 /* Set both together, unset both together: see the spec. */ 1139 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1140 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1141 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1142 1143 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1144 val |= VIDEO_DIP_ENABLE_GCP; 1145 1146 intel_de_write(dev_priv, reg, val); 1147 intel_de_posting_read(dev_priv, reg); 1148 1149 intel_write_infoframe(encoder, crtc_state, 1150 HDMI_INFOFRAME_TYPE_AVI, 1151 &crtc_state->infoframes.avi); 1152 intel_write_infoframe(encoder, crtc_state, 1153 HDMI_INFOFRAME_TYPE_SPD, 1154 &crtc_state->infoframes.spd); 1155 intel_write_infoframe(encoder, crtc_state, 1156 HDMI_INFOFRAME_TYPE_VENDOR, 1157 &crtc_state->infoframes.hdmi); 1158 } 1159 1160 static void vlv_set_infoframes(struct intel_encoder *encoder, 1161 bool enable, 1162 const struct intel_crtc_state *crtc_state, 1163 const struct drm_connector_state *conn_state) 1164 { 1165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1167 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1168 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 1169 u32 val = intel_de_read(dev_priv, reg); 1170 u32 port = VIDEO_DIP_PORT(encoder->port); 1171 1172 assert_hdmi_port_disabled(intel_hdmi); 1173 1174 /* See the big comment in g4x_set_infoframes() */ 1175 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1176 1177 if (!enable) { 1178 if (!(val & VIDEO_DIP_ENABLE)) 1179 return; 1180 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1181 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1182 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1183 intel_de_write(dev_priv, reg, val); 1184 intel_de_posting_read(dev_priv, reg); 1185 return; 1186 } 1187 1188 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1189 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1190 "DIP already enabled on port %c\n", 1191 (val & VIDEO_DIP_PORT_MASK) >> 29); 1192 val &= ~VIDEO_DIP_PORT_MASK; 1193 val |= port; 1194 } 1195 1196 val |= VIDEO_DIP_ENABLE; 1197 val &= ~(VIDEO_DIP_ENABLE_AVI | 1198 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1199 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1200 1201 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1202 val |= VIDEO_DIP_ENABLE_GCP; 1203 1204 intel_de_write(dev_priv, reg, val); 1205 intel_de_posting_read(dev_priv, reg); 1206 1207 intel_write_infoframe(encoder, crtc_state, 1208 HDMI_INFOFRAME_TYPE_AVI, 1209 &crtc_state->infoframes.avi); 1210 intel_write_infoframe(encoder, crtc_state, 1211 HDMI_INFOFRAME_TYPE_SPD, 1212 &crtc_state->infoframes.spd); 1213 intel_write_infoframe(encoder, crtc_state, 1214 HDMI_INFOFRAME_TYPE_VENDOR, 1215 &crtc_state->infoframes.hdmi); 1216 } 1217 1218 static void hsw_set_infoframes(struct intel_encoder *encoder, 1219 bool enable, 1220 const struct intel_crtc_state *crtc_state, 1221 const struct drm_connector_state *conn_state) 1222 { 1223 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1224 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1225 u32 val = intel_de_read(dev_priv, reg); 1226 1227 assert_hdmi_transcoder_func_disabled(dev_priv, 1228 crtc_state->cpu_transcoder); 1229 1230 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1231 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1232 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1233 VIDEO_DIP_ENABLE_DRM_GLK); 1234 1235 if (!enable) { 1236 intel_de_write(dev_priv, reg, val); 1237 intel_de_posting_read(dev_priv, reg); 1238 return; 1239 } 1240 1241 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1242 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1243 1244 intel_de_write(dev_priv, reg, val); 1245 intel_de_posting_read(dev_priv, reg); 1246 1247 intel_write_infoframe(encoder, crtc_state, 1248 HDMI_INFOFRAME_TYPE_AVI, 1249 &crtc_state->infoframes.avi); 1250 intel_write_infoframe(encoder, crtc_state, 1251 HDMI_INFOFRAME_TYPE_SPD, 1252 &crtc_state->infoframes.spd); 1253 intel_write_infoframe(encoder, crtc_state, 1254 HDMI_INFOFRAME_TYPE_VENDOR, 1255 &crtc_state->infoframes.hdmi); 1256 intel_write_infoframe(encoder, crtc_state, 1257 HDMI_INFOFRAME_TYPE_DRM, 1258 &crtc_state->infoframes.drm); 1259 } 1260 1261 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1262 { 1263 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1264 struct i2c_adapter *adapter = 1265 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1266 1267 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1268 return; 1269 1270 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", 1271 enable ? "Enabling" : "Disabling"); 1272 1273 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, 1274 adapter, enable); 1275 } 1276 1277 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1278 unsigned int offset, void *buffer, size_t size) 1279 { 1280 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1281 struct intel_hdmi *hdmi = &dig_port->hdmi; 1282 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1283 hdmi->ddc_bus); 1284 int ret; 1285 u8 start = offset & 0xff; 1286 struct i2c_msg msgs[] = { 1287 { 1288 .addr = DRM_HDCP_DDC_ADDR, 1289 .flags = 0, 1290 .len = 1, 1291 .buf = &start, 1292 }, 1293 { 1294 .addr = DRM_HDCP_DDC_ADDR, 1295 .flags = I2C_M_RD, 1296 .len = size, 1297 .buf = buffer 1298 } 1299 }; 1300 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1301 if (ret == ARRAY_SIZE(msgs)) 1302 return 0; 1303 return ret >= 0 ? -EIO : ret; 1304 } 1305 1306 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1307 unsigned int offset, void *buffer, size_t size) 1308 { 1309 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1310 struct intel_hdmi *hdmi = &dig_port->hdmi; 1311 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1312 hdmi->ddc_bus); 1313 int ret; 1314 u8 *write_buf; 1315 struct i2c_msg msg; 1316 1317 write_buf = kzalloc(size + 1, GFP_KERNEL); 1318 if (!write_buf) 1319 return -ENOMEM; 1320 1321 write_buf[0] = offset & 0xff; 1322 memcpy(&write_buf[1], buffer, size); 1323 1324 msg.addr = DRM_HDCP_DDC_ADDR; 1325 msg.flags = 0, 1326 msg.len = size + 1, 1327 msg.buf = write_buf; 1328 1329 ret = i2c_transfer(adapter, &msg, 1); 1330 if (ret == 1) 1331 ret = 0; 1332 else if (ret >= 0) 1333 ret = -EIO; 1334 1335 kfree(write_buf); 1336 return ret; 1337 } 1338 1339 static 1340 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1341 u8 *an) 1342 { 1343 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1344 struct intel_hdmi *hdmi = &dig_port->hdmi; 1345 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1346 hdmi->ddc_bus); 1347 int ret; 1348 1349 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1350 DRM_HDCP_AN_LEN); 1351 if (ret) { 1352 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", 1353 ret); 1354 return ret; 1355 } 1356 1357 ret = intel_gmbus_output_aksv(adapter); 1358 if (ret < 0) { 1359 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); 1360 return ret; 1361 } 1362 return 0; 1363 } 1364 1365 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1366 u8 *bksv) 1367 { 1368 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1369 1370 int ret; 1371 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1372 DRM_HDCP_KSV_LEN); 1373 if (ret) 1374 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", 1375 ret); 1376 return ret; 1377 } 1378 1379 static 1380 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1381 u8 *bstatus) 1382 { 1383 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1384 1385 int ret; 1386 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1387 bstatus, DRM_HDCP_BSTATUS_LEN); 1388 if (ret) 1389 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", 1390 ret); 1391 return ret; 1392 } 1393 1394 static 1395 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1396 bool *repeater_present) 1397 { 1398 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1399 int ret; 1400 u8 val; 1401 1402 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1403 if (ret) { 1404 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1405 ret); 1406 return ret; 1407 } 1408 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1409 return 0; 1410 } 1411 1412 static 1413 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1414 u8 *ri_prime) 1415 { 1416 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1417 1418 int ret; 1419 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1420 ri_prime, DRM_HDCP_RI_LEN); 1421 if (ret) 1422 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", 1423 ret); 1424 return ret; 1425 } 1426 1427 static 1428 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1429 bool *ksv_ready) 1430 { 1431 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1432 int ret; 1433 u8 val; 1434 1435 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1436 if (ret) { 1437 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1438 ret); 1439 return ret; 1440 } 1441 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1442 return 0; 1443 } 1444 1445 static 1446 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1447 int num_downstream, u8 *ksv_fifo) 1448 { 1449 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1450 int ret; 1451 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1452 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1453 if (ret) { 1454 drm_dbg_kms(&i915->drm, 1455 "Read ksv fifo over DDC failed (%d)\n", ret); 1456 return ret; 1457 } 1458 return 0; 1459 } 1460 1461 static 1462 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1463 int i, u32 *part) 1464 { 1465 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1466 int ret; 1467 1468 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1469 return -EINVAL; 1470 1471 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1472 part, DRM_HDCP_V_PRIME_PART_LEN); 1473 if (ret) 1474 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", 1475 i, ret); 1476 return ret; 1477 } 1478 1479 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1480 enum transcoder cpu_transcoder) 1481 { 1482 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1483 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1484 struct drm_crtc *crtc = connector->base.state->crtc; 1485 struct intel_crtc *intel_crtc = container_of(crtc, 1486 struct intel_crtc, base); 1487 u32 scanline; 1488 int ret; 1489 1490 for (;;) { 1491 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe)); 1492 if (scanline > 100 && scanline < 200) 1493 break; 1494 usleep_range(25, 50); 1495 } 1496 1497 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1498 false, TRANS_DDI_HDCP_SIGNALLING); 1499 if (ret) { 1500 drm_err(&dev_priv->drm, 1501 "Disable HDCP signalling failed (%d)\n", ret); 1502 return ret; 1503 } 1504 1505 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1506 true, TRANS_DDI_HDCP_SIGNALLING); 1507 if (ret) { 1508 drm_err(&dev_priv->drm, 1509 "Enable HDCP signalling failed (%d)\n", ret); 1510 return ret; 1511 } 1512 1513 return 0; 1514 } 1515 1516 static 1517 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1518 enum transcoder cpu_transcoder, 1519 bool enable) 1520 { 1521 struct intel_hdmi *hdmi = &dig_port->hdmi; 1522 struct intel_connector *connector = hdmi->attached_connector; 1523 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1524 int ret; 1525 1526 if (!enable) 1527 usleep_range(6, 60); /* Bspec says >= 6us */ 1528 1529 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1530 cpu_transcoder, enable, 1531 TRANS_DDI_HDCP_SIGNALLING); 1532 if (ret) { 1533 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", 1534 enable ? "Enable" : "Disable", ret); 1535 return ret; 1536 } 1537 1538 /* 1539 * WA: To fix incorrect positioning of the window of 1540 * opportunity and enc_en signalling in KABYLAKE. 1541 */ 1542 if (IS_KABYLAKE(dev_priv) && enable) 1543 return kbl_repositioning_enc_en_signal(connector, 1544 cpu_transcoder); 1545 1546 return 0; 1547 } 1548 1549 static 1550 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1551 struct intel_connector *connector) 1552 { 1553 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1554 enum port port = dig_port->base.port; 1555 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1556 int ret; 1557 union { 1558 u32 reg; 1559 u8 shim[DRM_HDCP_RI_LEN]; 1560 } ri; 1561 1562 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1563 if (ret) 1564 return false; 1565 1566 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1567 1568 /* Wait for Ri prime match */ 1569 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1570 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1571 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1572 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", 1573 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1574 port))); 1575 return false; 1576 } 1577 return true; 1578 } 1579 1580 static 1581 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1582 struct intel_connector *connector) 1583 { 1584 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1585 int retry; 1586 1587 for (retry = 0; retry < 3; retry++) 1588 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1589 return true; 1590 1591 drm_err(&i915->drm, "Link check failed\n"); 1592 return false; 1593 } 1594 1595 struct hdcp2_hdmi_msg_timeout { 1596 u8 msg_id; 1597 u16 timeout; 1598 }; 1599 1600 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1601 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1602 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1603 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1604 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1605 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1606 }; 1607 1608 static 1609 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1610 u8 *rx_status) 1611 { 1612 return intel_hdmi_hdcp_read(dig_port, 1613 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1614 rx_status, 1615 HDCP_2_2_HDMI_RXSTATUS_LEN); 1616 } 1617 1618 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1619 { 1620 int i; 1621 1622 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1623 if (is_paired) 1624 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1625 else 1626 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1627 } 1628 1629 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1630 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1631 return hdcp2_msg_timeout[i].timeout; 1632 } 1633 1634 return -EINVAL; 1635 } 1636 1637 static int 1638 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1639 u8 msg_id, bool *msg_ready, 1640 ssize_t *msg_sz) 1641 { 1642 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1643 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1644 int ret; 1645 1646 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1647 if (ret < 0) { 1648 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", 1649 ret); 1650 return ret; 1651 } 1652 1653 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1654 rx_status[0]); 1655 1656 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1657 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1658 *msg_sz); 1659 else 1660 *msg_ready = *msg_sz; 1661 1662 return 0; 1663 } 1664 1665 static ssize_t 1666 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1667 u8 msg_id, bool paired) 1668 { 1669 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1670 bool msg_ready = false; 1671 int timeout, ret; 1672 ssize_t msg_sz = 0; 1673 1674 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1675 if (timeout < 0) 1676 return timeout; 1677 1678 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1679 msg_id, &msg_ready, 1680 &msg_sz), 1681 !ret && msg_ready && msg_sz, timeout * 1000, 1682 1000, 5 * 1000); 1683 if (ret) 1684 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", 1685 msg_id, ret, timeout); 1686 1687 return ret ? ret : msg_sz; 1688 } 1689 1690 static 1691 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, 1692 void *buf, size_t size) 1693 { 1694 unsigned int offset; 1695 1696 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1697 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1698 } 1699 1700 static 1701 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, 1702 u8 msg_id, void *buf, size_t size) 1703 { 1704 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1705 struct intel_hdmi *hdmi = &dig_port->hdmi; 1706 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1707 unsigned int offset; 1708 ssize_t ret; 1709 1710 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1711 hdcp->is_paired); 1712 if (ret < 0) 1713 return ret; 1714 1715 /* 1716 * Available msg size should be equal to or lesser than the 1717 * available buffer. 1718 */ 1719 if (ret > size) { 1720 drm_dbg_kms(&i915->drm, 1721 "msg_sz(%zd) is more than exp size(%zu)\n", 1722 ret, size); 1723 return -1; 1724 } 1725 1726 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1727 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1728 if (ret) 1729 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", 1730 msg_id, ret); 1731 1732 return ret; 1733 } 1734 1735 static 1736 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1737 struct intel_connector *connector) 1738 { 1739 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1740 int ret; 1741 1742 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1743 if (ret) 1744 return ret; 1745 1746 /* 1747 * Re-auth request and Link Integrity Failures are represented by 1748 * same bit. i.e reauth_req. 1749 */ 1750 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1751 ret = HDCP_REAUTH_REQUEST; 1752 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1753 ret = HDCP_TOPOLOGY_CHANGE; 1754 1755 return ret; 1756 } 1757 1758 static 1759 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, 1760 bool *capable) 1761 { 1762 u8 hdcp2_version; 1763 int ret; 1764 1765 *capable = false; 1766 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1767 &hdcp2_version, sizeof(hdcp2_version)); 1768 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1769 *capable = true; 1770 1771 return ret; 1772 } 1773 1774 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1775 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1776 .read_bksv = intel_hdmi_hdcp_read_bksv, 1777 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1778 .repeater_present = intel_hdmi_hdcp_repeater_present, 1779 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1780 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1781 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1782 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1783 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1784 .check_link = intel_hdmi_hdcp_check_link, 1785 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1786 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1787 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1788 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1789 .protocol = HDCP_PROTOCOL_HDMI, 1790 }; 1791 1792 static void intel_hdmi_prepare(struct intel_encoder *encoder, 1793 const struct intel_crtc_state *crtc_state) 1794 { 1795 struct drm_device *dev = encoder->base.dev; 1796 struct drm_i915_private *dev_priv = to_i915(dev); 1797 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1798 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1799 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1800 u32 hdmi_val; 1801 1802 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 1803 1804 hdmi_val = SDVO_ENCODING_HDMI; 1805 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 1806 hdmi_val |= HDMI_COLOR_RANGE_16_235; 1807 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1808 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 1809 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1810 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 1811 1812 if (crtc_state->pipe_bpp > 24) 1813 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 1814 else 1815 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 1816 1817 if (crtc_state->has_hdmi_sink) 1818 hdmi_val |= HDMI_MODE_SELECT_HDMI; 1819 1820 if (HAS_PCH_CPT(dev_priv)) 1821 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1822 else if (IS_CHERRYVIEW(dev_priv)) 1823 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 1824 else 1825 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 1826 1827 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 1828 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1829 } 1830 1831 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 1832 enum pipe *pipe) 1833 { 1834 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1835 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1836 intel_wakeref_t wakeref; 1837 bool ret; 1838 1839 wakeref = intel_display_power_get_if_enabled(dev_priv, 1840 encoder->power_domain); 1841 if (!wakeref) 1842 return false; 1843 1844 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 1845 1846 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1847 1848 return ret; 1849 } 1850 1851 static void intel_hdmi_get_config(struct intel_encoder *encoder, 1852 struct intel_crtc_state *pipe_config) 1853 { 1854 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1855 struct drm_device *dev = encoder->base.dev; 1856 struct drm_i915_private *dev_priv = to_i915(dev); 1857 u32 tmp, flags = 0; 1858 int dotclock; 1859 1860 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 1861 1862 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1863 1864 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 1865 flags |= DRM_MODE_FLAG_PHSYNC; 1866 else 1867 flags |= DRM_MODE_FLAG_NHSYNC; 1868 1869 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 1870 flags |= DRM_MODE_FLAG_PVSYNC; 1871 else 1872 flags |= DRM_MODE_FLAG_NVSYNC; 1873 1874 if (tmp & HDMI_MODE_SELECT_HDMI) 1875 pipe_config->has_hdmi_sink = true; 1876 1877 pipe_config->infoframes.enable |= 1878 intel_hdmi_infoframes_enabled(encoder, pipe_config); 1879 1880 if (pipe_config->infoframes.enable) 1881 pipe_config->has_infoframe = true; 1882 1883 if (tmp & HDMI_AUDIO_ENABLE) 1884 pipe_config->has_audio = true; 1885 1886 if (!HAS_PCH_SPLIT(dev_priv) && 1887 tmp & HDMI_COLOR_RANGE_16_235) 1888 pipe_config->limited_color_range = true; 1889 1890 pipe_config->hw.adjusted_mode.flags |= flags; 1891 1892 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 1893 dotclock = pipe_config->port_clock * 2 / 3; 1894 else 1895 dotclock = pipe_config->port_clock; 1896 1897 if (pipe_config->pixel_multiplier) 1898 dotclock /= pipe_config->pixel_multiplier; 1899 1900 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1901 1902 pipe_config->lane_count = 4; 1903 1904 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 1905 1906 intel_read_infoframe(encoder, pipe_config, 1907 HDMI_INFOFRAME_TYPE_AVI, 1908 &pipe_config->infoframes.avi); 1909 intel_read_infoframe(encoder, pipe_config, 1910 HDMI_INFOFRAME_TYPE_SPD, 1911 &pipe_config->infoframes.spd); 1912 intel_read_infoframe(encoder, pipe_config, 1913 HDMI_INFOFRAME_TYPE_VENDOR, 1914 &pipe_config->infoframes.hdmi); 1915 } 1916 1917 static void intel_enable_hdmi_audio(struct intel_encoder *encoder, 1918 const struct intel_crtc_state *pipe_config, 1919 const struct drm_connector_state *conn_state) 1920 { 1921 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1922 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1923 1924 drm_WARN_ON(&i915->drm, !pipe_config->has_hdmi_sink); 1925 drm_dbg_kms(&i915->drm, "Enabling HDMI audio on pipe %c\n", 1926 pipe_name(crtc->pipe)); 1927 intel_audio_codec_enable(encoder, pipe_config, conn_state); 1928 } 1929 1930 static void g4x_enable_hdmi(struct intel_atomic_state *state, 1931 struct intel_encoder *encoder, 1932 const struct intel_crtc_state *pipe_config, 1933 const struct drm_connector_state *conn_state) 1934 { 1935 struct drm_device *dev = encoder->base.dev; 1936 struct drm_i915_private *dev_priv = to_i915(dev); 1937 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1938 u32 temp; 1939 1940 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1941 1942 temp |= SDVO_ENABLE; 1943 if (pipe_config->has_audio) 1944 temp |= HDMI_AUDIO_ENABLE; 1945 1946 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1947 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1948 1949 if (pipe_config->has_audio) 1950 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1951 } 1952 1953 static void ibx_enable_hdmi(struct intel_atomic_state *state, 1954 struct intel_encoder *encoder, 1955 const struct intel_crtc_state *pipe_config, 1956 const struct drm_connector_state *conn_state) 1957 { 1958 struct drm_device *dev = encoder->base.dev; 1959 struct drm_i915_private *dev_priv = to_i915(dev); 1960 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1961 u32 temp; 1962 1963 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1964 1965 temp |= SDVO_ENABLE; 1966 if (pipe_config->has_audio) 1967 temp |= HDMI_AUDIO_ENABLE; 1968 1969 /* 1970 * HW workaround, need to write this twice for issue 1971 * that may result in first write getting masked. 1972 */ 1973 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1974 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1975 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1976 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1977 1978 /* 1979 * HW workaround, need to toggle enable bit off and on 1980 * for 12bpc with pixel repeat. 1981 * 1982 * FIXME: BSpec says this should be done at the end of 1983 * of the modeset sequence, so not sure if this isn't too soon. 1984 */ 1985 if (pipe_config->pipe_bpp > 24 && 1986 pipe_config->pixel_multiplier > 1) { 1987 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 1988 temp & ~SDVO_ENABLE); 1989 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1990 1991 /* 1992 * HW workaround, need to write this twice for issue 1993 * that may result in first write getting masked. 1994 */ 1995 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1996 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1997 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1998 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1999 } 2000 2001 if (pipe_config->has_audio) 2002 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 2003 } 2004 2005 static void cpt_enable_hdmi(struct intel_atomic_state *state, 2006 struct intel_encoder *encoder, 2007 const struct intel_crtc_state *pipe_config, 2008 const struct drm_connector_state *conn_state) 2009 { 2010 struct drm_device *dev = encoder->base.dev; 2011 struct drm_i915_private *dev_priv = to_i915(dev); 2012 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2013 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2014 enum pipe pipe = crtc->pipe; 2015 u32 temp; 2016 2017 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 2018 2019 temp |= SDVO_ENABLE; 2020 if (pipe_config->has_audio) 2021 temp |= HDMI_AUDIO_ENABLE; 2022 2023 /* 2024 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 2025 * 2026 * The procedure for 12bpc is as follows: 2027 * 1. disable HDMI clock gating 2028 * 2. enable HDMI with 8bpc 2029 * 3. enable HDMI with 12bpc 2030 * 4. enable HDMI clock gating 2031 */ 2032 2033 if (pipe_config->pipe_bpp > 24) { 2034 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 2035 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 2036 2037 temp &= ~SDVO_COLOR_FORMAT_MASK; 2038 temp |= SDVO_COLOR_FORMAT_8bpc; 2039 } 2040 2041 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2042 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2043 2044 if (pipe_config->pipe_bpp > 24) { 2045 temp &= ~SDVO_COLOR_FORMAT_MASK; 2046 temp |= HDMI_COLOR_FORMAT_12bpc; 2047 2048 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2049 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2050 2051 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 2052 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 2053 } 2054 2055 if (pipe_config->has_audio) 2056 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 2057 } 2058 2059 static void vlv_enable_hdmi(struct intel_atomic_state *state, 2060 struct intel_encoder *encoder, 2061 const struct intel_crtc_state *pipe_config, 2062 const struct drm_connector_state *conn_state) 2063 { 2064 } 2065 2066 static void intel_disable_hdmi(struct intel_atomic_state *state, 2067 struct intel_encoder *encoder, 2068 const struct intel_crtc_state *old_crtc_state, 2069 const struct drm_connector_state *old_conn_state) 2070 { 2071 struct drm_device *dev = encoder->base.dev; 2072 struct drm_i915_private *dev_priv = to_i915(dev); 2073 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2074 struct intel_digital_port *dig_port = 2075 hdmi_to_dig_port(intel_hdmi); 2076 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2077 u32 temp; 2078 2079 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 2080 2081 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 2082 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2083 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2084 2085 /* 2086 * HW workaround for IBX, we need to move the port 2087 * to transcoder A after disabling it to allow the 2088 * matching DP port to be enabled on transcoder A. 2089 */ 2090 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 2091 /* 2092 * We get CPU/PCH FIFO underruns on the other pipe when 2093 * doing the workaround. Sweep them under the rug. 2094 */ 2095 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2096 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2097 2098 temp &= ~SDVO_PIPE_SEL_MASK; 2099 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 2100 /* 2101 * HW workaround, need to write this twice for issue 2102 * that may result in first write getting masked. 2103 */ 2104 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2105 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2106 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2107 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2108 2109 temp &= ~SDVO_ENABLE; 2110 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2111 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2112 2113 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 2114 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2115 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2116 } 2117 2118 dig_port->set_infoframes(encoder, 2119 false, 2120 old_crtc_state, old_conn_state); 2121 2122 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2123 } 2124 2125 static void g4x_disable_hdmi(struct intel_atomic_state *state, 2126 struct intel_encoder *encoder, 2127 const struct intel_crtc_state *old_crtc_state, 2128 const struct drm_connector_state *old_conn_state) 2129 { 2130 if (old_crtc_state->has_audio) 2131 intel_audio_codec_disable(encoder, 2132 old_crtc_state, old_conn_state); 2133 2134 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 2135 } 2136 2137 static void pch_disable_hdmi(struct intel_atomic_state *state, 2138 struct intel_encoder *encoder, 2139 const struct intel_crtc_state *old_crtc_state, 2140 const struct drm_connector_state *old_conn_state) 2141 { 2142 if (old_crtc_state->has_audio) 2143 intel_audio_codec_disable(encoder, 2144 old_crtc_state, old_conn_state); 2145 } 2146 2147 static void pch_post_disable_hdmi(struct intel_atomic_state *state, 2148 struct intel_encoder *encoder, 2149 const struct intel_crtc_state *old_crtc_state, 2150 const struct drm_connector_state *old_conn_state) 2151 { 2152 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 2153 } 2154 2155 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 2156 { 2157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2158 int max_tmds_clock, vbt_max_tmds_clock; 2159 2160 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2161 max_tmds_clock = 594000; 2162 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 2163 max_tmds_clock = 300000; 2164 else if (INTEL_GEN(dev_priv) >= 5) 2165 max_tmds_clock = 225000; 2166 else 2167 max_tmds_clock = 165000; 2168 2169 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); 2170 if (vbt_max_tmds_clock) 2171 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 2172 2173 return max_tmds_clock; 2174 } 2175 2176 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 2177 const struct drm_connector_state *conn_state) 2178 { 2179 return hdmi->has_hdmi_sink && 2180 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 2181 } 2182 2183 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 2184 bool respect_downstream_limits, 2185 bool has_hdmi_sink) 2186 { 2187 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2188 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 2189 2190 if (respect_downstream_limits) { 2191 struct intel_connector *connector = hdmi->attached_connector; 2192 const struct drm_display_info *info = &connector->base.display_info; 2193 2194 if (hdmi->dp_dual_mode.max_tmds_clock) 2195 max_tmds_clock = min(max_tmds_clock, 2196 hdmi->dp_dual_mode.max_tmds_clock); 2197 2198 if (info->max_tmds_clock) 2199 max_tmds_clock = min(max_tmds_clock, 2200 info->max_tmds_clock); 2201 else if (!has_hdmi_sink) 2202 max_tmds_clock = min(max_tmds_clock, 165000); 2203 } 2204 2205 return max_tmds_clock; 2206 } 2207 2208 static enum drm_mode_status 2209 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 2210 int clock, bool respect_downstream_limits, 2211 bool has_hdmi_sink) 2212 { 2213 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 2214 2215 if (clock < 25000) 2216 return MODE_CLOCK_LOW; 2217 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 2218 has_hdmi_sink)) 2219 return MODE_CLOCK_HIGH; 2220 2221 /* BXT DPLL can't generate 223-240 MHz */ 2222 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) 2223 return MODE_CLOCK_RANGE; 2224 2225 /* CHV DPLL can't generate 216-240 MHz */ 2226 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 2227 return MODE_CLOCK_RANGE; 2228 2229 return MODE_OK; 2230 } 2231 2232 static enum drm_mode_status 2233 intel_hdmi_mode_valid(struct drm_connector *connector, 2234 struct drm_display_mode *mode) 2235 { 2236 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2237 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 2238 struct drm_i915_private *dev_priv = to_i915(dev); 2239 enum drm_mode_status status; 2240 int clock = mode->clock; 2241 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 2242 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 2243 2244 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 2245 return MODE_NO_DBLESCAN; 2246 2247 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2248 clock *= 2; 2249 2250 if (clock > max_dotclk) 2251 return MODE_CLOCK_HIGH; 2252 2253 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2254 if (!has_hdmi_sink) 2255 return MODE_CLOCK_LOW; 2256 clock *= 2; 2257 } 2258 2259 if (drm_mode_is_420_only(&connector->display_info, mode)) 2260 clock /= 2; 2261 2262 /* check if we can do 8bpc */ 2263 status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink); 2264 2265 if (has_hdmi_sink) { 2266 /* if we can't do 8bpc we may still be able to do 12bpc */ 2267 if (status != MODE_OK && !HAS_GMCH(dev_priv)) 2268 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, 2269 true, has_hdmi_sink); 2270 2271 /* if we can't do 8,12bpc we may still be able to do 10bpc */ 2272 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) 2273 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, 2274 true, has_hdmi_sink); 2275 } 2276 if (status != MODE_OK) 2277 return status; 2278 2279 return intel_mode_valid_max_plane_size(dev_priv, mode, false); 2280 } 2281 2282 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 2283 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 2284 { 2285 struct drm_atomic_state *state = crtc_state->uapi.state; 2286 struct drm_connector_state *connector_state; 2287 struct drm_connector *connector; 2288 int i; 2289 2290 if (crtc_state->pipe_bpp < bpc * 3) 2291 return false; 2292 2293 if (!has_hdmi_sink) 2294 return false; 2295 2296 for_each_new_connector_in_state(state, connector, connector_state, i) { 2297 const struct drm_display_info *info = &connector->display_info; 2298 2299 if (connector_state->crtc != crtc_state->uapi.crtc) 2300 continue; 2301 2302 if (ycbcr420_output) { 2303 const struct drm_hdmi_info *hdmi = &info->hdmi; 2304 2305 if (bpc == 12 && !(hdmi->y420_dc_modes & 2306 DRM_EDID_YCBCR420_DC_36)) 2307 return false; 2308 else if (bpc == 10 && !(hdmi->y420_dc_modes & 2309 DRM_EDID_YCBCR420_DC_30)) 2310 return false; 2311 } else { 2312 if (bpc == 12 && !(info->edid_hdmi_dc_modes & 2313 DRM_EDID_HDMI_DC_36)) 2314 return false; 2315 else if (bpc == 10 && !(info->edid_hdmi_dc_modes & 2316 DRM_EDID_HDMI_DC_30)) 2317 return false; 2318 } 2319 } 2320 2321 return true; 2322 } 2323 2324 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 2325 int bpc) 2326 { 2327 struct drm_i915_private *dev_priv = 2328 to_i915(crtc_state->uapi.crtc->dev); 2329 const struct drm_display_mode *adjusted_mode = 2330 &crtc_state->hw.adjusted_mode; 2331 2332 if (HAS_GMCH(dev_priv)) 2333 return false; 2334 2335 if (bpc == 10 && INTEL_GEN(dev_priv) < 11) 2336 return false; 2337 2338 /* 2339 * HDMI deep color affects the clocks, so it's only possible 2340 * when not cloning with other encoder types. 2341 */ 2342 if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI)) 2343 return false; 2344 2345 /* Display Wa_1405510057:icl,ehl */ 2346 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 2347 bpc == 10 && IS_GEN(dev_priv, 11) && 2348 (adjusted_mode->crtc_hblank_end - 2349 adjusted_mode->crtc_hblank_start) % 8 == 2) 2350 return false; 2351 2352 return intel_hdmi_deep_color_possible(crtc_state, bpc, 2353 crtc_state->has_hdmi_sink, 2354 crtc_state->output_format == 2355 INTEL_OUTPUT_FORMAT_YCBCR420); 2356 } 2357 2358 static int 2359 intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state, 2360 const struct drm_connector_state *conn_state) 2361 { 2362 struct drm_connector *connector = conn_state->connector; 2363 struct drm_i915_private *i915 = to_i915(connector->dev); 2364 const struct drm_display_mode *adjusted_mode = 2365 &crtc_state->hw.adjusted_mode; 2366 2367 if (!drm_mode_is_420_only(&connector->display_info, adjusted_mode)) 2368 return 0; 2369 2370 if (!connector->ycbcr_420_allowed) { 2371 drm_err(&i915->drm, 2372 "Platform doesn't support YCBCR420 output\n"); 2373 return -EINVAL; 2374 } 2375 2376 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2377 2378 return intel_pch_panel_fitting(crtc_state, conn_state); 2379 } 2380 2381 static int intel_hdmi_port_clock(int clock, int bpc) 2382 { 2383 /* 2384 * Need to adjust the port link by: 2385 * 1.5x for 12bpc 2386 * 1.25x for 10bpc 2387 */ 2388 return clock * bpc / 8; 2389 } 2390 2391 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2392 struct intel_crtc_state *crtc_state, 2393 int clock) 2394 { 2395 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2396 int bpc; 2397 2398 for (bpc = 12; bpc >= 10; bpc -= 2) { 2399 if (hdmi_deep_color_possible(crtc_state, bpc) && 2400 hdmi_port_clock_valid(intel_hdmi, 2401 intel_hdmi_port_clock(clock, bpc), 2402 true, crtc_state->has_hdmi_sink) == MODE_OK) 2403 return bpc; 2404 } 2405 2406 return 8; 2407 } 2408 2409 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2410 struct intel_crtc_state *crtc_state) 2411 { 2412 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2413 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2414 const struct drm_display_mode *adjusted_mode = 2415 &crtc_state->hw.adjusted_mode; 2416 int bpc, clock = adjusted_mode->crtc_clock; 2417 2418 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2419 clock *= 2; 2420 2421 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 2422 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2423 clock /= 2; 2424 2425 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock); 2426 2427 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); 2428 2429 /* 2430 * pipe_bpp could already be below 8bpc due to 2431 * FDI bandwidth constraints. We shouldn't bump it 2432 * back up to 8bpc in that case. 2433 */ 2434 if (crtc_state->pipe_bpp > bpc * 3) 2435 crtc_state->pipe_bpp = bpc * 3; 2436 2437 drm_dbg_kms(&i915->drm, 2438 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2439 bpc, crtc_state->pipe_bpp); 2440 2441 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, 2442 false, crtc_state->has_hdmi_sink) != MODE_OK) { 2443 drm_dbg_kms(&i915->drm, 2444 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2445 crtc_state->port_clock); 2446 return -EINVAL; 2447 } 2448 2449 return 0; 2450 } 2451 2452 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2453 const struct drm_connector_state *conn_state) 2454 { 2455 const struct intel_digital_connector_state *intel_conn_state = 2456 to_intel_digital_connector_state(conn_state); 2457 const struct drm_display_mode *adjusted_mode = 2458 &crtc_state->hw.adjusted_mode; 2459 2460 /* 2461 * Our YCbCr output is always limited range. 2462 * crtc_state->limited_color_range only applies to RGB, 2463 * and it must never be set for YCbCr or we risk setting 2464 * some conflicting bits in PIPECONF which will mess up 2465 * the colors on the monitor. 2466 */ 2467 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2468 return false; 2469 2470 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2471 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2472 return crtc_state->has_hdmi_sink && 2473 drm_default_rgb_quant_range(adjusted_mode) == 2474 HDMI_QUANTIZATION_RANGE_LIMITED; 2475 } else { 2476 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2477 } 2478 } 2479 2480 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2481 const struct intel_crtc_state *crtc_state, 2482 const struct drm_connector_state *conn_state) 2483 { 2484 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2485 const struct intel_digital_connector_state *intel_conn_state = 2486 to_intel_digital_connector_state(conn_state); 2487 2488 if (!crtc_state->has_hdmi_sink) 2489 return false; 2490 2491 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2492 return intel_hdmi->has_audio; 2493 else 2494 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2495 } 2496 2497 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2498 struct intel_crtc_state *pipe_config, 2499 struct drm_connector_state *conn_state) 2500 { 2501 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2502 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2503 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2504 struct drm_connector *connector = conn_state->connector; 2505 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2506 int ret; 2507 2508 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2509 return -EINVAL; 2510 2511 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2512 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, 2513 conn_state); 2514 2515 if (pipe_config->has_hdmi_sink) 2516 pipe_config->has_infoframe = true; 2517 2518 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2519 pipe_config->pixel_multiplier = 2; 2520 2521 ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state); 2522 if (ret) 2523 return ret; 2524 2525 pipe_config->limited_color_range = 2526 intel_hdmi_limited_color_range(pipe_config, conn_state); 2527 2528 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 2529 pipe_config->has_pch_encoder = true; 2530 2531 pipe_config->has_audio = 2532 intel_hdmi_has_audio(encoder, pipe_config, conn_state); 2533 2534 ret = intel_hdmi_compute_clock(encoder, pipe_config); 2535 if (ret) 2536 return ret; 2537 2538 if (conn_state->picture_aspect_ratio) 2539 adjusted_mode->picture_aspect_ratio = 2540 conn_state->picture_aspect_ratio; 2541 2542 pipe_config->lane_count = 4; 2543 2544 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || 2545 IS_GEMINILAKE(dev_priv))) { 2546 if (scdc->scrambling.low_rates) 2547 pipe_config->hdmi_scrambling = true; 2548 2549 if (pipe_config->port_clock > 340000) { 2550 pipe_config->hdmi_scrambling = true; 2551 pipe_config->hdmi_high_tmds_clock_ratio = true; 2552 } 2553 } 2554 2555 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2556 conn_state); 2557 2558 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2559 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); 2560 return -EINVAL; 2561 } 2562 2563 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2564 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); 2565 return -EINVAL; 2566 } 2567 2568 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2569 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); 2570 return -EINVAL; 2571 } 2572 2573 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2574 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); 2575 return -EINVAL; 2576 } 2577 2578 return 0; 2579 } 2580 2581 static void 2582 intel_hdmi_unset_edid(struct drm_connector *connector) 2583 { 2584 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2585 2586 intel_hdmi->has_hdmi_sink = false; 2587 intel_hdmi->has_audio = false; 2588 2589 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2590 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2591 2592 kfree(to_intel_connector(connector)->detect_edid); 2593 to_intel_connector(connector)->detect_edid = NULL; 2594 } 2595 2596 static void 2597 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 2598 { 2599 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2600 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2601 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2602 struct i2c_adapter *adapter = 2603 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2604 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); 2605 2606 /* 2607 * Type 1 DVI adaptors are not required to implement any 2608 * registers, so we can't always detect their presence. 2609 * Ideally we should be able to check the state of the 2610 * CONFIG1 pin, but no such luck on our hardware. 2611 * 2612 * The only method left to us is to check the VBT to see 2613 * if the port is a dual mode capable DP port. But let's 2614 * only do that when we sucesfully read the EDID, to avoid 2615 * confusing log messages about DP dual mode adaptors when 2616 * there's nothing connected to the port. 2617 */ 2618 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2619 /* An overridden EDID imply that we want this port for testing. 2620 * Make sure not to set limits for that port. 2621 */ 2622 if (has_edid && !connector->override_edid && 2623 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2624 drm_dbg_kms(&dev_priv->drm, 2625 "Assuming DP dual mode adaptor presence based on VBT\n"); 2626 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2627 } else { 2628 type = DRM_DP_DUAL_MODE_NONE; 2629 } 2630 } 2631 2632 if (type == DRM_DP_DUAL_MODE_NONE) 2633 return; 2634 2635 hdmi->dp_dual_mode.type = type; 2636 hdmi->dp_dual_mode.max_tmds_clock = 2637 drm_dp_dual_mode_max_tmds_clock(type, adapter); 2638 2639 drm_dbg_kms(&dev_priv->drm, 2640 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2641 drm_dp_get_dual_mode_type_name(type), 2642 hdmi->dp_dual_mode.max_tmds_clock); 2643 } 2644 2645 static bool 2646 intel_hdmi_set_edid(struct drm_connector *connector) 2647 { 2648 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2649 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2650 intel_wakeref_t wakeref; 2651 struct edid *edid; 2652 bool connected = false; 2653 struct i2c_adapter *i2c; 2654 2655 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2656 2657 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2658 2659 edid = drm_get_edid(connector, i2c); 2660 2661 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2662 drm_dbg_kms(&dev_priv->drm, 2663 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2664 intel_gmbus_force_bit(i2c, true); 2665 edid = drm_get_edid(connector, i2c); 2666 intel_gmbus_force_bit(i2c, false); 2667 } 2668 2669 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 2670 2671 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2672 2673 to_intel_connector(connector)->detect_edid = edid; 2674 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2675 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2676 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2677 2678 connected = true; 2679 } 2680 2681 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2682 2683 return connected; 2684 } 2685 2686 static enum drm_connector_status 2687 intel_hdmi_detect(struct drm_connector *connector, bool force) 2688 { 2689 enum drm_connector_status status = connector_status_disconnected; 2690 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2691 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2692 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2693 intel_wakeref_t wakeref; 2694 2695 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2696 connector->base.id, connector->name); 2697 2698 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 2699 return connector_status_disconnected; 2700 2701 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2702 2703 if (INTEL_GEN(dev_priv) >= 11 && 2704 !intel_digital_port_connected(encoder)) 2705 goto out; 2706 2707 intel_hdmi_unset_edid(connector); 2708 2709 if (intel_hdmi_set_edid(connector)) 2710 status = connector_status_connected; 2711 2712 out: 2713 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2714 2715 if (status != connector_status_connected) 2716 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2717 2718 /* 2719 * Make sure the refs for power wells enabled during detect are 2720 * dropped to avoid a new detect cycle triggered by HPD polling. 2721 */ 2722 intel_display_power_flush_work(dev_priv); 2723 2724 return status; 2725 } 2726 2727 static void 2728 intel_hdmi_force(struct drm_connector *connector) 2729 { 2730 struct drm_i915_private *i915 = to_i915(connector->dev); 2731 2732 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2733 connector->base.id, connector->name); 2734 2735 intel_hdmi_unset_edid(connector); 2736 2737 if (connector->status != connector_status_connected) 2738 return; 2739 2740 intel_hdmi_set_edid(connector); 2741 } 2742 2743 static int intel_hdmi_get_modes(struct drm_connector *connector) 2744 { 2745 struct edid *edid; 2746 2747 edid = to_intel_connector(connector)->detect_edid; 2748 if (edid == NULL) 2749 return 0; 2750 2751 return intel_connector_update_modes(connector, edid); 2752 } 2753 2754 static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 2755 struct intel_encoder *encoder, 2756 const struct intel_crtc_state *pipe_config, 2757 const struct drm_connector_state *conn_state) 2758 { 2759 struct intel_digital_port *dig_port = 2760 enc_to_dig_port(encoder); 2761 2762 intel_hdmi_prepare(encoder, pipe_config); 2763 2764 dig_port->set_infoframes(encoder, 2765 pipe_config->has_infoframe, 2766 pipe_config, conn_state); 2767 } 2768 2769 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 2770 struct intel_encoder *encoder, 2771 const struct intel_crtc_state *pipe_config, 2772 const struct drm_connector_state *conn_state) 2773 { 2774 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2775 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2776 2777 vlv_phy_pre_encoder_enable(encoder, pipe_config); 2778 2779 /* HDMI 1.0V-2dB */ 2780 vlv_set_phy_signal_level(encoder, pipe_config, 2781 0x2b245f5f, 0x00002000, 2782 0x5578b83a, 0x2b247878); 2783 2784 dig_port->set_infoframes(encoder, 2785 pipe_config->has_infoframe, 2786 pipe_config, conn_state); 2787 2788 g4x_enable_hdmi(state, encoder, pipe_config, conn_state); 2789 2790 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 2791 } 2792 2793 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 2794 struct intel_encoder *encoder, 2795 const struct intel_crtc_state *pipe_config, 2796 const struct drm_connector_state *conn_state) 2797 { 2798 intel_hdmi_prepare(encoder, pipe_config); 2799 2800 vlv_phy_pre_pll_enable(encoder, pipe_config); 2801 } 2802 2803 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 2804 struct intel_encoder *encoder, 2805 const struct intel_crtc_state *pipe_config, 2806 const struct drm_connector_state *conn_state) 2807 { 2808 intel_hdmi_prepare(encoder, pipe_config); 2809 2810 chv_phy_pre_pll_enable(encoder, pipe_config); 2811 } 2812 2813 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 2814 struct intel_encoder *encoder, 2815 const struct intel_crtc_state *old_crtc_state, 2816 const struct drm_connector_state *old_conn_state) 2817 { 2818 chv_phy_post_pll_disable(encoder, old_crtc_state); 2819 } 2820 2821 static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 2822 struct intel_encoder *encoder, 2823 const struct intel_crtc_state *old_crtc_state, 2824 const struct drm_connector_state *old_conn_state) 2825 { 2826 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 2827 vlv_phy_reset_lanes(encoder, old_crtc_state); 2828 } 2829 2830 static void chv_hdmi_post_disable(struct intel_atomic_state *state, 2831 struct intel_encoder *encoder, 2832 const struct intel_crtc_state *old_crtc_state, 2833 const struct drm_connector_state *old_conn_state) 2834 { 2835 struct drm_device *dev = encoder->base.dev; 2836 struct drm_i915_private *dev_priv = to_i915(dev); 2837 2838 vlv_dpio_get(dev_priv); 2839 2840 /* Assert data lane reset */ 2841 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 2842 2843 vlv_dpio_put(dev_priv); 2844 } 2845 2846 static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 2847 struct intel_encoder *encoder, 2848 const struct intel_crtc_state *pipe_config, 2849 const struct drm_connector_state *conn_state) 2850 { 2851 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2852 struct drm_device *dev = encoder->base.dev; 2853 struct drm_i915_private *dev_priv = to_i915(dev); 2854 2855 chv_phy_pre_encoder_enable(encoder, pipe_config); 2856 2857 /* FIXME: Program the support xxx V-dB */ 2858 /* Use 800mV-0dB */ 2859 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); 2860 2861 dig_port->set_infoframes(encoder, 2862 pipe_config->has_infoframe, 2863 pipe_config, conn_state); 2864 2865 g4x_enable_hdmi(state, encoder, pipe_config, conn_state); 2866 2867 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 2868 2869 /* Second common lane will stay alive on its own now */ 2870 chv_phy_release_cl2_override(encoder); 2871 } 2872 2873 static struct i2c_adapter * 2874 intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2875 { 2876 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2877 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2878 2879 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2880 } 2881 2882 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2883 { 2884 struct drm_i915_private *i915 = to_i915(connector->dev); 2885 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2886 struct kobject *i2c_kobj = &adapter->dev.kobj; 2887 struct kobject *connector_kobj = &connector->kdev->kobj; 2888 int ret; 2889 2890 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2891 if (ret) 2892 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret); 2893 } 2894 2895 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2896 { 2897 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2898 struct kobject *i2c_kobj = &adapter->dev.kobj; 2899 struct kobject *connector_kobj = &connector->kdev->kobj; 2900 2901 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2902 } 2903 2904 static int 2905 intel_hdmi_connector_register(struct drm_connector *connector) 2906 { 2907 int ret; 2908 2909 ret = intel_connector_register(connector); 2910 if (ret) 2911 return ret; 2912 2913 intel_hdmi_create_i2c_symlink(connector); 2914 2915 return ret; 2916 } 2917 2918 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2919 { 2920 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2921 2922 cec_notifier_conn_unregister(n); 2923 2924 intel_hdmi_remove_i2c_symlink(connector); 2925 intel_connector_unregister(connector); 2926 } 2927 2928 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2929 .detect = intel_hdmi_detect, 2930 .force = intel_hdmi_force, 2931 .fill_modes = drm_helper_probe_single_connector_modes, 2932 .atomic_get_property = intel_digital_connector_atomic_get_property, 2933 .atomic_set_property = intel_digital_connector_atomic_set_property, 2934 .late_register = intel_hdmi_connector_register, 2935 .early_unregister = intel_hdmi_connector_unregister, 2936 .destroy = intel_connector_destroy, 2937 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2938 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2939 }; 2940 2941 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2942 .get_modes = intel_hdmi_get_modes, 2943 .mode_valid = intel_hdmi_mode_valid, 2944 .atomic_check = intel_digital_connector_atomic_check, 2945 }; 2946 2947 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 2948 .destroy = intel_encoder_destroy, 2949 }; 2950 2951 static void 2952 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2953 { 2954 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2955 2956 intel_attach_force_audio_property(connector); 2957 intel_attach_broadcast_rgb_property(connector); 2958 intel_attach_aspect_ratio_property(connector); 2959 2960 intel_attach_hdmi_colorspace_property(connector); 2961 drm_connector_attach_content_type_property(connector); 2962 2963 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2964 drm_object_attach_property(&connector->base, 2965 connector->dev->mode_config.hdr_output_metadata_property, 0); 2966 2967 if (!HAS_GMCH(dev_priv)) 2968 drm_connector_attach_max_bpc_property(connector, 8, 12); 2969 } 2970 2971 /* 2972 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2973 * @encoder: intel_encoder 2974 * @connector: drm_connector 2975 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2976 * or reset the high tmds clock ratio for scrambling 2977 * @scrambling: bool to Indicate if the function needs to set or reset 2978 * sink scrambling 2979 * 2980 * This function handles scrambling on HDMI 2.0 capable sinks. 2981 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2982 * it enables scrambling. This should be called before enabling the HDMI 2983 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2984 * detect a scrambled clock within 100 ms. 2985 * 2986 * Returns: 2987 * True on success, false on failure. 2988 */ 2989 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2990 struct drm_connector *connector, 2991 bool high_tmds_clock_ratio, 2992 bool scrambling) 2993 { 2994 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2995 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2996 struct drm_scrambling *sink_scrambling = 2997 &connector->display_info.hdmi.scdc.scrambling; 2998 struct i2c_adapter *adapter = 2999 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 3000 3001 if (!sink_scrambling->supported) 3002 return true; 3003 3004 drm_dbg_kms(&dev_priv->drm, 3005 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 3006 connector->base.id, connector->name, 3007 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); 3008 3009 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 3010 return drm_scdc_set_high_tmds_clock_ratio(adapter, 3011 high_tmds_clock_ratio) && 3012 drm_scdc_set_scrambling(adapter, scrambling); 3013 } 3014 3015 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3016 { 3017 u8 ddc_pin; 3018 3019 switch (port) { 3020 case PORT_B: 3021 ddc_pin = GMBUS_PIN_DPB; 3022 break; 3023 case PORT_C: 3024 ddc_pin = GMBUS_PIN_DPC; 3025 break; 3026 case PORT_D: 3027 ddc_pin = GMBUS_PIN_DPD_CHV; 3028 break; 3029 default: 3030 MISSING_CASE(port); 3031 ddc_pin = GMBUS_PIN_DPB; 3032 break; 3033 } 3034 return ddc_pin; 3035 } 3036 3037 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3038 { 3039 u8 ddc_pin; 3040 3041 switch (port) { 3042 case PORT_B: 3043 ddc_pin = GMBUS_PIN_1_BXT; 3044 break; 3045 case PORT_C: 3046 ddc_pin = GMBUS_PIN_2_BXT; 3047 break; 3048 default: 3049 MISSING_CASE(port); 3050 ddc_pin = GMBUS_PIN_1_BXT; 3051 break; 3052 } 3053 return ddc_pin; 3054 } 3055 3056 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 3057 enum port port) 3058 { 3059 u8 ddc_pin; 3060 3061 switch (port) { 3062 case PORT_B: 3063 ddc_pin = GMBUS_PIN_1_BXT; 3064 break; 3065 case PORT_C: 3066 ddc_pin = GMBUS_PIN_2_BXT; 3067 break; 3068 case PORT_D: 3069 ddc_pin = GMBUS_PIN_4_CNP; 3070 break; 3071 case PORT_F: 3072 ddc_pin = GMBUS_PIN_3_BXT; 3073 break; 3074 default: 3075 MISSING_CASE(port); 3076 ddc_pin = GMBUS_PIN_1_BXT; 3077 break; 3078 } 3079 return ddc_pin; 3080 } 3081 3082 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3083 { 3084 enum phy phy = intel_port_to_phy(dev_priv, port); 3085 3086 if (intel_phy_is_combo(dev_priv, phy)) 3087 return GMBUS_PIN_1_BXT + port; 3088 else if (intel_phy_is_tc(dev_priv, phy)) 3089 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 3090 3091 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 3092 return GMBUS_PIN_2_BXT; 3093 } 3094 3095 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3096 { 3097 enum phy phy = intel_port_to_phy(dev_priv, port); 3098 u8 ddc_pin; 3099 3100 switch (phy) { 3101 case PHY_A: 3102 ddc_pin = GMBUS_PIN_1_BXT; 3103 break; 3104 case PHY_B: 3105 ddc_pin = GMBUS_PIN_2_BXT; 3106 break; 3107 case PHY_C: 3108 ddc_pin = GMBUS_PIN_9_TC1_ICP; 3109 break; 3110 default: 3111 MISSING_CASE(phy); 3112 ddc_pin = GMBUS_PIN_1_BXT; 3113 break; 3114 } 3115 return ddc_pin; 3116 } 3117 3118 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3119 { 3120 enum phy phy = intel_port_to_phy(dev_priv, port); 3121 3122 WARN_ON(port == PORT_C); 3123 3124 /* 3125 * Pin mapping for RKL depends on which PCH is present. With TGP, the 3126 * final two outputs use type-c pins, even though they're actually 3127 * combo outputs. With CMP, the traditional DDI A-D pins are used for 3128 * all outputs. 3129 */ 3130 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 3131 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 3132 3133 return GMBUS_PIN_1_BXT + phy; 3134 } 3135 3136 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3137 { 3138 return intel_port_to_phy(dev_priv, port) + 1; 3139 } 3140 3141 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 3142 enum port port) 3143 { 3144 u8 ddc_pin; 3145 3146 switch (port) { 3147 case PORT_B: 3148 ddc_pin = GMBUS_PIN_DPB; 3149 break; 3150 case PORT_C: 3151 ddc_pin = GMBUS_PIN_DPC; 3152 break; 3153 case PORT_D: 3154 ddc_pin = GMBUS_PIN_DPD; 3155 break; 3156 default: 3157 MISSING_CASE(port); 3158 ddc_pin = GMBUS_PIN_DPB; 3159 break; 3160 } 3161 return ddc_pin; 3162 } 3163 3164 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 3165 { 3166 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3167 enum port port = encoder->port; 3168 u8 ddc_pin; 3169 3170 ddc_pin = intel_bios_alternate_ddc_pin(encoder); 3171 if (ddc_pin) { 3172 drm_dbg_kms(&dev_priv->drm, 3173 "Using DDC pin 0x%x for port %c (VBT)\n", 3174 ddc_pin, port_name(port)); 3175 return ddc_pin; 3176 } 3177 3178 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3179 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); 3180 else if (IS_ROCKETLAKE(dev_priv)) 3181 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); 3182 else if (HAS_PCH_MCC(dev_priv)) 3183 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 3184 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3185 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 3186 else if (HAS_PCH_CNP(dev_priv)) 3187 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 3188 else if (IS_GEN9_LP(dev_priv)) 3189 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 3190 else if (IS_CHERRYVIEW(dev_priv)) 3191 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 3192 else 3193 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 3194 3195 drm_dbg_kms(&dev_priv->drm, 3196 "Using DDC pin 0x%x for port %c (platform default)\n", 3197 ddc_pin, port_name(port)); 3198 3199 return ddc_pin; 3200 } 3201 3202 void intel_infoframe_init(struct intel_digital_port *dig_port) 3203 { 3204 struct drm_i915_private *dev_priv = 3205 to_i915(dig_port->base.base.dev); 3206 3207 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3208 dig_port->write_infoframe = vlv_write_infoframe; 3209 dig_port->read_infoframe = vlv_read_infoframe; 3210 dig_port->set_infoframes = vlv_set_infoframes; 3211 dig_port->infoframes_enabled = vlv_infoframes_enabled; 3212 } else if (IS_G4X(dev_priv)) { 3213 dig_port->write_infoframe = g4x_write_infoframe; 3214 dig_port->read_infoframe = g4x_read_infoframe; 3215 dig_port->set_infoframes = g4x_set_infoframes; 3216 dig_port->infoframes_enabled = g4x_infoframes_enabled; 3217 } else if (HAS_DDI(dev_priv)) { 3218 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) { 3219 dig_port->write_infoframe = lspcon_write_infoframe; 3220 dig_port->read_infoframe = lspcon_read_infoframe; 3221 dig_port->set_infoframes = lspcon_set_infoframes; 3222 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3223 } else { 3224 dig_port->write_infoframe = hsw_write_infoframe; 3225 dig_port->read_infoframe = hsw_read_infoframe; 3226 dig_port->set_infoframes = hsw_set_infoframes; 3227 dig_port->infoframes_enabled = hsw_infoframes_enabled; 3228 } 3229 } else if (HAS_PCH_IBX(dev_priv)) { 3230 dig_port->write_infoframe = ibx_write_infoframe; 3231 dig_port->read_infoframe = ibx_read_infoframe; 3232 dig_port->set_infoframes = ibx_set_infoframes; 3233 dig_port->infoframes_enabled = ibx_infoframes_enabled; 3234 } else { 3235 dig_port->write_infoframe = cpt_write_infoframe; 3236 dig_port->read_infoframe = cpt_read_infoframe; 3237 dig_port->set_infoframes = cpt_set_infoframes; 3238 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3239 } 3240 } 3241 3242 void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3243 struct intel_connector *intel_connector) 3244 { 3245 struct drm_connector *connector = &intel_connector->base; 3246 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3247 struct intel_encoder *intel_encoder = &dig_port->base; 3248 struct drm_device *dev = intel_encoder->base.dev; 3249 struct drm_i915_private *dev_priv = to_i915(dev); 3250 struct i2c_adapter *ddc; 3251 enum port port = intel_encoder->port; 3252 struct cec_connector_info conn_info; 3253 3254 drm_dbg_kms(&dev_priv->drm, 3255 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3256 intel_encoder->base.base.id, intel_encoder->base.name); 3257 3258 if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3259 return; 3260 3261 if (drm_WARN(dev, dig_port->max_lanes < 4, 3262 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3263 dig_port->max_lanes, intel_encoder->base.base.id, 3264 intel_encoder->base.name)) 3265 return; 3266 3267 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); 3268 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 3269 3270 drm_connector_init_with_ddc(dev, connector, 3271 &intel_hdmi_connector_funcs, 3272 DRM_MODE_CONNECTOR_HDMIA, 3273 ddc); 3274 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3275 3276 connector->interlace_allowed = 1; 3277 connector->doublescan_allowed = 0; 3278 connector->stereo_allowed = 1; 3279 3280 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 3281 connector->ycbcr_420_allowed = true; 3282 3283 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3284 3285 if (HAS_DDI(dev_priv)) 3286 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3287 else 3288 intel_connector->get_hw_state = intel_connector_get_hw_state; 3289 3290 intel_hdmi_add_properties(intel_hdmi, connector); 3291 3292 intel_connector_attach_encoder(intel_connector, intel_encoder); 3293 intel_hdmi->attached_connector = intel_connector; 3294 3295 if (is_hdcp_supported(dev_priv, port)) { 3296 int ret = intel_hdcp_init(intel_connector, dig_port, 3297 &intel_hdmi_hdcp_shim); 3298 if (ret) 3299 drm_dbg_kms(&dev_priv->drm, 3300 "HDCP init failed, skipping.\n"); 3301 } 3302 3303 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3304 * 0xd. Failure to do so will result in spurious interrupts being 3305 * generated on the port when a cable is not attached. 3306 */ 3307 if (IS_G45(dev_priv)) { 3308 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 3309 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 3310 (temp & ~0xf) | 0xd); 3311 } 3312 3313 cec_fill_conn_info_from_drm(&conn_info, connector); 3314 3315 intel_hdmi->cec_notifier = 3316 cec_notifier_conn_register(dev->dev, port_identifier(port), 3317 &conn_info); 3318 if (!intel_hdmi->cec_notifier) 3319 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); 3320 } 3321 3322 static enum intel_hotplug_state 3323 intel_hdmi_hotplug(struct intel_encoder *encoder, 3324 struct intel_connector *connector) 3325 { 3326 enum intel_hotplug_state state; 3327 3328 state = intel_encoder_hotplug(encoder, connector); 3329 3330 /* 3331 * On many platforms the HDMI live state signal is known to be 3332 * unreliable, so we can't use it to detect if a sink is connected or 3333 * not. Instead we detect if it's connected based on whether we can 3334 * read the EDID or not. That in turn has a problem during disconnect, 3335 * since the HPD interrupt may be raised before the DDC lines get 3336 * disconnected (due to how the required length of DDC vs. HPD 3337 * connector pins are specified) and so we'll still be able to get a 3338 * valid EDID. To solve this schedule another detection cycle if this 3339 * time around we didn't detect any change in the sink's connection 3340 * status. 3341 */ 3342 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 3343 state = INTEL_HOTPLUG_RETRY; 3344 3345 return state; 3346 } 3347 3348 void intel_hdmi_init(struct drm_i915_private *dev_priv, 3349 i915_reg_t hdmi_reg, enum port port) 3350 { 3351 struct intel_digital_port *dig_port; 3352 struct intel_encoder *intel_encoder; 3353 struct intel_connector *intel_connector; 3354 3355 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 3356 if (!dig_port) 3357 return; 3358 3359 intel_connector = intel_connector_alloc(); 3360 if (!intel_connector) { 3361 kfree(dig_port); 3362 return; 3363 } 3364 3365 intel_encoder = &dig_port->base; 3366 3367 mutex_init(&dig_port->hdcp_mutex); 3368 3369 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3370 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 3371 "HDMI %c", port_name(port)); 3372 3373 intel_encoder->hotplug = intel_hdmi_hotplug; 3374 intel_encoder->compute_config = intel_hdmi_compute_config; 3375 if (HAS_PCH_SPLIT(dev_priv)) { 3376 intel_encoder->disable = pch_disable_hdmi; 3377 intel_encoder->post_disable = pch_post_disable_hdmi; 3378 } else { 3379 intel_encoder->disable = g4x_disable_hdmi; 3380 } 3381 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 3382 intel_encoder->get_config = intel_hdmi_get_config; 3383 if (IS_CHERRYVIEW(dev_priv)) { 3384 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 3385 intel_encoder->pre_enable = chv_hdmi_pre_enable; 3386 intel_encoder->enable = vlv_enable_hdmi; 3387 intel_encoder->post_disable = chv_hdmi_post_disable; 3388 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 3389 } else if (IS_VALLEYVIEW(dev_priv)) { 3390 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 3391 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 3392 intel_encoder->enable = vlv_enable_hdmi; 3393 intel_encoder->post_disable = vlv_hdmi_post_disable; 3394 } else { 3395 intel_encoder->pre_enable = intel_hdmi_pre_enable; 3396 if (HAS_PCH_CPT(dev_priv)) 3397 intel_encoder->enable = cpt_enable_hdmi; 3398 else if (HAS_PCH_IBX(dev_priv)) 3399 intel_encoder->enable = ibx_enable_hdmi; 3400 else 3401 intel_encoder->enable = g4x_enable_hdmi; 3402 } 3403 3404 intel_encoder->type = INTEL_OUTPUT_HDMI; 3405 intel_encoder->power_domain = intel_port_to_power_domain(port); 3406 intel_encoder->port = port; 3407 if (IS_CHERRYVIEW(dev_priv)) { 3408 if (port == PORT_D) 3409 intel_encoder->pipe_mask = BIT(PIPE_C); 3410 else 3411 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 3412 } else { 3413 intel_encoder->pipe_mask = ~0; 3414 } 3415 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 3416 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 3417 /* 3418 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 3419 * to work on real hardware. And since g4x can send infoframes to 3420 * only one port anyway, nothing is lost by allowing it. 3421 */ 3422 if (IS_G4X(dev_priv)) 3423 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 3424 3425 dig_port->hdmi.hdmi_reg = hdmi_reg; 3426 dig_port->dp.output_reg = INVALID_MMIO_REG; 3427 dig_port->max_lanes = 4; 3428 3429 intel_infoframe_init(dig_port); 3430 3431 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 3432 intel_hdmi_init_connector(dig_port, intel_connector); 3433 } 3434 3435 /* 3436 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3437 * @vactive: Vactive of a display mode 3438 * 3439 * @return: appropriate dsc slice height for a given mode. 3440 */ 3441 int intel_hdmi_dsc_get_slice_height(int vactive) 3442 { 3443 int slice_height; 3444 3445 /* 3446 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3447 * Select smallest slice height >=96, that results in a valid PPS and 3448 * requires minimum padding lines required for final slice. 3449 * 3450 * Assumption : Vactive is even. 3451 */ 3452 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3453 if (vactive % slice_height == 0) 3454 return slice_height; 3455 3456 return 0; 3457 } 3458 3459 /* 3460 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3461 * and dsc decoder capabilities 3462 * 3463 * @crtc_state: intel crtc_state 3464 * @src_max_slices: maximum slices supported by the DSC encoder 3465 * @src_max_slice_width: maximum slice width supported by DSC encoder 3466 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3467 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3468 * 3469 * @return: num of dsc slices that can be supported by the dsc encoder 3470 * and decoder. 3471 */ 3472 int 3473 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3474 int src_max_slices, int src_max_slice_width, 3475 int hdmi_max_slices, int hdmi_throughput) 3476 { 3477 /* Pixel rates in KPixels/sec */ 3478 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3479 /* 3480 * Rates at which the source and sink are required to process pixels in each 3481 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3482 */ 3483 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3484 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3485 3486 /* Spec limits the slice width to 2720 pixels */ 3487 #define MAX_HDMI_SLICE_WIDTH 2720 3488 int kslice_adjust; 3489 int adjusted_clk_khz; 3490 int min_slices; 3491 int target_slices; 3492 int max_throughput; /* max clock freq. in khz per slice */ 3493 int max_slice_width; 3494 int slice_width; 3495 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3496 3497 if (!hdmi_throughput) 3498 return 0; 3499 3500 /* 3501 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3502 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3503 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3504 * dividing adjusted clock value by 10. 3505 */ 3506 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3507 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3508 kslice_adjust = 10; 3509 else 3510 kslice_adjust = 5; 3511 3512 /* 3513 * As per spec, the rate at which the source and the sink process 3514 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3515 * This depends upon the pixel clock rate and output formats 3516 * (kslice adjust). 3517 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3518 * at max 340MHz, otherwise they can be processed at max 400MHz. 3519 */ 3520 3521 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3522 3523 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3524 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3525 else 3526 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3527 3528 /* 3529 * Taking into account the sink's capability for maximum 3530 * clock per slice (in MHz) as read from HF-VSDB. 3531 */ 3532 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3533 3534 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3535 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3536 3537 /* 3538 * Keep on increasing the num of slices/line, starting from min_slices 3539 * per line till we get such a number, for which the slice_width is 3540 * just less than max_slice_width. The slices/line selected should be 3541 * less than or equal to the max horizontal slices that the combination 3542 * of PCON encoder and HDMI decoder can support. 3543 */ 3544 slice_width = max_slice_width; 3545 3546 do { 3547 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3548 target_slices = 1; 3549 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3550 target_slices = 2; 3551 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3552 target_slices = 4; 3553 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3554 target_slices = 8; 3555 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3556 target_slices = 12; 3557 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3558 target_slices = 16; 3559 else 3560 return 0; 3561 3562 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3563 if (slice_width >= max_slice_width) 3564 min_slices = target_slices + 1; 3565 } while (slice_width >= max_slice_width); 3566 3567 return target_slices; 3568 } 3569 3570 /* 3571 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3572 * source and sink capabilities. 3573 * 3574 * @src_fraction_bpp: fractional bpp supported by the source 3575 * @slice_width: dsc slice width supported by the source and sink 3576 * @num_slices: num of slices supported by the source and sink 3577 * @output_format: video output format 3578 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3579 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3580 * 3581 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3582 */ 3583 int 3584 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3585 int output_format, bool hdmi_all_bpp, 3586 int hdmi_max_chunk_bytes) 3587 { 3588 int max_dsc_bpp, min_dsc_bpp; 3589 int target_bytes; 3590 bool bpp_found = false; 3591 int bpp_decrement_x16; 3592 int bpp_target; 3593 int bpp_target_x16; 3594 3595 /* 3596 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3597 * Start with the max bpp and keep on decrementing with 3598 * fractional bpp, if supported by PCON DSC encoder 3599 * 3600 * for each bpp we check if no of bytes can be supported by HDMI sink 3601 */ 3602 3603 /* Assuming: bpc as 8*/ 3604 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3605 min_dsc_bpp = 6; 3606 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3607 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3608 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3609 min_dsc_bpp = 8; 3610 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3611 } else { 3612 /* Assuming 4:2:2 encoding */ 3613 min_dsc_bpp = 7; 3614 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3615 } 3616 3617 /* 3618 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3619 * Section 7.7.34 : Source shall not enable compressed Video 3620 * Transport with bpp_target settings above 12 bpp unless 3621 * DSC_all_bpp is set to 1. 3622 */ 3623 if (!hdmi_all_bpp) 3624 max_dsc_bpp = min(max_dsc_bpp, 12); 3625 3626 /* 3627 * The Sink has a limit of compressed data in bytes for a scanline, 3628 * as described in max_chunk_bytes field in HFVSDB block of edid. 3629 * The no. of bytes depend on the target bits per pixel that the 3630 * source configures. So we start with the max_bpp and calculate 3631 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3632 * till we get the target_chunk_bytes just less than what the sink's 3633 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3634 * 3635 * The decrement is according to the fractional support from PCON DSC 3636 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3637 * 3638 * bpp_target_x16 = bpp_target * 16 3639 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3640 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3641 */ 3642 3643 bpp_target = max_dsc_bpp; 3644 3645 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3646 if (!src_fractional_bpp) 3647 src_fractional_bpp = 1; 3648 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3649 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3650 3651 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3652 int bpp; 3653 3654 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3655 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3656 if (target_bytes <= hdmi_max_chunk_bytes) { 3657 bpp_found = true; 3658 break; 3659 } 3660 bpp_target_x16 -= bpp_decrement_x16; 3661 } 3662 if (bpp_found) 3663 return bpp_target_x16; 3664 3665 return 0; 3666 } 3667