1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * 5 * Authors: 6 * Sean Paul <seanpaul@chromium.org> 7 */ 8 9 #include <linux/component.h> 10 #include <linux/i2c.h> 11 #include <linux/random.h> 12 13 #include <drm/drm_hdcp.h> 14 #include <drm/i915_component.h> 15 16 #include "i915_reg.h" 17 #include "intel_drv.h" 18 #include "intel_hdcp.h" 19 #include "intel_sideband.h" 20 21 #define KEY_LOAD_TRIES 5 22 #define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50 23 #define HDCP2_LC_RETRY_CNT 3 24 25 static 26 bool intel_hdcp_is_ksv_valid(u8 *ksv) 27 { 28 int i, ones = 0; 29 /* KSV has 20 1's and 20 0's */ 30 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 31 ones += hweight8(ksv[i]); 32 if (ones != 20) 33 return false; 34 35 return true; 36 } 37 38 static 39 int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, 40 const struct intel_hdcp_shim *shim, u8 *bksv) 41 { 42 int ret, i, tries = 2; 43 44 /* HDCP spec states that we must retry the bksv if it is invalid */ 45 for (i = 0; i < tries; i++) { 46 ret = shim->read_bksv(intel_dig_port, bksv); 47 if (ret) 48 return ret; 49 if (intel_hdcp_is_ksv_valid(bksv)) 50 break; 51 } 52 if (i == tries) { 53 DRM_DEBUG_KMS("Bksv is invalid\n"); 54 return -ENODEV; 55 } 56 57 return 0; 58 } 59 60 /* Is HDCP1.4 capable on Platform and Sink */ 61 bool intel_hdcp_capable(struct intel_connector *connector) 62 { 63 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 64 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 65 bool capable = false; 66 u8 bksv[5]; 67 68 if (!shim) 69 return capable; 70 71 if (shim->hdcp_capable) { 72 shim->hdcp_capable(intel_dig_port, &capable); 73 } else { 74 if (!intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv)) 75 capable = true; 76 } 77 78 return capable; 79 } 80 81 /* Is HDCP2.2 capable on Platform and Sink */ 82 bool intel_hdcp2_capable(struct intel_connector *connector) 83 { 84 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 85 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 86 struct intel_hdcp *hdcp = &connector->hdcp; 87 bool capable = false; 88 89 /* I915 support for HDCP2.2 */ 90 if (!hdcp->hdcp2_supported) 91 return false; 92 93 /* MEI interface is solid */ 94 mutex_lock(&dev_priv->hdcp_comp_mutex); 95 if (!dev_priv->hdcp_comp_added || !dev_priv->hdcp_master) { 96 mutex_unlock(&dev_priv->hdcp_comp_mutex); 97 return false; 98 } 99 mutex_unlock(&dev_priv->hdcp_comp_mutex); 100 101 /* Sink's capability for HDCP2.2 */ 102 hdcp->shim->hdcp_2_2_capable(intel_dig_port, &capable); 103 104 return capable; 105 } 106 107 static inline bool intel_hdcp_in_use(struct intel_connector *connector) 108 { 109 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 110 enum port port = connector->encoder->port; 111 u32 reg; 112 113 reg = I915_READ(PORT_HDCP_STATUS(port)); 114 return reg & HDCP_STATUS_ENC; 115 } 116 117 static inline bool intel_hdcp2_in_use(struct intel_connector *connector) 118 { 119 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 120 enum port port = connector->encoder->port; 121 u32 reg; 122 123 reg = I915_READ(HDCP2_STATUS_DDI(port)); 124 return reg & LINK_ENCRYPTION_STATUS; 125 } 126 127 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port, 128 const struct intel_hdcp_shim *shim) 129 { 130 int ret, read_ret; 131 bool ksv_ready; 132 133 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 134 ret = __wait_for(read_ret = shim->read_ksv_ready(intel_dig_port, 135 &ksv_ready), 136 read_ret || ksv_ready, 5 * 1000 * 1000, 1000, 137 100 * 1000); 138 if (ret) 139 return ret; 140 if (read_ret) 141 return read_ret; 142 if (!ksv_ready) 143 return -ETIMEDOUT; 144 145 return 0; 146 } 147 148 static bool hdcp_key_loadable(struct drm_i915_private *dev_priv) 149 { 150 struct i915_power_domains *power_domains = &dev_priv->power_domains; 151 struct i915_power_well *power_well; 152 enum i915_power_well_id id; 153 bool enabled = false; 154 155 /* 156 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 157 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 158 */ 159 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 160 id = HSW_DISP_PW_GLOBAL; 161 else 162 id = SKL_DISP_PW_1; 163 164 mutex_lock(&power_domains->lock); 165 166 /* PG1 (power well #1) needs to be enabled */ 167 for_each_power_well(dev_priv, power_well) { 168 if (power_well->desc->id == id) { 169 enabled = power_well->desc->ops->is_enabled(dev_priv, 170 power_well); 171 break; 172 } 173 } 174 mutex_unlock(&power_domains->lock); 175 176 /* 177 * Another req for hdcp key loadability is enabled state of pll for 178 * cdclk. Without active crtc we wont land here. So we are assuming that 179 * cdclk is already on. 180 */ 181 182 return enabled; 183 } 184 185 static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv) 186 { 187 I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 188 I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | 189 HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 190 } 191 192 static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) 193 { 194 int ret; 195 u32 val; 196 197 val = I915_READ(HDCP_KEY_STATUS); 198 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 199 return 0; 200 201 /* 202 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 203 * out of reset. So if Key is not already loaded, its an error state. 204 */ 205 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 206 if (!(I915_READ(HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 207 return -ENXIO; 208 209 /* 210 * Initiate loading the HDCP key from fuses. 211 * 212 * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9 213 * platforms except BXT and GLK, differ in the key load trigger process 214 * from other platforms. So GEN9_BC uses the GT Driver Mailbox i/f. 215 */ 216 if (IS_GEN9_BC(dev_priv)) { 217 ret = sandybridge_pcode_write(dev_priv, 218 SKL_PCODE_LOAD_HDCP_KEYS, 1); 219 if (ret) { 220 DRM_ERROR("Failed to initiate HDCP key load (%d)\n", 221 ret); 222 return ret; 223 } 224 } else { 225 I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 226 } 227 228 /* Wait for the keys to load (500us) */ 229 ret = __intel_wait_for_register(&dev_priv->uncore, HDCP_KEY_STATUS, 230 HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, 231 10, 1, &val); 232 if (ret) 233 return ret; 234 else if (!(val & HDCP_KEY_LOAD_STATUS)) 235 return -ENXIO; 236 237 /* Send Aksv over to PCH display for use in authentication */ 238 I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 239 240 return 0; 241 } 242 243 /* Returns updated SHA-1 index */ 244 static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text) 245 { 246 I915_WRITE(HDCP_SHA_TEXT, sha_text); 247 if (intel_wait_for_register(&dev_priv->uncore, HDCP_REP_CTL, 248 HDCP_SHA1_READY, HDCP_SHA1_READY, 1)) { 249 DRM_ERROR("Timed out waiting for SHA1 ready\n"); 250 return -ETIMEDOUT; 251 } 252 return 0; 253 } 254 255 static 256 u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port) 257 { 258 enum port port = intel_dig_port->base.port; 259 switch (port) { 260 case PORT_A: 261 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 262 case PORT_B: 263 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 264 case PORT_C: 265 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 266 case PORT_D: 267 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 268 case PORT_E: 269 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 270 default: 271 break; 272 } 273 DRM_ERROR("Unknown port %d\n", port); 274 return -EINVAL; 275 } 276 277 static 278 int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port, 279 const struct intel_hdcp_shim *shim, 280 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 281 { 282 struct drm_i915_private *dev_priv; 283 u32 vprime, sha_text, sha_leftovers, rep_ctl; 284 int ret, i, j, sha_idx; 285 286 dev_priv = intel_dig_port->base.base.dev->dev_private; 287 288 /* Process V' values from the receiver */ 289 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 290 ret = shim->read_v_prime_part(intel_dig_port, i, &vprime); 291 if (ret) 292 return ret; 293 I915_WRITE(HDCP_SHA_V_PRIME(i), vprime); 294 } 295 296 /* 297 * We need to write the concatenation of all device KSVs, BINFO (DP) || 298 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 299 * stream is written via the HDCP_SHA_TEXT register in 32-bit 300 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 301 * index will keep track of our progress through the 64 bytes as well as 302 * helping us work the 40-bit KSVs through our 32-bit register. 303 * 304 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 305 */ 306 sha_idx = 0; 307 sha_text = 0; 308 sha_leftovers = 0; 309 rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port); 310 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 311 for (i = 0; i < num_downstream; i++) { 312 unsigned int sha_empty; 313 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 314 315 /* Fill up the empty slots in sha_text and write it out */ 316 sha_empty = sizeof(sha_text) - sha_leftovers; 317 for (j = 0; j < sha_empty; j++) 318 sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8); 319 320 ret = intel_write_sha_text(dev_priv, sha_text); 321 if (ret < 0) 322 return ret; 323 324 /* Programming guide writes this every 64 bytes */ 325 sha_idx += sizeof(sha_text); 326 if (!(sha_idx % 64)) 327 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 328 329 /* Store the leftover bytes from the ksv in sha_text */ 330 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 331 sha_text = 0; 332 for (j = 0; j < sha_leftovers; j++) 333 sha_text |= ksv[sha_empty + j] << 334 ((sizeof(sha_text) - j - 1) * 8); 335 336 /* 337 * If we still have room in sha_text for more data, continue. 338 * Otherwise, write it out immediately. 339 */ 340 if (sizeof(sha_text) > sha_leftovers) 341 continue; 342 343 ret = intel_write_sha_text(dev_priv, sha_text); 344 if (ret < 0) 345 return ret; 346 sha_leftovers = 0; 347 sha_text = 0; 348 sha_idx += sizeof(sha_text); 349 } 350 351 /* 352 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 353 * bytes are leftover from the last ksv, we might be able to fit them 354 * all in sha_text (first 2 cases), or we might need to split them up 355 * into 2 writes (last 2 cases). 356 */ 357 if (sha_leftovers == 0) { 358 /* Write 16 bits of text, 16 bits of M0 */ 359 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16); 360 ret = intel_write_sha_text(dev_priv, 361 bstatus[0] << 8 | bstatus[1]); 362 if (ret < 0) 363 return ret; 364 sha_idx += sizeof(sha_text); 365 366 /* Write 32 bits of M0 */ 367 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); 368 ret = intel_write_sha_text(dev_priv, 0); 369 if (ret < 0) 370 return ret; 371 sha_idx += sizeof(sha_text); 372 373 /* Write 16 bits of M0 */ 374 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16); 375 ret = intel_write_sha_text(dev_priv, 0); 376 if (ret < 0) 377 return ret; 378 sha_idx += sizeof(sha_text); 379 380 } else if (sha_leftovers == 1) { 381 /* Write 24 bits of text, 8 bits of M0 */ 382 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24); 383 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 384 /* Only 24-bits of data, must be in the LSB */ 385 sha_text = (sha_text & 0xffffff00) >> 8; 386 ret = intel_write_sha_text(dev_priv, sha_text); 387 if (ret < 0) 388 return ret; 389 sha_idx += sizeof(sha_text); 390 391 /* Write 32 bits of M0 */ 392 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); 393 ret = intel_write_sha_text(dev_priv, 0); 394 if (ret < 0) 395 return ret; 396 sha_idx += sizeof(sha_text); 397 398 /* Write 24 bits of M0 */ 399 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8); 400 ret = intel_write_sha_text(dev_priv, 0); 401 if (ret < 0) 402 return ret; 403 sha_idx += sizeof(sha_text); 404 405 } else if (sha_leftovers == 2) { 406 /* Write 32 bits of text */ 407 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 408 sha_text |= bstatus[0] << 24 | bstatus[1] << 16; 409 ret = intel_write_sha_text(dev_priv, sha_text); 410 if (ret < 0) 411 return ret; 412 sha_idx += sizeof(sha_text); 413 414 /* Write 64 bits of M0 */ 415 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); 416 for (i = 0; i < 2; i++) { 417 ret = intel_write_sha_text(dev_priv, 0); 418 if (ret < 0) 419 return ret; 420 sha_idx += sizeof(sha_text); 421 } 422 } else if (sha_leftovers == 3) { 423 /* Write 32 bits of text */ 424 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 425 sha_text |= bstatus[0] << 24; 426 ret = intel_write_sha_text(dev_priv, sha_text); 427 if (ret < 0) 428 return ret; 429 sha_idx += sizeof(sha_text); 430 431 /* Write 8 bits of text, 24 bits of M0 */ 432 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8); 433 ret = intel_write_sha_text(dev_priv, bstatus[1]); 434 if (ret < 0) 435 return ret; 436 sha_idx += sizeof(sha_text); 437 438 /* Write 32 bits of M0 */ 439 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); 440 ret = intel_write_sha_text(dev_priv, 0); 441 if (ret < 0) 442 return ret; 443 sha_idx += sizeof(sha_text); 444 445 /* Write 8 bits of M0 */ 446 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24); 447 ret = intel_write_sha_text(dev_priv, 0); 448 if (ret < 0) 449 return ret; 450 sha_idx += sizeof(sha_text); 451 } else { 452 DRM_DEBUG_KMS("Invalid number of leftovers %d\n", 453 sha_leftovers); 454 return -EINVAL; 455 } 456 457 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 458 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 459 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 460 ret = intel_write_sha_text(dev_priv, 0); 461 if (ret < 0) 462 return ret; 463 sha_idx += sizeof(sha_text); 464 } 465 466 /* 467 * Last write gets the length of the concatenation in bits. That is: 468 * - 5 bytes per device 469 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 470 */ 471 sha_text = (num_downstream * 5 + 10) * 8; 472 ret = intel_write_sha_text(dev_priv, sha_text); 473 if (ret < 0) 474 return ret; 475 476 /* Tell the HW we're done with the hash and wait for it to ACK */ 477 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_COMPLETE_HASH); 478 if (intel_wait_for_register(&dev_priv->uncore, HDCP_REP_CTL, 479 HDCP_SHA1_COMPLETE, 480 HDCP_SHA1_COMPLETE, 1)) { 481 DRM_ERROR("Timed out waiting for SHA1 complete\n"); 482 return -ETIMEDOUT; 483 } 484 if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 485 DRM_DEBUG_KMS("SHA-1 mismatch, HDCP failed\n"); 486 return -ENXIO; 487 } 488 489 return 0; 490 } 491 492 /* Implements Part 2 of the HDCP authorization procedure */ 493 static 494 int intel_hdcp_auth_downstream(struct intel_connector *connector) 495 { 496 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 497 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 498 struct drm_device *dev = connector->base.dev; 499 u8 bstatus[2], num_downstream, *ksv_fifo; 500 int ret, i, tries = 3; 501 502 ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim); 503 if (ret) { 504 DRM_DEBUG_KMS("KSV list failed to become ready (%d)\n", ret); 505 return ret; 506 } 507 508 ret = shim->read_bstatus(intel_dig_port, bstatus); 509 if (ret) 510 return ret; 511 512 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 513 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 514 DRM_DEBUG_KMS("Max Topology Limit Exceeded\n"); 515 return -EPERM; 516 } 517 518 /* 519 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 520 * the HDCP encryption. That implies that repeater can't have its own 521 * display. As there is no consumption of encrypted content in the 522 * repeater with 0 downstream devices, we are failing the 523 * authentication. 524 */ 525 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 526 if (num_downstream == 0) { 527 DRM_DEBUG_KMS("Repeater with zero downstream devices\n"); 528 return -EINVAL; 529 } 530 531 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 532 if (!ksv_fifo) { 533 DRM_DEBUG_KMS("Out of mem: ksv_fifo\n"); 534 return -ENOMEM; 535 } 536 537 ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo); 538 if (ret) 539 goto err; 540 541 if (drm_hdcp_check_ksvs_revoked(dev, ksv_fifo, num_downstream)) { 542 DRM_ERROR("Revoked Ksv(s) in ksv_fifo\n"); 543 return -EPERM; 544 } 545 546 /* 547 * When V prime mismatches, DP Spec mandates re-read of 548 * V prime atleast twice. 549 */ 550 for (i = 0; i < tries; i++) { 551 ret = intel_hdcp_validate_v_prime(intel_dig_port, shim, 552 ksv_fifo, num_downstream, 553 bstatus); 554 if (!ret) 555 break; 556 } 557 558 if (i == tries) { 559 DRM_DEBUG_KMS("V Prime validation failed.(%d)\n", ret); 560 goto err; 561 } 562 563 DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n", 564 num_downstream); 565 ret = 0; 566 err: 567 kfree(ksv_fifo); 568 return ret; 569 } 570 571 /* Implements Part 1 of the HDCP authorization procedure */ 572 static int intel_hdcp_auth(struct intel_connector *connector) 573 { 574 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 575 struct intel_hdcp *hdcp = &connector->hdcp; 576 struct drm_device *dev = connector->base.dev; 577 const struct intel_hdcp_shim *shim = hdcp->shim; 578 struct drm_i915_private *dev_priv; 579 enum port port; 580 unsigned long r0_prime_gen_start; 581 int ret, i, tries = 2; 582 union { 583 u32 reg[2]; 584 u8 shim[DRM_HDCP_AN_LEN]; 585 } an; 586 union { 587 u32 reg[2]; 588 u8 shim[DRM_HDCP_KSV_LEN]; 589 } bksv; 590 union { 591 u32 reg; 592 u8 shim[DRM_HDCP_RI_LEN]; 593 } ri; 594 bool repeater_present, hdcp_capable; 595 596 dev_priv = intel_dig_port->base.base.dev->dev_private; 597 598 port = intel_dig_port->base.port; 599 600 /* 601 * Detects whether the display is HDCP capable. Although we check for 602 * valid Bksv below, the HDCP over DP spec requires that we check 603 * whether the display supports HDCP before we write An. For HDMI 604 * displays, this is not necessary. 605 */ 606 if (shim->hdcp_capable) { 607 ret = shim->hdcp_capable(intel_dig_port, &hdcp_capable); 608 if (ret) 609 return ret; 610 if (!hdcp_capable) { 611 DRM_DEBUG_KMS("Panel is not HDCP capable\n"); 612 return -EINVAL; 613 } 614 } 615 616 /* Initialize An with 2 random values and acquire it */ 617 for (i = 0; i < 2; i++) 618 I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32()); 619 I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN); 620 621 /* Wait for An to be acquired */ 622 if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port), 623 HDCP_STATUS_AN_READY, 624 HDCP_STATUS_AN_READY, 1)) { 625 DRM_ERROR("Timed out waiting for An\n"); 626 return -ETIMEDOUT; 627 } 628 629 an.reg[0] = I915_READ(PORT_HDCP_ANLO(port)); 630 an.reg[1] = I915_READ(PORT_HDCP_ANHI(port)); 631 ret = shim->write_an_aksv(intel_dig_port, an.shim); 632 if (ret) 633 return ret; 634 635 r0_prime_gen_start = jiffies; 636 637 memset(&bksv, 0, sizeof(bksv)); 638 639 ret = intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv.shim); 640 if (ret < 0) 641 return ret; 642 643 if (drm_hdcp_check_ksvs_revoked(dev, bksv.shim, 1)) { 644 DRM_ERROR("BKSV is revoked\n"); 645 return -EPERM; 646 } 647 648 I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]); 649 I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]); 650 651 ret = shim->repeater_present(intel_dig_port, &repeater_present); 652 if (ret) 653 return ret; 654 if (repeater_present) 655 I915_WRITE(HDCP_REP_CTL, 656 intel_hdcp_get_repeater_ctl(intel_dig_port)); 657 658 ret = shim->toggle_signalling(intel_dig_port, true); 659 if (ret) 660 return ret; 661 662 I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC); 663 664 /* Wait for R0 ready */ 665 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & 666 (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) { 667 DRM_ERROR("Timed out waiting for R0 ready\n"); 668 return -ETIMEDOUT; 669 } 670 671 /* 672 * Wait for R0' to become available. The spec says 100ms from Aksv, but 673 * some monitors can take longer than this. We'll set the timeout at 674 * 300ms just to be sure. 675 * 676 * On DP, there's an R0_READY bit available but no such bit 677 * exists on HDMI. Since the upper-bound is the same, we'll just do 678 * the stupid thing instead of polling on one and not the other. 679 */ 680 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 681 682 tries = 3; 683 684 /* 685 * DP HDCP Spec mandates the two more reattempt to read R0, incase 686 * of R0 mismatch. 687 */ 688 for (i = 0; i < tries; i++) { 689 ri.reg = 0; 690 ret = shim->read_ri_prime(intel_dig_port, ri.shim); 691 if (ret) 692 return ret; 693 I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); 694 695 /* Wait for Ri prime match */ 696 if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) & 697 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) 698 break; 699 } 700 701 if (i == tries) { 702 DRM_DEBUG_KMS("Timed out waiting for Ri prime match (%x)\n", 703 I915_READ(PORT_HDCP_STATUS(port))); 704 return -ETIMEDOUT; 705 } 706 707 /* Wait for encryption confirmation */ 708 if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port), 709 HDCP_STATUS_ENC, HDCP_STATUS_ENC, 710 ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 711 DRM_ERROR("Timed out waiting for encryption\n"); 712 return -ETIMEDOUT; 713 } 714 715 /* 716 * XXX: If we have MST-connected devices, we need to enable encryption 717 * on those as well. 718 */ 719 720 if (repeater_present) 721 return intel_hdcp_auth_downstream(connector); 722 723 DRM_DEBUG_KMS("HDCP is enabled (no repeater present)\n"); 724 return 0; 725 } 726 727 static int _intel_hdcp_disable(struct intel_connector *connector) 728 { 729 struct intel_hdcp *hdcp = &connector->hdcp; 730 struct drm_i915_private *dev_priv = connector->base.dev->dev_private; 731 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 732 enum port port = intel_dig_port->base.port; 733 int ret; 734 735 DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n", 736 connector->base.name, connector->base.base.id); 737 738 hdcp->hdcp_encrypted = false; 739 I915_WRITE(PORT_HDCP_CONF(port), 0); 740 if (intel_wait_for_register(&dev_priv->uncore, 741 PORT_HDCP_STATUS(port), ~0, 0, 742 ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 743 DRM_ERROR("Failed to disable HDCP, timeout clearing status\n"); 744 return -ETIMEDOUT; 745 } 746 747 ret = hdcp->shim->toggle_signalling(intel_dig_port, false); 748 if (ret) { 749 DRM_ERROR("Failed to disable HDCP signalling\n"); 750 return ret; 751 } 752 753 DRM_DEBUG_KMS("HDCP is disabled\n"); 754 return 0; 755 } 756 757 static int _intel_hdcp_enable(struct intel_connector *connector) 758 { 759 struct intel_hdcp *hdcp = &connector->hdcp; 760 struct drm_i915_private *dev_priv = connector->base.dev->dev_private; 761 int i, ret, tries = 3; 762 763 DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n", 764 connector->base.name, connector->base.base.id); 765 766 if (!hdcp_key_loadable(dev_priv)) { 767 DRM_ERROR("HDCP key Load is not possible\n"); 768 return -ENXIO; 769 } 770 771 for (i = 0; i < KEY_LOAD_TRIES; i++) { 772 ret = intel_hdcp_load_keys(dev_priv); 773 if (!ret) 774 break; 775 intel_hdcp_clear_keys(dev_priv); 776 } 777 if (ret) { 778 DRM_ERROR("Could not load HDCP keys, (%d)\n", ret); 779 return ret; 780 } 781 782 /* Incase of authentication failures, HDCP spec expects reauth. */ 783 for (i = 0; i < tries; i++) { 784 ret = intel_hdcp_auth(connector); 785 if (!ret) { 786 hdcp->hdcp_encrypted = true; 787 return 0; 788 } 789 790 DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret); 791 792 /* Ensuring HDCP encryption and signalling are stopped. */ 793 _intel_hdcp_disable(connector); 794 } 795 796 DRM_DEBUG_KMS("HDCP authentication failed (%d tries/%d)\n", tries, ret); 797 return ret; 798 } 799 800 static inline 801 struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 802 { 803 return container_of(hdcp, struct intel_connector, hdcp); 804 } 805 806 /* Implements Part 3 of the HDCP authorization procedure */ 807 static int intel_hdcp_check_link(struct intel_connector *connector) 808 { 809 struct intel_hdcp *hdcp = &connector->hdcp; 810 struct drm_i915_private *dev_priv = connector->base.dev->dev_private; 811 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 812 enum port port = intel_dig_port->base.port; 813 int ret = 0; 814 815 mutex_lock(&hdcp->mutex); 816 817 /* Check_link valid only when HDCP1.4 is enabled */ 818 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 819 !hdcp->hdcp_encrypted) { 820 ret = -EINVAL; 821 goto out; 822 } 823 824 if (WARN_ON(!intel_hdcp_in_use(connector))) { 825 DRM_ERROR("%s:%d HDCP link stopped encryption,%x\n", 826 connector->base.name, connector->base.base.id, 827 I915_READ(PORT_HDCP_STATUS(port))); 828 ret = -ENXIO; 829 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 830 schedule_work(&hdcp->prop_work); 831 goto out; 832 } 833 834 if (hdcp->shim->check_link(intel_dig_port)) { 835 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 836 hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; 837 schedule_work(&hdcp->prop_work); 838 } 839 goto out; 840 } 841 842 DRM_DEBUG_KMS("[%s:%d] HDCP link failed, retrying authentication\n", 843 connector->base.name, connector->base.base.id); 844 845 ret = _intel_hdcp_disable(connector); 846 if (ret) { 847 DRM_ERROR("Failed to disable hdcp (%d)\n", ret); 848 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 849 schedule_work(&hdcp->prop_work); 850 goto out; 851 } 852 853 ret = _intel_hdcp_enable(connector); 854 if (ret) { 855 DRM_ERROR("Failed to enable hdcp (%d)\n", ret); 856 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 857 schedule_work(&hdcp->prop_work); 858 goto out; 859 } 860 861 out: 862 mutex_unlock(&hdcp->mutex); 863 return ret; 864 } 865 866 static void intel_hdcp_prop_work(struct work_struct *work) 867 { 868 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 869 prop_work); 870 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 871 struct drm_device *dev = connector->base.dev; 872 873 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 874 mutex_lock(&hdcp->mutex); 875 876 /* 877 * This worker is only used to flip between ENABLED/DESIRED. Either of 878 * those to UNDESIRED is handled by core. If value == UNDESIRED, 879 * we're running just after hdcp has been disabled, so just exit 880 */ 881 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 882 drm_hdcp_update_content_protection(&connector->base, 883 hdcp->value); 884 885 mutex_unlock(&hdcp->mutex); 886 drm_modeset_unlock(&dev->mode_config.connection_mutex); 887 } 888 889 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port) 890 { 891 /* PORT E doesn't have HDCP, and PORT F is disabled */ 892 return INTEL_GEN(dev_priv) >= 9 && port < PORT_E; 893 } 894 895 static int 896 hdcp2_prepare_ake_init(struct intel_connector *connector, 897 struct hdcp2_ake_init *ake_data) 898 { 899 struct hdcp_port_data *data = &connector->hdcp.port_data; 900 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 901 struct i915_hdcp_comp_master *comp; 902 int ret; 903 904 mutex_lock(&dev_priv->hdcp_comp_mutex); 905 comp = dev_priv->hdcp_master; 906 907 if (!comp || !comp->ops) { 908 mutex_unlock(&dev_priv->hdcp_comp_mutex); 909 return -EINVAL; 910 } 911 912 ret = comp->ops->initiate_hdcp2_session(comp->mei_dev, data, ake_data); 913 if (ret) 914 DRM_DEBUG_KMS("Prepare_ake_init failed. %d\n", ret); 915 mutex_unlock(&dev_priv->hdcp_comp_mutex); 916 917 return ret; 918 } 919 920 static int 921 hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 922 struct hdcp2_ake_send_cert *rx_cert, 923 bool *paired, 924 struct hdcp2_ake_no_stored_km *ek_pub_km, 925 size_t *msg_sz) 926 { 927 struct hdcp_port_data *data = &connector->hdcp.port_data; 928 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 929 struct i915_hdcp_comp_master *comp; 930 int ret; 931 932 mutex_lock(&dev_priv->hdcp_comp_mutex); 933 comp = dev_priv->hdcp_master; 934 935 if (!comp || !comp->ops) { 936 mutex_unlock(&dev_priv->hdcp_comp_mutex); 937 return -EINVAL; 938 } 939 940 ret = comp->ops->verify_receiver_cert_prepare_km(comp->mei_dev, data, 941 rx_cert, paired, 942 ek_pub_km, msg_sz); 943 if (ret < 0) 944 DRM_DEBUG_KMS("Verify rx_cert failed. %d\n", ret); 945 mutex_unlock(&dev_priv->hdcp_comp_mutex); 946 947 return ret; 948 } 949 950 static int hdcp2_verify_hprime(struct intel_connector *connector, 951 struct hdcp2_ake_send_hprime *rx_hprime) 952 { 953 struct hdcp_port_data *data = &connector->hdcp.port_data; 954 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 955 struct i915_hdcp_comp_master *comp; 956 int ret; 957 958 mutex_lock(&dev_priv->hdcp_comp_mutex); 959 comp = dev_priv->hdcp_master; 960 961 if (!comp || !comp->ops) { 962 mutex_unlock(&dev_priv->hdcp_comp_mutex); 963 return -EINVAL; 964 } 965 966 ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime); 967 if (ret < 0) 968 DRM_DEBUG_KMS("Verify hprime failed. %d\n", ret); 969 mutex_unlock(&dev_priv->hdcp_comp_mutex); 970 971 return ret; 972 } 973 974 static int 975 hdcp2_store_pairing_info(struct intel_connector *connector, 976 struct hdcp2_ake_send_pairing_info *pairing_info) 977 { 978 struct hdcp_port_data *data = &connector->hdcp.port_data; 979 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 980 struct i915_hdcp_comp_master *comp; 981 int ret; 982 983 mutex_lock(&dev_priv->hdcp_comp_mutex); 984 comp = dev_priv->hdcp_master; 985 986 if (!comp || !comp->ops) { 987 mutex_unlock(&dev_priv->hdcp_comp_mutex); 988 return -EINVAL; 989 } 990 991 ret = comp->ops->store_pairing_info(comp->mei_dev, data, pairing_info); 992 if (ret < 0) 993 DRM_DEBUG_KMS("Store pairing info failed. %d\n", ret); 994 mutex_unlock(&dev_priv->hdcp_comp_mutex); 995 996 return ret; 997 } 998 999 static int 1000 hdcp2_prepare_lc_init(struct intel_connector *connector, 1001 struct hdcp2_lc_init *lc_init) 1002 { 1003 struct hdcp_port_data *data = &connector->hdcp.port_data; 1004 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1005 struct i915_hdcp_comp_master *comp; 1006 int ret; 1007 1008 mutex_lock(&dev_priv->hdcp_comp_mutex); 1009 comp = dev_priv->hdcp_master; 1010 1011 if (!comp || !comp->ops) { 1012 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1013 return -EINVAL; 1014 } 1015 1016 ret = comp->ops->initiate_locality_check(comp->mei_dev, data, lc_init); 1017 if (ret < 0) 1018 DRM_DEBUG_KMS("Prepare lc_init failed. %d\n", ret); 1019 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1020 1021 return ret; 1022 } 1023 1024 static int 1025 hdcp2_verify_lprime(struct intel_connector *connector, 1026 struct hdcp2_lc_send_lprime *rx_lprime) 1027 { 1028 struct hdcp_port_data *data = &connector->hdcp.port_data; 1029 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1030 struct i915_hdcp_comp_master *comp; 1031 int ret; 1032 1033 mutex_lock(&dev_priv->hdcp_comp_mutex); 1034 comp = dev_priv->hdcp_master; 1035 1036 if (!comp || !comp->ops) { 1037 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1038 return -EINVAL; 1039 } 1040 1041 ret = comp->ops->verify_lprime(comp->mei_dev, data, rx_lprime); 1042 if (ret < 0) 1043 DRM_DEBUG_KMS("Verify L_Prime failed. %d\n", ret); 1044 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1045 1046 return ret; 1047 } 1048 1049 static int hdcp2_prepare_skey(struct intel_connector *connector, 1050 struct hdcp2_ske_send_eks *ske_data) 1051 { 1052 struct hdcp_port_data *data = &connector->hdcp.port_data; 1053 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1054 struct i915_hdcp_comp_master *comp; 1055 int ret; 1056 1057 mutex_lock(&dev_priv->hdcp_comp_mutex); 1058 comp = dev_priv->hdcp_master; 1059 1060 if (!comp || !comp->ops) { 1061 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1062 return -EINVAL; 1063 } 1064 1065 ret = comp->ops->get_session_key(comp->mei_dev, data, ske_data); 1066 if (ret < 0) 1067 DRM_DEBUG_KMS("Get session key failed. %d\n", ret); 1068 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1069 1070 return ret; 1071 } 1072 1073 static int 1074 hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1075 struct hdcp2_rep_send_receiverid_list 1076 *rep_topology, 1077 struct hdcp2_rep_send_ack *rep_send_ack) 1078 { 1079 struct hdcp_port_data *data = &connector->hdcp.port_data; 1080 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1081 struct i915_hdcp_comp_master *comp; 1082 int ret; 1083 1084 mutex_lock(&dev_priv->hdcp_comp_mutex); 1085 comp = dev_priv->hdcp_master; 1086 1087 if (!comp || !comp->ops) { 1088 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1089 return -EINVAL; 1090 } 1091 1092 ret = comp->ops->repeater_check_flow_prepare_ack(comp->mei_dev, data, 1093 rep_topology, 1094 rep_send_ack); 1095 if (ret < 0) 1096 DRM_DEBUG_KMS("Verify rep topology failed. %d\n", ret); 1097 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1098 1099 return ret; 1100 } 1101 1102 static int 1103 hdcp2_verify_mprime(struct intel_connector *connector, 1104 struct hdcp2_rep_stream_ready *stream_ready) 1105 { 1106 struct hdcp_port_data *data = &connector->hdcp.port_data; 1107 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1108 struct i915_hdcp_comp_master *comp; 1109 int ret; 1110 1111 mutex_lock(&dev_priv->hdcp_comp_mutex); 1112 comp = dev_priv->hdcp_master; 1113 1114 if (!comp || !comp->ops) { 1115 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1116 return -EINVAL; 1117 } 1118 1119 ret = comp->ops->verify_mprime(comp->mei_dev, data, stream_ready); 1120 if (ret < 0) 1121 DRM_DEBUG_KMS("Verify mprime failed. %d\n", ret); 1122 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1123 1124 return ret; 1125 } 1126 1127 static int hdcp2_authenticate_port(struct intel_connector *connector) 1128 { 1129 struct hdcp_port_data *data = &connector->hdcp.port_data; 1130 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1131 struct i915_hdcp_comp_master *comp; 1132 int ret; 1133 1134 mutex_lock(&dev_priv->hdcp_comp_mutex); 1135 comp = dev_priv->hdcp_master; 1136 1137 if (!comp || !comp->ops) { 1138 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1139 return -EINVAL; 1140 } 1141 1142 ret = comp->ops->enable_hdcp_authentication(comp->mei_dev, data); 1143 if (ret < 0) 1144 DRM_DEBUG_KMS("Enable hdcp auth failed. %d\n", ret); 1145 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1146 1147 return ret; 1148 } 1149 1150 static int hdcp2_close_mei_session(struct intel_connector *connector) 1151 { 1152 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1153 struct i915_hdcp_comp_master *comp; 1154 int ret; 1155 1156 mutex_lock(&dev_priv->hdcp_comp_mutex); 1157 comp = dev_priv->hdcp_master; 1158 1159 if (!comp || !comp->ops) { 1160 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1161 return -EINVAL; 1162 } 1163 1164 ret = comp->ops->close_hdcp_session(comp->mei_dev, 1165 &connector->hdcp.port_data); 1166 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1167 1168 return ret; 1169 } 1170 1171 static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1172 { 1173 return hdcp2_close_mei_session(connector); 1174 } 1175 1176 /* Authentication flow starts from here */ 1177 static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1178 { 1179 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1180 struct intel_hdcp *hdcp = &connector->hdcp; 1181 struct drm_device *dev = connector->base.dev; 1182 union { 1183 struct hdcp2_ake_init ake_init; 1184 struct hdcp2_ake_send_cert send_cert; 1185 struct hdcp2_ake_no_stored_km no_stored_km; 1186 struct hdcp2_ake_send_hprime send_hprime; 1187 struct hdcp2_ake_send_pairing_info pairing_info; 1188 } msgs; 1189 const struct intel_hdcp_shim *shim = hdcp->shim; 1190 size_t size; 1191 int ret; 1192 1193 /* Init for seq_num */ 1194 hdcp->seq_num_v = 0; 1195 hdcp->seq_num_m = 0; 1196 1197 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1198 if (ret < 0) 1199 return ret; 1200 1201 ret = shim->write_2_2_msg(intel_dig_port, &msgs.ake_init, 1202 sizeof(msgs.ake_init)); 1203 if (ret < 0) 1204 return ret; 1205 1206 ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_CERT, 1207 &msgs.send_cert, sizeof(msgs.send_cert)); 1208 if (ret < 0) 1209 return ret; 1210 1211 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { 1212 DRM_DEBUG_KMS("cert.rx_caps dont claim HDCP2.2\n"); 1213 return -EINVAL; 1214 } 1215 1216 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1217 1218 if (drm_hdcp_check_ksvs_revoked(dev, msgs.send_cert.cert_rx.receiver_id, 1219 1)) { 1220 DRM_ERROR("Receiver ID is revoked\n"); 1221 return -EPERM; 1222 } 1223 1224 /* 1225 * Here msgs.no_stored_km will hold msgs corresponding to the km 1226 * stored also. 1227 */ 1228 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1229 &hdcp->is_paired, 1230 &msgs.no_stored_km, &size); 1231 if (ret < 0) 1232 return ret; 1233 1234 ret = shim->write_2_2_msg(intel_dig_port, &msgs.no_stored_km, size); 1235 if (ret < 0) 1236 return ret; 1237 1238 ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_HPRIME, 1239 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1240 if (ret < 0) 1241 return ret; 1242 1243 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1244 if (ret < 0) 1245 return ret; 1246 1247 if (!hdcp->is_paired) { 1248 /* Pairing is required */ 1249 ret = shim->read_2_2_msg(intel_dig_port, 1250 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1251 &msgs.pairing_info, 1252 sizeof(msgs.pairing_info)); 1253 if (ret < 0) 1254 return ret; 1255 1256 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1257 if (ret < 0) 1258 return ret; 1259 hdcp->is_paired = true; 1260 } 1261 1262 return 0; 1263 } 1264 1265 static int hdcp2_locality_check(struct intel_connector *connector) 1266 { 1267 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1268 struct intel_hdcp *hdcp = &connector->hdcp; 1269 union { 1270 struct hdcp2_lc_init lc_init; 1271 struct hdcp2_lc_send_lprime send_lprime; 1272 } msgs; 1273 const struct intel_hdcp_shim *shim = hdcp->shim; 1274 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1275 1276 for (i = 0; i < tries; i++) { 1277 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1278 if (ret < 0) 1279 continue; 1280 1281 ret = shim->write_2_2_msg(intel_dig_port, &msgs.lc_init, 1282 sizeof(msgs.lc_init)); 1283 if (ret < 0) 1284 continue; 1285 1286 ret = shim->read_2_2_msg(intel_dig_port, 1287 HDCP_2_2_LC_SEND_LPRIME, 1288 &msgs.send_lprime, 1289 sizeof(msgs.send_lprime)); 1290 if (ret < 0) 1291 continue; 1292 1293 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1294 if (!ret) 1295 break; 1296 } 1297 1298 return ret; 1299 } 1300 1301 static int hdcp2_session_key_exchange(struct intel_connector *connector) 1302 { 1303 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1304 struct intel_hdcp *hdcp = &connector->hdcp; 1305 struct hdcp2_ske_send_eks send_eks; 1306 int ret; 1307 1308 ret = hdcp2_prepare_skey(connector, &send_eks); 1309 if (ret < 0) 1310 return ret; 1311 1312 ret = hdcp->shim->write_2_2_msg(intel_dig_port, &send_eks, 1313 sizeof(send_eks)); 1314 if (ret < 0) 1315 return ret; 1316 1317 return 0; 1318 } 1319 1320 static 1321 int hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1322 { 1323 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1324 struct intel_hdcp *hdcp = &connector->hdcp; 1325 union { 1326 struct hdcp2_rep_stream_manage stream_manage; 1327 struct hdcp2_rep_stream_ready stream_ready; 1328 } msgs; 1329 const struct intel_hdcp_shim *shim = hdcp->shim; 1330 int ret; 1331 1332 /* Prepare RepeaterAuth_Stream_Manage msg */ 1333 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1334 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1335 1336 /* K no of streams is fixed as 1. Stored as big-endian. */ 1337 msgs.stream_manage.k = cpu_to_be16(1); 1338 1339 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 1340 msgs.stream_manage.streams[0].stream_id = 0; 1341 msgs.stream_manage.streams[0].stream_type = hdcp->content_type; 1342 1343 /* Send it to Repeater */ 1344 ret = shim->write_2_2_msg(intel_dig_port, &msgs.stream_manage, 1345 sizeof(msgs.stream_manage)); 1346 if (ret < 0) 1347 return ret; 1348 1349 ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_STREAM_READY, 1350 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1351 if (ret < 0) 1352 return ret; 1353 1354 hdcp->port_data.seq_num_m = hdcp->seq_num_m; 1355 hdcp->port_data.streams[0].stream_type = hdcp->content_type; 1356 1357 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1358 if (ret < 0) 1359 return ret; 1360 1361 hdcp->seq_num_m++; 1362 1363 if (hdcp->seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 1364 DRM_DEBUG_KMS("seq_num_m roll over.\n"); 1365 return -1; 1366 } 1367 1368 return 0; 1369 } 1370 1371 static 1372 int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1373 { 1374 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1375 struct intel_hdcp *hdcp = &connector->hdcp; 1376 struct drm_device *dev = connector->base.dev; 1377 union { 1378 struct hdcp2_rep_send_receiverid_list recvid_list; 1379 struct hdcp2_rep_send_ack rep_ack; 1380 } msgs; 1381 const struct intel_hdcp_shim *shim = hdcp->shim; 1382 u32 seq_num_v, device_cnt; 1383 u8 *rx_info; 1384 int ret; 1385 1386 ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_SEND_RECVID_LIST, 1387 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1388 if (ret < 0) 1389 return ret; 1390 1391 rx_info = msgs.recvid_list.rx_info; 1392 1393 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1394 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1395 DRM_DEBUG_KMS("Topology Max Size Exceeded\n"); 1396 return -EINVAL; 1397 } 1398 1399 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1400 seq_num_v = 1401 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1402 1403 if (seq_num_v < hdcp->seq_num_v) { 1404 /* Roll over of the seq_num_v from repeater. Reauthenticate. */ 1405 DRM_DEBUG_KMS("Seq_num_v roll over.\n"); 1406 return -EINVAL; 1407 } 1408 1409 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1410 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1411 if (drm_hdcp_check_ksvs_revoked(dev, msgs.recvid_list.receiver_ids, 1412 device_cnt)) { 1413 DRM_ERROR("Revoked receiver ID(s) is in list\n"); 1414 return -EPERM; 1415 } 1416 1417 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1418 &msgs.recvid_list, 1419 &msgs.rep_ack); 1420 if (ret < 0) 1421 return ret; 1422 1423 hdcp->seq_num_v = seq_num_v; 1424 ret = shim->write_2_2_msg(intel_dig_port, &msgs.rep_ack, 1425 sizeof(msgs.rep_ack)); 1426 if (ret < 0) 1427 return ret; 1428 1429 return 0; 1430 } 1431 1432 static int hdcp2_authenticate_repeater(struct intel_connector *connector) 1433 { 1434 int ret; 1435 1436 ret = hdcp2_authenticate_repeater_topology(connector); 1437 if (ret < 0) 1438 return ret; 1439 1440 return hdcp2_propagate_stream_management_info(connector); 1441 } 1442 1443 static int hdcp2_authenticate_sink(struct intel_connector *connector) 1444 { 1445 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1446 struct intel_hdcp *hdcp = &connector->hdcp; 1447 const struct intel_hdcp_shim *shim = hdcp->shim; 1448 int ret; 1449 1450 ret = hdcp2_authentication_key_exchange(connector); 1451 if (ret < 0) { 1452 DRM_DEBUG_KMS("AKE Failed. Err : %d\n", ret); 1453 return ret; 1454 } 1455 1456 ret = hdcp2_locality_check(connector); 1457 if (ret < 0) { 1458 DRM_DEBUG_KMS("Locality Check failed. Err : %d\n", ret); 1459 return ret; 1460 } 1461 1462 ret = hdcp2_session_key_exchange(connector); 1463 if (ret < 0) { 1464 DRM_DEBUG_KMS("SKE Failed. Err : %d\n", ret); 1465 return ret; 1466 } 1467 1468 if (shim->config_stream_type) { 1469 ret = shim->config_stream_type(intel_dig_port, 1470 hdcp->is_repeater, 1471 hdcp->content_type); 1472 if (ret < 0) 1473 return ret; 1474 } 1475 1476 if (hdcp->is_repeater) { 1477 ret = hdcp2_authenticate_repeater(connector); 1478 if (ret < 0) { 1479 DRM_DEBUG_KMS("Repeater Auth Failed. Err: %d\n", ret); 1480 return ret; 1481 } 1482 } 1483 1484 hdcp->port_data.streams[0].stream_type = hdcp->content_type; 1485 ret = hdcp2_authenticate_port(connector); 1486 if (ret < 0) 1487 return ret; 1488 1489 return ret; 1490 } 1491 1492 static int hdcp2_enable_encryption(struct intel_connector *connector) 1493 { 1494 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1495 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1496 struct intel_hdcp *hdcp = &connector->hdcp; 1497 enum port port = connector->encoder->port; 1498 int ret; 1499 1500 WARN_ON(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS); 1501 1502 if (hdcp->shim->toggle_signalling) { 1503 ret = hdcp->shim->toggle_signalling(intel_dig_port, true); 1504 if (ret) { 1505 DRM_ERROR("Failed to enable HDCP signalling. %d\n", 1506 ret); 1507 return ret; 1508 } 1509 } 1510 1511 if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) { 1512 /* Link is Authenticated. Now set for Encryption */ 1513 I915_WRITE(HDCP2_CTL_DDI(port), 1514 I915_READ(HDCP2_CTL_DDI(port)) | 1515 CTL_LINK_ENCRYPTION_REQ); 1516 } 1517 1518 ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port), 1519 LINK_ENCRYPTION_STATUS, 1520 LINK_ENCRYPTION_STATUS, 1521 ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1522 1523 return ret; 1524 } 1525 1526 static int hdcp2_disable_encryption(struct intel_connector *connector) 1527 { 1528 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1529 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1530 struct intel_hdcp *hdcp = &connector->hdcp; 1531 enum port port = connector->encoder->port; 1532 int ret; 1533 1534 WARN_ON(!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS)); 1535 1536 I915_WRITE(HDCP2_CTL_DDI(port), 1537 I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ); 1538 1539 ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port), 1540 LINK_ENCRYPTION_STATUS, 0x0, 1541 ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1542 if (ret == -ETIMEDOUT) 1543 DRM_DEBUG_KMS("Disable Encryption Timedout"); 1544 1545 if (hdcp->shim->toggle_signalling) { 1546 ret = hdcp->shim->toggle_signalling(intel_dig_port, false); 1547 if (ret) { 1548 DRM_ERROR("Failed to disable HDCP signalling. %d\n", 1549 ret); 1550 return ret; 1551 } 1552 } 1553 1554 return ret; 1555 } 1556 1557 static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector) 1558 { 1559 int ret, i, tries = 3; 1560 1561 for (i = 0; i < tries; i++) { 1562 ret = hdcp2_authenticate_sink(connector); 1563 if (!ret) 1564 break; 1565 1566 /* Clearing the mei hdcp session */ 1567 DRM_DEBUG_KMS("HDCP2.2 Auth %d of %d Failed.(%d)\n", 1568 i + 1, tries, ret); 1569 if (hdcp2_deauthenticate_port(connector) < 0) 1570 DRM_DEBUG_KMS("Port deauth failed.\n"); 1571 } 1572 1573 if (i != tries) { 1574 /* 1575 * Ensuring the required 200mSec min time interval between 1576 * Session Key Exchange and encryption. 1577 */ 1578 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 1579 ret = hdcp2_enable_encryption(connector); 1580 if (ret < 0) { 1581 DRM_DEBUG_KMS("Encryption Enable Failed.(%d)\n", ret); 1582 if (hdcp2_deauthenticate_port(connector) < 0) 1583 DRM_DEBUG_KMS("Port deauth failed.\n"); 1584 } 1585 } 1586 1587 return ret; 1588 } 1589 1590 static int _intel_hdcp2_enable(struct intel_connector *connector) 1591 { 1592 struct intel_hdcp *hdcp = &connector->hdcp; 1593 int ret; 1594 1595 DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being enabled. Type: %d\n", 1596 connector->base.name, connector->base.base.id, 1597 hdcp->content_type); 1598 1599 ret = hdcp2_authenticate_and_encrypt(connector); 1600 if (ret) { 1601 DRM_DEBUG_KMS("HDCP2 Type%d Enabling Failed. (%d)\n", 1602 hdcp->content_type, ret); 1603 return ret; 1604 } 1605 1606 DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is enabled. Type %d\n", 1607 connector->base.name, connector->base.base.id, 1608 hdcp->content_type); 1609 1610 hdcp->hdcp2_encrypted = true; 1611 return 0; 1612 } 1613 1614 static int _intel_hdcp2_disable(struct intel_connector *connector) 1615 { 1616 int ret; 1617 1618 DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being Disabled\n", 1619 connector->base.name, connector->base.base.id); 1620 1621 ret = hdcp2_disable_encryption(connector); 1622 1623 if (hdcp2_deauthenticate_port(connector) < 0) 1624 DRM_DEBUG_KMS("Port deauth failed.\n"); 1625 1626 connector->hdcp.hdcp2_encrypted = false; 1627 1628 return ret; 1629 } 1630 1631 /* Implements the Link Integrity Check for HDCP2.2 */ 1632 static int intel_hdcp2_check_link(struct intel_connector *connector) 1633 { 1634 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1635 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1636 struct intel_hdcp *hdcp = &connector->hdcp; 1637 enum port port = connector->encoder->port; 1638 int ret = 0; 1639 1640 mutex_lock(&hdcp->mutex); 1641 1642 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 1643 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1644 !hdcp->hdcp2_encrypted) { 1645 ret = -EINVAL; 1646 goto out; 1647 } 1648 1649 if (WARN_ON(!intel_hdcp2_in_use(connector))) { 1650 DRM_ERROR("HDCP2.2 link stopped the encryption, %x\n", 1651 I915_READ(HDCP2_STATUS_DDI(port))); 1652 ret = -ENXIO; 1653 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 1654 schedule_work(&hdcp->prop_work); 1655 goto out; 1656 } 1657 1658 ret = hdcp->shim->check_2_2_link(intel_dig_port); 1659 if (ret == HDCP_LINK_PROTECTED) { 1660 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1661 hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; 1662 schedule_work(&hdcp->prop_work); 1663 } 1664 goto out; 1665 } 1666 1667 if (ret == HDCP_TOPOLOGY_CHANGE) { 1668 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1669 goto out; 1670 1671 DRM_DEBUG_KMS("HDCP2.2 Downstream topology change\n"); 1672 ret = hdcp2_authenticate_repeater_topology(connector); 1673 if (!ret) { 1674 hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; 1675 schedule_work(&hdcp->prop_work); 1676 goto out; 1677 } 1678 DRM_DEBUG_KMS("[%s:%d] Repeater topology auth failed.(%d)\n", 1679 connector->base.name, connector->base.base.id, 1680 ret); 1681 } else { 1682 DRM_DEBUG_KMS("[%s:%d] HDCP2.2 link failed, retrying auth\n", 1683 connector->base.name, connector->base.base.id); 1684 } 1685 1686 ret = _intel_hdcp2_disable(connector); 1687 if (ret) { 1688 DRM_ERROR("[%s:%d] Failed to disable hdcp2.2 (%d)\n", 1689 connector->base.name, connector->base.base.id, ret); 1690 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 1691 schedule_work(&hdcp->prop_work); 1692 goto out; 1693 } 1694 1695 ret = _intel_hdcp2_enable(connector); 1696 if (ret) { 1697 DRM_DEBUG_KMS("[%s:%d] Failed to enable hdcp2.2 (%d)\n", 1698 connector->base.name, connector->base.base.id, 1699 ret); 1700 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 1701 schedule_work(&hdcp->prop_work); 1702 goto out; 1703 } 1704 1705 out: 1706 mutex_unlock(&hdcp->mutex); 1707 return ret; 1708 } 1709 1710 static void intel_hdcp_check_work(struct work_struct *work) 1711 { 1712 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 1713 struct intel_hdcp, 1714 check_work); 1715 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1716 1717 if (!intel_hdcp2_check_link(connector)) 1718 schedule_delayed_work(&hdcp->check_work, 1719 DRM_HDCP2_CHECK_PERIOD_MS); 1720 else if (!intel_hdcp_check_link(connector)) 1721 schedule_delayed_work(&hdcp->check_work, 1722 DRM_HDCP_CHECK_PERIOD_MS); 1723 } 1724 1725 static int i915_hdcp_component_bind(struct device *i915_kdev, 1726 struct device *mei_kdev, void *data) 1727 { 1728 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1729 1730 DRM_DEBUG("I915 HDCP comp bind\n"); 1731 mutex_lock(&dev_priv->hdcp_comp_mutex); 1732 dev_priv->hdcp_master = (struct i915_hdcp_comp_master *)data; 1733 dev_priv->hdcp_master->mei_dev = mei_kdev; 1734 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1735 1736 return 0; 1737 } 1738 1739 static void i915_hdcp_component_unbind(struct device *i915_kdev, 1740 struct device *mei_kdev, void *data) 1741 { 1742 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1743 1744 DRM_DEBUG("I915 HDCP comp unbind\n"); 1745 mutex_lock(&dev_priv->hdcp_comp_mutex); 1746 dev_priv->hdcp_master = NULL; 1747 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1748 } 1749 1750 static const struct component_ops i915_hdcp_component_ops = { 1751 .bind = i915_hdcp_component_bind, 1752 .unbind = i915_hdcp_component_unbind, 1753 }; 1754 1755 static inline int initialize_hdcp_port_data(struct intel_connector *connector, 1756 const struct intel_hdcp_shim *shim) 1757 { 1758 struct intel_hdcp *hdcp = &connector->hdcp; 1759 struct hdcp_port_data *data = &hdcp->port_data; 1760 1761 data->port = connector->encoder->port; 1762 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 1763 data->protocol = (u8)shim->protocol; 1764 1765 data->k = 1; 1766 if (!data->streams) 1767 data->streams = kcalloc(data->k, 1768 sizeof(struct hdcp2_streamid_type), 1769 GFP_KERNEL); 1770 if (!data->streams) { 1771 DRM_ERROR("Out of Memory\n"); 1772 return -ENOMEM; 1773 } 1774 1775 data->streams[0].stream_id = 0; 1776 data->streams[0].stream_type = hdcp->content_type; 1777 1778 return 0; 1779 } 1780 1781 static bool is_hdcp2_supported(struct drm_i915_private *dev_priv) 1782 { 1783 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 1784 return false; 1785 1786 return (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || 1787 IS_KABYLAKE(dev_priv)); 1788 } 1789 1790 void intel_hdcp_component_init(struct drm_i915_private *dev_priv) 1791 { 1792 int ret; 1793 1794 if (!is_hdcp2_supported(dev_priv)) 1795 return; 1796 1797 mutex_lock(&dev_priv->hdcp_comp_mutex); 1798 WARN_ON(dev_priv->hdcp_comp_added); 1799 1800 dev_priv->hdcp_comp_added = true; 1801 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1802 ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops, 1803 I915_COMPONENT_HDCP); 1804 if (ret < 0) { 1805 DRM_DEBUG_KMS("Failed at component add(%d)\n", ret); 1806 mutex_lock(&dev_priv->hdcp_comp_mutex); 1807 dev_priv->hdcp_comp_added = false; 1808 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1809 return; 1810 } 1811 } 1812 1813 static void intel_hdcp2_init(struct intel_connector *connector, 1814 const struct intel_hdcp_shim *shim) 1815 { 1816 struct intel_hdcp *hdcp = &connector->hdcp; 1817 int ret; 1818 1819 ret = initialize_hdcp_port_data(connector, shim); 1820 if (ret) { 1821 DRM_DEBUG_KMS("Mei hdcp data init failed\n"); 1822 return; 1823 } 1824 1825 hdcp->hdcp2_supported = true; 1826 } 1827 1828 int intel_hdcp_init(struct intel_connector *connector, 1829 const struct intel_hdcp_shim *shim) 1830 { 1831 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1832 struct intel_hdcp *hdcp = &connector->hdcp; 1833 int ret; 1834 1835 if (!shim) 1836 return -EINVAL; 1837 1838 if (is_hdcp2_supported(dev_priv)) 1839 intel_hdcp2_init(connector, shim); 1840 1841 ret = 1842 drm_connector_attach_content_protection_property(&connector->base, 1843 hdcp->hdcp2_supported); 1844 if (ret) { 1845 hdcp->hdcp2_supported = false; 1846 kfree(hdcp->port_data.streams); 1847 return ret; 1848 } 1849 1850 hdcp->shim = shim; 1851 mutex_init(&hdcp->mutex); 1852 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 1853 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 1854 init_waitqueue_head(&hdcp->cp_irq_queue); 1855 1856 return 0; 1857 } 1858 1859 int intel_hdcp_enable(struct intel_connector *connector, u8 content_type) 1860 { 1861 struct intel_hdcp *hdcp = &connector->hdcp; 1862 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 1863 int ret = -EINVAL; 1864 1865 if (!hdcp->shim) 1866 return -ENOENT; 1867 1868 mutex_lock(&hdcp->mutex); 1869 WARN_ON(hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 1870 hdcp->content_type = content_type; 1871 1872 /* 1873 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 1874 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 1875 */ 1876 if (intel_hdcp2_capable(connector)) { 1877 ret = _intel_hdcp2_enable(connector); 1878 if (!ret) 1879 check_link_interval = DRM_HDCP2_CHECK_PERIOD_MS; 1880 } 1881 1882 /* 1883 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will 1884 * be attempted. 1885 */ 1886 if (ret && intel_hdcp_capable(connector) && 1887 hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { 1888 ret = _intel_hdcp_enable(connector); 1889 } 1890 1891 if (!ret) { 1892 schedule_delayed_work(&hdcp->check_work, check_link_interval); 1893 hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; 1894 schedule_work(&hdcp->prop_work); 1895 } 1896 1897 mutex_unlock(&hdcp->mutex); 1898 return ret; 1899 } 1900 1901 int intel_hdcp_disable(struct intel_connector *connector) 1902 { 1903 struct intel_hdcp *hdcp = &connector->hdcp; 1904 int ret = 0; 1905 1906 if (!hdcp->shim) 1907 return -ENOENT; 1908 1909 mutex_lock(&hdcp->mutex); 1910 1911 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1912 hdcp->value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 1913 if (hdcp->hdcp2_encrypted) 1914 ret = _intel_hdcp2_disable(connector); 1915 else if (hdcp->hdcp_encrypted) 1916 ret = _intel_hdcp_disable(connector); 1917 } 1918 1919 mutex_unlock(&hdcp->mutex); 1920 cancel_delayed_work_sync(&hdcp->check_work); 1921 return ret; 1922 } 1923 1924 void intel_hdcp_component_fini(struct drm_i915_private *dev_priv) 1925 { 1926 mutex_lock(&dev_priv->hdcp_comp_mutex); 1927 if (!dev_priv->hdcp_comp_added) { 1928 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1929 return; 1930 } 1931 1932 dev_priv->hdcp_comp_added = false; 1933 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1934 1935 component_del(dev_priv->drm.dev, &i915_hdcp_component_ops); 1936 } 1937 1938 void intel_hdcp_cleanup(struct intel_connector *connector) 1939 { 1940 if (!connector->hdcp.shim) 1941 return; 1942 1943 mutex_lock(&connector->hdcp.mutex); 1944 kfree(connector->hdcp.port_data.streams); 1945 mutex_unlock(&connector->hdcp.mutex); 1946 } 1947 1948 void intel_hdcp_atomic_check(struct drm_connector *connector, 1949 struct drm_connector_state *old_state, 1950 struct drm_connector_state *new_state) 1951 { 1952 u64 old_cp = old_state->content_protection; 1953 u64 new_cp = new_state->content_protection; 1954 struct drm_crtc_state *crtc_state; 1955 1956 if (!new_state->crtc) { 1957 /* 1958 * If the connector is being disabled with CP enabled, mark it 1959 * desired so it's re-enabled when the connector is brought back 1960 */ 1961 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 1962 new_state->content_protection = 1963 DRM_MODE_CONTENT_PROTECTION_DESIRED; 1964 return; 1965 } 1966 1967 /* 1968 * Nothing to do if the state didn't change, or HDCP was activated since 1969 * the last commit. And also no change in hdcp content type. 1970 */ 1971 if (old_cp == new_cp || 1972 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 1973 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { 1974 if (old_state->hdcp_content_type == 1975 new_state->hdcp_content_type) 1976 return; 1977 } 1978 1979 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 1980 new_state->crtc); 1981 crtc_state->mode_changed = true; 1982 } 1983 1984 /* Handles the CP_IRQ raised from the DP HDCP sink */ 1985 void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 1986 { 1987 struct intel_hdcp *hdcp = &connector->hdcp; 1988 1989 if (!hdcp->shim) 1990 return; 1991 1992 atomic_inc(&connector->hdcp.cp_irq_count); 1993 wake_up_all(&connector->hdcp.cp_irq_queue); 1994 1995 schedule_delayed_work(&hdcp->check_work, 0); 1996 } 1997