1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * Copyright _ 2017-2019, Intel Corporation. 5 * 6 * Authors: 7 * Sean Paul <seanpaul@chromium.org> 8 * Ramalingam C <ramalingam.c@intel.com> 9 */ 10 11 #include <linux/component.h> 12 #include <linux/i2c.h> 13 #include <linux/random.h> 14 15 #include <drm/display/drm_hdcp_helper.h> 16 #include <drm/i915_component.h> 17 18 #include "i915_drv.h" 19 #include "i915_reg.h" 20 #include "intel_connector.h" 21 #include "intel_de.h" 22 #include "intel_display_power.h" 23 #include "intel_display_power_well.h" 24 #include "intel_display_types.h" 25 #include "intel_hdcp.h" 26 #include "intel_hdcp_gsc.h" 27 #include "intel_hdcp_regs.h" 28 #include "intel_pcode.h" 29 30 #define KEY_LOAD_TRIES 5 31 #define HDCP2_LC_RETRY_CNT 3 32 33 static int intel_conn_to_vcpi(struct drm_atomic_state *state, 34 struct intel_connector *connector) 35 { 36 struct drm_dp_mst_topology_mgr *mgr; 37 struct drm_dp_mst_atomic_payload *payload; 38 struct drm_dp_mst_topology_state *mst_state; 39 int vcpi = 0; 40 41 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 42 if (!connector->port) 43 return 0; 44 mgr = connector->port->mgr; 45 46 drm_modeset_lock(&mgr->base.lock, state->acquire_ctx); 47 mst_state = to_drm_dp_mst_topology_state(mgr->base.state); 48 payload = drm_atomic_get_mst_payload_state(mst_state, connector->port); 49 if (drm_WARN_ON(mgr->dev, !payload)) 50 goto out; 51 52 vcpi = payload->vcpi; 53 if (drm_WARN_ON(mgr->dev, vcpi < 0)) { 54 vcpi = 0; 55 goto out; 56 } 57 out: 58 return vcpi; 59 } 60 61 /* 62 * intel_hdcp_required_content_stream selects the most highest common possible HDCP 63 * content_type for all streams in DP MST topology because security f/w doesn't 64 * have any provision to mark content_type for each stream separately, it marks 65 * all available streams with the content_type proivided at the time of port 66 * authentication. This may prohibit the userspace to use type1 content on 67 * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in 68 * DP MST topology. Though it is not compulsory, security fw should change its 69 * policy to mark different content_types for different streams. 70 */ 71 static void 72 intel_hdcp_required_content_stream(struct intel_digital_port *dig_port) 73 { 74 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 75 bool enforce_type0 = false; 76 int k; 77 78 if (dig_port->hdcp_auth_status) 79 return; 80 81 if (!dig_port->hdcp_mst_type1_capable) 82 enforce_type0 = true; 83 84 /* 85 * Apply common protection level across all streams in DP MST Topology. 86 * Use highest supported content type for all streams in DP MST Topology. 87 */ 88 for (k = 0; k < data->k; k++) 89 data->streams[k].stream_type = 90 enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1; 91 } 92 93 static void intel_hdcp_prepare_streams(struct intel_connector *connector) 94 { 95 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 96 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 97 struct intel_hdcp *hdcp = &connector->hdcp; 98 99 if (!intel_encoder_is_mst(intel_attached_encoder(connector))) { 100 data->streams[0].stream_type = hdcp->content_type; 101 } else { 102 intel_hdcp_required_content_stream(dig_port); 103 } 104 } 105 106 static 107 bool intel_hdcp_is_ksv_valid(u8 *ksv) 108 { 109 int i, ones = 0; 110 /* KSV has 20 1's and 20 0's */ 111 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 112 ones += hweight8(ksv[i]); 113 if (ones != 20) 114 return false; 115 116 return true; 117 } 118 119 static 120 int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, 121 const struct intel_hdcp_shim *shim, u8 *bksv) 122 { 123 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 124 int ret, i, tries = 2; 125 126 /* HDCP spec states that we must retry the bksv if it is invalid */ 127 for (i = 0; i < tries; i++) { 128 ret = shim->read_bksv(dig_port, bksv); 129 if (ret) 130 return ret; 131 if (intel_hdcp_is_ksv_valid(bksv)) 132 break; 133 } 134 if (i == tries) { 135 drm_dbg_kms(&i915->drm, "Bksv is invalid\n"); 136 return -ENODEV; 137 } 138 139 return 0; 140 } 141 142 /* Is HDCP1.4 capable on Platform and Sink */ 143 bool intel_hdcp_capable(struct intel_connector *connector) 144 { 145 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 146 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 147 bool capable = false; 148 u8 bksv[5]; 149 150 if (!shim) 151 return capable; 152 153 if (shim->hdcp_capable) { 154 shim->hdcp_capable(dig_port, &capable); 155 } else { 156 if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) 157 capable = true; 158 } 159 160 return capable; 161 } 162 163 /* Is HDCP2.2 capable on Platform and Sink */ 164 bool intel_hdcp2_capable(struct intel_connector *connector) 165 { 166 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 167 struct drm_i915_private *i915 = to_i915(connector->base.dev); 168 struct intel_hdcp *hdcp = &connector->hdcp; 169 bool capable = false; 170 171 /* I915 support for HDCP2.2 */ 172 if (!hdcp->hdcp2_supported) 173 return false; 174 175 /* If MTL+ make sure gsc is loaded and proxy is setup */ 176 if (intel_hdcp_gsc_cs_required(i915)) { 177 struct intel_gt *gt = i915->media_gt; 178 struct intel_gsc_uc *gsc = gt ? >->uc.gsc : NULL; 179 180 if (!gsc || !intel_uc_fw_is_running(&gsc->fw)) { 181 drm_dbg_kms(&i915->drm, 182 "GSC components required for HDCP2.2 are not ready\n"); 183 return false; 184 } 185 } 186 187 /* MEI/GSC interface is solid depending on which is used */ 188 mutex_lock(&i915->display.hdcp.hdcp_mutex); 189 if (!i915->display.hdcp.comp_added || !i915->display.hdcp.arbiter) { 190 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 191 return false; 192 } 193 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 194 195 /* Sink's capability for HDCP2.2 */ 196 hdcp->shim->hdcp_2_2_capable(dig_port, &capable); 197 198 return capable; 199 } 200 201 static bool intel_hdcp_in_use(struct drm_i915_private *i915, 202 enum transcoder cpu_transcoder, enum port port) 203 { 204 return intel_de_read(i915, 205 HDCP_STATUS(i915, cpu_transcoder, port)) & 206 HDCP_STATUS_ENC; 207 } 208 209 static bool intel_hdcp2_in_use(struct drm_i915_private *i915, 210 enum transcoder cpu_transcoder, enum port port) 211 { 212 return intel_de_read(i915, 213 HDCP2_STATUS(i915, cpu_transcoder, port)) & 214 LINK_ENCRYPTION_STATUS; 215 } 216 217 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, 218 const struct intel_hdcp_shim *shim) 219 { 220 int ret, read_ret; 221 bool ksv_ready; 222 223 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 224 ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port, 225 &ksv_ready), 226 read_ret || ksv_ready, 5 * 1000 * 1000, 1000, 227 100 * 1000); 228 if (ret) 229 return ret; 230 if (read_ret) 231 return read_ret; 232 if (!ksv_ready) 233 return -ETIMEDOUT; 234 235 return 0; 236 } 237 238 static bool hdcp_key_loadable(struct drm_i915_private *i915) 239 { 240 enum i915_power_well_id id; 241 intel_wakeref_t wakeref; 242 bool enabled = false; 243 244 /* 245 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 246 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 247 */ 248 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 249 id = HSW_DISP_PW_GLOBAL; 250 else 251 id = SKL_DISP_PW_1; 252 253 /* PG1 (power well #1) needs to be enabled */ 254 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 255 enabled = intel_display_power_well_is_enabled(i915, id); 256 257 /* 258 * Another req for hdcp key loadability is enabled state of pll for 259 * cdclk. Without active crtc we wont land here. So we are assuming that 260 * cdclk is already on. 261 */ 262 263 return enabled; 264 } 265 266 static void intel_hdcp_clear_keys(struct drm_i915_private *i915) 267 { 268 intel_de_write(i915, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 269 intel_de_write(i915, HDCP_KEY_STATUS, 270 HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 271 } 272 273 static int intel_hdcp_load_keys(struct drm_i915_private *i915) 274 { 275 int ret; 276 u32 val; 277 278 val = intel_de_read(i915, HDCP_KEY_STATUS); 279 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 280 return 0; 281 282 /* 283 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 284 * out of reset. So if Key is not already loaded, its an error state. 285 */ 286 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 287 if (!(intel_de_read(i915, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 288 return -ENXIO; 289 290 /* 291 * Initiate loading the HDCP key from fuses. 292 * 293 * BXT+ platforms, HDCP key needs to be loaded by SW. Only display 294 * version 9 platforms (minus BXT) differ in the key load trigger 295 * process from other platforms. These platforms use the GT Driver 296 * Mailbox interface. 297 */ 298 if (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915)) { 299 ret = snb_pcode_write(&i915->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1); 300 if (ret) { 301 drm_err(&i915->drm, 302 "Failed to initiate HDCP key load (%d)\n", 303 ret); 304 return ret; 305 } 306 } else { 307 intel_de_write(i915, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 308 } 309 310 /* Wait for the keys to load (500us) */ 311 ret = __intel_wait_for_register(&i915->uncore, HDCP_KEY_STATUS, 312 HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, 313 10, 1, &val); 314 if (ret) 315 return ret; 316 else if (!(val & HDCP_KEY_LOAD_STATUS)) 317 return -ENXIO; 318 319 /* Send Aksv over to PCH display for use in authentication */ 320 intel_de_write(i915, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 321 322 return 0; 323 } 324 325 /* Returns updated SHA-1 index */ 326 static int intel_write_sha_text(struct drm_i915_private *i915, u32 sha_text) 327 { 328 intel_de_write(i915, HDCP_SHA_TEXT, sha_text); 329 if (intel_de_wait_for_set(i915, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { 330 drm_err(&i915->drm, "Timed out waiting for SHA1 ready\n"); 331 return -ETIMEDOUT; 332 } 333 return 0; 334 } 335 336 static 337 u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *i915, 338 enum transcoder cpu_transcoder, enum port port) 339 { 340 if (DISPLAY_VER(i915) >= 12) { 341 switch (cpu_transcoder) { 342 case TRANSCODER_A: 343 return HDCP_TRANSA_REP_PRESENT | 344 HDCP_TRANSA_SHA1_M0; 345 case TRANSCODER_B: 346 return HDCP_TRANSB_REP_PRESENT | 347 HDCP_TRANSB_SHA1_M0; 348 case TRANSCODER_C: 349 return HDCP_TRANSC_REP_PRESENT | 350 HDCP_TRANSC_SHA1_M0; 351 case TRANSCODER_D: 352 return HDCP_TRANSD_REP_PRESENT | 353 HDCP_TRANSD_SHA1_M0; 354 default: 355 drm_err(&i915->drm, "Unknown transcoder %d\n", 356 cpu_transcoder); 357 return -EINVAL; 358 } 359 } 360 361 switch (port) { 362 case PORT_A: 363 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 364 case PORT_B: 365 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 366 case PORT_C: 367 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 368 case PORT_D: 369 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 370 case PORT_E: 371 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 372 default: 373 drm_err(&i915->drm, "Unknown port %d\n", port); 374 return -EINVAL; 375 } 376 } 377 378 static 379 int intel_hdcp_validate_v_prime(struct intel_connector *connector, 380 const struct intel_hdcp_shim *shim, 381 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 382 { 383 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 384 struct drm_i915_private *i915 = to_i915(connector->base.dev); 385 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 386 enum port port = dig_port->base.port; 387 u32 vprime, sha_text, sha_leftovers, rep_ctl; 388 int ret, i, j, sha_idx; 389 390 /* Process V' values from the receiver */ 391 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 392 ret = shim->read_v_prime_part(dig_port, i, &vprime); 393 if (ret) 394 return ret; 395 intel_de_write(i915, HDCP_SHA_V_PRIME(i), vprime); 396 } 397 398 /* 399 * We need to write the concatenation of all device KSVs, BINFO (DP) || 400 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 401 * stream is written via the HDCP_SHA_TEXT register in 32-bit 402 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 403 * index will keep track of our progress through the 64 bytes as well as 404 * helping us work the 40-bit KSVs through our 32-bit register. 405 * 406 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 407 */ 408 sha_idx = 0; 409 sha_text = 0; 410 sha_leftovers = 0; 411 rep_ctl = intel_hdcp_get_repeater_ctl(i915, cpu_transcoder, port); 412 intel_de_write(i915, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 413 for (i = 0; i < num_downstream; i++) { 414 unsigned int sha_empty; 415 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 416 417 /* Fill up the empty slots in sha_text and write it out */ 418 sha_empty = sizeof(sha_text) - sha_leftovers; 419 for (j = 0; j < sha_empty; j++) { 420 u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); 421 sha_text |= ksv[j] << off; 422 } 423 424 ret = intel_write_sha_text(i915, sha_text); 425 if (ret < 0) 426 return ret; 427 428 /* Programming guide writes this every 64 bytes */ 429 sha_idx += sizeof(sha_text); 430 if (!(sha_idx % 64)) 431 intel_de_write(i915, HDCP_REP_CTL, 432 rep_ctl | HDCP_SHA1_TEXT_32); 433 434 /* Store the leftover bytes from the ksv in sha_text */ 435 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 436 sha_text = 0; 437 for (j = 0; j < sha_leftovers; j++) 438 sha_text |= ksv[sha_empty + j] << 439 ((sizeof(sha_text) - j - 1) * 8); 440 441 /* 442 * If we still have room in sha_text for more data, continue. 443 * Otherwise, write it out immediately. 444 */ 445 if (sizeof(sha_text) > sha_leftovers) 446 continue; 447 448 ret = intel_write_sha_text(i915, sha_text); 449 if (ret < 0) 450 return ret; 451 sha_leftovers = 0; 452 sha_text = 0; 453 sha_idx += sizeof(sha_text); 454 } 455 456 /* 457 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 458 * bytes are leftover from the last ksv, we might be able to fit them 459 * all in sha_text (first 2 cases), or we might need to split them up 460 * into 2 writes (last 2 cases). 461 */ 462 if (sha_leftovers == 0) { 463 /* Write 16 bits of text, 16 bits of M0 */ 464 intel_de_write(i915, HDCP_REP_CTL, 465 rep_ctl | HDCP_SHA1_TEXT_16); 466 ret = intel_write_sha_text(i915, 467 bstatus[0] << 8 | bstatus[1]); 468 if (ret < 0) 469 return ret; 470 sha_idx += sizeof(sha_text); 471 472 /* Write 32 bits of M0 */ 473 intel_de_write(i915, HDCP_REP_CTL, 474 rep_ctl | HDCP_SHA1_TEXT_0); 475 ret = intel_write_sha_text(i915, 0); 476 if (ret < 0) 477 return ret; 478 sha_idx += sizeof(sha_text); 479 480 /* Write 16 bits of M0 */ 481 intel_de_write(i915, HDCP_REP_CTL, 482 rep_ctl | HDCP_SHA1_TEXT_16); 483 ret = intel_write_sha_text(i915, 0); 484 if (ret < 0) 485 return ret; 486 sha_idx += sizeof(sha_text); 487 488 } else if (sha_leftovers == 1) { 489 /* Write 24 bits of text, 8 bits of M0 */ 490 intel_de_write(i915, HDCP_REP_CTL, 491 rep_ctl | HDCP_SHA1_TEXT_24); 492 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 493 /* Only 24-bits of data, must be in the LSB */ 494 sha_text = (sha_text & 0xffffff00) >> 8; 495 ret = intel_write_sha_text(i915, sha_text); 496 if (ret < 0) 497 return ret; 498 sha_idx += sizeof(sha_text); 499 500 /* Write 32 bits of M0 */ 501 intel_de_write(i915, HDCP_REP_CTL, 502 rep_ctl | HDCP_SHA1_TEXT_0); 503 ret = intel_write_sha_text(i915, 0); 504 if (ret < 0) 505 return ret; 506 sha_idx += sizeof(sha_text); 507 508 /* Write 24 bits of M0 */ 509 intel_de_write(i915, HDCP_REP_CTL, 510 rep_ctl | HDCP_SHA1_TEXT_8); 511 ret = intel_write_sha_text(i915, 0); 512 if (ret < 0) 513 return ret; 514 sha_idx += sizeof(sha_text); 515 516 } else if (sha_leftovers == 2) { 517 /* Write 32 bits of text */ 518 intel_de_write(i915, HDCP_REP_CTL, 519 rep_ctl | HDCP_SHA1_TEXT_32); 520 sha_text |= bstatus[0] << 8 | bstatus[1]; 521 ret = intel_write_sha_text(i915, sha_text); 522 if (ret < 0) 523 return ret; 524 sha_idx += sizeof(sha_text); 525 526 /* Write 64 bits of M0 */ 527 intel_de_write(i915, HDCP_REP_CTL, 528 rep_ctl | HDCP_SHA1_TEXT_0); 529 for (i = 0; i < 2; i++) { 530 ret = intel_write_sha_text(i915, 0); 531 if (ret < 0) 532 return ret; 533 sha_idx += sizeof(sha_text); 534 } 535 536 /* 537 * Terminate the SHA-1 stream by hand. For the other leftover 538 * cases this is appended by the hardware. 539 */ 540 intel_de_write(i915, HDCP_REP_CTL, 541 rep_ctl | HDCP_SHA1_TEXT_32); 542 sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; 543 ret = intel_write_sha_text(i915, sha_text); 544 if (ret < 0) 545 return ret; 546 sha_idx += sizeof(sha_text); 547 } else if (sha_leftovers == 3) { 548 /* Write 32 bits of text (filled from LSB) */ 549 intel_de_write(i915, HDCP_REP_CTL, 550 rep_ctl | HDCP_SHA1_TEXT_32); 551 sha_text |= bstatus[0]; 552 ret = intel_write_sha_text(i915, sha_text); 553 if (ret < 0) 554 return ret; 555 sha_idx += sizeof(sha_text); 556 557 /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ 558 intel_de_write(i915, HDCP_REP_CTL, 559 rep_ctl | HDCP_SHA1_TEXT_8); 560 ret = intel_write_sha_text(i915, bstatus[1]); 561 if (ret < 0) 562 return ret; 563 sha_idx += sizeof(sha_text); 564 565 /* Write 32 bits of M0 */ 566 intel_de_write(i915, HDCP_REP_CTL, 567 rep_ctl | HDCP_SHA1_TEXT_0); 568 ret = intel_write_sha_text(i915, 0); 569 if (ret < 0) 570 return ret; 571 sha_idx += sizeof(sha_text); 572 573 /* Write 8 bits of M0 */ 574 intel_de_write(i915, HDCP_REP_CTL, 575 rep_ctl | HDCP_SHA1_TEXT_24); 576 ret = intel_write_sha_text(i915, 0); 577 if (ret < 0) 578 return ret; 579 sha_idx += sizeof(sha_text); 580 } else { 581 drm_dbg_kms(&i915->drm, "Invalid number of leftovers %d\n", 582 sha_leftovers); 583 return -EINVAL; 584 } 585 586 intel_de_write(i915, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 587 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 588 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 589 ret = intel_write_sha_text(i915, 0); 590 if (ret < 0) 591 return ret; 592 sha_idx += sizeof(sha_text); 593 } 594 595 /* 596 * Last write gets the length of the concatenation in bits. That is: 597 * - 5 bytes per device 598 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 599 */ 600 sha_text = (num_downstream * 5 + 10) * 8; 601 ret = intel_write_sha_text(i915, sha_text); 602 if (ret < 0) 603 return ret; 604 605 /* Tell the HW we're done with the hash and wait for it to ACK */ 606 intel_de_write(i915, HDCP_REP_CTL, 607 rep_ctl | HDCP_SHA1_COMPLETE_HASH); 608 if (intel_de_wait_for_set(i915, HDCP_REP_CTL, 609 HDCP_SHA1_COMPLETE, 1)) { 610 drm_err(&i915->drm, "Timed out waiting for SHA1 complete\n"); 611 return -ETIMEDOUT; 612 } 613 if (!(intel_de_read(i915, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 614 drm_dbg_kms(&i915->drm, "SHA-1 mismatch, HDCP failed\n"); 615 return -ENXIO; 616 } 617 618 return 0; 619 } 620 621 /* Implements Part 2 of the HDCP authorization procedure */ 622 static 623 int intel_hdcp_auth_downstream(struct intel_connector *connector) 624 { 625 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 626 struct drm_i915_private *i915 = to_i915(connector->base.dev); 627 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 628 u8 bstatus[2], num_downstream, *ksv_fifo; 629 int ret, i, tries = 3; 630 631 ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); 632 if (ret) { 633 drm_dbg_kms(&i915->drm, 634 "KSV list failed to become ready (%d)\n", ret); 635 return ret; 636 } 637 638 ret = shim->read_bstatus(dig_port, bstatus); 639 if (ret) 640 return ret; 641 642 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 643 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 644 drm_dbg_kms(&i915->drm, "Max Topology Limit Exceeded\n"); 645 return -EPERM; 646 } 647 648 /* 649 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 650 * the HDCP encryption. That implies that repeater can't have its own 651 * display. As there is no consumption of encrypted content in the 652 * repeater with 0 downstream devices, we are failing the 653 * authentication. 654 */ 655 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 656 if (num_downstream == 0) { 657 drm_dbg_kms(&i915->drm, 658 "Repeater with zero downstream devices\n"); 659 return -EINVAL; 660 } 661 662 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 663 if (!ksv_fifo) { 664 drm_dbg_kms(&i915->drm, "Out of mem: ksv_fifo\n"); 665 return -ENOMEM; 666 } 667 668 ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); 669 if (ret) 670 goto err; 671 672 if (drm_hdcp_check_ksvs_revoked(&i915->drm, ksv_fifo, 673 num_downstream) > 0) { 674 drm_err(&i915->drm, "Revoked Ksv(s) in ksv_fifo\n"); 675 ret = -EPERM; 676 goto err; 677 } 678 679 /* 680 * When V prime mismatches, DP Spec mandates re-read of 681 * V prime atleast twice. 682 */ 683 for (i = 0; i < tries; i++) { 684 ret = intel_hdcp_validate_v_prime(connector, shim, 685 ksv_fifo, num_downstream, 686 bstatus); 687 if (!ret) 688 break; 689 } 690 691 if (i == tries) { 692 drm_dbg_kms(&i915->drm, 693 "V Prime validation failed.(%d)\n", ret); 694 goto err; 695 } 696 697 drm_dbg_kms(&i915->drm, "HDCP is enabled (%d downstream devices)\n", 698 num_downstream); 699 ret = 0; 700 err: 701 kfree(ksv_fifo); 702 return ret; 703 } 704 705 /* Implements Part 1 of the HDCP authorization procedure */ 706 static int intel_hdcp_auth(struct intel_connector *connector) 707 { 708 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 709 struct drm_i915_private *i915 = to_i915(connector->base.dev); 710 struct intel_hdcp *hdcp = &connector->hdcp; 711 const struct intel_hdcp_shim *shim = hdcp->shim; 712 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 713 enum port port = dig_port->base.port; 714 unsigned long r0_prime_gen_start; 715 int ret, i, tries = 2; 716 union { 717 u32 reg[2]; 718 u8 shim[DRM_HDCP_AN_LEN]; 719 } an; 720 union { 721 u32 reg[2]; 722 u8 shim[DRM_HDCP_KSV_LEN]; 723 } bksv; 724 union { 725 u32 reg; 726 u8 shim[DRM_HDCP_RI_LEN]; 727 } ri; 728 bool repeater_present, hdcp_capable; 729 730 /* 731 * Detects whether the display is HDCP capable. Although we check for 732 * valid Bksv below, the HDCP over DP spec requires that we check 733 * whether the display supports HDCP before we write An. For HDMI 734 * displays, this is not necessary. 735 */ 736 if (shim->hdcp_capable) { 737 ret = shim->hdcp_capable(dig_port, &hdcp_capable); 738 if (ret) 739 return ret; 740 if (!hdcp_capable) { 741 drm_dbg_kms(&i915->drm, 742 "Panel is not HDCP capable\n"); 743 return -EINVAL; 744 } 745 } 746 747 /* Initialize An with 2 random values and acquire it */ 748 for (i = 0; i < 2; i++) 749 intel_de_write(i915, 750 HDCP_ANINIT(i915, cpu_transcoder, port), 751 get_random_u32()); 752 intel_de_write(i915, HDCP_CONF(i915, cpu_transcoder, port), 753 HDCP_CONF_CAPTURE_AN); 754 755 /* Wait for An to be acquired */ 756 if (intel_de_wait_for_set(i915, 757 HDCP_STATUS(i915, cpu_transcoder, port), 758 HDCP_STATUS_AN_READY, 1)) { 759 drm_err(&i915->drm, "Timed out waiting for An\n"); 760 return -ETIMEDOUT; 761 } 762 763 an.reg[0] = intel_de_read(i915, 764 HDCP_ANLO(i915, cpu_transcoder, port)); 765 an.reg[1] = intel_de_read(i915, 766 HDCP_ANHI(i915, cpu_transcoder, port)); 767 ret = shim->write_an_aksv(dig_port, an.shim); 768 if (ret) 769 return ret; 770 771 r0_prime_gen_start = jiffies; 772 773 memset(&bksv, 0, sizeof(bksv)); 774 775 ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); 776 if (ret < 0) 777 return ret; 778 779 if (drm_hdcp_check_ksvs_revoked(&i915->drm, bksv.shim, 1) > 0) { 780 drm_err(&i915->drm, "BKSV is revoked\n"); 781 return -EPERM; 782 } 783 784 intel_de_write(i915, HDCP_BKSVLO(i915, cpu_transcoder, port), 785 bksv.reg[0]); 786 intel_de_write(i915, HDCP_BKSVHI(i915, cpu_transcoder, port), 787 bksv.reg[1]); 788 789 ret = shim->repeater_present(dig_port, &repeater_present); 790 if (ret) 791 return ret; 792 if (repeater_present) 793 intel_de_write(i915, HDCP_REP_CTL, 794 intel_hdcp_get_repeater_ctl(i915, cpu_transcoder, port)); 795 796 ret = shim->toggle_signalling(dig_port, cpu_transcoder, true); 797 if (ret) 798 return ret; 799 800 intel_de_write(i915, HDCP_CONF(i915, cpu_transcoder, port), 801 HDCP_CONF_AUTH_AND_ENC); 802 803 /* Wait for R0 ready */ 804 if (wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 805 (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) { 806 drm_err(&i915->drm, "Timed out waiting for R0 ready\n"); 807 return -ETIMEDOUT; 808 } 809 810 /* 811 * Wait for R0' to become available. The spec says 100ms from Aksv, but 812 * some monitors can take longer than this. We'll set the timeout at 813 * 300ms just to be sure. 814 * 815 * On DP, there's an R0_READY bit available but no such bit 816 * exists on HDMI. Since the upper-bound is the same, we'll just do 817 * the stupid thing instead of polling on one and not the other. 818 */ 819 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 820 821 tries = 3; 822 823 /* 824 * DP HDCP Spec mandates the two more reattempt to read R0, incase 825 * of R0 mismatch. 826 */ 827 for (i = 0; i < tries; i++) { 828 ri.reg = 0; 829 ret = shim->read_ri_prime(dig_port, ri.shim); 830 if (ret) 831 return ret; 832 intel_de_write(i915, 833 HDCP_RPRIME(i915, cpu_transcoder, port), 834 ri.reg); 835 836 /* Wait for Ri prime match */ 837 if (!wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 838 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) 839 break; 840 } 841 842 if (i == tries) { 843 drm_dbg_kms(&i915->drm, 844 "Timed out waiting for Ri prime match (%x)\n", 845 intel_de_read(i915, 846 HDCP_STATUS(i915, cpu_transcoder, port))); 847 return -ETIMEDOUT; 848 } 849 850 /* Wait for encryption confirmation */ 851 if (intel_de_wait_for_set(i915, 852 HDCP_STATUS(i915, cpu_transcoder, port), 853 HDCP_STATUS_ENC, 854 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 855 drm_err(&i915->drm, "Timed out waiting for encryption\n"); 856 return -ETIMEDOUT; 857 } 858 859 /* DP MST Auth Part 1 Step 2.a and Step 2.b */ 860 if (shim->stream_encryption) { 861 ret = shim->stream_encryption(connector, true); 862 if (ret) { 863 drm_err(&i915->drm, "[%s:%d] Failed to enable HDCP 1.4 stream enc\n", 864 connector->base.name, connector->base.base.id); 865 return ret; 866 } 867 drm_dbg_kms(&i915->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", 868 transcoder_name(hdcp->stream_transcoder)); 869 } 870 871 if (repeater_present) 872 return intel_hdcp_auth_downstream(connector); 873 874 drm_dbg_kms(&i915->drm, "HDCP is enabled (no repeater present)\n"); 875 return 0; 876 } 877 878 static int _intel_hdcp_disable(struct intel_connector *connector) 879 { 880 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 881 struct drm_i915_private *i915 = to_i915(connector->base.dev); 882 struct intel_hdcp *hdcp = &connector->hdcp; 883 enum port port = dig_port->base.port; 884 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 885 u32 repeater_ctl; 886 int ret; 887 888 drm_dbg_kms(&i915->drm, "[%s:%d] HDCP is being disabled...\n", 889 connector->base.name, connector->base.base.id); 890 891 if (hdcp->shim->stream_encryption) { 892 ret = hdcp->shim->stream_encryption(connector, false); 893 if (ret) { 894 drm_err(&i915->drm, "[%s:%d] Failed to disable HDCP 1.4 stream enc\n", 895 connector->base.name, connector->base.base.id); 896 return ret; 897 } 898 drm_dbg_kms(&i915->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", 899 transcoder_name(hdcp->stream_transcoder)); 900 /* 901 * If there are other connectors on this port using HDCP, 902 * don't disable it until it disabled HDCP encryption for 903 * all connectors in MST topology. 904 */ 905 if (dig_port->num_hdcp_streams > 0) 906 return 0; 907 } 908 909 hdcp->hdcp_encrypted = false; 910 intel_de_write(i915, HDCP_CONF(i915, cpu_transcoder, port), 0); 911 if (intel_de_wait_for_clear(i915, 912 HDCP_STATUS(i915, cpu_transcoder, port), 913 ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 914 drm_err(&i915->drm, 915 "Failed to disable HDCP, timeout clearing status\n"); 916 return -ETIMEDOUT; 917 } 918 919 repeater_ctl = intel_hdcp_get_repeater_ctl(i915, cpu_transcoder, 920 port); 921 intel_de_rmw(i915, HDCP_REP_CTL, repeater_ctl, 0); 922 923 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false); 924 if (ret) { 925 drm_err(&i915->drm, "Failed to disable HDCP signalling\n"); 926 return ret; 927 } 928 929 drm_dbg_kms(&i915->drm, "HDCP is disabled\n"); 930 return 0; 931 } 932 933 static int _intel_hdcp_enable(struct intel_connector *connector) 934 { 935 struct drm_i915_private *i915 = to_i915(connector->base.dev); 936 struct intel_hdcp *hdcp = &connector->hdcp; 937 int i, ret, tries = 3; 938 939 drm_dbg_kms(&i915->drm, "[%s:%d] HDCP is being enabled...\n", 940 connector->base.name, connector->base.base.id); 941 942 if (!hdcp_key_loadable(i915)) { 943 drm_err(&i915->drm, "HDCP key Load is not possible\n"); 944 return -ENXIO; 945 } 946 947 for (i = 0; i < KEY_LOAD_TRIES; i++) { 948 ret = intel_hdcp_load_keys(i915); 949 if (!ret) 950 break; 951 intel_hdcp_clear_keys(i915); 952 } 953 if (ret) { 954 drm_err(&i915->drm, "Could not load HDCP keys, (%d)\n", 955 ret); 956 return ret; 957 } 958 959 /* Incase of authentication failures, HDCP spec expects reauth. */ 960 for (i = 0; i < tries; i++) { 961 ret = intel_hdcp_auth(connector); 962 if (!ret) { 963 hdcp->hdcp_encrypted = true; 964 return 0; 965 } 966 967 drm_dbg_kms(&i915->drm, "HDCP Auth failure (%d)\n", ret); 968 969 /* Ensuring HDCP encryption and signalling are stopped. */ 970 _intel_hdcp_disable(connector); 971 } 972 973 drm_dbg_kms(&i915->drm, 974 "HDCP authentication failed (%d tries/%d)\n", tries, ret); 975 return ret; 976 } 977 978 static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 979 { 980 return container_of(hdcp, struct intel_connector, hdcp); 981 } 982 983 static void intel_hdcp_update_value(struct intel_connector *connector, 984 u64 value, bool update_property) 985 { 986 struct drm_device *dev = connector->base.dev; 987 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 988 struct intel_hdcp *hdcp = &connector->hdcp; 989 struct drm_i915_private *i915 = to_i915(connector->base.dev); 990 991 drm_WARN_ON(connector->base.dev, !mutex_is_locked(&hdcp->mutex)); 992 993 if (hdcp->value == value) 994 return; 995 996 drm_WARN_ON(dev, !mutex_is_locked(&dig_port->hdcp_mutex)); 997 998 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 999 if (!drm_WARN_ON(dev, dig_port->num_hdcp_streams == 0)) 1000 dig_port->num_hdcp_streams--; 1001 } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1002 dig_port->num_hdcp_streams++; 1003 } 1004 1005 hdcp->value = value; 1006 if (update_property) { 1007 drm_connector_get(&connector->base); 1008 if (!queue_work(i915->unordered_wq, &hdcp->prop_work)) 1009 drm_connector_put(&connector->base); 1010 } 1011 } 1012 1013 /* Implements Part 3 of the HDCP authorization procedure */ 1014 static int intel_hdcp_check_link(struct intel_connector *connector) 1015 { 1016 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1017 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1018 struct intel_hdcp *hdcp = &connector->hdcp; 1019 enum port port = dig_port->base.port; 1020 enum transcoder cpu_transcoder; 1021 int ret = 0; 1022 1023 mutex_lock(&hdcp->mutex); 1024 mutex_lock(&dig_port->hdcp_mutex); 1025 1026 cpu_transcoder = hdcp->cpu_transcoder; 1027 1028 /* Check_link valid only when HDCP1.4 is enabled */ 1029 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1030 !hdcp->hdcp_encrypted) { 1031 ret = -EINVAL; 1032 goto out; 1033 } 1034 1035 if (drm_WARN_ON(&i915->drm, 1036 !intel_hdcp_in_use(i915, cpu_transcoder, port))) { 1037 drm_err(&i915->drm, 1038 "%s:%d HDCP link stopped encryption,%x\n", 1039 connector->base.name, connector->base.base.id, 1040 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port))); 1041 ret = -ENXIO; 1042 intel_hdcp_update_value(connector, 1043 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1044 true); 1045 goto out; 1046 } 1047 1048 if (hdcp->shim->check_link(dig_port, connector)) { 1049 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1050 intel_hdcp_update_value(connector, 1051 DRM_MODE_CONTENT_PROTECTION_ENABLED, true); 1052 } 1053 goto out; 1054 } 1055 1056 drm_dbg_kms(&i915->drm, 1057 "[%s:%d] HDCP link failed, retrying authentication\n", 1058 connector->base.name, connector->base.base.id); 1059 1060 ret = _intel_hdcp_disable(connector); 1061 if (ret) { 1062 drm_err(&i915->drm, "Failed to disable hdcp (%d)\n", ret); 1063 intel_hdcp_update_value(connector, 1064 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1065 true); 1066 goto out; 1067 } 1068 1069 ret = _intel_hdcp_enable(connector); 1070 if (ret) { 1071 drm_err(&i915->drm, "Failed to enable hdcp (%d)\n", ret); 1072 intel_hdcp_update_value(connector, 1073 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1074 true); 1075 goto out; 1076 } 1077 1078 out: 1079 mutex_unlock(&dig_port->hdcp_mutex); 1080 mutex_unlock(&hdcp->mutex); 1081 return ret; 1082 } 1083 1084 static void intel_hdcp_prop_work(struct work_struct *work) 1085 { 1086 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 1087 prop_work); 1088 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1089 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1090 1091 drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); 1092 mutex_lock(&hdcp->mutex); 1093 1094 /* 1095 * This worker is only used to flip between ENABLED/DESIRED. Either of 1096 * those to UNDESIRED is handled by core. If value == UNDESIRED, 1097 * we're running just after hdcp has been disabled, so just exit 1098 */ 1099 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1100 drm_hdcp_update_content_protection(&connector->base, 1101 hdcp->value); 1102 1103 mutex_unlock(&hdcp->mutex); 1104 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1105 1106 drm_connector_put(&connector->base); 1107 } 1108 1109 bool is_hdcp_supported(struct drm_i915_private *i915, enum port port) 1110 { 1111 return DISPLAY_RUNTIME_INFO(i915)->has_hdcp && 1112 (DISPLAY_VER(i915) >= 12 || port < PORT_E); 1113 } 1114 1115 static int 1116 hdcp2_prepare_ake_init(struct intel_connector *connector, 1117 struct hdcp2_ake_init *ake_data) 1118 { 1119 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1120 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1121 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1122 struct i915_hdcp_arbiter *arbiter; 1123 int ret; 1124 1125 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1126 arbiter = i915->display.hdcp.arbiter; 1127 1128 if (!arbiter || !arbiter->ops) { 1129 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1130 return -EINVAL; 1131 } 1132 1133 ret = arbiter->ops->initiate_hdcp2_session(arbiter->hdcp_dev, data, ake_data); 1134 if (ret) 1135 drm_dbg_kms(&i915->drm, "Prepare_ake_init failed. %d\n", 1136 ret); 1137 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1138 1139 return ret; 1140 } 1141 1142 static int 1143 hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 1144 struct hdcp2_ake_send_cert *rx_cert, 1145 bool *paired, 1146 struct hdcp2_ake_no_stored_km *ek_pub_km, 1147 size_t *msg_sz) 1148 { 1149 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1150 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1151 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1152 struct i915_hdcp_arbiter *arbiter; 1153 int ret; 1154 1155 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1156 arbiter = i915->display.hdcp.arbiter; 1157 1158 if (!arbiter || !arbiter->ops) { 1159 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1160 return -EINVAL; 1161 } 1162 1163 ret = arbiter->ops->verify_receiver_cert_prepare_km(arbiter->hdcp_dev, data, 1164 rx_cert, paired, 1165 ek_pub_km, msg_sz); 1166 if (ret < 0) 1167 drm_dbg_kms(&i915->drm, "Verify rx_cert failed. %d\n", 1168 ret); 1169 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1170 1171 return ret; 1172 } 1173 1174 static int hdcp2_verify_hprime(struct intel_connector *connector, 1175 struct hdcp2_ake_send_hprime *rx_hprime) 1176 { 1177 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1178 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1179 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1180 struct i915_hdcp_arbiter *arbiter; 1181 int ret; 1182 1183 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1184 arbiter = i915->display.hdcp.arbiter; 1185 1186 if (!arbiter || !arbiter->ops) { 1187 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1188 return -EINVAL; 1189 } 1190 1191 ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime); 1192 if (ret < 0) 1193 drm_dbg_kms(&i915->drm, "Verify hprime failed. %d\n", ret); 1194 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1195 1196 return ret; 1197 } 1198 1199 static int 1200 hdcp2_store_pairing_info(struct intel_connector *connector, 1201 struct hdcp2_ake_send_pairing_info *pairing_info) 1202 { 1203 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1204 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1205 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1206 struct i915_hdcp_arbiter *arbiter; 1207 int ret; 1208 1209 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1210 arbiter = i915->display.hdcp.arbiter; 1211 1212 if (!arbiter || !arbiter->ops) { 1213 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1214 return -EINVAL; 1215 } 1216 1217 ret = arbiter->ops->store_pairing_info(arbiter->hdcp_dev, data, pairing_info); 1218 if (ret < 0) 1219 drm_dbg_kms(&i915->drm, "Store pairing info failed. %d\n", 1220 ret); 1221 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1222 1223 return ret; 1224 } 1225 1226 static int 1227 hdcp2_prepare_lc_init(struct intel_connector *connector, 1228 struct hdcp2_lc_init *lc_init) 1229 { 1230 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1231 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1232 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1233 struct i915_hdcp_arbiter *arbiter; 1234 int ret; 1235 1236 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1237 arbiter = i915->display.hdcp.arbiter; 1238 1239 if (!arbiter || !arbiter->ops) { 1240 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1241 return -EINVAL; 1242 } 1243 1244 ret = arbiter->ops->initiate_locality_check(arbiter->hdcp_dev, data, lc_init); 1245 if (ret < 0) 1246 drm_dbg_kms(&i915->drm, "Prepare lc_init failed. %d\n", 1247 ret); 1248 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1249 1250 return ret; 1251 } 1252 1253 static int 1254 hdcp2_verify_lprime(struct intel_connector *connector, 1255 struct hdcp2_lc_send_lprime *rx_lprime) 1256 { 1257 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1258 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1259 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1260 struct i915_hdcp_arbiter *arbiter; 1261 int ret; 1262 1263 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1264 arbiter = i915->display.hdcp.arbiter; 1265 1266 if (!arbiter || !arbiter->ops) { 1267 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1268 return -EINVAL; 1269 } 1270 1271 ret = arbiter->ops->verify_lprime(arbiter->hdcp_dev, data, rx_lprime); 1272 if (ret < 0) 1273 drm_dbg_kms(&i915->drm, "Verify L_Prime failed. %d\n", 1274 ret); 1275 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1276 1277 return ret; 1278 } 1279 1280 static int hdcp2_prepare_skey(struct intel_connector *connector, 1281 struct hdcp2_ske_send_eks *ske_data) 1282 { 1283 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1284 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1285 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1286 struct i915_hdcp_arbiter *arbiter; 1287 int ret; 1288 1289 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1290 arbiter = i915->display.hdcp.arbiter; 1291 1292 if (!arbiter || !arbiter->ops) { 1293 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1294 return -EINVAL; 1295 } 1296 1297 ret = arbiter->ops->get_session_key(arbiter->hdcp_dev, data, ske_data); 1298 if (ret < 0) 1299 drm_dbg_kms(&i915->drm, "Get session key failed. %d\n", 1300 ret); 1301 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1302 1303 return ret; 1304 } 1305 1306 static int 1307 hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1308 struct hdcp2_rep_send_receiverid_list 1309 *rep_topology, 1310 struct hdcp2_rep_send_ack *rep_send_ack) 1311 { 1312 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1313 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1314 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1315 struct i915_hdcp_arbiter *arbiter; 1316 int ret; 1317 1318 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1319 arbiter = i915->display.hdcp.arbiter; 1320 1321 if (!arbiter || !arbiter->ops) { 1322 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1323 return -EINVAL; 1324 } 1325 1326 ret = arbiter->ops->repeater_check_flow_prepare_ack(arbiter->hdcp_dev, 1327 data, 1328 rep_topology, 1329 rep_send_ack); 1330 if (ret < 0) 1331 drm_dbg_kms(&i915->drm, 1332 "Verify rep topology failed. %d\n", ret); 1333 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1334 1335 return ret; 1336 } 1337 1338 static int 1339 hdcp2_verify_mprime(struct intel_connector *connector, 1340 struct hdcp2_rep_stream_ready *stream_ready) 1341 { 1342 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1343 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1344 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1345 struct i915_hdcp_arbiter *arbiter; 1346 int ret; 1347 1348 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1349 arbiter = i915->display.hdcp.arbiter; 1350 1351 if (!arbiter || !arbiter->ops) { 1352 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1353 return -EINVAL; 1354 } 1355 1356 ret = arbiter->ops->verify_mprime(arbiter->hdcp_dev, data, stream_ready); 1357 if (ret < 0) 1358 drm_dbg_kms(&i915->drm, "Verify mprime failed. %d\n", ret); 1359 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1360 1361 return ret; 1362 } 1363 1364 static int hdcp2_authenticate_port(struct intel_connector *connector) 1365 { 1366 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1367 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1368 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1369 struct i915_hdcp_arbiter *arbiter; 1370 int ret; 1371 1372 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1373 arbiter = i915->display.hdcp.arbiter; 1374 1375 if (!arbiter || !arbiter->ops) { 1376 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1377 return -EINVAL; 1378 } 1379 1380 ret = arbiter->ops->enable_hdcp_authentication(arbiter->hdcp_dev, data); 1381 if (ret < 0) 1382 drm_dbg_kms(&i915->drm, "Enable hdcp auth failed. %d\n", 1383 ret); 1384 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1385 1386 return ret; 1387 } 1388 1389 static int hdcp2_close_session(struct intel_connector *connector) 1390 { 1391 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1392 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1393 struct i915_hdcp_arbiter *arbiter; 1394 int ret; 1395 1396 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1397 arbiter = i915->display.hdcp.arbiter; 1398 1399 if (!arbiter || !arbiter->ops) { 1400 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1401 return -EINVAL; 1402 } 1403 1404 ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, 1405 &dig_port->hdcp_port_data); 1406 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1407 1408 return ret; 1409 } 1410 1411 static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1412 { 1413 return hdcp2_close_session(connector); 1414 } 1415 1416 /* Authentication flow starts from here */ 1417 static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1418 { 1419 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1420 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1421 struct intel_hdcp *hdcp = &connector->hdcp; 1422 union { 1423 struct hdcp2_ake_init ake_init; 1424 struct hdcp2_ake_send_cert send_cert; 1425 struct hdcp2_ake_no_stored_km no_stored_km; 1426 struct hdcp2_ake_send_hprime send_hprime; 1427 struct hdcp2_ake_send_pairing_info pairing_info; 1428 } msgs; 1429 const struct intel_hdcp_shim *shim = hdcp->shim; 1430 size_t size; 1431 int ret; 1432 1433 /* Init for seq_num */ 1434 hdcp->seq_num_v = 0; 1435 hdcp->seq_num_m = 0; 1436 1437 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1438 if (ret < 0) 1439 return ret; 1440 1441 ret = shim->write_2_2_msg(dig_port, &msgs.ake_init, 1442 sizeof(msgs.ake_init)); 1443 if (ret < 0) 1444 return ret; 1445 1446 ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_CERT, 1447 &msgs.send_cert, sizeof(msgs.send_cert)); 1448 if (ret < 0) 1449 return ret; 1450 1451 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { 1452 drm_dbg_kms(&i915->drm, "cert.rx_caps dont claim HDCP2.2\n"); 1453 return -EINVAL; 1454 } 1455 1456 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1457 1458 if (drm_hdcp_check_ksvs_revoked(&i915->drm, 1459 msgs.send_cert.cert_rx.receiver_id, 1460 1) > 0) { 1461 drm_err(&i915->drm, "Receiver ID is revoked\n"); 1462 return -EPERM; 1463 } 1464 1465 /* 1466 * Here msgs.no_stored_km will hold msgs corresponding to the km 1467 * stored also. 1468 */ 1469 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1470 &hdcp->is_paired, 1471 &msgs.no_stored_km, &size); 1472 if (ret < 0) 1473 return ret; 1474 1475 ret = shim->write_2_2_msg(dig_port, &msgs.no_stored_km, size); 1476 if (ret < 0) 1477 return ret; 1478 1479 ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_HPRIME, 1480 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1481 if (ret < 0) 1482 return ret; 1483 1484 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1485 if (ret < 0) 1486 return ret; 1487 1488 if (!hdcp->is_paired) { 1489 /* Pairing is required */ 1490 ret = shim->read_2_2_msg(dig_port, 1491 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1492 &msgs.pairing_info, 1493 sizeof(msgs.pairing_info)); 1494 if (ret < 0) 1495 return ret; 1496 1497 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1498 if (ret < 0) 1499 return ret; 1500 hdcp->is_paired = true; 1501 } 1502 1503 return 0; 1504 } 1505 1506 static int hdcp2_locality_check(struct intel_connector *connector) 1507 { 1508 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1509 struct intel_hdcp *hdcp = &connector->hdcp; 1510 union { 1511 struct hdcp2_lc_init lc_init; 1512 struct hdcp2_lc_send_lprime send_lprime; 1513 } msgs; 1514 const struct intel_hdcp_shim *shim = hdcp->shim; 1515 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1516 1517 for (i = 0; i < tries; i++) { 1518 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1519 if (ret < 0) 1520 continue; 1521 1522 ret = shim->write_2_2_msg(dig_port, &msgs.lc_init, 1523 sizeof(msgs.lc_init)); 1524 if (ret < 0) 1525 continue; 1526 1527 ret = shim->read_2_2_msg(dig_port, 1528 HDCP_2_2_LC_SEND_LPRIME, 1529 &msgs.send_lprime, 1530 sizeof(msgs.send_lprime)); 1531 if (ret < 0) 1532 continue; 1533 1534 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1535 if (!ret) 1536 break; 1537 } 1538 1539 return ret; 1540 } 1541 1542 static int hdcp2_session_key_exchange(struct intel_connector *connector) 1543 { 1544 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1545 struct intel_hdcp *hdcp = &connector->hdcp; 1546 struct hdcp2_ske_send_eks send_eks; 1547 int ret; 1548 1549 ret = hdcp2_prepare_skey(connector, &send_eks); 1550 if (ret < 0) 1551 return ret; 1552 1553 ret = hdcp->shim->write_2_2_msg(dig_port, &send_eks, 1554 sizeof(send_eks)); 1555 if (ret < 0) 1556 return ret; 1557 1558 return 0; 1559 } 1560 1561 static 1562 int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1563 { 1564 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1565 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1566 struct intel_hdcp *hdcp = &connector->hdcp; 1567 union { 1568 struct hdcp2_rep_stream_manage stream_manage; 1569 struct hdcp2_rep_stream_ready stream_ready; 1570 } msgs; 1571 const struct intel_hdcp_shim *shim = hdcp->shim; 1572 int ret, streams_size_delta, i; 1573 1574 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) 1575 return -ERANGE; 1576 1577 /* Prepare RepeaterAuth_Stream_Manage msg */ 1578 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1579 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1580 1581 msgs.stream_manage.k = cpu_to_be16(data->k); 1582 1583 for (i = 0; i < data->k; i++) { 1584 msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; 1585 msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; 1586 } 1587 1588 streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) * 1589 sizeof(struct hdcp2_streamid_type); 1590 /* Send it to Repeater */ 1591 ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage, 1592 sizeof(msgs.stream_manage) - streams_size_delta); 1593 if (ret < 0) 1594 goto out; 1595 1596 ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_STREAM_READY, 1597 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1598 if (ret < 0) 1599 goto out; 1600 1601 data->seq_num_m = hdcp->seq_num_m; 1602 1603 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1604 1605 out: 1606 hdcp->seq_num_m++; 1607 1608 return ret; 1609 } 1610 1611 static 1612 int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1613 { 1614 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1615 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1616 struct intel_hdcp *hdcp = &connector->hdcp; 1617 union { 1618 struct hdcp2_rep_send_receiverid_list recvid_list; 1619 struct hdcp2_rep_send_ack rep_ack; 1620 } msgs; 1621 const struct intel_hdcp_shim *shim = hdcp->shim; 1622 u32 seq_num_v, device_cnt; 1623 u8 *rx_info; 1624 int ret; 1625 1626 ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_SEND_RECVID_LIST, 1627 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1628 if (ret < 0) 1629 return ret; 1630 1631 rx_info = msgs.recvid_list.rx_info; 1632 1633 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1634 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1635 drm_dbg_kms(&i915->drm, "Topology Max Size Exceeded\n"); 1636 return -EINVAL; 1637 } 1638 1639 /* 1640 * MST topology is not Type 1 capable if it contains a downstream 1641 * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. 1642 */ 1643 dig_port->hdcp_mst_type1_capable = 1644 !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && 1645 !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); 1646 1647 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1648 seq_num_v = 1649 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1650 1651 if (!hdcp->hdcp2_encrypted && seq_num_v) { 1652 drm_dbg_kms(&i915->drm, 1653 "Non zero Seq_num_v at first RecvId_List msg\n"); 1654 return -EINVAL; 1655 } 1656 1657 if (seq_num_v < hdcp->seq_num_v) { 1658 /* Roll over of the seq_num_v from repeater. Reauthenticate. */ 1659 drm_dbg_kms(&i915->drm, "Seq_num_v roll over.\n"); 1660 return -EINVAL; 1661 } 1662 1663 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1664 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1665 if (drm_hdcp_check_ksvs_revoked(&i915->drm, 1666 msgs.recvid_list.receiver_ids, 1667 device_cnt) > 0) { 1668 drm_err(&i915->drm, "Revoked receiver ID(s) is in list\n"); 1669 return -EPERM; 1670 } 1671 1672 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1673 &msgs.recvid_list, 1674 &msgs.rep_ack); 1675 if (ret < 0) 1676 return ret; 1677 1678 hdcp->seq_num_v = seq_num_v; 1679 ret = shim->write_2_2_msg(dig_port, &msgs.rep_ack, 1680 sizeof(msgs.rep_ack)); 1681 if (ret < 0) 1682 return ret; 1683 1684 return 0; 1685 } 1686 1687 static int hdcp2_authenticate_sink(struct intel_connector *connector) 1688 { 1689 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1690 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1691 struct intel_hdcp *hdcp = &connector->hdcp; 1692 const struct intel_hdcp_shim *shim = hdcp->shim; 1693 int ret; 1694 1695 ret = hdcp2_authentication_key_exchange(connector); 1696 if (ret < 0) { 1697 drm_dbg_kms(&i915->drm, "AKE Failed. Err : %d\n", ret); 1698 return ret; 1699 } 1700 1701 ret = hdcp2_locality_check(connector); 1702 if (ret < 0) { 1703 drm_dbg_kms(&i915->drm, 1704 "Locality Check failed. Err : %d\n", ret); 1705 return ret; 1706 } 1707 1708 ret = hdcp2_session_key_exchange(connector); 1709 if (ret < 0) { 1710 drm_dbg_kms(&i915->drm, "SKE Failed. Err : %d\n", ret); 1711 return ret; 1712 } 1713 1714 if (shim->config_stream_type) { 1715 ret = shim->config_stream_type(dig_port, 1716 hdcp->is_repeater, 1717 hdcp->content_type); 1718 if (ret < 0) 1719 return ret; 1720 } 1721 1722 if (hdcp->is_repeater) { 1723 ret = hdcp2_authenticate_repeater_topology(connector); 1724 if (ret < 0) { 1725 drm_dbg_kms(&i915->drm, 1726 "Repeater Auth Failed. Err: %d\n", ret); 1727 return ret; 1728 } 1729 } 1730 1731 return ret; 1732 } 1733 1734 static int hdcp2_enable_stream_encryption(struct intel_connector *connector) 1735 { 1736 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1737 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1738 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1739 struct intel_hdcp *hdcp = &connector->hdcp; 1740 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1741 enum port port = dig_port->base.port; 1742 int ret = 0; 1743 1744 if (!(intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & 1745 LINK_ENCRYPTION_STATUS)) { 1746 drm_err(&i915->drm, "[%s:%d] HDCP 2.2 Link is not encrypted\n", 1747 connector->base.name, connector->base.base.id); 1748 ret = -EPERM; 1749 goto link_recover; 1750 } 1751 1752 if (hdcp->shim->stream_2_2_encryption) { 1753 ret = hdcp->shim->stream_2_2_encryption(connector, true); 1754 if (ret) { 1755 drm_err(&i915->drm, "[%s:%d] Failed to enable HDCP 2.2 stream enc\n", 1756 connector->base.name, connector->base.base.id); 1757 return ret; 1758 } 1759 drm_dbg_kms(&i915->drm, "HDCP 2.2 transcoder: %s stream encrypted\n", 1760 transcoder_name(hdcp->stream_transcoder)); 1761 } 1762 1763 return 0; 1764 1765 link_recover: 1766 if (hdcp2_deauthenticate_port(connector) < 0) 1767 drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); 1768 1769 dig_port->hdcp_auth_status = false; 1770 data->k = 0; 1771 1772 return ret; 1773 } 1774 1775 static int hdcp2_enable_encryption(struct intel_connector *connector) 1776 { 1777 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1778 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1779 struct intel_hdcp *hdcp = &connector->hdcp; 1780 enum port port = dig_port->base.port; 1781 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1782 int ret; 1783 1784 drm_WARN_ON(&i915->drm, 1785 intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & 1786 LINK_ENCRYPTION_STATUS); 1787 if (hdcp->shim->toggle_signalling) { 1788 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1789 true); 1790 if (ret) { 1791 drm_err(&i915->drm, 1792 "Failed to enable HDCP signalling. %d\n", 1793 ret); 1794 return ret; 1795 } 1796 } 1797 1798 if (intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & 1799 LINK_AUTH_STATUS) 1800 /* Link is Authenticated. Now set for Encryption */ 1801 intel_de_rmw(i915, HDCP2_CTL(i915, cpu_transcoder, port), 1802 0, CTL_LINK_ENCRYPTION_REQ); 1803 1804 ret = intel_de_wait_for_set(i915, 1805 HDCP2_STATUS(i915, cpu_transcoder, 1806 port), 1807 LINK_ENCRYPTION_STATUS, 1808 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1809 dig_port->hdcp_auth_status = true; 1810 1811 return ret; 1812 } 1813 1814 static int hdcp2_disable_encryption(struct intel_connector *connector) 1815 { 1816 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1817 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1818 struct intel_hdcp *hdcp = &connector->hdcp; 1819 enum port port = dig_port->base.port; 1820 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1821 int ret; 1822 1823 drm_WARN_ON(&i915->drm, !(intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & 1824 LINK_ENCRYPTION_STATUS)); 1825 1826 intel_de_rmw(i915, HDCP2_CTL(i915, cpu_transcoder, port), 1827 CTL_LINK_ENCRYPTION_REQ, 0); 1828 1829 ret = intel_de_wait_for_clear(i915, 1830 HDCP2_STATUS(i915, cpu_transcoder, 1831 port), 1832 LINK_ENCRYPTION_STATUS, 1833 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1834 if (ret == -ETIMEDOUT) 1835 drm_dbg_kms(&i915->drm, "Disable Encryption Timedout"); 1836 1837 if (hdcp->shim->toggle_signalling) { 1838 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1839 false); 1840 if (ret) { 1841 drm_err(&i915->drm, 1842 "Failed to disable HDCP signalling. %d\n", 1843 ret); 1844 return ret; 1845 } 1846 } 1847 1848 return ret; 1849 } 1850 1851 static int 1852 hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1853 { 1854 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1855 int i, tries = 3, ret; 1856 1857 if (!connector->hdcp.is_repeater) 1858 return 0; 1859 1860 for (i = 0; i < tries; i++) { 1861 ret = _hdcp2_propagate_stream_management_info(connector); 1862 if (!ret) 1863 break; 1864 1865 /* Lets restart the auth incase of seq_num_m roll over */ 1866 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 1867 drm_dbg_kms(&i915->drm, 1868 "seq_num_m roll over.(%d)\n", ret); 1869 break; 1870 } 1871 1872 drm_dbg_kms(&i915->drm, 1873 "HDCP2 stream management %d of %d Failed.(%d)\n", 1874 i + 1, tries, ret); 1875 } 1876 1877 return ret; 1878 } 1879 1880 static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector) 1881 { 1882 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1883 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1884 int ret = 0, i, tries = 3; 1885 1886 for (i = 0; i < tries && !dig_port->hdcp_auth_status; i++) { 1887 ret = hdcp2_authenticate_sink(connector); 1888 if (!ret) { 1889 intel_hdcp_prepare_streams(connector); 1890 1891 ret = hdcp2_propagate_stream_management_info(connector); 1892 if (ret) { 1893 drm_dbg_kms(&i915->drm, 1894 "Stream management failed.(%d)\n", 1895 ret); 1896 break; 1897 } 1898 1899 ret = hdcp2_authenticate_port(connector); 1900 if (!ret) 1901 break; 1902 drm_dbg_kms(&i915->drm, "HDCP2 port auth failed.(%d)\n", 1903 ret); 1904 } 1905 1906 /* Clearing the mei hdcp session */ 1907 drm_dbg_kms(&i915->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", 1908 i + 1, tries, ret); 1909 if (hdcp2_deauthenticate_port(connector) < 0) 1910 drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); 1911 } 1912 1913 if (!ret && !dig_port->hdcp_auth_status) { 1914 /* 1915 * Ensuring the required 200mSec min time interval between 1916 * Session Key Exchange and encryption. 1917 */ 1918 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 1919 ret = hdcp2_enable_encryption(connector); 1920 if (ret < 0) { 1921 drm_dbg_kms(&i915->drm, 1922 "Encryption Enable Failed.(%d)\n", ret); 1923 if (hdcp2_deauthenticate_port(connector) < 0) 1924 drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); 1925 } 1926 } 1927 1928 if (!ret) 1929 ret = hdcp2_enable_stream_encryption(connector); 1930 1931 return ret; 1932 } 1933 1934 static int _intel_hdcp2_enable(struct intel_connector *connector) 1935 { 1936 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1937 struct intel_hdcp *hdcp = &connector->hdcp; 1938 int ret; 1939 1940 drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being enabled. Type: %d\n", 1941 connector->base.name, connector->base.base.id, 1942 hdcp->content_type); 1943 1944 ret = hdcp2_authenticate_and_encrypt(connector); 1945 if (ret) { 1946 drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", 1947 hdcp->content_type, ret); 1948 return ret; 1949 } 1950 1951 drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is enabled. Type %d\n", 1952 connector->base.name, connector->base.base.id, 1953 hdcp->content_type); 1954 1955 hdcp->hdcp2_encrypted = true; 1956 return 0; 1957 } 1958 1959 static int 1960 _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery) 1961 { 1962 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1963 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1964 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1965 struct intel_hdcp *hdcp = &connector->hdcp; 1966 int ret; 1967 1968 drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n", 1969 connector->base.name, connector->base.base.id); 1970 1971 if (hdcp->shim->stream_2_2_encryption) { 1972 ret = hdcp->shim->stream_2_2_encryption(connector, false); 1973 if (ret) { 1974 drm_err(&i915->drm, "[%s:%d] Failed to disable HDCP 2.2 stream enc\n", 1975 connector->base.name, connector->base.base.id); 1976 return ret; 1977 } 1978 drm_dbg_kms(&i915->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", 1979 transcoder_name(hdcp->stream_transcoder)); 1980 1981 if (dig_port->num_hdcp_streams > 0 && !hdcp2_link_recovery) 1982 return 0; 1983 } 1984 1985 ret = hdcp2_disable_encryption(connector); 1986 1987 if (hdcp2_deauthenticate_port(connector) < 0) 1988 drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); 1989 1990 connector->hdcp.hdcp2_encrypted = false; 1991 dig_port->hdcp_auth_status = false; 1992 data->k = 0; 1993 1994 return ret; 1995 } 1996 1997 /* Implements the Link Integrity Check for HDCP2.2 */ 1998 static int intel_hdcp2_check_link(struct intel_connector *connector) 1999 { 2000 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2001 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2002 struct intel_hdcp *hdcp = &connector->hdcp; 2003 enum port port = dig_port->base.port; 2004 enum transcoder cpu_transcoder; 2005 int ret = 0; 2006 2007 mutex_lock(&hdcp->mutex); 2008 mutex_lock(&dig_port->hdcp_mutex); 2009 cpu_transcoder = hdcp->cpu_transcoder; 2010 2011 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 2012 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 2013 !hdcp->hdcp2_encrypted) { 2014 ret = -EINVAL; 2015 goto out; 2016 } 2017 2018 if (drm_WARN_ON(&i915->drm, 2019 !intel_hdcp2_in_use(i915, cpu_transcoder, port))) { 2020 drm_err(&i915->drm, 2021 "HDCP2.2 link stopped the encryption, %x\n", 2022 intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port))); 2023 ret = -ENXIO; 2024 _intel_hdcp2_disable(connector, true); 2025 intel_hdcp_update_value(connector, 2026 DRM_MODE_CONTENT_PROTECTION_DESIRED, 2027 true); 2028 goto out; 2029 } 2030 2031 ret = hdcp->shim->check_2_2_link(dig_port, connector); 2032 if (ret == HDCP_LINK_PROTECTED) { 2033 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2034 intel_hdcp_update_value(connector, 2035 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2036 true); 2037 } 2038 goto out; 2039 } 2040 2041 if (ret == HDCP_TOPOLOGY_CHANGE) { 2042 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2043 goto out; 2044 2045 drm_dbg_kms(&i915->drm, 2046 "HDCP2.2 Downstream topology change\n"); 2047 ret = hdcp2_authenticate_repeater_topology(connector); 2048 if (!ret) { 2049 intel_hdcp_update_value(connector, 2050 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2051 true); 2052 goto out; 2053 } 2054 drm_dbg_kms(&i915->drm, 2055 "[%s:%d] Repeater topology auth failed.(%d)\n", 2056 connector->base.name, connector->base.base.id, 2057 ret); 2058 } else { 2059 drm_dbg_kms(&i915->drm, 2060 "[%s:%d] HDCP2.2 link failed, retrying auth\n", 2061 connector->base.name, connector->base.base.id); 2062 } 2063 2064 ret = _intel_hdcp2_disable(connector, true); 2065 if (ret) { 2066 drm_err(&i915->drm, 2067 "[%s:%d] Failed to disable hdcp2.2 (%d)\n", 2068 connector->base.name, connector->base.base.id, ret); 2069 intel_hdcp_update_value(connector, 2070 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2071 goto out; 2072 } 2073 2074 ret = _intel_hdcp2_enable(connector); 2075 if (ret) { 2076 drm_dbg_kms(&i915->drm, 2077 "[%s:%d] Failed to enable hdcp2.2 (%d)\n", 2078 connector->base.name, connector->base.base.id, 2079 ret); 2080 intel_hdcp_update_value(connector, 2081 DRM_MODE_CONTENT_PROTECTION_DESIRED, 2082 true); 2083 goto out; 2084 } 2085 2086 out: 2087 mutex_unlock(&dig_port->hdcp_mutex); 2088 mutex_unlock(&hdcp->mutex); 2089 return ret; 2090 } 2091 2092 static void intel_hdcp_check_work(struct work_struct *work) 2093 { 2094 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 2095 struct intel_hdcp, 2096 check_work); 2097 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 2098 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2099 2100 if (drm_connector_is_unregistered(&connector->base)) 2101 return; 2102 2103 if (!intel_hdcp2_check_link(connector)) 2104 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2105 DRM_HDCP2_CHECK_PERIOD_MS); 2106 else if (!intel_hdcp_check_link(connector)) 2107 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2108 DRM_HDCP_CHECK_PERIOD_MS); 2109 } 2110 2111 static int i915_hdcp_component_bind(struct device *i915_kdev, 2112 struct device *mei_kdev, void *data) 2113 { 2114 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 2115 2116 drm_dbg(&i915->drm, "I915 HDCP comp bind\n"); 2117 mutex_lock(&i915->display.hdcp.hdcp_mutex); 2118 i915->display.hdcp.arbiter = (struct i915_hdcp_arbiter *)data; 2119 i915->display.hdcp.arbiter->hdcp_dev = mei_kdev; 2120 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2121 2122 return 0; 2123 } 2124 2125 static void i915_hdcp_component_unbind(struct device *i915_kdev, 2126 struct device *mei_kdev, void *data) 2127 { 2128 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 2129 2130 drm_dbg(&i915->drm, "I915 HDCP comp unbind\n"); 2131 mutex_lock(&i915->display.hdcp.hdcp_mutex); 2132 i915->display.hdcp.arbiter = NULL; 2133 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2134 } 2135 2136 static const struct component_ops i915_hdcp_ops = { 2137 .bind = i915_hdcp_component_bind, 2138 .unbind = i915_hdcp_component_unbind, 2139 }; 2140 2141 static enum hdcp_ddi intel_get_hdcp_ddi_index(enum port port) 2142 { 2143 switch (port) { 2144 case PORT_A: 2145 return HDCP_DDI_A; 2146 case PORT_B ... PORT_F: 2147 return (enum hdcp_ddi)port; 2148 default: 2149 return HDCP_DDI_INVALID_PORT; 2150 } 2151 } 2152 2153 static enum hdcp_transcoder intel_get_hdcp_transcoder(enum transcoder cpu_transcoder) 2154 { 2155 switch (cpu_transcoder) { 2156 case TRANSCODER_A ... TRANSCODER_D: 2157 return (enum hdcp_transcoder)(cpu_transcoder | 0x10); 2158 default: /* eDP, DSI TRANSCODERS are non HDCP capable */ 2159 return HDCP_INVALID_TRANSCODER; 2160 } 2161 } 2162 2163 static int initialize_hdcp_port_data(struct intel_connector *connector, 2164 struct intel_digital_port *dig_port, 2165 const struct intel_hdcp_shim *shim) 2166 { 2167 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2168 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 2169 enum port port = dig_port->base.port; 2170 2171 if (DISPLAY_VER(i915) < 12) 2172 data->hdcp_ddi = intel_get_hdcp_ddi_index(port); 2173 else 2174 /* 2175 * As per ME FW API expectation, for GEN 12+, hdcp_ddi is filled 2176 * with zero(INVALID PORT index). 2177 */ 2178 data->hdcp_ddi = HDCP_DDI_INVALID_PORT; 2179 2180 /* 2181 * As associated transcoder is set and modified at modeset, here hdcp_transcoder 2182 * is initialized to zero (invalid transcoder index). This will be 2183 * retained for <Gen12 forever. 2184 */ 2185 data->hdcp_transcoder = HDCP_INVALID_TRANSCODER; 2186 2187 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 2188 data->protocol = (u8)shim->protocol; 2189 2190 if (!data->streams) 2191 data->streams = kcalloc(INTEL_NUM_PIPES(i915), 2192 sizeof(struct hdcp2_streamid_type), 2193 GFP_KERNEL); 2194 if (!data->streams) { 2195 drm_err(&i915->drm, "Out of Memory\n"); 2196 return -ENOMEM; 2197 } 2198 2199 return 0; 2200 } 2201 2202 static bool is_hdcp2_supported(struct drm_i915_private *i915) 2203 { 2204 if (intel_hdcp_gsc_cs_required(i915)) 2205 return true; 2206 2207 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 2208 return false; 2209 2210 return (DISPLAY_VER(i915) >= 10 || 2211 IS_KABYLAKE(i915) || 2212 IS_COFFEELAKE(i915) || 2213 IS_COMETLAKE(i915)); 2214 } 2215 2216 void intel_hdcp_component_init(struct drm_i915_private *i915) 2217 { 2218 int ret; 2219 2220 if (!is_hdcp2_supported(i915)) 2221 return; 2222 2223 mutex_lock(&i915->display.hdcp.hdcp_mutex); 2224 drm_WARN_ON(&i915->drm, i915->display.hdcp.comp_added); 2225 2226 i915->display.hdcp.comp_added = true; 2227 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2228 if (intel_hdcp_gsc_cs_required(i915)) 2229 ret = intel_hdcp_gsc_init(i915); 2230 else 2231 ret = component_add_typed(i915->drm.dev, &i915_hdcp_ops, 2232 I915_COMPONENT_HDCP); 2233 2234 if (ret < 0) { 2235 drm_dbg_kms(&i915->drm, "Failed at fw component add(%d)\n", 2236 ret); 2237 mutex_lock(&i915->display.hdcp.hdcp_mutex); 2238 i915->display.hdcp.comp_added = false; 2239 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2240 return; 2241 } 2242 } 2243 2244 static void intel_hdcp2_init(struct intel_connector *connector, 2245 struct intel_digital_port *dig_port, 2246 const struct intel_hdcp_shim *shim) 2247 { 2248 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2249 struct intel_hdcp *hdcp = &connector->hdcp; 2250 int ret; 2251 2252 ret = initialize_hdcp_port_data(connector, dig_port, shim); 2253 if (ret) { 2254 drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n"); 2255 return; 2256 } 2257 2258 hdcp->hdcp2_supported = true; 2259 } 2260 2261 int intel_hdcp_init(struct intel_connector *connector, 2262 struct intel_digital_port *dig_port, 2263 const struct intel_hdcp_shim *shim) 2264 { 2265 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2266 struct intel_hdcp *hdcp = &connector->hdcp; 2267 int ret; 2268 2269 if (!shim) 2270 return -EINVAL; 2271 2272 if (is_hdcp2_supported(i915)) 2273 intel_hdcp2_init(connector, dig_port, shim); 2274 2275 ret = 2276 drm_connector_attach_content_protection_property(&connector->base, 2277 hdcp->hdcp2_supported); 2278 if (ret) { 2279 hdcp->hdcp2_supported = false; 2280 kfree(dig_port->hdcp_port_data.streams); 2281 return ret; 2282 } 2283 2284 hdcp->shim = shim; 2285 mutex_init(&hdcp->mutex); 2286 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 2287 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 2288 init_waitqueue_head(&hdcp->cp_irq_queue); 2289 2290 return 0; 2291 } 2292 2293 static int 2294 intel_hdcp_set_streams(struct intel_digital_port *dig_port, 2295 struct intel_atomic_state *state) 2296 { 2297 struct drm_connector_list_iter conn_iter; 2298 struct intel_digital_port *conn_dig_port; 2299 struct intel_connector *connector; 2300 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2301 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 2302 2303 if (!intel_encoder_is_mst(&dig_port->base)) { 2304 data->k = 1; 2305 data->streams[0].stream_id = 0; 2306 return 0; 2307 } 2308 2309 data->k = 0; 2310 2311 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 2312 for_each_intel_connector_iter(connector, &conn_iter) { 2313 if (connector->base.status == connector_status_disconnected) 2314 continue; 2315 2316 if (!intel_encoder_is_mst(intel_attached_encoder(connector))) 2317 continue; 2318 2319 conn_dig_port = intel_attached_dig_port(connector); 2320 if (conn_dig_port != dig_port) 2321 continue; 2322 2323 data->streams[data->k].stream_id = 2324 intel_conn_to_vcpi(&state->base, connector); 2325 data->k++; 2326 2327 /* if there is only one active stream */ 2328 if (dig_port->dp.active_mst_links <= 1) 2329 break; 2330 } 2331 drm_connector_list_iter_end(&conn_iter); 2332 2333 if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0)) 2334 return -EINVAL; 2335 2336 return 0; 2337 } 2338 2339 int intel_hdcp_enable(struct intel_atomic_state *state, 2340 struct intel_encoder *encoder, 2341 const struct intel_crtc_state *pipe_config, 2342 const struct drm_connector_state *conn_state) 2343 { 2344 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2345 struct intel_connector *connector = 2346 to_intel_connector(conn_state->connector); 2347 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2348 struct intel_hdcp *hdcp = &connector->hdcp; 2349 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 2350 int ret = -EINVAL; 2351 2352 if (!hdcp->shim) 2353 return -ENOENT; 2354 2355 if (!connector->encoder) { 2356 drm_err(&i915->drm, "[%s:%d] encoder is not initialized\n", 2357 connector->base.name, connector->base.base.id); 2358 return -ENODEV; 2359 } 2360 2361 mutex_lock(&hdcp->mutex); 2362 mutex_lock(&dig_port->hdcp_mutex); 2363 drm_WARN_ON(&i915->drm, 2364 hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 2365 hdcp->content_type = (u8)conn_state->hdcp_content_type; 2366 2367 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { 2368 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; 2369 hdcp->stream_transcoder = pipe_config->cpu_transcoder; 2370 } else { 2371 hdcp->cpu_transcoder = pipe_config->cpu_transcoder; 2372 hdcp->stream_transcoder = INVALID_TRANSCODER; 2373 } 2374 2375 if (DISPLAY_VER(i915) >= 12) 2376 dig_port->hdcp_port_data.hdcp_transcoder = 2377 intel_get_hdcp_transcoder(hdcp->cpu_transcoder); 2378 2379 /* 2380 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 2381 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 2382 */ 2383 if (intel_hdcp2_capable(connector)) { 2384 ret = intel_hdcp_set_streams(dig_port, state); 2385 if (!ret) { 2386 ret = _intel_hdcp2_enable(connector); 2387 if (!ret) 2388 check_link_interval = 2389 DRM_HDCP2_CHECK_PERIOD_MS; 2390 } else { 2391 drm_dbg_kms(&i915->drm, 2392 "Set content streams failed: (%d)\n", 2393 ret); 2394 } 2395 } 2396 2397 /* 2398 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will 2399 * be attempted. 2400 */ 2401 if (ret && intel_hdcp_capable(connector) && 2402 hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { 2403 ret = _intel_hdcp_enable(connector); 2404 } 2405 2406 if (!ret) { 2407 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2408 check_link_interval); 2409 intel_hdcp_update_value(connector, 2410 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2411 true); 2412 } 2413 2414 mutex_unlock(&dig_port->hdcp_mutex); 2415 mutex_unlock(&hdcp->mutex); 2416 return ret; 2417 } 2418 2419 int intel_hdcp_disable(struct intel_connector *connector) 2420 { 2421 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2422 struct intel_hdcp *hdcp = &connector->hdcp; 2423 int ret = 0; 2424 2425 if (!hdcp->shim) 2426 return -ENOENT; 2427 2428 mutex_lock(&hdcp->mutex); 2429 mutex_lock(&dig_port->hdcp_mutex); 2430 2431 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2432 goto out; 2433 2434 intel_hdcp_update_value(connector, 2435 DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); 2436 if (hdcp->hdcp2_encrypted) 2437 ret = _intel_hdcp2_disable(connector, false); 2438 else if (hdcp->hdcp_encrypted) 2439 ret = _intel_hdcp_disable(connector); 2440 2441 out: 2442 mutex_unlock(&dig_port->hdcp_mutex); 2443 mutex_unlock(&hdcp->mutex); 2444 cancel_delayed_work_sync(&hdcp->check_work); 2445 return ret; 2446 } 2447 2448 void intel_hdcp_update_pipe(struct intel_atomic_state *state, 2449 struct intel_encoder *encoder, 2450 const struct intel_crtc_state *crtc_state, 2451 const struct drm_connector_state *conn_state) 2452 { 2453 struct intel_connector *connector = 2454 to_intel_connector(conn_state->connector); 2455 struct intel_hdcp *hdcp = &connector->hdcp; 2456 bool content_protection_type_changed, desired_and_not_enabled = false; 2457 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2458 2459 if (!connector->hdcp.shim) 2460 return; 2461 2462 content_protection_type_changed = 2463 (conn_state->hdcp_content_type != hdcp->content_type && 2464 conn_state->content_protection != 2465 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 2466 2467 /* 2468 * During the HDCP encryption session if Type change is requested, 2469 * disable the HDCP and reenable it with new TYPE value. 2470 */ 2471 if (conn_state->content_protection == 2472 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 2473 content_protection_type_changed) 2474 intel_hdcp_disable(connector); 2475 2476 /* 2477 * Mark the hdcp state as DESIRED after the hdcp disable of type 2478 * change procedure. 2479 */ 2480 if (content_protection_type_changed) { 2481 mutex_lock(&hdcp->mutex); 2482 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2483 drm_connector_get(&connector->base); 2484 if (!queue_work(i915->unordered_wq, &hdcp->prop_work)) 2485 drm_connector_put(&connector->base); 2486 mutex_unlock(&hdcp->mutex); 2487 } 2488 2489 if (conn_state->content_protection == 2490 DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2491 mutex_lock(&hdcp->mutex); 2492 /* Avoid enabling hdcp, if it already ENABLED */ 2493 desired_and_not_enabled = 2494 hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; 2495 mutex_unlock(&hdcp->mutex); 2496 /* 2497 * If HDCP already ENABLED and CP property is DESIRED, schedule 2498 * prop_work to update correct CP property to user space. 2499 */ 2500 if (!desired_and_not_enabled && !content_protection_type_changed) { 2501 drm_connector_get(&connector->base); 2502 if (!queue_work(i915->unordered_wq, &hdcp->prop_work)) 2503 drm_connector_put(&connector->base); 2504 2505 } 2506 } 2507 2508 if (desired_and_not_enabled || content_protection_type_changed) 2509 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2510 } 2511 2512 void intel_hdcp_component_fini(struct drm_i915_private *i915) 2513 { 2514 mutex_lock(&i915->display.hdcp.hdcp_mutex); 2515 if (!i915->display.hdcp.comp_added) { 2516 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2517 return; 2518 } 2519 2520 i915->display.hdcp.comp_added = false; 2521 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2522 2523 if (intel_hdcp_gsc_cs_required(i915)) 2524 intel_hdcp_gsc_fini(i915); 2525 else 2526 component_del(i915->drm.dev, &i915_hdcp_ops); 2527 } 2528 2529 void intel_hdcp_cleanup(struct intel_connector *connector) 2530 { 2531 struct intel_hdcp *hdcp = &connector->hdcp; 2532 2533 if (!hdcp->shim) 2534 return; 2535 2536 /* 2537 * If the connector is registered, it's possible userspace could kick 2538 * off another HDCP enable, which would re-spawn the workers. 2539 */ 2540 drm_WARN_ON(connector->base.dev, 2541 connector->base.registration_state == DRM_CONNECTOR_REGISTERED); 2542 2543 /* 2544 * Now that the connector is not registered, check_work won't be run, 2545 * but cancel any outstanding instances of it 2546 */ 2547 cancel_delayed_work_sync(&hdcp->check_work); 2548 2549 /* 2550 * We don't cancel prop_work in the same way as check_work since it 2551 * requires connection_mutex which could be held while calling this 2552 * function. Instead, we rely on the connector references grabbed before 2553 * scheduling prop_work to ensure the connector is alive when prop_work 2554 * is run. So if we're in the destroy path (which is where this 2555 * function should be called), we're "guaranteed" that prop_work is not 2556 * active (tl;dr This Should Never Happen). 2557 */ 2558 drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); 2559 2560 mutex_lock(&hdcp->mutex); 2561 hdcp->shim = NULL; 2562 mutex_unlock(&hdcp->mutex); 2563 } 2564 2565 void intel_hdcp_atomic_check(struct drm_connector *connector, 2566 struct drm_connector_state *old_state, 2567 struct drm_connector_state *new_state) 2568 { 2569 u64 old_cp = old_state->content_protection; 2570 u64 new_cp = new_state->content_protection; 2571 struct drm_crtc_state *crtc_state; 2572 2573 if (!new_state->crtc) { 2574 /* 2575 * If the connector is being disabled with CP enabled, mark it 2576 * desired so it's re-enabled when the connector is brought back 2577 */ 2578 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2579 new_state->content_protection = 2580 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2581 return; 2582 } 2583 2584 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 2585 new_state->crtc); 2586 /* 2587 * Fix the HDCP uapi content protection state in case of modeset. 2588 * FIXME: As per HDCP content protection property uapi doc, an uevent() 2589 * need to be sent if there is transition from ENABLED->DESIRED. 2590 */ 2591 if (drm_atomic_crtc_needs_modeset(crtc_state) && 2592 (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && 2593 new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2594 new_state->content_protection = 2595 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2596 2597 /* 2598 * Nothing to do if the state didn't change, or HDCP was activated since 2599 * the last commit. And also no change in hdcp content type. 2600 */ 2601 if (old_cp == new_cp || 2602 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 2603 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { 2604 if (old_state->hdcp_content_type == 2605 new_state->hdcp_content_type) 2606 return; 2607 } 2608 2609 crtc_state->mode_changed = true; 2610 } 2611 2612 /* Handles the CP_IRQ raised from the DP HDCP sink */ 2613 void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 2614 { 2615 struct intel_hdcp *hdcp = &connector->hdcp; 2616 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2617 2618 if (!hdcp->shim) 2619 return; 2620 2621 atomic_inc(&connector->hdcp.cp_irq_count); 2622 wake_up_all(&connector->hdcp.cp_irq_queue); 2623 2624 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 0); 2625 } 2626