1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * 5 * Authors: 6 * Sean Paul <seanpaul@chromium.org> 7 */ 8 9 #include <linux/component.h> 10 #include <linux/i2c.h> 11 #include <linux/random.h> 12 13 #include <drm/drm_hdcp.h> 14 #include <drm/i915_component.h> 15 16 #include "i915_reg.h" 17 #include "intel_drv.h" 18 #include "intel_hdcp.h" 19 #include "intel_sideband.h" 20 21 #define KEY_LOAD_TRIES 5 22 #define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50 23 #define HDCP2_LC_RETRY_CNT 3 24 25 static 26 bool intel_hdcp_is_ksv_valid(u8 *ksv) 27 { 28 int i, ones = 0; 29 /* KSV has 20 1's and 20 0's */ 30 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 31 ones += hweight8(ksv[i]); 32 if (ones != 20) 33 return false; 34 35 return true; 36 } 37 38 static 39 int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, 40 const struct intel_hdcp_shim *shim, u8 *bksv) 41 { 42 int ret, i, tries = 2; 43 44 /* HDCP spec states that we must retry the bksv if it is invalid */ 45 for (i = 0; i < tries; i++) { 46 ret = shim->read_bksv(intel_dig_port, bksv); 47 if (ret) 48 return ret; 49 if (intel_hdcp_is_ksv_valid(bksv)) 50 break; 51 } 52 if (i == tries) { 53 DRM_DEBUG_KMS("Bksv is invalid\n"); 54 return -ENODEV; 55 } 56 57 return 0; 58 } 59 60 /* Is HDCP1.4 capable on Platform and Sink */ 61 bool intel_hdcp_capable(struct intel_connector *connector) 62 { 63 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 64 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 65 bool capable = false; 66 u8 bksv[5]; 67 68 if (!shim) 69 return capable; 70 71 if (shim->hdcp_capable) { 72 shim->hdcp_capable(intel_dig_port, &capable); 73 } else { 74 if (!intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv)) 75 capable = true; 76 } 77 78 return capable; 79 } 80 81 /* Is HDCP2.2 capable on Platform and Sink */ 82 bool intel_hdcp2_capable(struct intel_connector *connector) 83 { 84 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 85 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 86 struct intel_hdcp *hdcp = &connector->hdcp; 87 bool capable = false; 88 89 /* I915 support for HDCP2.2 */ 90 if (!hdcp->hdcp2_supported) 91 return false; 92 93 /* MEI interface is solid */ 94 mutex_lock(&dev_priv->hdcp_comp_mutex); 95 if (!dev_priv->hdcp_comp_added || !dev_priv->hdcp_master) { 96 mutex_unlock(&dev_priv->hdcp_comp_mutex); 97 return false; 98 } 99 mutex_unlock(&dev_priv->hdcp_comp_mutex); 100 101 /* Sink's capability for HDCP2.2 */ 102 hdcp->shim->hdcp_2_2_capable(intel_dig_port, &capable); 103 104 return capable; 105 } 106 107 static inline bool intel_hdcp_in_use(struct intel_connector *connector) 108 { 109 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 110 enum port port = connector->encoder->port; 111 u32 reg; 112 113 reg = I915_READ(PORT_HDCP_STATUS(port)); 114 return reg & HDCP_STATUS_ENC; 115 } 116 117 static inline bool intel_hdcp2_in_use(struct intel_connector *connector) 118 { 119 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 120 enum port port = connector->encoder->port; 121 u32 reg; 122 123 reg = I915_READ(HDCP2_STATUS_DDI(port)); 124 return reg & LINK_ENCRYPTION_STATUS; 125 } 126 127 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port, 128 const struct intel_hdcp_shim *shim) 129 { 130 int ret, read_ret; 131 bool ksv_ready; 132 133 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 134 ret = __wait_for(read_ret = shim->read_ksv_ready(intel_dig_port, 135 &ksv_ready), 136 read_ret || ksv_ready, 5 * 1000 * 1000, 1000, 137 100 * 1000); 138 if (ret) 139 return ret; 140 if (read_ret) 141 return read_ret; 142 if (!ksv_ready) 143 return -ETIMEDOUT; 144 145 return 0; 146 } 147 148 static bool hdcp_key_loadable(struct drm_i915_private *dev_priv) 149 { 150 struct i915_power_domains *power_domains = &dev_priv->power_domains; 151 struct i915_power_well *power_well; 152 enum i915_power_well_id id; 153 bool enabled = false; 154 155 /* 156 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 157 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 158 */ 159 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 160 id = HSW_DISP_PW_GLOBAL; 161 else 162 id = SKL_DISP_PW_1; 163 164 mutex_lock(&power_domains->lock); 165 166 /* PG1 (power well #1) needs to be enabled */ 167 for_each_power_well(dev_priv, power_well) { 168 if (power_well->desc->id == id) { 169 enabled = power_well->desc->ops->is_enabled(dev_priv, 170 power_well); 171 break; 172 } 173 } 174 mutex_unlock(&power_domains->lock); 175 176 /* 177 * Another req for hdcp key loadability is enabled state of pll for 178 * cdclk. Without active crtc we wont land here. So we are assuming that 179 * cdclk is already on. 180 */ 181 182 return enabled; 183 } 184 185 static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv) 186 { 187 I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 188 I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | 189 HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 190 } 191 192 static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) 193 { 194 int ret; 195 u32 val; 196 197 val = I915_READ(HDCP_KEY_STATUS); 198 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 199 return 0; 200 201 /* 202 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 203 * out of reset. So if Key is not already loaded, its an error state. 204 */ 205 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 206 if (!(I915_READ(HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 207 return -ENXIO; 208 209 /* 210 * Initiate loading the HDCP key from fuses. 211 * 212 * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9 213 * platforms except BXT and GLK, differ in the key load trigger process 214 * from other platforms. So GEN9_BC uses the GT Driver Mailbox i/f. 215 */ 216 if (IS_GEN9_BC(dev_priv)) { 217 ret = sandybridge_pcode_write(dev_priv, 218 SKL_PCODE_LOAD_HDCP_KEYS, 1); 219 if (ret) { 220 DRM_ERROR("Failed to initiate HDCP key load (%d)\n", 221 ret); 222 return ret; 223 } 224 } else { 225 I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 226 } 227 228 /* Wait for the keys to load (500us) */ 229 ret = __intel_wait_for_register(&dev_priv->uncore, HDCP_KEY_STATUS, 230 HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, 231 10, 1, &val); 232 if (ret) 233 return ret; 234 else if (!(val & HDCP_KEY_LOAD_STATUS)) 235 return -ENXIO; 236 237 /* Send Aksv over to PCH display for use in authentication */ 238 I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 239 240 return 0; 241 } 242 243 /* Returns updated SHA-1 index */ 244 static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text) 245 { 246 I915_WRITE(HDCP_SHA_TEXT, sha_text); 247 if (intel_wait_for_register(&dev_priv->uncore, HDCP_REP_CTL, 248 HDCP_SHA1_READY, HDCP_SHA1_READY, 1)) { 249 DRM_ERROR("Timed out waiting for SHA1 ready\n"); 250 return -ETIMEDOUT; 251 } 252 return 0; 253 } 254 255 static 256 u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port) 257 { 258 enum port port = intel_dig_port->base.port; 259 switch (port) { 260 case PORT_A: 261 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 262 case PORT_B: 263 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 264 case PORT_C: 265 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 266 case PORT_D: 267 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 268 case PORT_E: 269 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 270 default: 271 break; 272 } 273 DRM_ERROR("Unknown port %d\n", port); 274 return -EINVAL; 275 } 276 277 static 278 int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port, 279 const struct intel_hdcp_shim *shim, 280 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 281 { 282 struct drm_i915_private *dev_priv; 283 u32 vprime, sha_text, sha_leftovers, rep_ctl; 284 int ret, i, j, sha_idx; 285 286 dev_priv = intel_dig_port->base.base.dev->dev_private; 287 288 /* Process V' values from the receiver */ 289 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 290 ret = shim->read_v_prime_part(intel_dig_port, i, &vprime); 291 if (ret) 292 return ret; 293 I915_WRITE(HDCP_SHA_V_PRIME(i), vprime); 294 } 295 296 /* 297 * We need to write the concatenation of all device KSVs, BINFO (DP) || 298 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 299 * stream is written via the HDCP_SHA_TEXT register in 32-bit 300 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 301 * index will keep track of our progress through the 64 bytes as well as 302 * helping us work the 40-bit KSVs through our 32-bit register. 303 * 304 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 305 */ 306 sha_idx = 0; 307 sha_text = 0; 308 sha_leftovers = 0; 309 rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port); 310 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 311 for (i = 0; i < num_downstream; i++) { 312 unsigned int sha_empty; 313 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 314 315 /* Fill up the empty slots in sha_text and write it out */ 316 sha_empty = sizeof(sha_text) - sha_leftovers; 317 for (j = 0; j < sha_empty; j++) 318 sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8); 319 320 ret = intel_write_sha_text(dev_priv, sha_text); 321 if (ret < 0) 322 return ret; 323 324 /* Programming guide writes this every 64 bytes */ 325 sha_idx += sizeof(sha_text); 326 if (!(sha_idx % 64)) 327 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 328 329 /* Store the leftover bytes from the ksv in sha_text */ 330 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 331 sha_text = 0; 332 for (j = 0; j < sha_leftovers; j++) 333 sha_text |= ksv[sha_empty + j] << 334 ((sizeof(sha_text) - j - 1) * 8); 335 336 /* 337 * If we still have room in sha_text for more data, continue. 338 * Otherwise, write it out immediately. 339 */ 340 if (sizeof(sha_text) > sha_leftovers) 341 continue; 342 343 ret = intel_write_sha_text(dev_priv, sha_text); 344 if (ret < 0) 345 return ret; 346 sha_leftovers = 0; 347 sha_text = 0; 348 sha_idx += sizeof(sha_text); 349 } 350 351 /* 352 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 353 * bytes are leftover from the last ksv, we might be able to fit them 354 * all in sha_text (first 2 cases), or we might need to split them up 355 * into 2 writes (last 2 cases). 356 */ 357 if (sha_leftovers == 0) { 358 /* Write 16 bits of text, 16 bits of M0 */ 359 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16); 360 ret = intel_write_sha_text(dev_priv, 361 bstatus[0] << 8 | bstatus[1]); 362 if (ret < 0) 363 return ret; 364 sha_idx += sizeof(sha_text); 365 366 /* Write 32 bits of M0 */ 367 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); 368 ret = intel_write_sha_text(dev_priv, 0); 369 if (ret < 0) 370 return ret; 371 sha_idx += sizeof(sha_text); 372 373 /* Write 16 bits of M0 */ 374 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16); 375 ret = intel_write_sha_text(dev_priv, 0); 376 if (ret < 0) 377 return ret; 378 sha_idx += sizeof(sha_text); 379 380 } else if (sha_leftovers == 1) { 381 /* Write 24 bits of text, 8 bits of M0 */ 382 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24); 383 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 384 /* Only 24-bits of data, must be in the LSB */ 385 sha_text = (sha_text & 0xffffff00) >> 8; 386 ret = intel_write_sha_text(dev_priv, sha_text); 387 if (ret < 0) 388 return ret; 389 sha_idx += sizeof(sha_text); 390 391 /* Write 32 bits of M0 */ 392 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); 393 ret = intel_write_sha_text(dev_priv, 0); 394 if (ret < 0) 395 return ret; 396 sha_idx += sizeof(sha_text); 397 398 /* Write 24 bits of M0 */ 399 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8); 400 ret = intel_write_sha_text(dev_priv, 0); 401 if (ret < 0) 402 return ret; 403 sha_idx += sizeof(sha_text); 404 405 } else if (sha_leftovers == 2) { 406 /* Write 32 bits of text */ 407 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 408 sha_text |= bstatus[0] << 24 | bstatus[1] << 16; 409 ret = intel_write_sha_text(dev_priv, sha_text); 410 if (ret < 0) 411 return ret; 412 sha_idx += sizeof(sha_text); 413 414 /* Write 64 bits of M0 */ 415 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); 416 for (i = 0; i < 2; i++) { 417 ret = intel_write_sha_text(dev_priv, 0); 418 if (ret < 0) 419 return ret; 420 sha_idx += sizeof(sha_text); 421 } 422 } else if (sha_leftovers == 3) { 423 /* Write 32 bits of text */ 424 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 425 sha_text |= bstatus[0] << 24; 426 ret = intel_write_sha_text(dev_priv, sha_text); 427 if (ret < 0) 428 return ret; 429 sha_idx += sizeof(sha_text); 430 431 /* Write 8 bits of text, 24 bits of M0 */ 432 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8); 433 ret = intel_write_sha_text(dev_priv, bstatus[1]); 434 if (ret < 0) 435 return ret; 436 sha_idx += sizeof(sha_text); 437 438 /* Write 32 bits of M0 */ 439 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); 440 ret = intel_write_sha_text(dev_priv, 0); 441 if (ret < 0) 442 return ret; 443 sha_idx += sizeof(sha_text); 444 445 /* Write 8 bits of M0 */ 446 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24); 447 ret = intel_write_sha_text(dev_priv, 0); 448 if (ret < 0) 449 return ret; 450 sha_idx += sizeof(sha_text); 451 } else { 452 DRM_DEBUG_KMS("Invalid number of leftovers %d\n", 453 sha_leftovers); 454 return -EINVAL; 455 } 456 457 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 458 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 459 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 460 ret = intel_write_sha_text(dev_priv, 0); 461 if (ret < 0) 462 return ret; 463 sha_idx += sizeof(sha_text); 464 } 465 466 /* 467 * Last write gets the length of the concatenation in bits. That is: 468 * - 5 bytes per device 469 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 470 */ 471 sha_text = (num_downstream * 5 + 10) * 8; 472 ret = intel_write_sha_text(dev_priv, sha_text); 473 if (ret < 0) 474 return ret; 475 476 /* Tell the HW we're done with the hash and wait for it to ACK */ 477 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_COMPLETE_HASH); 478 if (intel_wait_for_register(&dev_priv->uncore, HDCP_REP_CTL, 479 HDCP_SHA1_COMPLETE, 480 HDCP_SHA1_COMPLETE, 1)) { 481 DRM_ERROR("Timed out waiting for SHA1 complete\n"); 482 return -ETIMEDOUT; 483 } 484 if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 485 DRM_DEBUG_KMS("SHA-1 mismatch, HDCP failed\n"); 486 return -ENXIO; 487 } 488 489 return 0; 490 } 491 492 /* Implements Part 2 of the HDCP authorization procedure */ 493 static 494 int intel_hdcp_auth_downstream(struct intel_connector *connector) 495 { 496 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 497 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 498 struct drm_device *dev = connector->base.dev; 499 u8 bstatus[2], num_downstream, *ksv_fifo; 500 int ret, i, tries = 3; 501 502 ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim); 503 if (ret) { 504 DRM_DEBUG_KMS("KSV list failed to become ready (%d)\n", ret); 505 return ret; 506 } 507 508 ret = shim->read_bstatus(intel_dig_port, bstatus); 509 if (ret) 510 return ret; 511 512 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 513 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 514 DRM_DEBUG_KMS("Max Topology Limit Exceeded\n"); 515 return -EPERM; 516 } 517 518 /* 519 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 520 * the HDCP encryption. That implies that repeater can't have its own 521 * display. As there is no consumption of encrypted content in the 522 * repeater with 0 downstream devices, we are failing the 523 * authentication. 524 */ 525 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 526 if (num_downstream == 0) 527 return -EINVAL; 528 529 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 530 if (!ksv_fifo) 531 return -ENOMEM; 532 533 ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo); 534 if (ret) 535 goto err; 536 537 if (drm_hdcp_check_ksvs_revoked(dev, ksv_fifo, num_downstream)) { 538 DRM_ERROR("Revoked Ksv(s) in ksv_fifo\n"); 539 return -EPERM; 540 } 541 542 /* 543 * When V prime mismatches, DP Spec mandates re-read of 544 * V prime atleast twice. 545 */ 546 for (i = 0; i < tries; i++) { 547 ret = intel_hdcp_validate_v_prime(intel_dig_port, shim, 548 ksv_fifo, num_downstream, 549 bstatus); 550 if (!ret) 551 break; 552 } 553 554 if (i == tries) { 555 DRM_DEBUG_KMS("V Prime validation failed.(%d)\n", ret); 556 goto err; 557 } 558 559 DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n", 560 num_downstream); 561 ret = 0; 562 err: 563 kfree(ksv_fifo); 564 return ret; 565 } 566 567 /* Implements Part 1 of the HDCP authorization procedure */ 568 static int intel_hdcp_auth(struct intel_connector *connector) 569 { 570 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 571 struct intel_hdcp *hdcp = &connector->hdcp; 572 struct drm_device *dev = connector->base.dev; 573 const struct intel_hdcp_shim *shim = hdcp->shim; 574 struct drm_i915_private *dev_priv; 575 enum port port; 576 unsigned long r0_prime_gen_start; 577 int ret, i, tries = 2; 578 union { 579 u32 reg[2]; 580 u8 shim[DRM_HDCP_AN_LEN]; 581 } an; 582 union { 583 u32 reg[2]; 584 u8 shim[DRM_HDCP_KSV_LEN]; 585 } bksv; 586 union { 587 u32 reg; 588 u8 shim[DRM_HDCP_RI_LEN]; 589 } ri; 590 bool repeater_present, hdcp_capable; 591 592 dev_priv = intel_dig_port->base.base.dev->dev_private; 593 594 port = intel_dig_port->base.port; 595 596 /* 597 * Detects whether the display is HDCP capable. Although we check for 598 * valid Bksv below, the HDCP over DP spec requires that we check 599 * whether the display supports HDCP before we write An. For HDMI 600 * displays, this is not necessary. 601 */ 602 if (shim->hdcp_capable) { 603 ret = shim->hdcp_capable(intel_dig_port, &hdcp_capable); 604 if (ret) 605 return ret; 606 if (!hdcp_capable) { 607 DRM_DEBUG_KMS("Panel is not HDCP capable\n"); 608 return -EINVAL; 609 } 610 } 611 612 /* Initialize An with 2 random values and acquire it */ 613 for (i = 0; i < 2; i++) 614 I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32()); 615 I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN); 616 617 /* Wait for An to be acquired */ 618 if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port), 619 HDCP_STATUS_AN_READY, 620 HDCP_STATUS_AN_READY, 1)) { 621 DRM_ERROR("Timed out waiting for An\n"); 622 return -ETIMEDOUT; 623 } 624 625 an.reg[0] = I915_READ(PORT_HDCP_ANLO(port)); 626 an.reg[1] = I915_READ(PORT_HDCP_ANHI(port)); 627 ret = shim->write_an_aksv(intel_dig_port, an.shim); 628 if (ret) 629 return ret; 630 631 r0_prime_gen_start = jiffies; 632 633 memset(&bksv, 0, sizeof(bksv)); 634 635 ret = intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv.shim); 636 if (ret < 0) 637 return ret; 638 639 if (drm_hdcp_check_ksvs_revoked(dev, bksv.shim, 1)) { 640 DRM_ERROR("BKSV is revoked\n"); 641 return -EPERM; 642 } 643 644 I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]); 645 I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]); 646 647 ret = shim->repeater_present(intel_dig_port, &repeater_present); 648 if (ret) 649 return ret; 650 if (repeater_present) 651 I915_WRITE(HDCP_REP_CTL, 652 intel_hdcp_get_repeater_ctl(intel_dig_port)); 653 654 ret = shim->toggle_signalling(intel_dig_port, true); 655 if (ret) 656 return ret; 657 658 I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC); 659 660 /* Wait for R0 ready */ 661 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & 662 (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) { 663 DRM_ERROR("Timed out waiting for R0 ready\n"); 664 return -ETIMEDOUT; 665 } 666 667 /* 668 * Wait for R0' to become available. The spec says 100ms from Aksv, but 669 * some monitors can take longer than this. We'll set the timeout at 670 * 300ms just to be sure. 671 * 672 * On DP, there's an R0_READY bit available but no such bit 673 * exists on HDMI. Since the upper-bound is the same, we'll just do 674 * the stupid thing instead of polling on one and not the other. 675 */ 676 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 677 678 tries = 3; 679 680 /* 681 * DP HDCP Spec mandates the two more reattempt to read R0, incase 682 * of R0 mismatch. 683 */ 684 for (i = 0; i < tries; i++) { 685 ri.reg = 0; 686 ret = shim->read_ri_prime(intel_dig_port, ri.shim); 687 if (ret) 688 return ret; 689 I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); 690 691 /* Wait for Ri prime match */ 692 if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) & 693 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) 694 break; 695 } 696 697 if (i == tries) { 698 DRM_DEBUG_KMS("Timed out waiting for Ri prime match (%x)\n", 699 I915_READ(PORT_HDCP_STATUS(port))); 700 return -ETIMEDOUT; 701 } 702 703 /* Wait for encryption confirmation */ 704 if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port), 705 HDCP_STATUS_ENC, HDCP_STATUS_ENC, 706 ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 707 DRM_ERROR("Timed out waiting for encryption\n"); 708 return -ETIMEDOUT; 709 } 710 711 /* 712 * XXX: If we have MST-connected devices, we need to enable encryption 713 * on those as well. 714 */ 715 716 if (repeater_present) 717 return intel_hdcp_auth_downstream(connector); 718 719 DRM_DEBUG_KMS("HDCP is enabled (no repeater present)\n"); 720 return 0; 721 } 722 723 static int _intel_hdcp_disable(struct intel_connector *connector) 724 { 725 struct intel_hdcp *hdcp = &connector->hdcp; 726 struct drm_i915_private *dev_priv = connector->base.dev->dev_private; 727 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 728 enum port port = intel_dig_port->base.port; 729 int ret; 730 731 DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n", 732 connector->base.name, connector->base.base.id); 733 734 hdcp->hdcp_encrypted = false; 735 I915_WRITE(PORT_HDCP_CONF(port), 0); 736 if (intel_wait_for_register(&dev_priv->uncore, 737 PORT_HDCP_STATUS(port), ~0, 0, 738 ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 739 DRM_ERROR("Failed to disable HDCP, timeout clearing status\n"); 740 return -ETIMEDOUT; 741 } 742 743 ret = hdcp->shim->toggle_signalling(intel_dig_port, false); 744 if (ret) { 745 DRM_ERROR("Failed to disable HDCP signalling\n"); 746 return ret; 747 } 748 749 DRM_DEBUG_KMS("HDCP is disabled\n"); 750 return 0; 751 } 752 753 static int _intel_hdcp_enable(struct intel_connector *connector) 754 { 755 struct intel_hdcp *hdcp = &connector->hdcp; 756 struct drm_i915_private *dev_priv = connector->base.dev->dev_private; 757 int i, ret, tries = 3; 758 759 DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n", 760 connector->base.name, connector->base.base.id); 761 762 if (!hdcp_key_loadable(dev_priv)) { 763 DRM_ERROR("HDCP key Load is not possible\n"); 764 return -ENXIO; 765 } 766 767 for (i = 0; i < KEY_LOAD_TRIES; i++) { 768 ret = intel_hdcp_load_keys(dev_priv); 769 if (!ret) 770 break; 771 intel_hdcp_clear_keys(dev_priv); 772 } 773 if (ret) { 774 DRM_ERROR("Could not load HDCP keys, (%d)\n", ret); 775 return ret; 776 } 777 778 /* Incase of authentication failures, HDCP spec expects reauth. */ 779 for (i = 0; i < tries; i++) { 780 ret = intel_hdcp_auth(connector); 781 if (!ret) { 782 hdcp->hdcp_encrypted = true; 783 return 0; 784 } 785 786 DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret); 787 788 /* Ensuring HDCP encryption and signalling are stopped. */ 789 _intel_hdcp_disable(connector); 790 } 791 792 DRM_DEBUG_KMS("HDCP authentication failed (%d tries/%d)\n", tries, ret); 793 return ret; 794 } 795 796 static inline 797 struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 798 { 799 return container_of(hdcp, struct intel_connector, hdcp); 800 } 801 802 /* Implements Part 3 of the HDCP authorization procedure */ 803 static int intel_hdcp_check_link(struct intel_connector *connector) 804 { 805 struct intel_hdcp *hdcp = &connector->hdcp; 806 struct drm_i915_private *dev_priv = connector->base.dev->dev_private; 807 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 808 enum port port = intel_dig_port->base.port; 809 int ret = 0; 810 811 mutex_lock(&hdcp->mutex); 812 813 /* Check_link valid only when HDCP1.4 is enabled */ 814 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 815 !hdcp->hdcp_encrypted) { 816 ret = -EINVAL; 817 goto out; 818 } 819 820 if (WARN_ON(!intel_hdcp_in_use(connector))) { 821 DRM_ERROR("%s:%d HDCP link stopped encryption,%x\n", 822 connector->base.name, connector->base.base.id, 823 I915_READ(PORT_HDCP_STATUS(port))); 824 ret = -ENXIO; 825 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 826 schedule_work(&hdcp->prop_work); 827 goto out; 828 } 829 830 if (hdcp->shim->check_link(intel_dig_port)) { 831 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 832 hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; 833 schedule_work(&hdcp->prop_work); 834 } 835 goto out; 836 } 837 838 DRM_DEBUG_KMS("[%s:%d] HDCP link failed, retrying authentication\n", 839 connector->base.name, connector->base.base.id); 840 841 ret = _intel_hdcp_disable(connector); 842 if (ret) { 843 DRM_ERROR("Failed to disable hdcp (%d)\n", ret); 844 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 845 schedule_work(&hdcp->prop_work); 846 goto out; 847 } 848 849 ret = _intel_hdcp_enable(connector); 850 if (ret) { 851 DRM_ERROR("Failed to enable hdcp (%d)\n", ret); 852 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 853 schedule_work(&hdcp->prop_work); 854 goto out; 855 } 856 857 out: 858 mutex_unlock(&hdcp->mutex); 859 return ret; 860 } 861 862 static void intel_hdcp_prop_work(struct work_struct *work) 863 { 864 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 865 prop_work); 866 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 867 struct drm_device *dev = connector->base.dev; 868 struct drm_connector_state *state; 869 870 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 871 mutex_lock(&hdcp->mutex); 872 873 /* 874 * This worker is only used to flip between ENABLED/DESIRED. Either of 875 * those to UNDESIRED is handled by core. If value == UNDESIRED, 876 * we're running just after hdcp has been disabled, so just exit 877 */ 878 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 879 state = connector->base.state; 880 state->content_protection = hdcp->value; 881 } 882 883 mutex_unlock(&hdcp->mutex); 884 drm_modeset_unlock(&dev->mode_config.connection_mutex); 885 } 886 887 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port) 888 { 889 /* PORT E doesn't have HDCP, and PORT F is disabled */ 890 return INTEL_GEN(dev_priv) >= 9 && port < PORT_E; 891 } 892 893 static int 894 hdcp2_prepare_ake_init(struct intel_connector *connector, 895 struct hdcp2_ake_init *ake_data) 896 { 897 struct hdcp_port_data *data = &connector->hdcp.port_data; 898 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 899 struct i915_hdcp_comp_master *comp; 900 int ret; 901 902 mutex_lock(&dev_priv->hdcp_comp_mutex); 903 comp = dev_priv->hdcp_master; 904 905 if (!comp || !comp->ops) { 906 mutex_unlock(&dev_priv->hdcp_comp_mutex); 907 return -EINVAL; 908 } 909 910 ret = comp->ops->initiate_hdcp2_session(comp->mei_dev, data, ake_data); 911 if (ret) 912 DRM_DEBUG_KMS("Prepare_ake_init failed. %d\n", ret); 913 mutex_unlock(&dev_priv->hdcp_comp_mutex); 914 915 return ret; 916 } 917 918 static int 919 hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 920 struct hdcp2_ake_send_cert *rx_cert, 921 bool *paired, 922 struct hdcp2_ake_no_stored_km *ek_pub_km, 923 size_t *msg_sz) 924 { 925 struct hdcp_port_data *data = &connector->hdcp.port_data; 926 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 927 struct i915_hdcp_comp_master *comp; 928 int ret; 929 930 mutex_lock(&dev_priv->hdcp_comp_mutex); 931 comp = dev_priv->hdcp_master; 932 933 if (!comp || !comp->ops) { 934 mutex_unlock(&dev_priv->hdcp_comp_mutex); 935 return -EINVAL; 936 } 937 938 ret = comp->ops->verify_receiver_cert_prepare_km(comp->mei_dev, data, 939 rx_cert, paired, 940 ek_pub_km, msg_sz); 941 if (ret < 0) 942 DRM_DEBUG_KMS("Verify rx_cert failed. %d\n", ret); 943 mutex_unlock(&dev_priv->hdcp_comp_mutex); 944 945 return ret; 946 } 947 948 static int hdcp2_verify_hprime(struct intel_connector *connector, 949 struct hdcp2_ake_send_hprime *rx_hprime) 950 { 951 struct hdcp_port_data *data = &connector->hdcp.port_data; 952 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 953 struct i915_hdcp_comp_master *comp; 954 int ret; 955 956 mutex_lock(&dev_priv->hdcp_comp_mutex); 957 comp = dev_priv->hdcp_master; 958 959 if (!comp || !comp->ops) { 960 mutex_unlock(&dev_priv->hdcp_comp_mutex); 961 return -EINVAL; 962 } 963 964 ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime); 965 if (ret < 0) 966 DRM_DEBUG_KMS("Verify hprime failed. %d\n", ret); 967 mutex_unlock(&dev_priv->hdcp_comp_mutex); 968 969 return ret; 970 } 971 972 static int 973 hdcp2_store_pairing_info(struct intel_connector *connector, 974 struct hdcp2_ake_send_pairing_info *pairing_info) 975 { 976 struct hdcp_port_data *data = &connector->hdcp.port_data; 977 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 978 struct i915_hdcp_comp_master *comp; 979 int ret; 980 981 mutex_lock(&dev_priv->hdcp_comp_mutex); 982 comp = dev_priv->hdcp_master; 983 984 if (!comp || !comp->ops) { 985 mutex_unlock(&dev_priv->hdcp_comp_mutex); 986 return -EINVAL; 987 } 988 989 ret = comp->ops->store_pairing_info(comp->mei_dev, data, pairing_info); 990 if (ret < 0) 991 DRM_DEBUG_KMS("Store pairing info failed. %d\n", ret); 992 mutex_unlock(&dev_priv->hdcp_comp_mutex); 993 994 return ret; 995 } 996 997 static int 998 hdcp2_prepare_lc_init(struct intel_connector *connector, 999 struct hdcp2_lc_init *lc_init) 1000 { 1001 struct hdcp_port_data *data = &connector->hdcp.port_data; 1002 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1003 struct i915_hdcp_comp_master *comp; 1004 int ret; 1005 1006 mutex_lock(&dev_priv->hdcp_comp_mutex); 1007 comp = dev_priv->hdcp_master; 1008 1009 if (!comp || !comp->ops) { 1010 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1011 return -EINVAL; 1012 } 1013 1014 ret = comp->ops->initiate_locality_check(comp->mei_dev, data, lc_init); 1015 if (ret < 0) 1016 DRM_DEBUG_KMS("Prepare lc_init failed. %d\n", ret); 1017 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1018 1019 return ret; 1020 } 1021 1022 static int 1023 hdcp2_verify_lprime(struct intel_connector *connector, 1024 struct hdcp2_lc_send_lprime *rx_lprime) 1025 { 1026 struct hdcp_port_data *data = &connector->hdcp.port_data; 1027 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1028 struct i915_hdcp_comp_master *comp; 1029 int ret; 1030 1031 mutex_lock(&dev_priv->hdcp_comp_mutex); 1032 comp = dev_priv->hdcp_master; 1033 1034 if (!comp || !comp->ops) { 1035 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1036 return -EINVAL; 1037 } 1038 1039 ret = comp->ops->verify_lprime(comp->mei_dev, data, rx_lprime); 1040 if (ret < 0) 1041 DRM_DEBUG_KMS("Verify L_Prime failed. %d\n", ret); 1042 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1043 1044 return ret; 1045 } 1046 1047 static int hdcp2_prepare_skey(struct intel_connector *connector, 1048 struct hdcp2_ske_send_eks *ske_data) 1049 { 1050 struct hdcp_port_data *data = &connector->hdcp.port_data; 1051 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1052 struct i915_hdcp_comp_master *comp; 1053 int ret; 1054 1055 mutex_lock(&dev_priv->hdcp_comp_mutex); 1056 comp = dev_priv->hdcp_master; 1057 1058 if (!comp || !comp->ops) { 1059 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1060 return -EINVAL; 1061 } 1062 1063 ret = comp->ops->get_session_key(comp->mei_dev, data, ske_data); 1064 if (ret < 0) 1065 DRM_DEBUG_KMS("Get session key failed. %d\n", ret); 1066 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1067 1068 return ret; 1069 } 1070 1071 static int 1072 hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1073 struct hdcp2_rep_send_receiverid_list 1074 *rep_topology, 1075 struct hdcp2_rep_send_ack *rep_send_ack) 1076 { 1077 struct hdcp_port_data *data = &connector->hdcp.port_data; 1078 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1079 struct i915_hdcp_comp_master *comp; 1080 int ret; 1081 1082 mutex_lock(&dev_priv->hdcp_comp_mutex); 1083 comp = dev_priv->hdcp_master; 1084 1085 if (!comp || !comp->ops) { 1086 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1087 return -EINVAL; 1088 } 1089 1090 ret = comp->ops->repeater_check_flow_prepare_ack(comp->mei_dev, data, 1091 rep_topology, 1092 rep_send_ack); 1093 if (ret < 0) 1094 DRM_DEBUG_KMS("Verify rep topology failed. %d\n", ret); 1095 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1096 1097 return ret; 1098 } 1099 1100 static int 1101 hdcp2_verify_mprime(struct intel_connector *connector, 1102 struct hdcp2_rep_stream_ready *stream_ready) 1103 { 1104 struct hdcp_port_data *data = &connector->hdcp.port_data; 1105 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1106 struct i915_hdcp_comp_master *comp; 1107 int ret; 1108 1109 mutex_lock(&dev_priv->hdcp_comp_mutex); 1110 comp = dev_priv->hdcp_master; 1111 1112 if (!comp || !comp->ops) { 1113 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1114 return -EINVAL; 1115 } 1116 1117 ret = comp->ops->verify_mprime(comp->mei_dev, data, stream_ready); 1118 if (ret < 0) 1119 DRM_DEBUG_KMS("Verify mprime failed. %d\n", ret); 1120 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1121 1122 return ret; 1123 } 1124 1125 static int hdcp2_authenticate_port(struct intel_connector *connector) 1126 { 1127 struct hdcp_port_data *data = &connector->hdcp.port_data; 1128 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1129 struct i915_hdcp_comp_master *comp; 1130 int ret; 1131 1132 mutex_lock(&dev_priv->hdcp_comp_mutex); 1133 comp = dev_priv->hdcp_master; 1134 1135 if (!comp || !comp->ops) { 1136 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1137 return -EINVAL; 1138 } 1139 1140 ret = comp->ops->enable_hdcp_authentication(comp->mei_dev, data); 1141 if (ret < 0) 1142 DRM_DEBUG_KMS("Enable hdcp auth failed. %d\n", ret); 1143 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1144 1145 return ret; 1146 } 1147 1148 static int hdcp2_close_mei_session(struct intel_connector *connector) 1149 { 1150 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1151 struct i915_hdcp_comp_master *comp; 1152 int ret; 1153 1154 mutex_lock(&dev_priv->hdcp_comp_mutex); 1155 comp = dev_priv->hdcp_master; 1156 1157 if (!comp || !comp->ops) { 1158 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1159 return -EINVAL; 1160 } 1161 1162 ret = comp->ops->close_hdcp_session(comp->mei_dev, 1163 &connector->hdcp.port_data); 1164 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1165 1166 return ret; 1167 } 1168 1169 static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1170 { 1171 return hdcp2_close_mei_session(connector); 1172 } 1173 1174 /* Authentication flow starts from here */ 1175 static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1176 { 1177 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1178 struct intel_hdcp *hdcp = &connector->hdcp; 1179 struct drm_device *dev = connector->base.dev; 1180 union { 1181 struct hdcp2_ake_init ake_init; 1182 struct hdcp2_ake_send_cert send_cert; 1183 struct hdcp2_ake_no_stored_km no_stored_km; 1184 struct hdcp2_ake_send_hprime send_hprime; 1185 struct hdcp2_ake_send_pairing_info pairing_info; 1186 } msgs; 1187 const struct intel_hdcp_shim *shim = hdcp->shim; 1188 size_t size; 1189 int ret; 1190 1191 /* Init for seq_num */ 1192 hdcp->seq_num_v = 0; 1193 hdcp->seq_num_m = 0; 1194 1195 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1196 if (ret < 0) 1197 return ret; 1198 1199 ret = shim->write_2_2_msg(intel_dig_port, &msgs.ake_init, 1200 sizeof(msgs.ake_init)); 1201 if (ret < 0) 1202 return ret; 1203 1204 ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_CERT, 1205 &msgs.send_cert, sizeof(msgs.send_cert)); 1206 if (ret < 0) 1207 return ret; 1208 1209 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) 1210 return -EINVAL; 1211 1212 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1213 1214 if (drm_hdcp_check_ksvs_revoked(dev, msgs.send_cert.cert_rx.receiver_id, 1215 1)) { 1216 DRM_ERROR("Receiver ID is revoked\n"); 1217 return -EPERM; 1218 } 1219 1220 /* 1221 * Here msgs.no_stored_km will hold msgs corresponding to the km 1222 * stored also. 1223 */ 1224 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1225 &hdcp->is_paired, 1226 &msgs.no_stored_km, &size); 1227 if (ret < 0) 1228 return ret; 1229 1230 ret = shim->write_2_2_msg(intel_dig_port, &msgs.no_stored_km, size); 1231 if (ret < 0) 1232 return ret; 1233 1234 ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_HPRIME, 1235 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1236 if (ret < 0) 1237 return ret; 1238 1239 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1240 if (ret < 0) 1241 return ret; 1242 1243 if (!hdcp->is_paired) { 1244 /* Pairing is required */ 1245 ret = shim->read_2_2_msg(intel_dig_port, 1246 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1247 &msgs.pairing_info, 1248 sizeof(msgs.pairing_info)); 1249 if (ret < 0) 1250 return ret; 1251 1252 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1253 if (ret < 0) 1254 return ret; 1255 hdcp->is_paired = true; 1256 } 1257 1258 return 0; 1259 } 1260 1261 static int hdcp2_locality_check(struct intel_connector *connector) 1262 { 1263 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1264 struct intel_hdcp *hdcp = &connector->hdcp; 1265 union { 1266 struct hdcp2_lc_init lc_init; 1267 struct hdcp2_lc_send_lprime send_lprime; 1268 } msgs; 1269 const struct intel_hdcp_shim *shim = hdcp->shim; 1270 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1271 1272 for (i = 0; i < tries; i++) { 1273 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1274 if (ret < 0) 1275 continue; 1276 1277 ret = shim->write_2_2_msg(intel_dig_port, &msgs.lc_init, 1278 sizeof(msgs.lc_init)); 1279 if (ret < 0) 1280 continue; 1281 1282 ret = shim->read_2_2_msg(intel_dig_port, 1283 HDCP_2_2_LC_SEND_LPRIME, 1284 &msgs.send_lprime, 1285 sizeof(msgs.send_lprime)); 1286 if (ret < 0) 1287 continue; 1288 1289 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1290 if (!ret) 1291 break; 1292 } 1293 1294 return ret; 1295 } 1296 1297 static int hdcp2_session_key_exchange(struct intel_connector *connector) 1298 { 1299 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1300 struct intel_hdcp *hdcp = &connector->hdcp; 1301 struct hdcp2_ske_send_eks send_eks; 1302 int ret; 1303 1304 ret = hdcp2_prepare_skey(connector, &send_eks); 1305 if (ret < 0) 1306 return ret; 1307 1308 ret = hdcp->shim->write_2_2_msg(intel_dig_port, &send_eks, 1309 sizeof(send_eks)); 1310 if (ret < 0) 1311 return ret; 1312 1313 return 0; 1314 } 1315 1316 static 1317 int hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1318 { 1319 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1320 struct intel_hdcp *hdcp = &connector->hdcp; 1321 union { 1322 struct hdcp2_rep_stream_manage stream_manage; 1323 struct hdcp2_rep_stream_ready stream_ready; 1324 } msgs; 1325 const struct intel_hdcp_shim *shim = hdcp->shim; 1326 int ret; 1327 1328 /* Prepare RepeaterAuth_Stream_Manage msg */ 1329 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1330 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1331 1332 /* K no of streams is fixed as 1. Stored as big-endian. */ 1333 msgs.stream_manage.k = cpu_to_be16(1); 1334 1335 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 1336 msgs.stream_manage.streams[0].stream_id = 0; 1337 msgs.stream_manage.streams[0].stream_type = hdcp->content_type; 1338 1339 /* Send it to Repeater */ 1340 ret = shim->write_2_2_msg(intel_dig_port, &msgs.stream_manage, 1341 sizeof(msgs.stream_manage)); 1342 if (ret < 0) 1343 return ret; 1344 1345 ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_STREAM_READY, 1346 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1347 if (ret < 0) 1348 return ret; 1349 1350 hdcp->port_data.seq_num_m = hdcp->seq_num_m; 1351 hdcp->port_data.streams[0].stream_type = hdcp->content_type; 1352 1353 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1354 if (ret < 0) 1355 return ret; 1356 1357 hdcp->seq_num_m++; 1358 1359 if (hdcp->seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 1360 DRM_DEBUG_KMS("seq_num_m roll over.\n"); 1361 return -1; 1362 } 1363 1364 return 0; 1365 } 1366 1367 static 1368 int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1369 { 1370 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1371 struct intel_hdcp *hdcp = &connector->hdcp; 1372 struct drm_device *dev = connector->base.dev; 1373 union { 1374 struct hdcp2_rep_send_receiverid_list recvid_list; 1375 struct hdcp2_rep_send_ack rep_ack; 1376 } msgs; 1377 const struct intel_hdcp_shim *shim = hdcp->shim; 1378 u32 seq_num_v, device_cnt; 1379 u8 *rx_info; 1380 int ret; 1381 1382 ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_SEND_RECVID_LIST, 1383 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1384 if (ret < 0) 1385 return ret; 1386 1387 rx_info = msgs.recvid_list.rx_info; 1388 1389 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1390 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1391 DRM_DEBUG_KMS("Topology Max Size Exceeded\n"); 1392 return -EINVAL; 1393 } 1394 1395 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1396 seq_num_v = 1397 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1398 1399 if (seq_num_v < hdcp->seq_num_v) { 1400 /* Roll over of the seq_num_v from repeater. Reauthenticate. */ 1401 DRM_DEBUG_KMS("Seq_num_v roll over.\n"); 1402 return -EINVAL; 1403 } 1404 1405 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1406 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1407 if (drm_hdcp_check_ksvs_revoked(dev, msgs.recvid_list.receiver_ids, 1408 device_cnt)) { 1409 DRM_ERROR("Revoked receiver ID(s) is in list\n"); 1410 return -EPERM; 1411 } 1412 1413 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1414 &msgs.recvid_list, 1415 &msgs.rep_ack); 1416 if (ret < 0) 1417 return ret; 1418 1419 hdcp->seq_num_v = seq_num_v; 1420 ret = shim->write_2_2_msg(intel_dig_port, &msgs.rep_ack, 1421 sizeof(msgs.rep_ack)); 1422 if (ret < 0) 1423 return ret; 1424 1425 return 0; 1426 } 1427 1428 static int hdcp2_authenticate_repeater(struct intel_connector *connector) 1429 { 1430 int ret; 1431 1432 ret = hdcp2_authenticate_repeater_topology(connector); 1433 if (ret < 0) 1434 return ret; 1435 1436 return hdcp2_propagate_stream_management_info(connector); 1437 } 1438 1439 static int hdcp2_authenticate_sink(struct intel_connector *connector) 1440 { 1441 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1442 struct intel_hdcp *hdcp = &connector->hdcp; 1443 const struct intel_hdcp_shim *shim = hdcp->shim; 1444 int ret; 1445 1446 ret = hdcp2_authentication_key_exchange(connector); 1447 if (ret < 0) { 1448 DRM_DEBUG_KMS("AKE Failed. Err : %d\n", ret); 1449 return ret; 1450 } 1451 1452 ret = hdcp2_locality_check(connector); 1453 if (ret < 0) { 1454 DRM_DEBUG_KMS("Locality Check failed. Err : %d\n", ret); 1455 return ret; 1456 } 1457 1458 ret = hdcp2_session_key_exchange(connector); 1459 if (ret < 0) { 1460 DRM_DEBUG_KMS("SKE Failed. Err : %d\n", ret); 1461 return ret; 1462 } 1463 1464 if (shim->config_stream_type) { 1465 ret = shim->config_stream_type(intel_dig_port, 1466 hdcp->is_repeater, 1467 hdcp->content_type); 1468 if (ret < 0) 1469 return ret; 1470 } 1471 1472 if (hdcp->is_repeater) { 1473 ret = hdcp2_authenticate_repeater(connector); 1474 if (ret < 0) { 1475 DRM_DEBUG_KMS("Repeater Auth Failed. Err: %d\n", ret); 1476 return ret; 1477 } 1478 } 1479 1480 hdcp->port_data.streams[0].stream_type = hdcp->content_type; 1481 ret = hdcp2_authenticate_port(connector); 1482 if (ret < 0) 1483 return ret; 1484 1485 return ret; 1486 } 1487 1488 static int hdcp2_enable_encryption(struct intel_connector *connector) 1489 { 1490 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1491 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1492 struct intel_hdcp *hdcp = &connector->hdcp; 1493 enum port port = connector->encoder->port; 1494 int ret; 1495 1496 WARN_ON(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS); 1497 1498 if (hdcp->shim->toggle_signalling) { 1499 ret = hdcp->shim->toggle_signalling(intel_dig_port, true); 1500 if (ret) { 1501 DRM_ERROR("Failed to enable HDCP signalling. %d\n", 1502 ret); 1503 return ret; 1504 } 1505 } 1506 1507 if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) { 1508 /* Link is Authenticated. Now set for Encryption */ 1509 I915_WRITE(HDCP2_CTL_DDI(port), 1510 I915_READ(HDCP2_CTL_DDI(port)) | 1511 CTL_LINK_ENCRYPTION_REQ); 1512 } 1513 1514 ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port), 1515 LINK_ENCRYPTION_STATUS, 1516 LINK_ENCRYPTION_STATUS, 1517 ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1518 1519 return ret; 1520 } 1521 1522 static int hdcp2_disable_encryption(struct intel_connector *connector) 1523 { 1524 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1525 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1526 struct intel_hdcp *hdcp = &connector->hdcp; 1527 enum port port = connector->encoder->port; 1528 int ret; 1529 1530 WARN_ON(!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS)); 1531 1532 I915_WRITE(HDCP2_CTL_DDI(port), 1533 I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ); 1534 1535 ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port), 1536 LINK_ENCRYPTION_STATUS, 0x0, 1537 ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1538 if (ret == -ETIMEDOUT) 1539 DRM_DEBUG_KMS("Disable Encryption Timedout"); 1540 1541 if (hdcp->shim->toggle_signalling) { 1542 ret = hdcp->shim->toggle_signalling(intel_dig_port, false); 1543 if (ret) { 1544 DRM_ERROR("Failed to disable HDCP signalling. %d\n", 1545 ret); 1546 return ret; 1547 } 1548 } 1549 1550 return ret; 1551 } 1552 1553 static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector) 1554 { 1555 int ret, i, tries = 3; 1556 1557 for (i = 0; i < tries; i++) { 1558 ret = hdcp2_authenticate_sink(connector); 1559 if (!ret) 1560 break; 1561 1562 /* Clearing the mei hdcp session */ 1563 DRM_DEBUG_KMS("HDCP2.2 Auth %d of %d Failed.(%d)\n", 1564 i + 1, tries, ret); 1565 if (hdcp2_deauthenticate_port(connector) < 0) 1566 DRM_DEBUG_KMS("Port deauth failed.\n"); 1567 } 1568 1569 if (i != tries) { 1570 /* 1571 * Ensuring the required 200mSec min time interval between 1572 * Session Key Exchange and encryption. 1573 */ 1574 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 1575 ret = hdcp2_enable_encryption(connector); 1576 if (ret < 0) { 1577 DRM_DEBUG_KMS("Encryption Enable Failed.(%d)\n", ret); 1578 if (hdcp2_deauthenticate_port(connector) < 0) 1579 DRM_DEBUG_KMS("Port deauth failed.\n"); 1580 } 1581 } 1582 1583 return ret; 1584 } 1585 1586 static int _intel_hdcp2_enable(struct intel_connector *connector) 1587 { 1588 struct intel_hdcp *hdcp = &connector->hdcp; 1589 int ret; 1590 1591 DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being enabled. Type: %d\n", 1592 connector->base.name, connector->base.base.id, 1593 hdcp->content_type); 1594 1595 ret = hdcp2_authenticate_and_encrypt(connector); 1596 if (ret) { 1597 DRM_DEBUG_KMS("HDCP2 Type%d Enabling Failed. (%d)\n", 1598 hdcp->content_type, ret); 1599 return ret; 1600 } 1601 1602 DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is enabled. Type %d\n", 1603 connector->base.name, connector->base.base.id, 1604 hdcp->content_type); 1605 1606 hdcp->hdcp2_encrypted = true; 1607 return 0; 1608 } 1609 1610 static int _intel_hdcp2_disable(struct intel_connector *connector) 1611 { 1612 int ret; 1613 1614 DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being Disabled\n", 1615 connector->base.name, connector->base.base.id); 1616 1617 ret = hdcp2_disable_encryption(connector); 1618 1619 if (hdcp2_deauthenticate_port(connector) < 0) 1620 DRM_DEBUG_KMS("Port deauth failed.\n"); 1621 1622 connector->hdcp.hdcp2_encrypted = false; 1623 1624 return ret; 1625 } 1626 1627 /* Implements the Link Integrity Check for HDCP2.2 */ 1628 static int intel_hdcp2_check_link(struct intel_connector *connector) 1629 { 1630 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); 1631 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1632 struct intel_hdcp *hdcp = &connector->hdcp; 1633 enum port port = connector->encoder->port; 1634 int ret = 0; 1635 1636 mutex_lock(&hdcp->mutex); 1637 1638 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 1639 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1640 !hdcp->hdcp2_encrypted) { 1641 ret = -EINVAL; 1642 goto out; 1643 } 1644 1645 if (WARN_ON(!intel_hdcp2_in_use(connector))) { 1646 DRM_ERROR("HDCP2.2 link stopped the encryption, %x\n", 1647 I915_READ(HDCP2_STATUS_DDI(port))); 1648 ret = -ENXIO; 1649 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 1650 schedule_work(&hdcp->prop_work); 1651 goto out; 1652 } 1653 1654 ret = hdcp->shim->check_2_2_link(intel_dig_port); 1655 if (ret == HDCP_LINK_PROTECTED) { 1656 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1657 hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; 1658 schedule_work(&hdcp->prop_work); 1659 } 1660 goto out; 1661 } 1662 1663 if (ret == HDCP_TOPOLOGY_CHANGE) { 1664 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1665 goto out; 1666 1667 DRM_DEBUG_KMS("HDCP2.2 Downstream topology change\n"); 1668 ret = hdcp2_authenticate_repeater_topology(connector); 1669 if (!ret) { 1670 hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; 1671 schedule_work(&hdcp->prop_work); 1672 goto out; 1673 } 1674 DRM_DEBUG_KMS("[%s:%d] Repeater topology auth failed.(%d)\n", 1675 connector->base.name, connector->base.base.id, 1676 ret); 1677 } else { 1678 DRM_DEBUG_KMS("[%s:%d] HDCP2.2 link failed, retrying auth\n", 1679 connector->base.name, connector->base.base.id); 1680 } 1681 1682 ret = _intel_hdcp2_disable(connector); 1683 if (ret) { 1684 DRM_ERROR("[%s:%d] Failed to disable hdcp2.2 (%d)\n", 1685 connector->base.name, connector->base.base.id, ret); 1686 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 1687 schedule_work(&hdcp->prop_work); 1688 goto out; 1689 } 1690 1691 ret = _intel_hdcp2_enable(connector); 1692 if (ret) { 1693 DRM_DEBUG_KMS("[%s:%d] Failed to enable hdcp2.2 (%d)\n", 1694 connector->base.name, connector->base.base.id, 1695 ret); 1696 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 1697 schedule_work(&hdcp->prop_work); 1698 goto out; 1699 } 1700 1701 out: 1702 mutex_unlock(&hdcp->mutex); 1703 return ret; 1704 } 1705 1706 static void intel_hdcp_check_work(struct work_struct *work) 1707 { 1708 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 1709 struct intel_hdcp, 1710 check_work); 1711 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1712 1713 if (!intel_hdcp2_check_link(connector)) 1714 schedule_delayed_work(&hdcp->check_work, 1715 DRM_HDCP2_CHECK_PERIOD_MS); 1716 else if (!intel_hdcp_check_link(connector)) 1717 schedule_delayed_work(&hdcp->check_work, 1718 DRM_HDCP_CHECK_PERIOD_MS); 1719 } 1720 1721 static int i915_hdcp_component_bind(struct device *i915_kdev, 1722 struct device *mei_kdev, void *data) 1723 { 1724 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1725 1726 DRM_DEBUG("I915 HDCP comp bind\n"); 1727 mutex_lock(&dev_priv->hdcp_comp_mutex); 1728 dev_priv->hdcp_master = (struct i915_hdcp_comp_master *)data; 1729 dev_priv->hdcp_master->mei_dev = mei_kdev; 1730 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1731 1732 return 0; 1733 } 1734 1735 static void i915_hdcp_component_unbind(struct device *i915_kdev, 1736 struct device *mei_kdev, void *data) 1737 { 1738 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1739 1740 DRM_DEBUG("I915 HDCP comp unbind\n"); 1741 mutex_lock(&dev_priv->hdcp_comp_mutex); 1742 dev_priv->hdcp_master = NULL; 1743 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1744 } 1745 1746 static const struct component_ops i915_hdcp_component_ops = { 1747 .bind = i915_hdcp_component_bind, 1748 .unbind = i915_hdcp_component_unbind, 1749 }; 1750 1751 static inline int initialize_hdcp_port_data(struct intel_connector *connector) 1752 { 1753 struct intel_hdcp *hdcp = &connector->hdcp; 1754 struct hdcp_port_data *data = &hdcp->port_data; 1755 1756 data->port = connector->encoder->port; 1757 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 1758 data->protocol = (u8)hdcp->shim->protocol; 1759 1760 data->k = 1; 1761 if (!data->streams) 1762 data->streams = kcalloc(data->k, 1763 sizeof(struct hdcp2_streamid_type), 1764 GFP_KERNEL); 1765 if (!data->streams) { 1766 DRM_ERROR("Out of Memory\n"); 1767 return -ENOMEM; 1768 } 1769 1770 data->streams[0].stream_id = 0; 1771 data->streams[0].stream_type = hdcp->content_type; 1772 1773 return 0; 1774 } 1775 1776 static bool is_hdcp2_supported(struct drm_i915_private *dev_priv) 1777 { 1778 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 1779 return false; 1780 1781 return (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || 1782 IS_KABYLAKE(dev_priv)); 1783 } 1784 1785 void intel_hdcp_component_init(struct drm_i915_private *dev_priv) 1786 { 1787 int ret; 1788 1789 if (!is_hdcp2_supported(dev_priv)) 1790 return; 1791 1792 mutex_lock(&dev_priv->hdcp_comp_mutex); 1793 WARN_ON(dev_priv->hdcp_comp_added); 1794 1795 dev_priv->hdcp_comp_added = true; 1796 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1797 ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops, 1798 I915_COMPONENT_HDCP); 1799 if (ret < 0) { 1800 DRM_DEBUG_KMS("Failed at component add(%d)\n", ret); 1801 mutex_lock(&dev_priv->hdcp_comp_mutex); 1802 dev_priv->hdcp_comp_added = false; 1803 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1804 return; 1805 } 1806 } 1807 1808 static void intel_hdcp2_init(struct intel_connector *connector) 1809 { 1810 struct intel_hdcp *hdcp = &connector->hdcp; 1811 int ret; 1812 1813 ret = initialize_hdcp_port_data(connector); 1814 if (ret) { 1815 DRM_DEBUG_KMS("Mei hdcp data init failed\n"); 1816 return; 1817 } 1818 1819 hdcp->hdcp2_supported = true; 1820 } 1821 1822 int intel_hdcp_init(struct intel_connector *connector, 1823 const struct intel_hdcp_shim *shim) 1824 { 1825 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1826 struct intel_hdcp *hdcp = &connector->hdcp; 1827 int ret; 1828 1829 if (!shim) 1830 return -EINVAL; 1831 1832 ret = drm_connector_attach_content_protection_property(&connector->base); 1833 if (ret) 1834 return ret; 1835 1836 hdcp->shim = shim; 1837 mutex_init(&hdcp->mutex); 1838 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 1839 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 1840 1841 if (is_hdcp2_supported(dev_priv)) 1842 intel_hdcp2_init(connector); 1843 init_waitqueue_head(&hdcp->cp_irq_queue); 1844 1845 return 0; 1846 } 1847 1848 int intel_hdcp_enable(struct intel_connector *connector) 1849 { 1850 struct intel_hdcp *hdcp = &connector->hdcp; 1851 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 1852 int ret = -EINVAL; 1853 1854 if (!hdcp->shim) 1855 return -ENOENT; 1856 1857 mutex_lock(&hdcp->mutex); 1858 WARN_ON(hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 1859 1860 /* 1861 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 1862 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 1863 */ 1864 if (intel_hdcp2_capable(connector)) { 1865 ret = _intel_hdcp2_enable(connector); 1866 if (!ret) 1867 check_link_interval = DRM_HDCP2_CHECK_PERIOD_MS; 1868 } 1869 1870 /* When HDCP2.2 fails, HDCP1.4 will be attempted */ 1871 if (ret && intel_hdcp_capable(connector)) { 1872 ret = _intel_hdcp_enable(connector); 1873 } 1874 1875 if (!ret) { 1876 schedule_delayed_work(&hdcp->check_work, check_link_interval); 1877 hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; 1878 schedule_work(&hdcp->prop_work); 1879 } 1880 1881 mutex_unlock(&hdcp->mutex); 1882 return ret; 1883 } 1884 1885 int intel_hdcp_disable(struct intel_connector *connector) 1886 { 1887 struct intel_hdcp *hdcp = &connector->hdcp; 1888 int ret = 0; 1889 1890 if (!hdcp->shim) 1891 return -ENOENT; 1892 1893 mutex_lock(&hdcp->mutex); 1894 1895 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1896 hdcp->value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 1897 if (hdcp->hdcp2_encrypted) 1898 ret = _intel_hdcp2_disable(connector); 1899 else if (hdcp->hdcp_encrypted) 1900 ret = _intel_hdcp_disable(connector); 1901 } 1902 1903 mutex_unlock(&hdcp->mutex); 1904 cancel_delayed_work_sync(&hdcp->check_work); 1905 return ret; 1906 } 1907 1908 void intel_hdcp_component_fini(struct drm_i915_private *dev_priv) 1909 { 1910 mutex_lock(&dev_priv->hdcp_comp_mutex); 1911 if (!dev_priv->hdcp_comp_added) { 1912 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1913 return; 1914 } 1915 1916 dev_priv->hdcp_comp_added = false; 1917 mutex_unlock(&dev_priv->hdcp_comp_mutex); 1918 1919 component_del(dev_priv->drm.dev, &i915_hdcp_component_ops); 1920 } 1921 1922 void intel_hdcp_cleanup(struct intel_connector *connector) 1923 { 1924 if (!connector->hdcp.shim) 1925 return; 1926 1927 mutex_lock(&connector->hdcp.mutex); 1928 kfree(connector->hdcp.port_data.streams); 1929 mutex_unlock(&connector->hdcp.mutex); 1930 } 1931 1932 void intel_hdcp_atomic_check(struct drm_connector *connector, 1933 struct drm_connector_state *old_state, 1934 struct drm_connector_state *new_state) 1935 { 1936 u64 old_cp = old_state->content_protection; 1937 u64 new_cp = new_state->content_protection; 1938 struct drm_crtc_state *crtc_state; 1939 1940 if (!new_state->crtc) { 1941 /* 1942 * If the connector is being disabled with CP enabled, mark it 1943 * desired so it's re-enabled when the connector is brought back 1944 */ 1945 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 1946 new_state->content_protection = 1947 DRM_MODE_CONTENT_PROTECTION_DESIRED; 1948 return; 1949 } 1950 1951 /* 1952 * Nothing to do if the state didn't change, or HDCP was activated since 1953 * the last commit 1954 */ 1955 if (old_cp == new_cp || 1956 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 1957 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) 1958 return; 1959 1960 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 1961 new_state->crtc); 1962 crtc_state->mode_changed = true; 1963 } 1964 1965 /* Handles the CP_IRQ raised from the DP HDCP sink */ 1966 void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 1967 { 1968 struct intel_hdcp *hdcp = &connector->hdcp; 1969 1970 if (!hdcp->shim) 1971 return; 1972 1973 atomic_inc(&connector->hdcp.cp_irq_count); 1974 wake_up_all(&connector->hdcp.cp_irq_queue); 1975 1976 schedule_delayed_work(&hdcp->check_work, 0); 1977 } 1978