1 /*
2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2008,2010 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  *
25  * Authors:
26  *	Eric Anholt <eric@anholt.net>
27  *	Chris Wilson <chris@chris-wilson.co.uk>
28  */
29 
30 #include <linux/export.h>
31 #include <linux/i2c-algo-bit.h>
32 #include <linux/i2c.h>
33 
34 #include <drm/drm_hdcp.h>
35 
36 #include "i915_drv.h"
37 #include "intel_de.h"
38 #include "intel_display_types.h"
39 #include "intel_gmbus.h"
40 
41 struct gmbus_pin {
42 	const char *name;
43 	enum i915_gpio gpio;
44 };
45 
46 /* Map gmbus pin pairs to names and registers. */
47 static const struct gmbus_pin gmbus_pins[] = {
48 	[GMBUS_PIN_SSC] = { "ssc", GPIOB },
49 	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
50 	[GMBUS_PIN_PANEL] = { "panel", GPIOC },
51 	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
52 	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
53 	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
54 };
55 
56 static const struct gmbus_pin gmbus_pins_bdw[] = {
57 	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
58 	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
59 	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
60 	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
61 };
62 
63 static const struct gmbus_pin gmbus_pins_skl[] = {
64 	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
65 	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
66 	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
67 };
68 
69 static const struct gmbus_pin gmbus_pins_bxt[] = {
70 	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
71 	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
72 	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
73 };
74 
75 static const struct gmbus_pin gmbus_pins_cnp[] = {
76 	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
77 	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
78 	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
79 	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
80 };
81 
82 static const struct gmbus_pin gmbus_pins_icp[] = {
83 	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
84 	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
85 	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
86 	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
87 	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
88 	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
89 	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
90 	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
91 	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
92 };
93 
94 static const struct gmbus_pin gmbus_pins_dg1[] = {
95 	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
96 	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
97 	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
98 	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
99 };
100 
101 static const struct gmbus_pin gmbus_pins_dg2[] = {
102 	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
103 	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
104 	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
105 	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
106 	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
107 };
108 
109 /* pin is expected to be valid */
110 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
111 					     unsigned int pin)
112 {
113 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
114 		return &gmbus_pins_dg2[pin];
115 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
116 		return &gmbus_pins_dg1[pin];
117 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
118 		return &gmbus_pins_icp[pin];
119 	else if (HAS_PCH_CNP(dev_priv))
120 		return &gmbus_pins_cnp[pin];
121 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
122 		return &gmbus_pins_bxt[pin];
123 	else if (DISPLAY_VER(dev_priv) == 9)
124 		return &gmbus_pins_skl[pin];
125 	else if (IS_BROADWELL(dev_priv))
126 		return &gmbus_pins_bdw[pin];
127 	else
128 		return &gmbus_pins[pin];
129 }
130 
131 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
132 			      unsigned int pin)
133 {
134 	unsigned int size;
135 
136 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
137 		size = ARRAY_SIZE(gmbus_pins_dg2);
138 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
139 		size = ARRAY_SIZE(gmbus_pins_dg1);
140 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
141 		size = ARRAY_SIZE(gmbus_pins_icp);
142 	else if (HAS_PCH_CNP(dev_priv))
143 		size = ARRAY_SIZE(gmbus_pins_cnp);
144 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
145 		size = ARRAY_SIZE(gmbus_pins_bxt);
146 	else if (DISPLAY_VER(dev_priv) == 9)
147 		size = ARRAY_SIZE(gmbus_pins_skl);
148 	else if (IS_BROADWELL(dev_priv))
149 		size = ARRAY_SIZE(gmbus_pins_bdw);
150 	else
151 		size = ARRAY_SIZE(gmbus_pins);
152 
153 	return pin < size && get_gmbus_pin(dev_priv, pin)->name;
154 }
155 
156 /* Intel GPIO access functions */
157 
158 #define I2C_RISEFALL_TIME 10
159 
160 static inline struct intel_gmbus *
161 to_intel_gmbus(struct i2c_adapter *i2c)
162 {
163 	return container_of(i2c, struct intel_gmbus, adapter);
164 }
165 
166 void
167 intel_gmbus_reset(struct drm_i915_private *dev_priv)
168 {
169 	intel_de_write(dev_priv, GMBUS0, 0);
170 	intel_de_write(dev_priv, GMBUS4, 0);
171 }
172 
173 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
174 				   bool enable)
175 {
176 	u32 val;
177 
178 	/* When using bit bashing for I2C, this bit needs to be set to 1 */
179 	val = intel_de_read(dev_priv, DSPCLK_GATE_D);
180 	if (!enable)
181 		val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
182 	else
183 		val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
184 	intel_de_write(dev_priv, DSPCLK_GATE_D, val);
185 }
186 
187 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
188 				   bool enable)
189 {
190 	u32 val;
191 
192 	val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
193 	if (!enable)
194 		val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
195 	else
196 		val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
197 	intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
198 }
199 
200 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
201 				   bool enable)
202 {
203 	u32 val;
204 
205 	val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4);
206 	if (!enable)
207 		val |= BXT_GMBUS_GATING_DIS;
208 	else
209 		val &= ~BXT_GMBUS_GATING_DIS;
210 	intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val);
211 }
212 
213 static u32 get_reserved(struct intel_gmbus *bus)
214 {
215 	struct drm_i915_private *i915 = bus->dev_priv;
216 	struct intel_uncore *uncore = &i915->uncore;
217 	u32 reserved = 0;
218 
219 	/* On most chips, these bits must be preserved in software. */
220 	if (!IS_I830(i915) && !IS_I845G(i915))
221 		reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
222 			   (GPIO_DATA_PULLUP_DISABLE |
223 			    GPIO_CLOCK_PULLUP_DISABLE);
224 
225 	return reserved;
226 }
227 
228 static int get_clock(void *data)
229 {
230 	struct intel_gmbus *bus = data;
231 	struct intel_uncore *uncore = &bus->dev_priv->uncore;
232 	u32 reserved = get_reserved(bus);
233 
234 	intel_uncore_write_notrace(uncore,
235 				   bus->gpio_reg,
236 				   reserved | GPIO_CLOCK_DIR_MASK);
237 	intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
238 
239 	return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
240 		GPIO_CLOCK_VAL_IN) != 0;
241 }
242 
243 static int get_data(void *data)
244 {
245 	struct intel_gmbus *bus = data;
246 	struct intel_uncore *uncore = &bus->dev_priv->uncore;
247 	u32 reserved = get_reserved(bus);
248 
249 	intel_uncore_write_notrace(uncore,
250 				   bus->gpio_reg,
251 				   reserved | GPIO_DATA_DIR_MASK);
252 	intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
253 
254 	return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
255 		GPIO_DATA_VAL_IN) != 0;
256 }
257 
258 static void set_clock(void *data, int state_high)
259 {
260 	struct intel_gmbus *bus = data;
261 	struct intel_uncore *uncore = &bus->dev_priv->uncore;
262 	u32 reserved = get_reserved(bus);
263 	u32 clock_bits;
264 
265 	if (state_high)
266 		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
267 	else
268 		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
269 			     GPIO_CLOCK_VAL_MASK;
270 
271 	intel_uncore_write_notrace(uncore,
272 				   bus->gpio_reg,
273 				   reserved | clock_bits);
274 	intel_uncore_posting_read(uncore, bus->gpio_reg);
275 }
276 
277 static void set_data(void *data, int state_high)
278 {
279 	struct intel_gmbus *bus = data;
280 	struct intel_uncore *uncore = &bus->dev_priv->uncore;
281 	u32 reserved = get_reserved(bus);
282 	u32 data_bits;
283 
284 	if (state_high)
285 		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
286 	else
287 		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
288 			GPIO_DATA_VAL_MASK;
289 
290 	intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
291 	intel_uncore_posting_read(uncore, bus->gpio_reg);
292 }
293 
294 static int
295 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
296 {
297 	struct intel_gmbus *bus = container_of(adapter,
298 					       struct intel_gmbus,
299 					       adapter);
300 	struct drm_i915_private *dev_priv = bus->dev_priv;
301 
302 	intel_gmbus_reset(dev_priv);
303 
304 	if (IS_PINEVIEW(dev_priv))
305 		pnv_gmbus_clock_gating(dev_priv, false);
306 
307 	set_data(bus, 1);
308 	set_clock(bus, 1);
309 	udelay(I2C_RISEFALL_TIME);
310 	return 0;
311 }
312 
313 static void
314 intel_gpio_post_xfer(struct i2c_adapter *adapter)
315 {
316 	struct intel_gmbus *bus = container_of(adapter,
317 					       struct intel_gmbus,
318 					       adapter);
319 	struct drm_i915_private *dev_priv = bus->dev_priv;
320 
321 	set_data(bus, 1);
322 	set_clock(bus, 1);
323 
324 	if (IS_PINEVIEW(dev_priv))
325 		pnv_gmbus_clock_gating(dev_priv, true);
326 }
327 
328 static void
329 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
330 {
331 	struct drm_i915_private *dev_priv = bus->dev_priv;
332 	struct i2c_algo_bit_data *algo;
333 
334 	algo = &bus->bit_algo;
335 
336 	bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
337 	bus->adapter.algo_data = algo;
338 	algo->setsda = set_data;
339 	algo->setscl = set_clock;
340 	algo->getsda = get_data;
341 	algo->getscl = get_clock;
342 	algo->pre_xfer = intel_gpio_pre_xfer;
343 	algo->post_xfer = intel_gpio_post_xfer;
344 	algo->udelay = I2C_RISEFALL_TIME;
345 	algo->timeout = usecs_to_jiffies(2200);
346 	algo->data = bus;
347 }
348 
349 static bool has_gmbus_irq(struct drm_i915_private *i915)
350 {
351 	/*
352 	 * encoder->shutdown() may want to use GMBUS
353 	 * after irqs have already been disabled.
354 	 */
355 	return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915);
356 }
357 
358 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
359 {
360 	DEFINE_WAIT(wait);
361 	u32 gmbus2;
362 	int ret;
363 
364 	/* Important: The hw handles only the first bit, so set only one! Since
365 	 * we also need to check for NAKs besides the hw ready/idle signal, we
366 	 * need to wake up periodically and check that ourselves.
367 	 */
368 	if (!has_gmbus_irq(dev_priv))
369 		irq_en = 0;
370 
371 	add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
372 	intel_de_write_fw(dev_priv, GMBUS4, irq_en);
373 
374 	status |= GMBUS_SATOER;
375 	ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
376 			  2);
377 	if (ret)
378 		ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
379 			       50);
380 
381 	intel_de_write_fw(dev_priv, GMBUS4, 0);
382 	remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
383 
384 	if (gmbus2 & GMBUS_SATOER)
385 		return -ENXIO;
386 
387 	return ret;
388 }
389 
390 static int
391 gmbus_wait_idle(struct drm_i915_private *dev_priv)
392 {
393 	DEFINE_WAIT(wait);
394 	u32 irq_enable;
395 	int ret;
396 
397 	/* Important: The hw handles only the first bit, so set only one! */
398 	irq_enable = 0;
399 	if (has_gmbus_irq(dev_priv))
400 		irq_enable = GMBUS_IDLE_EN;
401 
402 	add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
403 	intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
404 
405 	ret = intel_wait_for_register_fw(&dev_priv->uncore,
406 					 GMBUS2, GMBUS_ACTIVE, 0,
407 					 10);
408 
409 	intel_de_write_fw(dev_priv, GMBUS4, 0);
410 	remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
411 
412 	return ret;
413 }
414 
415 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
416 {
417 	return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
418 	       GMBUS_BYTE_COUNT_MAX;
419 }
420 
421 static int
422 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
423 		      unsigned short addr, u8 *buf, unsigned int len,
424 		      u32 gmbus0_reg, u32 gmbus1_index)
425 {
426 	unsigned int size = len;
427 	bool burst_read = len > gmbus_max_xfer_size(dev_priv);
428 	bool extra_byte_added = false;
429 
430 	if (burst_read) {
431 		/*
432 		 * As per HW Spec, for 512Bytes need to read extra Byte and
433 		 * Ignore the extra byte read.
434 		 */
435 		if (len == 512) {
436 			extra_byte_added = true;
437 			len++;
438 		}
439 		size = len % 256 + 256;
440 		intel_de_write_fw(dev_priv, GMBUS0,
441 				  gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
442 	}
443 
444 	intel_de_write_fw(dev_priv, GMBUS1,
445 			  gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
446 	while (len) {
447 		int ret;
448 		u32 val, loop = 0;
449 
450 		ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
451 		if (ret)
452 			return ret;
453 
454 		val = intel_de_read_fw(dev_priv, GMBUS3);
455 		do {
456 			if (extra_byte_added && len == 1)
457 				break;
458 
459 			*buf++ = val & 0xff;
460 			val >>= 8;
461 		} while (--len && ++loop < 4);
462 
463 		if (burst_read && len == size - 4)
464 			/* Reset the override bit */
465 			intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);
466 	}
467 
468 	return 0;
469 }
470 
471 /*
472  * HW spec says that 512Bytes in Burst read need special treatment.
473  * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
474  * an I2C slave, which supports such a lengthy burst read too for experiments.
475  *
476  * So until things get clarified on HW support, to avoid the burst read length
477  * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
478  */
479 #define INTEL_GMBUS_BURST_READ_MAX_LEN		767U
480 
481 static int
482 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
483 		u32 gmbus0_reg, u32 gmbus1_index)
484 {
485 	u8 *buf = msg->buf;
486 	unsigned int rx_size = msg->len;
487 	unsigned int len;
488 	int ret;
489 
490 	do {
491 		if (HAS_GMBUS_BURST_READ(dev_priv))
492 			len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
493 		else
494 			len = min(rx_size, gmbus_max_xfer_size(dev_priv));
495 
496 		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
497 					    gmbus0_reg, gmbus1_index);
498 		if (ret)
499 			return ret;
500 
501 		rx_size -= len;
502 		buf += len;
503 	} while (rx_size != 0);
504 
505 	return 0;
506 }
507 
508 static int
509 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
510 		       unsigned short addr, u8 *buf, unsigned int len,
511 		       u32 gmbus1_index)
512 {
513 	unsigned int chunk_size = len;
514 	u32 val, loop;
515 
516 	val = loop = 0;
517 	while (len && loop < 4) {
518 		val |= *buf++ << (8 * loop++);
519 		len -= 1;
520 	}
521 
522 	intel_de_write_fw(dev_priv, GMBUS3, val);
523 	intel_de_write_fw(dev_priv, GMBUS1,
524 			  gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
525 	while (len) {
526 		int ret;
527 
528 		val = loop = 0;
529 		do {
530 			val |= *buf++ << (8 * loop);
531 		} while (--len && ++loop < 4);
532 
533 		intel_de_write_fw(dev_priv, GMBUS3, val);
534 
535 		ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
536 		if (ret)
537 			return ret;
538 	}
539 
540 	return 0;
541 }
542 
543 static int
544 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
545 		 u32 gmbus1_index)
546 {
547 	u8 *buf = msg->buf;
548 	unsigned int tx_size = msg->len;
549 	unsigned int len;
550 	int ret;
551 
552 	do {
553 		len = min(tx_size, gmbus_max_xfer_size(dev_priv));
554 
555 		ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
556 					     gmbus1_index);
557 		if (ret)
558 			return ret;
559 
560 		buf += len;
561 		tx_size -= len;
562 	} while (tx_size != 0);
563 
564 	return 0;
565 }
566 
567 /*
568  * The gmbus controller can combine a 1 or 2 byte write with another read/write
569  * that immediately follows it by using an "INDEX" cycle.
570  */
571 static bool
572 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
573 {
574 	return (i + 1 < num &&
575 		msgs[i].addr == msgs[i + 1].addr &&
576 		!(msgs[i].flags & I2C_M_RD) &&
577 		(msgs[i].len == 1 || msgs[i].len == 2) &&
578 		msgs[i + 1].len > 0);
579 }
580 
581 static int
582 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
583 		 u32 gmbus0_reg)
584 {
585 	u32 gmbus1_index = 0;
586 	u32 gmbus5 = 0;
587 	int ret;
588 
589 	if (msgs[0].len == 2)
590 		gmbus5 = GMBUS_2BYTE_INDEX_EN |
591 			 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
592 	if (msgs[0].len == 1)
593 		gmbus1_index = GMBUS_CYCLE_INDEX |
594 			       (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
595 
596 	/* GMBUS5 holds 16-bit index */
597 	if (gmbus5)
598 		intel_de_write_fw(dev_priv, GMBUS5, gmbus5);
599 
600 	if (msgs[1].flags & I2C_M_RD)
601 		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
602 				      gmbus1_index);
603 	else
604 		ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
605 
606 	/* Clear GMBUS5 after each index transfer */
607 	if (gmbus5)
608 		intel_de_write_fw(dev_priv, GMBUS5, 0);
609 
610 	return ret;
611 }
612 
613 static int
614 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
615 	      u32 gmbus0_source)
616 {
617 	struct intel_gmbus *bus = container_of(adapter,
618 					       struct intel_gmbus,
619 					       adapter);
620 	struct drm_i915_private *dev_priv = bus->dev_priv;
621 	int i = 0, inc, try = 0;
622 	int ret = 0;
623 
624 	/* Display WA #0868: skl,bxt,kbl,cfl,glk */
625 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
626 		bxt_gmbus_clock_gating(dev_priv, false);
627 	else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
628 		pch_gmbus_clock_gating(dev_priv, false);
629 
630 retry:
631 	intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);
632 
633 	for (; i < num; i += inc) {
634 		inc = 1;
635 		if (gmbus_is_index_xfer(msgs, i, num)) {
636 			ret = gmbus_index_xfer(dev_priv, &msgs[i],
637 					       gmbus0_source | bus->reg0);
638 			inc = 2; /* an index transmission is two msgs */
639 		} else if (msgs[i].flags & I2C_M_RD) {
640 			ret = gmbus_xfer_read(dev_priv, &msgs[i],
641 					      gmbus0_source | bus->reg0, 0);
642 		} else {
643 			ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
644 		}
645 
646 		if (!ret)
647 			ret = gmbus_wait(dev_priv,
648 					 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
649 		if (ret == -ETIMEDOUT)
650 			goto timeout;
651 		else if (ret)
652 			goto clear_err;
653 	}
654 
655 	/* Generate a STOP condition on the bus. Note that gmbus can't generata
656 	 * a STOP on the very first cycle. To simplify the code we
657 	 * unconditionally generate the STOP condition with an additional gmbus
658 	 * cycle. */
659 	intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
660 
661 	/* Mark the GMBUS interface as disabled after waiting for idle.
662 	 * We will re-enable it at the start of the next xfer,
663 	 * till then let it sleep.
664 	 */
665 	if (gmbus_wait_idle(dev_priv)) {
666 		drm_dbg_kms(&dev_priv->drm,
667 			    "GMBUS [%s] timed out waiting for idle\n",
668 			    adapter->name);
669 		ret = -ETIMEDOUT;
670 	}
671 	intel_de_write_fw(dev_priv, GMBUS0, 0);
672 	ret = ret ?: i;
673 	goto out;
674 
675 clear_err:
676 	/*
677 	 * Wait for bus to IDLE before clearing NAK.
678 	 * If we clear the NAK while bus is still active, then it will stay
679 	 * active and the next transaction may fail.
680 	 *
681 	 * If no ACK is received during the address phase of a transaction, the
682 	 * adapter must report -ENXIO. It is not clear what to return if no ACK
683 	 * is received at other times. But we have to be careful to not return
684 	 * spurious -ENXIO because that will prevent i2c and drm edid functions
685 	 * from retrying. So return -ENXIO only when gmbus properly quiescents -
686 	 * timing out seems to happen when there _is_ a ddc chip present, but
687 	 * it's slow responding and only answers on the 2nd retry.
688 	 */
689 	ret = -ENXIO;
690 	if (gmbus_wait_idle(dev_priv)) {
691 		drm_dbg_kms(&dev_priv->drm,
692 			    "GMBUS [%s] timed out after NAK\n",
693 			    adapter->name);
694 		ret = -ETIMEDOUT;
695 	}
696 
697 	/* Toggle the Software Clear Interrupt bit. This has the effect
698 	 * of resetting the GMBUS controller and so clearing the
699 	 * BUS_ERROR raised by the slave's NAK.
700 	 */
701 	intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);
702 	intel_de_write_fw(dev_priv, GMBUS1, 0);
703 	intel_de_write_fw(dev_priv, GMBUS0, 0);
704 
705 	drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
706 		    adapter->name, msgs[i].addr,
707 		    (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
708 
709 	/*
710 	 * Passive adapters sometimes NAK the first probe. Retry the first
711 	 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
712 	 * has retries internally. See also the retry loop in
713 	 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
714 	 */
715 	if (ret == -ENXIO && i == 0 && try++ == 0) {
716 		drm_dbg_kms(&dev_priv->drm,
717 			    "GMBUS [%s] NAK on first message, retry\n",
718 			    adapter->name);
719 		goto retry;
720 	}
721 
722 	goto out;
723 
724 timeout:
725 	drm_dbg_kms(&dev_priv->drm,
726 		    "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
727 		    bus->adapter.name, bus->reg0 & 0xff);
728 	intel_de_write_fw(dev_priv, GMBUS0, 0);
729 
730 	/*
731 	 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
732 	 * instead. Use EAGAIN to have i2c core retry.
733 	 */
734 	ret = -EAGAIN;
735 
736 out:
737 	/* Display WA #0868: skl,bxt,kbl,cfl,glk */
738 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
739 		bxt_gmbus_clock_gating(dev_priv, true);
740 	else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
741 		pch_gmbus_clock_gating(dev_priv, true);
742 
743 	return ret;
744 }
745 
746 static int
747 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
748 {
749 	struct intel_gmbus *bus =
750 		container_of(adapter, struct intel_gmbus, adapter);
751 	struct drm_i915_private *dev_priv = bus->dev_priv;
752 	intel_wakeref_t wakeref;
753 	int ret;
754 
755 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
756 
757 	if (bus->force_bit) {
758 		ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
759 		if (ret < 0)
760 			bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
761 	} else {
762 		ret = do_gmbus_xfer(adapter, msgs, num, 0);
763 		if (ret == -EAGAIN)
764 			bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
765 	}
766 
767 	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
768 
769 	return ret;
770 }
771 
772 int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
773 {
774 	struct intel_gmbus *bus =
775 		container_of(adapter, struct intel_gmbus, adapter);
776 	struct drm_i915_private *dev_priv = bus->dev_priv;
777 	u8 cmd = DRM_HDCP_DDC_AKSV;
778 	u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
779 	struct i2c_msg msgs[] = {
780 		{
781 			.addr = DRM_HDCP_DDC_ADDR,
782 			.flags = 0,
783 			.len = sizeof(cmd),
784 			.buf = &cmd,
785 		},
786 		{
787 			.addr = DRM_HDCP_DDC_ADDR,
788 			.flags = 0,
789 			.len = sizeof(buf),
790 			.buf = buf,
791 		}
792 	};
793 	intel_wakeref_t wakeref;
794 	int ret;
795 
796 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
797 	mutex_lock(&dev_priv->gmbus_mutex);
798 
799 	/*
800 	 * In order to output Aksv to the receiver, use an indexed write to
801 	 * pass the i2c command, and tell GMBUS to use the HW-provided value
802 	 * instead of sourcing GMBUS3 for the data.
803 	 */
804 	ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
805 
806 	mutex_unlock(&dev_priv->gmbus_mutex);
807 	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
808 
809 	return ret;
810 }
811 
812 static u32 gmbus_func(struct i2c_adapter *adapter)
813 {
814 	return i2c_bit_algo.functionality(adapter) &
815 		(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
816 		/* I2C_FUNC_10BIT_ADDR | */
817 		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
818 		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
819 }
820 
821 static const struct i2c_algorithm gmbus_algorithm = {
822 	.master_xfer	= gmbus_xfer,
823 	.functionality	= gmbus_func
824 };
825 
826 static void gmbus_lock_bus(struct i2c_adapter *adapter,
827 			   unsigned int flags)
828 {
829 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
830 	struct drm_i915_private *dev_priv = bus->dev_priv;
831 
832 	mutex_lock(&dev_priv->gmbus_mutex);
833 }
834 
835 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
836 			     unsigned int flags)
837 {
838 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
839 	struct drm_i915_private *dev_priv = bus->dev_priv;
840 
841 	return mutex_trylock(&dev_priv->gmbus_mutex);
842 }
843 
844 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
845 			     unsigned int flags)
846 {
847 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
848 	struct drm_i915_private *dev_priv = bus->dev_priv;
849 
850 	mutex_unlock(&dev_priv->gmbus_mutex);
851 }
852 
853 static const struct i2c_lock_operations gmbus_lock_ops = {
854 	.lock_bus =    gmbus_lock_bus,
855 	.trylock_bus = gmbus_trylock_bus,
856 	.unlock_bus =  gmbus_unlock_bus,
857 };
858 
859 /**
860  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
861  * @dev_priv: i915 device private
862  */
863 int intel_gmbus_setup(struct drm_i915_private *dev_priv)
864 {
865 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
866 	struct intel_gmbus *bus;
867 	unsigned int pin;
868 	int ret;
869 
870 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
871 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
872 	else if (!HAS_GMCH(dev_priv))
873 		/*
874 		 * Broxton uses the same PCH offsets for South Display Engine,
875 		 * even though it doesn't have a PCH.
876 		 */
877 		dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
878 
879 	mutex_init(&dev_priv->gmbus_mutex);
880 	init_waitqueue_head(&dev_priv->gmbus_wait_queue);
881 
882 	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
883 		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
884 			continue;
885 
886 		bus = &dev_priv->gmbus[pin];
887 
888 		bus->adapter.owner = THIS_MODULE;
889 		bus->adapter.class = I2C_CLASS_DDC;
890 		snprintf(bus->adapter.name,
891 			 sizeof(bus->adapter.name),
892 			 "i915 gmbus %s",
893 			 get_gmbus_pin(dev_priv, pin)->name);
894 
895 		bus->adapter.dev.parent = &pdev->dev;
896 		bus->dev_priv = dev_priv;
897 
898 		bus->adapter.algo = &gmbus_algorithm;
899 		bus->adapter.lock_ops = &gmbus_lock_ops;
900 
901 		/*
902 		 * We wish to retry with bit banging
903 		 * after a timed out GMBUS attempt.
904 		 */
905 		bus->adapter.retries = 1;
906 
907 		/* By default use a conservative clock rate */
908 		bus->reg0 = pin | GMBUS_RATE_100KHZ;
909 
910 		/* gmbus seems to be broken on i830 */
911 		if (IS_I830(dev_priv))
912 			bus->force_bit = 1;
913 
914 		intel_gpio_setup(bus, pin);
915 
916 		ret = i2c_add_adapter(&bus->adapter);
917 		if (ret)
918 			goto err;
919 	}
920 
921 	intel_gmbus_reset(dev_priv);
922 
923 	return 0;
924 
925 err:
926 	while (pin--) {
927 		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
928 			continue;
929 
930 		bus = &dev_priv->gmbus[pin];
931 		i2c_del_adapter(&bus->adapter);
932 	}
933 	return ret;
934 }
935 
936 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
937 					    unsigned int pin)
938 {
939 	if (drm_WARN_ON(&dev_priv->drm,
940 			!intel_gmbus_is_valid_pin(dev_priv, pin)))
941 		return NULL;
942 
943 	return &dev_priv->gmbus[pin].adapter;
944 }
945 
946 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
947 {
948 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
949 	struct drm_i915_private *dev_priv = bus->dev_priv;
950 
951 	mutex_lock(&dev_priv->gmbus_mutex);
952 
953 	bus->force_bit += force_bit ? 1 : -1;
954 	drm_dbg_kms(&dev_priv->drm,
955 		    "%sabling bit-banging on %s. force bit now %d\n",
956 		    force_bit ? "en" : "dis", adapter->name,
957 		    bus->force_bit);
958 
959 	mutex_unlock(&dev_priv->gmbus_mutex);
960 }
961 
962 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
963 {
964 	struct intel_gmbus *bus = to_intel_gmbus(adapter);
965 
966 	return bus->force_bit;
967 }
968 
969 void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
970 {
971 	struct intel_gmbus *bus;
972 	unsigned int pin;
973 
974 	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
975 		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
976 			continue;
977 
978 		bus = &dev_priv->gmbus[pin];
979 		i2c_del_adapter(&bus->adapter);
980 	}
981 }
982