1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/drm_hdcp.h> 35 #include <drm/i915_drm.h> 36 37 #include "i915_drv.h" 38 #include "intel_drv.h" 39 #include "intel_gmbus.h" 40 41 struct gmbus_pin { 42 const char *name; 43 enum i915_gpio gpio; 44 }; 45 46 /* Map gmbus pin pairs to names and registers. */ 47 static const struct gmbus_pin gmbus_pins[] = { 48 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 49 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 50 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 51 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 52 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 53 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 54 }; 55 56 static const struct gmbus_pin gmbus_pins_bdw[] = { 57 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 58 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 59 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 60 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 61 }; 62 63 static const struct gmbus_pin gmbus_pins_skl[] = { 64 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 65 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 66 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 67 }; 68 69 static const struct gmbus_pin gmbus_pins_bxt[] = { 70 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 71 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 72 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 73 }; 74 75 static const struct gmbus_pin gmbus_pins_cnp[] = { 76 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 77 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 78 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 79 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 80 }; 81 82 static const struct gmbus_pin gmbus_pins_icp[] = { 83 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 84 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 85 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 86 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 87 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 88 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 89 }; 90 91 static const struct gmbus_pin gmbus_pins_mcc[] = { 92 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 93 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 94 [GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ }, 95 }; 96 97 /* pin is expected to be valid */ 98 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, 99 unsigned int pin) 100 { 101 if (HAS_PCH_MCC(dev_priv)) 102 return &gmbus_pins_mcc[pin]; 103 else if (HAS_PCH_ICP(dev_priv)) 104 return &gmbus_pins_icp[pin]; 105 else if (HAS_PCH_CNP(dev_priv)) 106 return &gmbus_pins_cnp[pin]; 107 else if (IS_GEN9_LP(dev_priv)) 108 return &gmbus_pins_bxt[pin]; 109 else if (IS_GEN9_BC(dev_priv)) 110 return &gmbus_pins_skl[pin]; 111 else if (IS_BROADWELL(dev_priv)) 112 return &gmbus_pins_bdw[pin]; 113 else 114 return &gmbus_pins[pin]; 115 } 116 117 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 118 unsigned int pin) 119 { 120 unsigned int size; 121 122 if (HAS_PCH_MCC(dev_priv)) 123 size = ARRAY_SIZE(gmbus_pins_mcc); 124 else if (HAS_PCH_ICP(dev_priv)) 125 size = ARRAY_SIZE(gmbus_pins_icp); 126 else if (HAS_PCH_CNP(dev_priv)) 127 size = ARRAY_SIZE(gmbus_pins_cnp); 128 else if (IS_GEN9_LP(dev_priv)) 129 size = ARRAY_SIZE(gmbus_pins_bxt); 130 else if (IS_GEN9_BC(dev_priv)) 131 size = ARRAY_SIZE(gmbus_pins_skl); 132 else if (IS_BROADWELL(dev_priv)) 133 size = ARRAY_SIZE(gmbus_pins_bdw); 134 else 135 size = ARRAY_SIZE(gmbus_pins); 136 137 return pin < size && get_gmbus_pin(dev_priv, pin)->name; 138 } 139 140 /* Intel GPIO access functions */ 141 142 #define I2C_RISEFALL_TIME 10 143 144 static inline struct intel_gmbus * 145 to_intel_gmbus(struct i2c_adapter *i2c) 146 { 147 return container_of(i2c, struct intel_gmbus, adapter); 148 } 149 150 void 151 intel_gmbus_reset(struct drm_i915_private *dev_priv) 152 { 153 I915_WRITE(GMBUS0, 0); 154 I915_WRITE(GMBUS4, 0); 155 } 156 157 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, 158 bool enable) 159 { 160 u32 val; 161 162 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 163 val = I915_READ(DSPCLK_GATE_D); 164 if (!enable) 165 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 166 else 167 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 168 I915_WRITE(DSPCLK_GATE_D, val); 169 } 170 171 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, 172 bool enable) 173 { 174 u32 val; 175 176 val = I915_READ(SOUTH_DSPCLK_GATE_D); 177 if (!enable) 178 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 179 else 180 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 181 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 182 } 183 184 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, 185 bool enable) 186 { 187 u32 val; 188 189 val = I915_READ(GEN9_CLKGATE_DIS_4); 190 if (!enable) 191 val |= BXT_GMBUS_GATING_DIS; 192 else 193 val &= ~BXT_GMBUS_GATING_DIS; 194 I915_WRITE(GEN9_CLKGATE_DIS_4, val); 195 } 196 197 static u32 get_reserved(struct intel_gmbus *bus) 198 { 199 struct drm_i915_private *i915 = bus->dev_priv; 200 struct intel_uncore *uncore = &i915->uncore; 201 u32 reserved = 0; 202 203 /* On most chips, these bits must be preserved in software. */ 204 if (!IS_I830(i915) && !IS_I845G(i915)) 205 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 206 (GPIO_DATA_PULLUP_DISABLE | 207 GPIO_CLOCK_PULLUP_DISABLE); 208 209 return reserved; 210 } 211 212 static int get_clock(void *data) 213 { 214 struct intel_gmbus *bus = data; 215 struct intel_uncore *uncore = &bus->dev_priv->uncore; 216 u32 reserved = get_reserved(bus); 217 218 intel_uncore_write_notrace(uncore, 219 bus->gpio_reg, 220 reserved | GPIO_CLOCK_DIR_MASK); 221 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 222 223 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 224 GPIO_CLOCK_VAL_IN) != 0; 225 } 226 227 static int get_data(void *data) 228 { 229 struct intel_gmbus *bus = data; 230 struct intel_uncore *uncore = &bus->dev_priv->uncore; 231 u32 reserved = get_reserved(bus); 232 233 intel_uncore_write_notrace(uncore, 234 bus->gpio_reg, 235 reserved | GPIO_DATA_DIR_MASK); 236 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 237 238 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 239 GPIO_DATA_VAL_IN) != 0; 240 } 241 242 static void set_clock(void *data, int state_high) 243 { 244 struct intel_gmbus *bus = data; 245 struct intel_uncore *uncore = &bus->dev_priv->uncore; 246 u32 reserved = get_reserved(bus); 247 u32 clock_bits; 248 249 if (state_high) 250 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 251 else 252 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 253 GPIO_CLOCK_VAL_MASK; 254 255 intel_uncore_write_notrace(uncore, 256 bus->gpio_reg, 257 reserved | clock_bits); 258 intel_uncore_posting_read(uncore, bus->gpio_reg); 259 } 260 261 static void set_data(void *data, int state_high) 262 { 263 struct intel_gmbus *bus = data; 264 struct intel_uncore *uncore = &bus->dev_priv->uncore; 265 u32 reserved = get_reserved(bus); 266 u32 data_bits; 267 268 if (state_high) 269 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 270 else 271 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 272 GPIO_DATA_VAL_MASK; 273 274 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 275 intel_uncore_posting_read(uncore, bus->gpio_reg); 276 } 277 278 static int 279 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 280 { 281 struct intel_gmbus *bus = container_of(adapter, 282 struct intel_gmbus, 283 adapter); 284 struct drm_i915_private *dev_priv = bus->dev_priv; 285 286 intel_gmbus_reset(dev_priv); 287 288 if (IS_PINEVIEW(dev_priv)) 289 pnv_gmbus_clock_gating(dev_priv, false); 290 291 set_data(bus, 1); 292 set_clock(bus, 1); 293 udelay(I2C_RISEFALL_TIME); 294 return 0; 295 } 296 297 static void 298 intel_gpio_post_xfer(struct i2c_adapter *adapter) 299 { 300 struct intel_gmbus *bus = container_of(adapter, 301 struct intel_gmbus, 302 adapter); 303 struct drm_i915_private *dev_priv = bus->dev_priv; 304 305 set_data(bus, 1); 306 set_clock(bus, 1); 307 308 if (IS_PINEVIEW(dev_priv)) 309 pnv_gmbus_clock_gating(dev_priv, true); 310 } 311 312 static void 313 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) 314 { 315 struct drm_i915_private *dev_priv = bus->dev_priv; 316 struct i2c_algo_bit_data *algo; 317 318 algo = &bus->bit_algo; 319 320 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); 321 bus->adapter.algo_data = algo; 322 algo->setsda = set_data; 323 algo->setscl = set_clock; 324 algo->getsda = get_data; 325 algo->getscl = get_clock; 326 algo->pre_xfer = intel_gpio_pre_xfer; 327 algo->post_xfer = intel_gpio_post_xfer; 328 algo->udelay = I2C_RISEFALL_TIME; 329 algo->timeout = usecs_to_jiffies(2200); 330 algo->data = bus; 331 } 332 333 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 334 { 335 DEFINE_WAIT(wait); 336 u32 gmbus2; 337 int ret; 338 339 /* Important: The hw handles only the first bit, so set only one! Since 340 * we also need to check for NAKs besides the hw ready/idle signal, we 341 * need to wake up periodically and check that ourselves. 342 */ 343 if (!HAS_GMBUS_IRQ(dev_priv)) 344 irq_en = 0; 345 346 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 347 I915_WRITE_FW(GMBUS4, irq_en); 348 349 status |= GMBUS_SATOER; 350 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); 351 if (ret) 352 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); 353 354 I915_WRITE_FW(GMBUS4, 0); 355 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 356 357 if (gmbus2 & GMBUS_SATOER) 358 return -ENXIO; 359 360 return ret; 361 } 362 363 static int 364 gmbus_wait_idle(struct drm_i915_private *dev_priv) 365 { 366 DEFINE_WAIT(wait); 367 u32 irq_enable; 368 int ret; 369 370 /* Important: The hw handles only the first bit, so set only one! */ 371 irq_enable = 0; 372 if (HAS_GMBUS_IRQ(dev_priv)) 373 irq_enable = GMBUS_IDLE_EN; 374 375 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 376 I915_WRITE_FW(GMBUS4, irq_enable); 377 378 ret = intel_wait_for_register_fw(&dev_priv->uncore, 379 GMBUS2, GMBUS_ACTIVE, 0, 380 10); 381 382 I915_WRITE_FW(GMBUS4, 0); 383 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 384 385 return ret; 386 } 387 388 static inline 389 unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) 390 { 391 return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 392 GMBUS_BYTE_COUNT_MAX; 393 } 394 395 static int 396 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 397 unsigned short addr, u8 *buf, unsigned int len, 398 u32 gmbus0_reg, u32 gmbus1_index) 399 { 400 unsigned int size = len; 401 bool burst_read = len > gmbus_max_xfer_size(dev_priv); 402 bool extra_byte_added = false; 403 404 if (burst_read) { 405 /* 406 * As per HW Spec, for 512Bytes need to read extra Byte and 407 * Ignore the extra byte read. 408 */ 409 if (len == 512) { 410 extra_byte_added = true; 411 len++; 412 } 413 size = len % 256 + 256; 414 I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 415 } 416 417 I915_WRITE_FW(GMBUS1, 418 gmbus1_index | 419 GMBUS_CYCLE_WAIT | 420 (size << GMBUS_BYTE_COUNT_SHIFT) | 421 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 422 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 423 while (len) { 424 int ret; 425 u32 val, loop = 0; 426 427 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 428 if (ret) 429 return ret; 430 431 val = I915_READ_FW(GMBUS3); 432 do { 433 if (extra_byte_added && len == 1) 434 break; 435 436 *buf++ = val & 0xff; 437 val >>= 8; 438 } while (--len && ++loop < 4); 439 440 if (burst_read && len == size - 4) 441 /* Reset the override bit */ 442 I915_WRITE_FW(GMBUS0, gmbus0_reg); 443 } 444 445 return 0; 446 } 447 448 /* 449 * HW spec says that 512Bytes in Burst read need special treatment. 450 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 451 * an I2C slave, which supports such a lengthy burst read too for experiments. 452 * 453 * So until things get clarified on HW support, to avoid the burst read length 454 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 455 */ 456 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 457 458 static int 459 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 460 u32 gmbus0_reg, u32 gmbus1_index) 461 { 462 u8 *buf = msg->buf; 463 unsigned int rx_size = msg->len; 464 unsigned int len; 465 int ret; 466 467 do { 468 if (HAS_GMBUS_BURST_READ(dev_priv)) 469 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 470 else 471 len = min(rx_size, gmbus_max_xfer_size(dev_priv)); 472 473 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, 474 gmbus0_reg, gmbus1_index); 475 if (ret) 476 return ret; 477 478 rx_size -= len; 479 buf += len; 480 } while (rx_size != 0); 481 482 return 0; 483 } 484 485 static int 486 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 487 unsigned short addr, u8 *buf, unsigned int len, 488 u32 gmbus1_index) 489 { 490 unsigned int chunk_size = len; 491 u32 val, loop; 492 493 val = loop = 0; 494 while (len && loop < 4) { 495 val |= *buf++ << (8 * loop++); 496 len -= 1; 497 } 498 499 I915_WRITE_FW(GMBUS3, val); 500 I915_WRITE_FW(GMBUS1, 501 gmbus1_index | GMBUS_CYCLE_WAIT | 502 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | 503 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 504 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 505 while (len) { 506 int ret; 507 508 val = loop = 0; 509 do { 510 val |= *buf++ << (8 * loop); 511 } while (--len && ++loop < 4); 512 513 I915_WRITE_FW(GMBUS3, val); 514 515 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 516 if (ret) 517 return ret; 518 } 519 520 return 0; 521 } 522 523 static int 524 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 525 u32 gmbus1_index) 526 { 527 u8 *buf = msg->buf; 528 unsigned int tx_size = msg->len; 529 unsigned int len; 530 int ret; 531 532 do { 533 len = min(tx_size, gmbus_max_xfer_size(dev_priv)); 534 535 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, 536 gmbus1_index); 537 if (ret) 538 return ret; 539 540 buf += len; 541 tx_size -= len; 542 } while (tx_size != 0); 543 544 return 0; 545 } 546 547 /* 548 * The gmbus controller can combine a 1 or 2 byte write with another read/write 549 * that immediately follows it by using an "INDEX" cycle. 550 */ 551 static bool 552 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 553 { 554 return (i + 1 < num && 555 msgs[i].addr == msgs[i + 1].addr && 556 !(msgs[i].flags & I2C_M_RD) && 557 (msgs[i].len == 1 || msgs[i].len == 2) && 558 msgs[i + 1].len > 0); 559 } 560 561 static int 562 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, 563 u32 gmbus0_reg) 564 { 565 u32 gmbus1_index = 0; 566 u32 gmbus5 = 0; 567 int ret; 568 569 if (msgs[0].len == 2) 570 gmbus5 = GMBUS_2BYTE_INDEX_EN | 571 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 572 if (msgs[0].len == 1) 573 gmbus1_index = GMBUS_CYCLE_INDEX | 574 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 575 576 /* GMBUS5 holds 16-bit index */ 577 if (gmbus5) 578 I915_WRITE_FW(GMBUS5, gmbus5); 579 580 if (msgs[1].flags & I2C_M_RD) 581 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, 582 gmbus1_index); 583 else 584 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); 585 586 /* Clear GMBUS5 after each index transfer */ 587 if (gmbus5) 588 I915_WRITE_FW(GMBUS5, 0); 589 590 return ret; 591 } 592 593 static int 594 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 595 u32 gmbus0_source) 596 { 597 struct intel_gmbus *bus = container_of(adapter, 598 struct intel_gmbus, 599 adapter); 600 struct drm_i915_private *dev_priv = bus->dev_priv; 601 int i = 0, inc, try = 0; 602 int ret = 0; 603 604 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ 605 if (IS_GEN9_LP(dev_priv)) 606 bxt_gmbus_clock_gating(dev_priv, false); 607 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 608 pch_gmbus_clock_gating(dev_priv, false); 609 610 retry: 611 I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); 612 613 for (; i < num; i += inc) { 614 inc = 1; 615 if (gmbus_is_index_xfer(msgs, i, num)) { 616 ret = gmbus_index_xfer(dev_priv, &msgs[i], 617 gmbus0_source | bus->reg0); 618 inc = 2; /* an index transmission is two msgs */ 619 } else if (msgs[i].flags & I2C_M_RD) { 620 ret = gmbus_xfer_read(dev_priv, &msgs[i], 621 gmbus0_source | bus->reg0, 0); 622 } else { 623 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); 624 } 625 626 if (!ret) 627 ret = gmbus_wait(dev_priv, 628 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 629 if (ret == -ETIMEDOUT) 630 goto timeout; 631 else if (ret) 632 goto clear_err; 633 } 634 635 /* Generate a STOP condition on the bus. Note that gmbus can't generata 636 * a STOP on the very first cycle. To simplify the code we 637 * unconditionally generate the STOP condition with an additional gmbus 638 * cycle. */ 639 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 640 641 /* Mark the GMBUS interface as disabled after waiting for idle. 642 * We will re-enable it at the start of the next xfer, 643 * till then let it sleep. 644 */ 645 if (gmbus_wait_idle(dev_priv)) { 646 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 647 adapter->name); 648 ret = -ETIMEDOUT; 649 } 650 I915_WRITE_FW(GMBUS0, 0); 651 ret = ret ?: i; 652 goto out; 653 654 clear_err: 655 /* 656 * Wait for bus to IDLE before clearing NAK. 657 * If we clear the NAK while bus is still active, then it will stay 658 * active and the next transaction may fail. 659 * 660 * If no ACK is received during the address phase of a transaction, the 661 * adapter must report -ENXIO. It is not clear what to return if no ACK 662 * is received at other times. But we have to be careful to not return 663 * spurious -ENXIO because that will prevent i2c and drm edid functions 664 * from retrying. So return -ENXIO only when gmbus properly quiescents - 665 * timing out seems to happen when there _is_ a ddc chip present, but 666 * it's slow responding and only answers on the 2nd retry. 667 */ 668 ret = -ENXIO; 669 if (gmbus_wait_idle(dev_priv)) { 670 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 671 adapter->name); 672 ret = -ETIMEDOUT; 673 } 674 675 /* Toggle the Software Clear Interrupt bit. This has the effect 676 * of resetting the GMBUS controller and so clearing the 677 * BUS_ERROR raised by the slave's NAK. 678 */ 679 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); 680 I915_WRITE_FW(GMBUS1, 0); 681 I915_WRITE_FW(GMBUS0, 0); 682 683 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 684 adapter->name, msgs[i].addr, 685 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 686 687 /* 688 * Passive adapters sometimes NAK the first probe. Retry the first 689 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 690 * has retries internally. See also the retry loop in 691 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 692 */ 693 if (ret == -ENXIO && i == 0 && try++ == 0) { 694 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", 695 adapter->name); 696 goto retry; 697 } 698 699 goto out; 700 701 timeout: 702 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 703 bus->adapter.name, bus->reg0 & 0xff); 704 I915_WRITE_FW(GMBUS0, 0); 705 706 /* 707 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 708 * instead. Use EAGAIN to have i2c core retry. 709 */ 710 ret = -EAGAIN; 711 712 out: 713 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ 714 if (IS_GEN9_LP(dev_priv)) 715 bxt_gmbus_clock_gating(dev_priv, true); 716 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 717 pch_gmbus_clock_gating(dev_priv, true); 718 719 return ret; 720 } 721 722 static int 723 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 724 { 725 struct intel_gmbus *bus = 726 container_of(adapter, struct intel_gmbus, adapter); 727 struct drm_i915_private *dev_priv = bus->dev_priv; 728 intel_wakeref_t wakeref; 729 int ret; 730 731 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 732 733 if (bus->force_bit) { 734 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 735 if (ret < 0) 736 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 737 } else { 738 ret = do_gmbus_xfer(adapter, msgs, num, 0); 739 if (ret == -EAGAIN) 740 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 741 } 742 743 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 744 745 return ret; 746 } 747 748 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 749 { 750 struct intel_gmbus *bus = 751 container_of(adapter, struct intel_gmbus, adapter); 752 struct drm_i915_private *dev_priv = bus->dev_priv; 753 u8 cmd = DRM_HDCP_DDC_AKSV; 754 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 755 struct i2c_msg msgs[] = { 756 { 757 .addr = DRM_HDCP_DDC_ADDR, 758 .flags = 0, 759 .len = sizeof(cmd), 760 .buf = &cmd, 761 }, 762 { 763 .addr = DRM_HDCP_DDC_ADDR, 764 .flags = 0, 765 .len = sizeof(buf), 766 .buf = buf, 767 } 768 }; 769 intel_wakeref_t wakeref; 770 int ret; 771 772 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 773 mutex_lock(&dev_priv->gmbus_mutex); 774 775 /* 776 * In order to output Aksv to the receiver, use an indexed write to 777 * pass the i2c command, and tell GMBUS to use the HW-provided value 778 * instead of sourcing GMBUS3 for the data. 779 */ 780 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 781 782 mutex_unlock(&dev_priv->gmbus_mutex); 783 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 784 785 return ret; 786 } 787 788 static u32 gmbus_func(struct i2c_adapter *adapter) 789 { 790 return i2c_bit_algo.functionality(adapter) & 791 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 792 /* I2C_FUNC_10BIT_ADDR | */ 793 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 794 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 795 } 796 797 static const struct i2c_algorithm gmbus_algorithm = { 798 .master_xfer = gmbus_xfer, 799 .functionality = gmbus_func 800 }; 801 802 static void gmbus_lock_bus(struct i2c_adapter *adapter, 803 unsigned int flags) 804 { 805 struct intel_gmbus *bus = to_intel_gmbus(adapter); 806 struct drm_i915_private *dev_priv = bus->dev_priv; 807 808 mutex_lock(&dev_priv->gmbus_mutex); 809 } 810 811 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 812 unsigned int flags) 813 { 814 struct intel_gmbus *bus = to_intel_gmbus(adapter); 815 struct drm_i915_private *dev_priv = bus->dev_priv; 816 817 return mutex_trylock(&dev_priv->gmbus_mutex); 818 } 819 820 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 821 unsigned int flags) 822 { 823 struct intel_gmbus *bus = to_intel_gmbus(adapter); 824 struct drm_i915_private *dev_priv = bus->dev_priv; 825 826 mutex_unlock(&dev_priv->gmbus_mutex); 827 } 828 829 static const struct i2c_lock_operations gmbus_lock_ops = { 830 .lock_bus = gmbus_lock_bus, 831 .trylock_bus = gmbus_trylock_bus, 832 .unlock_bus = gmbus_unlock_bus, 833 }; 834 835 /** 836 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 837 * @dev_priv: i915 device private 838 */ 839 int intel_gmbus_setup(struct drm_i915_private *dev_priv) 840 { 841 struct pci_dev *pdev = dev_priv->drm.pdev; 842 struct intel_gmbus *bus; 843 unsigned int pin; 844 int ret; 845 846 if (!HAS_DISPLAY(dev_priv)) 847 return 0; 848 849 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 850 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 851 else if (!HAS_GMCH(dev_priv)) 852 /* 853 * Broxton uses the same PCH offsets for South Display Engine, 854 * even though it doesn't have a PCH. 855 */ 856 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; 857 858 mutex_init(&dev_priv->gmbus_mutex); 859 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 860 861 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 862 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 863 continue; 864 865 bus = &dev_priv->gmbus[pin]; 866 867 bus->adapter.owner = THIS_MODULE; 868 bus->adapter.class = I2C_CLASS_DDC; 869 snprintf(bus->adapter.name, 870 sizeof(bus->adapter.name), 871 "i915 gmbus %s", 872 get_gmbus_pin(dev_priv, pin)->name); 873 874 bus->adapter.dev.parent = &pdev->dev; 875 bus->dev_priv = dev_priv; 876 877 bus->adapter.algo = &gmbus_algorithm; 878 bus->adapter.lock_ops = &gmbus_lock_ops; 879 880 /* 881 * We wish to retry with bit banging 882 * after a timed out GMBUS attempt. 883 */ 884 bus->adapter.retries = 1; 885 886 /* By default use a conservative clock rate */ 887 bus->reg0 = pin | GMBUS_RATE_100KHZ; 888 889 /* gmbus seems to be broken on i830 */ 890 if (IS_I830(dev_priv)) 891 bus->force_bit = 1; 892 893 intel_gpio_setup(bus, pin); 894 895 ret = i2c_add_adapter(&bus->adapter); 896 if (ret) 897 goto err; 898 } 899 900 intel_gmbus_reset(dev_priv); 901 902 return 0; 903 904 err: 905 while (pin--) { 906 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 907 continue; 908 909 bus = &dev_priv->gmbus[pin]; 910 i2c_del_adapter(&bus->adapter); 911 } 912 return ret; 913 } 914 915 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 916 unsigned int pin) 917 { 918 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) 919 return NULL; 920 921 return &dev_priv->gmbus[pin].adapter; 922 } 923 924 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) 925 { 926 struct intel_gmbus *bus = to_intel_gmbus(adapter); 927 928 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 929 } 930 931 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 932 { 933 struct intel_gmbus *bus = to_intel_gmbus(adapter); 934 struct drm_i915_private *dev_priv = bus->dev_priv; 935 936 mutex_lock(&dev_priv->gmbus_mutex); 937 938 bus->force_bit += force_bit ? 1 : -1; 939 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 940 force_bit ? "en" : "dis", adapter->name, 941 bus->force_bit); 942 943 mutex_unlock(&dev_priv->gmbus_mutex); 944 } 945 946 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 947 { 948 struct intel_gmbus *bus = to_intel_gmbus(adapter); 949 950 return bus->force_bit; 951 } 952 953 void intel_gmbus_teardown(struct drm_i915_private *dev_priv) 954 { 955 struct intel_gmbus *bus; 956 unsigned int pin; 957 958 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 959 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 960 continue; 961 962 bus = &dev_priv->gmbus[pin]; 963 i2c_del_adapter(&bus->adapter); 964 } 965 } 966