1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/drm_hdcp.h> 35 #include <drm/i915_drm.h> 36 37 #include "i915_drv.h" 38 #include "intel_drv.h" 39 #include "intel_gmbus.h" 40 41 struct gmbus_pin { 42 const char *name; 43 enum i915_gpio gpio; 44 }; 45 46 /* Map gmbus pin pairs to names and registers. */ 47 static const struct gmbus_pin gmbus_pins[] = { 48 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 49 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 50 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 51 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 52 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 53 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 54 }; 55 56 static const struct gmbus_pin gmbus_pins_bdw[] = { 57 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 58 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 59 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 60 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 61 }; 62 63 static const struct gmbus_pin gmbus_pins_skl[] = { 64 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 65 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 66 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 67 }; 68 69 static const struct gmbus_pin gmbus_pins_bxt[] = { 70 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 71 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 72 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 73 }; 74 75 static const struct gmbus_pin gmbus_pins_cnp[] = { 76 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 77 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 78 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 79 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 80 }; 81 82 static const struct gmbus_pin gmbus_pins_icp[] = { 83 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 84 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 85 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 86 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 87 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 88 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 89 }; 90 91 static const struct gmbus_pin gmbus_pins_mcc[] = { 92 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 93 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 94 [GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ }, 95 }; 96 97 static const struct gmbus_pin gmbus_pins_tgp[] = { 98 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 99 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 100 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 101 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 102 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 103 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 104 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 105 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 106 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 107 }; 108 109 /* pin is expected to be valid */ 110 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, 111 unsigned int pin) 112 { 113 if (HAS_PCH_TGP(dev_priv)) 114 return &gmbus_pins_tgp[pin]; 115 else if (HAS_PCH_MCC(dev_priv)) 116 return &gmbus_pins_mcc[pin]; 117 else if (HAS_PCH_ICP(dev_priv)) 118 return &gmbus_pins_icp[pin]; 119 else if (HAS_PCH_CNP(dev_priv)) 120 return &gmbus_pins_cnp[pin]; 121 else if (IS_GEN9_LP(dev_priv)) 122 return &gmbus_pins_bxt[pin]; 123 else if (IS_GEN9_BC(dev_priv)) 124 return &gmbus_pins_skl[pin]; 125 else if (IS_BROADWELL(dev_priv)) 126 return &gmbus_pins_bdw[pin]; 127 else 128 return &gmbus_pins[pin]; 129 } 130 131 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 132 unsigned int pin) 133 { 134 unsigned int size; 135 136 if (HAS_PCH_TGP(dev_priv)) 137 size = ARRAY_SIZE(gmbus_pins_tgp); 138 else if (HAS_PCH_MCC(dev_priv)) 139 size = ARRAY_SIZE(gmbus_pins_mcc); 140 else if (HAS_PCH_ICP(dev_priv)) 141 size = ARRAY_SIZE(gmbus_pins_icp); 142 else if (HAS_PCH_CNP(dev_priv)) 143 size = ARRAY_SIZE(gmbus_pins_cnp); 144 else if (IS_GEN9_LP(dev_priv)) 145 size = ARRAY_SIZE(gmbus_pins_bxt); 146 else if (IS_GEN9_BC(dev_priv)) 147 size = ARRAY_SIZE(gmbus_pins_skl); 148 else if (IS_BROADWELL(dev_priv)) 149 size = ARRAY_SIZE(gmbus_pins_bdw); 150 else 151 size = ARRAY_SIZE(gmbus_pins); 152 153 return pin < size && get_gmbus_pin(dev_priv, pin)->name; 154 } 155 156 /* Intel GPIO access functions */ 157 158 #define I2C_RISEFALL_TIME 10 159 160 static inline struct intel_gmbus * 161 to_intel_gmbus(struct i2c_adapter *i2c) 162 { 163 return container_of(i2c, struct intel_gmbus, adapter); 164 } 165 166 void 167 intel_gmbus_reset(struct drm_i915_private *dev_priv) 168 { 169 I915_WRITE(GMBUS0, 0); 170 I915_WRITE(GMBUS4, 0); 171 } 172 173 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, 174 bool enable) 175 { 176 u32 val; 177 178 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 179 val = I915_READ(DSPCLK_GATE_D); 180 if (!enable) 181 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 182 else 183 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 184 I915_WRITE(DSPCLK_GATE_D, val); 185 } 186 187 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, 188 bool enable) 189 { 190 u32 val; 191 192 val = I915_READ(SOUTH_DSPCLK_GATE_D); 193 if (!enable) 194 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 195 else 196 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 197 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 198 } 199 200 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, 201 bool enable) 202 { 203 u32 val; 204 205 val = I915_READ(GEN9_CLKGATE_DIS_4); 206 if (!enable) 207 val |= BXT_GMBUS_GATING_DIS; 208 else 209 val &= ~BXT_GMBUS_GATING_DIS; 210 I915_WRITE(GEN9_CLKGATE_DIS_4, val); 211 } 212 213 static u32 get_reserved(struct intel_gmbus *bus) 214 { 215 struct drm_i915_private *i915 = bus->dev_priv; 216 struct intel_uncore *uncore = &i915->uncore; 217 u32 reserved = 0; 218 219 /* On most chips, these bits must be preserved in software. */ 220 if (!IS_I830(i915) && !IS_I845G(i915)) 221 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 222 (GPIO_DATA_PULLUP_DISABLE | 223 GPIO_CLOCK_PULLUP_DISABLE); 224 225 return reserved; 226 } 227 228 static int get_clock(void *data) 229 { 230 struct intel_gmbus *bus = data; 231 struct intel_uncore *uncore = &bus->dev_priv->uncore; 232 u32 reserved = get_reserved(bus); 233 234 intel_uncore_write_notrace(uncore, 235 bus->gpio_reg, 236 reserved | GPIO_CLOCK_DIR_MASK); 237 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 238 239 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 240 GPIO_CLOCK_VAL_IN) != 0; 241 } 242 243 static int get_data(void *data) 244 { 245 struct intel_gmbus *bus = data; 246 struct intel_uncore *uncore = &bus->dev_priv->uncore; 247 u32 reserved = get_reserved(bus); 248 249 intel_uncore_write_notrace(uncore, 250 bus->gpio_reg, 251 reserved | GPIO_DATA_DIR_MASK); 252 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 253 254 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 255 GPIO_DATA_VAL_IN) != 0; 256 } 257 258 static void set_clock(void *data, int state_high) 259 { 260 struct intel_gmbus *bus = data; 261 struct intel_uncore *uncore = &bus->dev_priv->uncore; 262 u32 reserved = get_reserved(bus); 263 u32 clock_bits; 264 265 if (state_high) 266 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 267 else 268 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 269 GPIO_CLOCK_VAL_MASK; 270 271 intel_uncore_write_notrace(uncore, 272 bus->gpio_reg, 273 reserved | clock_bits); 274 intel_uncore_posting_read(uncore, bus->gpio_reg); 275 } 276 277 static void set_data(void *data, int state_high) 278 { 279 struct intel_gmbus *bus = data; 280 struct intel_uncore *uncore = &bus->dev_priv->uncore; 281 u32 reserved = get_reserved(bus); 282 u32 data_bits; 283 284 if (state_high) 285 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 286 else 287 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 288 GPIO_DATA_VAL_MASK; 289 290 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 291 intel_uncore_posting_read(uncore, bus->gpio_reg); 292 } 293 294 static int 295 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 296 { 297 struct intel_gmbus *bus = container_of(adapter, 298 struct intel_gmbus, 299 adapter); 300 struct drm_i915_private *dev_priv = bus->dev_priv; 301 302 intel_gmbus_reset(dev_priv); 303 304 if (IS_PINEVIEW(dev_priv)) 305 pnv_gmbus_clock_gating(dev_priv, false); 306 307 set_data(bus, 1); 308 set_clock(bus, 1); 309 udelay(I2C_RISEFALL_TIME); 310 return 0; 311 } 312 313 static void 314 intel_gpio_post_xfer(struct i2c_adapter *adapter) 315 { 316 struct intel_gmbus *bus = container_of(adapter, 317 struct intel_gmbus, 318 adapter); 319 struct drm_i915_private *dev_priv = bus->dev_priv; 320 321 set_data(bus, 1); 322 set_clock(bus, 1); 323 324 if (IS_PINEVIEW(dev_priv)) 325 pnv_gmbus_clock_gating(dev_priv, true); 326 } 327 328 static void 329 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) 330 { 331 struct drm_i915_private *dev_priv = bus->dev_priv; 332 struct i2c_algo_bit_data *algo; 333 334 algo = &bus->bit_algo; 335 336 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); 337 bus->adapter.algo_data = algo; 338 algo->setsda = set_data; 339 algo->setscl = set_clock; 340 algo->getsda = get_data; 341 algo->getscl = get_clock; 342 algo->pre_xfer = intel_gpio_pre_xfer; 343 algo->post_xfer = intel_gpio_post_xfer; 344 algo->udelay = I2C_RISEFALL_TIME; 345 algo->timeout = usecs_to_jiffies(2200); 346 algo->data = bus; 347 } 348 349 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 350 { 351 DEFINE_WAIT(wait); 352 u32 gmbus2; 353 int ret; 354 355 /* Important: The hw handles only the first bit, so set only one! Since 356 * we also need to check for NAKs besides the hw ready/idle signal, we 357 * need to wake up periodically and check that ourselves. 358 */ 359 if (!HAS_GMBUS_IRQ(dev_priv)) 360 irq_en = 0; 361 362 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 363 I915_WRITE_FW(GMBUS4, irq_en); 364 365 status |= GMBUS_SATOER; 366 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); 367 if (ret) 368 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); 369 370 I915_WRITE_FW(GMBUS4, 0); 371 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 372 373 if (gmbus2 & GMBUS_SATOER) 374 return -ENXIO; 375 376 return ret; 377 } 378 379 static int 380 gmbus_wait_idle(struct drm_i915_private *dev_priv) 381 { 382 DEFINE_WAIT(wait); 383 u32 irq_enable; 384 int ret; 385 386 /* Important: The hw handles only the first bit, so set only one! */ 387 irq_enable = 0; 388 if (HAS_GMBUS_IRQ(dev_priv)) 389 irq_enable = GMBUS_IDLE_EN; 390 391 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 392 I915_WRITE_FW(GMBUS4, irq_enable); 393 394 ret = intel_wait_for_register_fw(&dev_priv->uncore, 395 GMBUS2, GMBUS_ACTIVE, 0, 396 10); 397 398 I915_WRITE_FW(GMBUS4, 0); 399 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 400 401 return ret; 402 } 403 404 static inline 405 unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) 406 { 407 return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 408 GMBUS_BYTE_COUNT_MAX; 409 } 410 411 static int 412 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 413 unsigned short addr, u8 *buf, unsigned int len, 414 u32 gmbus0_reg, u32 gmbus1_index) 415 { 416 unsigned int size = len; 417 bool burst_read = len > gmbus_max_xfer_size(dev_priv); 418 bool extra_byte_added = false; 419 420 if (burst_read) { 421 /* 422 * As per HW Spec, for 512Bytes need to read extra Byte and 423 * Ignore the extra byte read. 424 */ 425 if (len == 512) { 426 extra_byte_added = true; 427 len++; 428 } 429 size = len % 256 + 256; 430 I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 431 } 432 433 I915_WRITE_FW(GMBUS1, 434 gmbus1_index | 435 GMBUS_CYCLE_WAIT | 436 (size << GMBUS_BYTE_COUNT_SHIFT) | 437 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 438 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 439 while (len) { 440 int ret; 441 u32 val, loop = 0; 442 443 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 444 if (ret) 445 return ret; 446 447 val = I915_READ_FW(GMBUS3); 448 do { 449 if (extra_byte_added && len == 1) 450 break; 451 452 *buf++ = val & 0xff; 453 val >>= 8; 454 } while (--len && ++loop < 4); 455 456 if (burst_read && len == size - 4) 457 /* Reset the override bit */ 458 I915_WRITE_FW(GMBUS0, gmbus0_reg); 459 } 460 461 return 0; 462 } 463 464 /* 465 * HW spec says that 512Bytes in Burst read need special treatment. 466 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 467 * an I2C slave, which supports such a lengthy burst read too for experiments. 468 * 469 * So until things get clarified on HW support, to avoid the burst read length 470 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 471 */ 472 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 473 474 static int 475 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 476 u32 gmbus0_reg, u32 gmbus1_index) 477 { 478 u8 *buf = msg->buf; 479 unsigned int rx_size = msg->len; 480 unsigned int len; 481 int ret; 482 483 do { 484 if (HAS_GMBUS_BURST_READ(dev_priv)) 485 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 486 else 487 len = min(rx_size, gmbus_max_xfer_size(dev_priv)); 488 489 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, 490 gmbus0_reg, gmbus1_index); 491 if (ret) 492 return ret; 493 494 rx_size -= len; 495 buf += len; 496 } while (rx_size != 0); 497 498 return 0; 499 } 500 501 static int 502 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 503 unsigned short addr, u8 *buf, unsigned int len, 504 u32 gmbus1_index) 505 { 506 unsigned int chunk_size = len; 507 u32 val, loop; 508 509 val = loop = 0; 510 while (len && loop < 4) { 511 val |= *buf++ << (8 * loop++); 512 len -= 1; 513 } 514 515 I915_WRITE_FW(GMBUS3, val); 516 I915_WRITE_FW(GMBUS1, 517 gmbus1_index | GMBUS_CYCLE_WAIT | 518 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | 519 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 520 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 521 while (len) { 522 int ret; 523 524 val = loop = 0; 525 do { 526 val |= *buf++ << (8 * loop); 527 } while (--len && ++loop < 4); 528 529 I915_WRITE_FW(GMBUS3, val); 530 531 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 532 if (ret) 533 return ret; 534 } 535 536 return 0; 537 } 538 539 static int 540 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 541 u32 gmbus1_index) 542 { 543 u8 *buf = msg->buf; 544 unsigned int tx_size = msg->len; 545 unsigned int len; 546 int ret; 547 548 do { 549 len = min(tx_size, gmbus_max_xfer_size(dev_priv)); 550 551 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, 552 gmbus1_index); 553 if (ret) 554 return ret; 555 556 buf += len; 557 tx_size -= len; 558 } while (tx_size != 0); 559 560 return 0; 561 } 562 563 /* 564 * The gmbus controller can combine a 1 or 2 byte write with another read/write 565 * that immediately follows it by using an "INDEX" cycle. 566 */ 567 static bool 568 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 569 { 570 return (i + 1 < num && 571 msgs[i].addr == msgs[i + 1].addr && 572 !(msgs[i].flags & I2C_M_RD) && 573 (msgs[i].len == 1 || msgs[i].len == 2) && 574 msgs[i + 1].len > 0); 575 } 576 577 static int 578 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, 579 u32 gmbus0_reg) 580 { 581 u32 gmbus1_index = 0; 582 u32 gmbus5 = 0; 583 int ret; 584 585 if (msgs[0].len == 2) 586 gmbus5 = GMBUS_2BYTE_INDEX_EN | 587 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 588 if (msgs[0].len == 1) 589 gmbus1_index = GMBUS_CYCLE_INDEX | 590 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 591 592 /* GMBUS5 holds 16-bit index */ 593 if (gmbus5) 594 I915_WRITE_FW(GMBUS5, gmbus5); 595 596 if (msgs[1].flags & I2C_M_RD) 597 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, 598 gmbus1_index); 599 else 600 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); 601 602 /* Clear GMBUS5 after each index transfer */ 603 if (gmbus5) 604 I915_WRITE_FW(GMBUS5, 0); 605 606 return ret; 607 } 608 609 static int 610 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 611 u32 gmbus0_source) 612 { 613 struct intel_gmbus *bus = container_of(adapter, 614 struct intel_gmbus, 615 adapter); 616 struct drm_i915_private *dev_priv = bus->dev_priv; 617 int i = 0, inc, try = 0; 618 int ret = 0; 619 620 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ 621 if (IS_GEN9_LP(dev_priv)) 622 bxt_gmbus_clock_gating(dev_priv, false); 623 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 624 pch_gmbus_clock_gating(dev_priv, false); 625 626 retry: 627 I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); 628 629 for (; i < num; i += inc) { 630 inc = 1; 631 if (gmbus_is_index_xfer(msgs, i, num)) { 632 ret = gmbus_index_xfer(dev_priv, &msgs[i], 633 gmbus0_source | bus->reg0); 634 inc = 2; /* an index transmission is two msgs */ 635 } else if (msgs[i].flags & I2C_M_RD) { 636 ret = gmbus_xfer_read(dev_priv, &msgs[i], 637 gmbus0_source | bus->reg0, 0); 638 } else { 639 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); 640 } 641 642 if (!ret) 643 ret = gmbus_wait(dev_priv, 644 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 645 if (ret == -ETIMEDOUT) 646 goto timeout; 647 else if (ret) 648 goto clear_err; 649 } 650 651 /* Generate a STOP condition on the bus. Note that gmbus can't generata 652 * a STOP on the very first cycle. To simplify the code we 653 * unconditionally generate the STOP condition with an additional gmbus 654 * cycle. */ 655 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 656 657 /* Mark the GMBUS interface as disabled after waiting for idle. 658 * We will re-enable it at the start of the next xfer, 659 * till then let it sleep. 660 */ 661 if (gmbus_wait_idle(dev_priv)) { 662 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 663 adapter->name); 664 ret = -ETIMEDOUT; 665 } 666 I915_WRITE_FW(GMBUS0, 0); 667 ret = ret ?: i; 668 goto out; 669 670 clear_err: 671 /* 672 * Wait for bus to IDLE before clearing NAK. 673 * If we clear the NAK while bus is still active, then it will stay 674 * active and the next transaction may fail. 675 * 676 * If no ACK is received during the address phase of a transaction, the 677 * adapter must report -ENXIO. It is not clear what to return if no ACK 678 * is received at other times. But we have to be careful to not return 679 * spurious -ENXIO because that will prevent i2c and drm edid functions 680 * from retrying. So return -ENXIO only when gmbus properly quiescents - 681 * timing out seems to happen when there _is_ a ddc chip present, but 682 * it's slow responding and only answers on the 2nd retry. 683 */ 684 ret = -ENXIO; 685 if (gmbus_wait_idle(dev_priv)) { 686 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 687 adapter->name); 688 ret = -ETIMEDOUT; 689 } 690 691 /* Toggle the Software Clear Interrupt bit. This has the effect 692 * of resetting the GMBUS controller and so clearing the 693 * BUS_ERROR raised by the slave's NAK. 694 */ 695 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); 696 I915_WRITE_FW(GMBUS1, 0); 697 I915_WRITE_FW(GMBUS0, 0); 698 699 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 700 adapter->name, msgs[i].addr, 701 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 702 703 /* 704 * Passive adapters sometimes NAK the first probe. Retry the first 705 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 706 * has retries internally. See also the retry loop in 707 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 708 */ 709 if (ret == -ENXIO && i == 0 && try++ == 0) { 710 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", 711 adapter->name); 712 goto retry; 713 } 714 715 goto out; 716 717 timeout: 718 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 719 bus->adapter.name, bus->reg0 & 0xff); 720 I915_WRITE_FW(GMBUS0, 0); 721 722 /* 723 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 724 * instead. Use EAGAIN to have i2c core retry. 725 */ 726 ret = -EAGAIN; 727 728 out: 729 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ 730 if (IS_GEN9_LP(dev_priv)) 731 bxt_gmbus_clock_gating(dev_priv, true); 732 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 733 pch_gmbus_clock_gating(dev_priv, true); 734 735 return ret; 736 } 737 738 static int 739 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 740 { 741 struct intel_gmbus *bus = 742 container_of(adapter, struct intel_gmbus, adapter); 743 struct drm_i915_private *dev_priv = bus->dev_priv; 744 intel_wakeref_t wakeref; 745 int ret; 746 747 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 748 749 if (bus->force_bit) { 750 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 751 if (ret < 0) 752 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 753 } else { 754 ret = do_gmbus_xfer(adapter, msgs, num, 0); 755 if (ret == -EAGAIN) 756 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 757 } 758 759 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 760 761 return ret; 762 } 763 764 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 765 { 766 struct intel_gmbus *bus = 767 container_of(adapter, struct intel_gmbus, adapter); 768 struct drm_i915_private *dev_priv = bus->dev_priv; 769 u8 cmd = DRM_HDCP_DDC_AKSV; 770 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 771 struct i2c_msg msgs[] = { 772 { 773 .addr = DRM_HDCP_DDC_ADDR, 774 .flags = 0, 775 .len = sizeof(cmd), 776 .buf = &cmd, 777 }, 778 { 779 .addr = DRM_HDCP_DDC_ADDR, 780 .flags = 0, 781 .len = sizeof(buf), 782 .buf = buf, 783 } 784 }; 785 intel_wakeref_t wakeref; 786 int ret; 787 788 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 789 mutex_lock(&dev_priv->gmbus_mutex); 790 791 /* 792 * In order to output Aksv to the receiver, use an indexed write to 793 * pass the i2c command, and tell GMBUS to use the HW-provided value 794 * instead of sourcing GMBUS3 for the data. 795 */ 796 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 797 798 mutex_unlock(&dev_priv->gmbus_mutex); 799 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 800 801 return ret; 802 } 803 804 static u32 gmbus_func(struct i2c_adapter *adapter) 805 { 806 return i2c_bit_algo.functionality(adapter) & 807 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 808 /* I2C_FUNC_10BIT_ADDR | */ 809 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 810 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 811 } 812 813 static const struct i2c_algorithm gmbus_algorithm = { 814 .master_xfer = gmbus_xfer, 815 .functionality = gmbus_func 816 }; 817 818 static void gmbus_lock_bus(struct i2c_adapter *adapter, 819 unsigned int flags) 820 { 821 struct intel_gmbus *bus = to_intel_gmbus(adapter); 822 struct drm_i915_private *dev_priv = bus->dev_priv; 823 824 mutex_lock(&dev_priv->gmbus_mutex); 825 } 826 827 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 828 unsigned int flags) 829 { 830 struct intel_gmbus *bus = to_intel_gmbus(adapter); 831 struct drm_i915_private *dev_priv = bus->dev_priv; 832 833 return mutex_trylock(&dev_priv->gmbus_mutex); 834 } 835 836 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 837 unsigned int flags) 838 { 839 struct intel_gmbus *bus = to_intel_gmbus(adapter); 840 struct drm_i915_private *dev_priv = bus->dev_priv; 841 842 mutex_unlock(&dev_priv->gmbus_mutex); 843 } 844 845 static const struct i2c_lock_operations gmbus_lock_ops = { 846 .lock_bus = gmbus_lock_bus, 847 .trylock_bus = gmbus_trylock_bus, 848 .unlock_bus = gmbus_unlock_bus, 849 }; 850 851 /** 852 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 853 * @dev_priv: i915 device private 854 */ 855 int intel_gmbus_setup(struct drm_i915_private *dev_priv) 856 { 857 struct pci_dev *pdev = dev_priv->drm.pdev; 858 struct intel_gmbus *bus; 859 unsigned int pin; 860 int ret; 861 862 if (!HAS_DISPLAY(dev_priv)) 863 return 0; 864 865 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 866 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 867 else if (!HAS_GMCH(dev_priv)) 868 /* 869 * Broxton uses the same PCH offsets for South Display Engine, 870 * even though it doesn't have a PCH. 871 */ 872 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; 873 874 mutex_init(&dev_priv->gmbus_mutex); 875 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 876 877 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 878 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 879 continue; 880 881 bus = &dev_priv->gmbus[pin]; 882 883 bus->adapter.owner = THIS_MODULE; 884 bus->adapter.class = I2C_CLASS_DDC; 885 snprintf(bus->adapter.name, 886 sizeof(bus->adapter.name), 887 "i915 gmbus %s", 888 get_gmbus_pin(dev_priv, pin)->name); 889 890 bus->adapter.dev.parent = &pdev->dev; 891 bus->dev_priv = dev_priv; 892 893 bus->adapter.algo = &gmbus_algorithm; 894 bus->adapter.lock_ops = &gmbus_lock_ops; 895 896 /* 897 * We wish to retry with bit banging 898 * after a timed out GMBUS attempt. 899 */ 900 bus->adapter.retries = 1; 901 902 /* By default use a conservative clock rate */ 903 bus->reg0 = pin | GMBUS_RATE_100KHZ; 904 905 /* gmbus seems to be broken on i830 */ 906 if (IS_I830(dev_priv)) 907 bus->force_bit = 1; 908 909 intel_gpio_setup(bus, pin); 910 911 ret = i2c_add_adapter(&bus->adapter); 912 if (ret) 913 goto err; 914 } 915 916 intel_gmbus_reset(dev_priv); 917 918 return 0; 919 920 err: 921 while (pin--) { 922 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 923 continue; 924 925 bus = &dev_priv->gmbus[pin]; 926 i2c_del_adapter(&bus->adapter); 927 } 928 return ret; 929 } 930 931 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 932 unsigned int pin) 933 { 934 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) 935 return NULL; 936 937 return &dev_priv->gmbus[pin].adapter; 938 } 939 940 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) 941 { 942 struct intel_gmbus *bus = to_intel_gmbus(adapter); 943 944 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 945 } 946 947 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 948 { 949 struct intel_gmbus *bus = to_intel_gmbus(adapter); 950 struct drm_i915_private *dev_priv = bus->dev_priv; 951 952 mutex_lock(&dev_priv->gmbus_mutex); 953 954 bus->force_bit += force_bit ? 1 : -1; 955 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 956 force_bit ? "en" : "dis", adapter->name, 957 bus->force_bit); 958 959 mutex_unlock(&dev_priv->gmbus_mutex); 960 } 961 962 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 963 { 964 struct intel_gmbus *bus = to_intel_gmbus(adapter); 965 966 return bus->force_bit; 967 } 968 969 void intel_gmbus_teardown(struct drm_i915_private *dev_priv) 970 { 971 struct intel_gmbus *bus; 972 unsigned int pin; 973 974 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 975 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 976 continue; 977 978 bus = &dev_priv->gmbus[pin]; 979 i2c_del_adapter(&bus->adapter); 980 } 981 } 982