1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/display/drm_hdcp_helper.h> 35 36 #include "i915_drv.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_gmbus.h" 40 #include "intel_gmbus_regs.h" 41 42 struct intel_gmbus { 43 struct i2c_adapter adapter; 44 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 45 u32 force_bit; 46 u32 reg0; 47 i915_reg_t gpio_reg; 48 struct i2c_algo_bit_data bit_algo; 49 struct drm_i915_private *i915; 50 }; 51 52 struct gmbus_pin { 53 const char *name; 54 enum i915_gpio gpio; 55 }; 56 57 /* Map gmbus pin pairs to names and registers. */ 58 static const struct gmbus_pin gmbus_pins[] = { 59 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 60 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 61 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 62 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 63 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 64 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 65 }; 66 67 static const struct gmbus_pin gmbus_pins_bdw[] = { 68 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 69 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 70 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 71 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 72 }; 73 74 static const struct gmbus_pin gmbus_pins_skl[] = { 75 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 76 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 77 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 78 }; 79 80 static const struct gmbus_pin gmbus_pins_bxt[] = { 81 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 82 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 83 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 84 }; 85 86 static const struct gmbus_pin gmbus_pins_cnp[] = { 87 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 88 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 89 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 90 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 91 }; 92 93 static const struct gmbus_pin gmbus_pins_icp[] = { 94 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 95 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 96 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 97 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 98 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 99 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 100 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 101 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 102 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 103 }; 104 105 static const struct gmbus_pin gmbus_pins_dg1[] = { 106 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 107 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 108 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 109 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 110 }; 111 112 static const struct gmbus_pin gmbus_pins_dg2[] = { 113 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 114 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 115 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 116 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 117 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 118 }; 119 120 static const struct gmbus_pin gmbus_pins_mtp[] = { 121 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 122 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 123 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 124 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 125 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 126 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 127 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 128 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 129 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 130 }; 131 132 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 133 unsigned int pin) 134 { 135 const struct gmbus_pin *pins; 136 size_t size; 137 138 if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { 139 pins = gmbus_pins_dg2; 140 size = ARRAY_SIZE(gmbus_pins_dg2); 141 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 142 pins = gmbus_pins_dg1; 143 size = ARRAY_SIZE(gmbus_pins_dg1); 144 } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) { 145 pins = gmbus_pins_mtp; 146 size = ARRAY_SIZE(gmbus_pins_mtp); 147 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 148 pins = gmbus_pins_icp; 149 size = ARRAY_SIZE(gmbus_pins_icp); 150 } else if (HAS_PCH_CNP(i915)) { 151 pins = gmbus_pins_cnp; 152 size = ARRAY_SIZE(gmbus_pins_cnp); 153 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 154 pins = gmbus_pins_bxt; 155 size = ARRAY_SIZE(gmbus_pins_bxt); 156 } else if (DISPLAY_VER(i915) == 9) { 157 pins = gmbus_pins_skl; 158 size = ARRAY_SIZE(gmbus_pins_skl); 159 } else if (IS_BROADWELL(i915)) { 160 pins = gmbus_pins_bdw; 161 size = ARRAY_SIZE(gmbus_pins_bdw); 162 } else { 163 pins = gmbus_pins; 164 size = ARRAY_SIZE(gmbus_pins); 165 } 166 167 if (pin >= size || !pins[pin].name) 168 return NULL; 169 170 return &pins[pin]; 171 } 172 173 bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin) 174 { 175 return get_gmbus_pin(i915, pin); 176 } 177 178 /* Intel GPIO access functions */ 179 180 #define I2C_RISEFALL_TIME 10 181 182 static inline struct intel_gmbus * 183 to_intel_gmbus(struct i2c_adapter *i2c) 184 { 185 return container_of(i2c, struct intel_gmbus, adapter); 186 } 187 188 void 189 intel_gmbus_reset(struct drm_i915_private *i915) 190 { 191 intel_de_write(i915, GMBUS0(i915), 0); 192 intel_de_write(i915, GMBUS4(i915), 0); 193 } 194 195 static void pnv_gmbus_clock_gating(struct drm_i915_private *i915, 196 bool enable) 197 { 198 u32 val; 199 200 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 201 val = intel_de_read(i915, DSPCLK_GATE_D(i915)); 202 if (!enable) 203 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 204 else 205 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 206 intel_de_write(i915, DSPCLK_GATE_D(i915), val); 207 } 208 209 static void pch_gmbus_clock_gating(struct drm_i915_private *i915, 210 bool enable) 211 { 212 u32 val; 213 214 val = intel_de_read(i915, SOUTH_DSPCLK_GATE_D); 215 if (!enable) 216 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 217 else 218 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 219 intel_de_write(i915, SOUTH_DSPCLK_GATE_D, val); 220 } 221 222 static void bxt_gmbus_clock_gating(struct drm_i915_private *i915, 223 bool enable) 224 { 225 u32 val; 226 227 val = intel_de_read(i915, GEN9_CLKGATE_DIS_4); 228 if (!enable) 229 val |= BXT_GMBUS_GATING_DIS; 230 else 231 val &= ~BXT_GMBUS_GATING_DIS; 232 intel_de_write(i915, GEN9_CLKGATE_DIS_4, val); 233 } 234 235 static u32 get_reserved(struct intel_gmbus *bus) 236 { 237 struct drm_i915_private *i915 = bus->i915; 238 struct intel_uncore *uncore = &i915->uncore; 239 u32 reserved = 0; 240 241 /* On most chips, these bits must be preserved in software. */ 242 if (!IS_I830(i915) && !IS_I845G(i915)) 243 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 244 (GPIO_DATA_PULLUP_DISABLE | 245 GPIO_CLOCK_PULLUP_DISABLE); 246 247 return reserved; 248 } 249 250 static int get_clock(void *data) 251 { 252 struct intel_gmbus *bus = data; 253 struct intel_uncore *uncore = &bus->i915->uncore; 254 u32 reserved = get_reserved(bus); 255 256 intel_uncore_write_notrace(uncore, 257 bus->gpio_reg, 258 reserved | GPIO_CLOCK_DIR_MASK); 259 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 260 261 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 262 GPIO_CLOCK_VAL_IN) != 0; 263 } 264 265 static int get_data(void *data) 266 { 267 struct intel_gmbus *bus = data; 268 struct intel_uncore *uncore = &bus->i915->uncore; 269 u32 reserved = get_reserved(bus); 270 271 intel_uncore_write_notrace(uncore, 272 bus->gpio_reg, 273 reserved | GPIO_DATA_DIR_MASK); 274 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 275 276 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 277 GPIO_DATA_VAL_IN) != 0; 278 } 279 280 static void set_clock(void *data, int state_high) 281 { 282 struct intel_gmbus *bus = data; 283 struct intel_uncore *uncore = &bus->i915->uncore; 284 u32 reserved = get_reserved(bus); 285 u32 clock_bits; 286 287 if (state_high) 288 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 289 else 290 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 291 GPIO_CLOCK_VAL_MASK; 292 293 intel_uncore_write_notrace(uncore, 294 bus->gpio_reg, 295 reserved | clock_bits); 296 intel_uncore_posting_read(uncore, bus->gpio_reg); 297 } 298 299 static void set_data(void *data, int state_high) 300 { 301 struct intel_gmbus *bus = data; 302 struct intel_uncore *uncore = &bus->i915->uncore; 303 u32 reserved = get_reserved(bus); 304 u32 data_bits; 305 306 if (state_high) 307 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 308 else 309 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 310 GPIO_DATA_VAL_MASK; 311 312 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 313 intel_uncore_posting_read(uncore, bus->gpio_reg); 314 } 315 316 static int 317 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 318 { 319 struct intel_gmbus *bus = to_intel_gmbus(adapter); 320 struct drm_i915_private *i915 = bus->i915; 321 322 intel_gmbus_reset(i915); 323 324 if (IS_PINEVIEW(i915)) 325 pnv_gmbus_clock_gating(i915, false); 326 327 set_data(bus, 1); 328 set_clock(bus, 1); 329 udelay(I2C_RISEFALL_TIME); 330 return 0; 331 } 332 333 static void 334 intel_gpio_post_xfer(struct i2c_adapter *adapter) 335 { 336 struct intel_gmbus *bus = to_intel_gmbus(adapter); 337 struct drm_i915_private *i915 = bus->i915; 338 339 set_data(bus, 1); 340 set_clock(bus, 1); 341 342 if (IS_PINEVIEW(i915)) 343 pnv_gmbus_clock_gating(i915, true); 344 } 345 346 static void 347 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 348 { 349 struct i2c_algo_bit_data *algo; 350 351 algo = &bus->bit_algo; 352 353 bus->gpio_reg = gpio_reg; 354 bus->adapter.algo_data = algo; 355 algo->setsda = set_data; 356 algo->setscl = set_clock; 357 algo->getsda = get_data; 358 algo->getscl = get_clock; 359 algo->pre_xfer = intel_gpio_pre_xfer; 360 algo->post_xfer = intel_gpio_post_xfer; 361 algo->udelay = I2C_RISEFALL_TIME; 362 algo->timeout = usecs_to_jiffies(2200); 363 algo->data = bus; 364 } 365 366 static bool has_gmbus_irq(struct drm_i915_private *i915) 367 { 368 /* 369 * encoder->shutdown() may want to use GMBUS 370 * after irqs have already been disabled. 371 */ 372 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); 373 } 374 375 static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en) 376 { 377 DEFINE_WAIT(wait); 378 u32 gmbus2; 379 int ret; 380 381 /* Important: The hw handles only the first bit, so set only one! Since 382 * we also need to check for NAKs besides the hw ready/idle signal, we 383 * need to wake up periodically and check that ourselves. 384 */ 385 if (!has_gmbus_irq(i915)) 386 irq_en = 0; 387 388 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 389 intel_de_write_fw(i915, GMBUS4(i915), irq_en); 390 391 status |= GMBUS_SATOER; 392 ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 393 2); 394 if (ret) 395 ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 396 50); 397 398 intel_de_write_fw(i915, GMBUS4(i915), 0); 399 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 400 401 if (gmbus2 & GMBUS_SATOER) 402 return -ENXIO; 403 404 return ret; 405 } 406 407 static int 408 gmbus_wait_idle(struct drm_i915_private *i915) 409 { 410 DEFINE_WAIT(wait); 411 u32 irq_enable; 412 int ret; 413 414 /* Important: The hw handles only the first bit, so set only one! */ 415 irq_enable = 0; 416 if (has_gmbus_irq(i915)) 417 irq_enable = GMBUS_IDLE_EN; 418 419 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 420 intel_de_write_fw(i915, GMBUS4(i915), irq_enable); 421 422 ret = intel_wait_for_register_fw(&i915->uncore, 423 GMBUS2(i915), GMBUS_ACTIVE, 0, 424 10); 425 426 intel_de_write_fw(i915, GMBUS4(i915), 0); 427 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 428 429 return ret; 430 } 431 432 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915) 433 { 434 return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 435 GMBUS_BYTE_COUNT_MAX; 436 } 437 438 static int 439 gmbus_xfer_read_chunk(struct drm_i915_private *i915, 440 unsigned short addr, u8 *buf, unsigned int len, 441 u32 gmbus0_reg, u32 gmbus1_index) 442 { 443 unsigned int size = len; 444 bool burst_read = len > gmbus_max_xfer_size(i915); 445 bool extra_byte_added = false; 446 447 if (burst_read) { 448 /* 449 * As per HW Spec, for 512Bytes need to read extra Byte and 450 * Ignore the extra byte read. 451 */ 452 if (len == 512) { 453 extra_byte_added = true; 454 len++; 455 } 456 size = len % 256 + 256; 457 intel_de_write_fw(i915, GMBUS0(i915), 458 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 459 } 460 461 intel_de_write_fw(i915, GMBUS1(i915), 462 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 463 while (len) { 464 int ret; 465 u32 val, loop = 0; 466 467 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 468 if (ret) 469 return ret; 470 471 val = intel_de_read_fw(i915, GMBUS3(i915)); 472 do { 473 if (extra_byte_added && len == 1) 474 break; 475 476 *buf++ = val & 0xff; 477 val >>= 8; 478 } while (--len && ++loop < 4); 479 480 if (burst_read && len == size - 4) 481 /* Reset the override bit */ 482 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg); 483 } 484 485 return 0; 486 } 487 488 /* 489 * HW spec says that 512Bytes in Burst read need special treatment. 490 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 491 * an I2C slave, which supports such a lengthy burst read too for experiments. 492 * 493 * So until things get clarified on HW support, to avoid the burst read length 494 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 495 */ 496 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 497 498 static int 499 gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg, 500 u32 gmbus0_reg, u32 gmbus1_index) 501 { 502 u8 *buf = msg->buf; 503 unsigned int rx_size = msg->len; 504 unsigned int len; 505 int ret; 506 507 do { 508 if (HAS_GMBUS_BURST_READ(i915)) 509 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 510 else 511 len = min(rx_size, gmbus_max_xfer_size(i915)); 512 513 ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len, 514 gmbus0_reg, gmbus1_index); 515 if (ret) 516 return ret; 517 518 rx_size -= len; 519 buf += len; 520 } while (rx_size != 0); 521 522 return 0; 523 } 524 525 static int 526 gmbus_xfer_write_chunk(struct drm_i915_private *i915, 527 unsigned short addr, u8 *buf, unsigned int len, 528 u32 gmbus1_index) 529 { 530 unsigned int chunk_size = len; 531 u32 val, loop; 532 533 val = loop = 0; 534 while (len && loop < 4) { 535 val |= *buf++ << (8 * loop++); 536 len -= 1; 537 } 538 539 intel_de_write_fw(i915, GMBUS3(i915), val); 540 intel_de_write_fw(i915, GMBUS1(i915), 541 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 542 while (len) { 543 int ret; 544 545 val = loop = 0; 546 do { 547 val |= *buf++ << (8 * loop); 548 } while (--len && ++loop < 4); 549 550 intel_de_write_fw(i915, GMBUS3(i915), val); 551 552 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 553 if (ret) 554 return ret; 555 } 556 557 return 0; 558 } 559 560 static int 561 gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg, 562 u32 gmbus1_index) 563 { 564 u8 *buf = msg->buf; 565 unsigned int tx_size = msg->len; 566 unsigned int len; 567 int ret; 568 569 do { 570 len = min(tx_size, gmbus_max_xfer_size(i915)); 571 572 ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len, 573 gmbus1_index); 574 if (ret) 575 return ret; 576 577 buf += len; 578 tx_size -= len; 579 } while (tx_size != 0); 580 581 return 0; 582 } 583 584 /* 585 * The gmbus controller can combine a 1 or 2 byte write with another read/write 586 * that immediately follows it by using an "INDEX" cycle. 587 */ 588 static bool 589 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 590 { 591 return (i + 1 < num && 592 msgs[i].addr == msgs[i + 1].addr && 593 !(msgs[i].flags & I2C_M_RD) && 594 (msgs[i].len == 1 || msgs[i].len == 2) && 595 msgs[i + 1].len > 0); 596 } 597 598 static int 599 gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs, 600 u32 gmbus0_reg) 601 { 602 u32 gmbus1_index = 0; 603 u32 gmbus5 = 0; 604 int ret; 605 606 if (msgs[0].len == 2) 607 gmbus5 = GMBUS_2BYTE_INDEX_EN | 608 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 609 if (msgs[0].len == 1) 610 gmbus1_index = GMBUS_CYCLE_INDEX | 611 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 612 613 /* GMBUS5 holds 16-bit index */ 614 if (gmbus5) 615 intel_de_write_fw(i915, GMBUS5(i915), gmbus5); 616 617 if (msgs[1].flags & I2C_M_RD) 618 ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg, 619 gmbus1_index); 620 else 621 ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index); 622 623 /* Clear GMBUS5 after each index transfer */ 624 if (gmbus5) 625 intel_de_write_fw(i915, GMBUS5(i915), 0); 626 627 return ret; 628 } 629 630 static int 631 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 632 u32 gmbus0_source) 633 { 634 struct intel_gmbus *bus = to_intel_gmbus(adapter); 635 struct drm_i915_private *i915 = bus->i915; 636 int i = 0, inc, try = 0; 637 int ret = 0; 638 639 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 640 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 641 bxt_gmbus_clock_gating(i915, false); 642 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 643 pch_gmbus_clock_gating(i915, false); 644 645 retry: 646 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0); 647 648 for (; i < num; i += inc) { 649 inc = 1; 650 if (gmbus_is_index_xfer(msgs, i, num)) { 651 ret = gmbus_index_xfer(i915, &msgs[i], 652 gmbus0_source | bus->reg0); 653 inc = 2; /* an index transmission is two msgs */ 654 } else if (msgs[i].flags & I2C_M_RD) { 655 ret = gmbus_xfer_read(i915, &msgs[i], 656 gmbus0_source | bus->reg0, 0); 657 } else { 658 ret = gmbus_xfer_write(i915, &msgs[i], 0); 659 } 660 661 if (!ret) 662 ret = gmbus_wait(i915, 663 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 664 if (ret == -ETIMEDOUT) 665 goto timeout; 666 else if (ret) 667 goto clear_err; 668 } 669 670 /* Generate a STOP condition on the bus. Note that gmbus can't generata 671 * a STOP on the very first cycle. To simplify the code we 672 * unconditionally generate the STOP condition with an additional gmbus 673 * cycle. */ 674 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 675 676 /* Mark the GMBUS interface as disabled after waiting for idle. 677 * We will re-enable it at the start of the next xfer, 678 * till then let it sleep. 679 */ 680 if (gmbus_wait_idle(i915)) { 681 drm_dbg_kms(&i915->drm, 682 "GMBUS [%s] timed out waiting for idle\n", 683 adapter->name); 684 ret = -ETIMEDOUT; 685 } 686 intel_de_write_fw(i915, GMBUS0(i915), 0); 687 ret = ret ?: i; 688 goto out; 689 690 clear_err: 691 /* 692 * Wait for bus to IDLE before clearing NAK. 693 * If we clear the NAK while bus is still active, then it will stay 694 * active and the next transaction may fail. 695 * 696 * If no ACK is received during the address phase of a transaction, the 697 * adapter must report -ENXIO. It is not clear what to return if no ACK 698 * is received at other times. But we have to be careful to not return 699 * spurious -ENXIO because that will prevent i2c and drm edid functions 700 * from retrying. So return -ENXIO only when gmbus properly quiescents - 701 * timing out seems to happen when there _is_ a ddc chip present, but 702 * it's slow responding and only answers on the 2nd retry. 703 */ 704 ret = -ENXIO; 705 if (gmbus_wait_idle(i915)) { 706 drm_dbg_kms(&i915->drm, 707 "GMBUS [%s] timed out after NAK\n", 708 adapter->name); 709 ret = -ETIMEDOUT; 710 } 711 712 /* Toggle the Software Clear Interrupt bit. This has the effect 713 * of resetting the GMBUS controller and so clearing the 714 * BUS_ERROR raised by the slave's NAK. 715 */ 716 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT); 717 intel_de_write_fw(i915, GMBUS1(i915), 0); 718 intel_de_write_fw(i915, GMBUS0(i915), 0); 719 720 drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 721 adapter->name, msgs[i].addr, 722 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 723 724 /* 725 * Passive adapters sometimes NAK the first probe. Retry the first 726 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 727 * has retries internally. See also the retry loop in 728 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 729 */ 730 if (ret == -ENXIO && i == 0 && try++ == 0) { 731 drm_dbg_kms(&i915->drm, 732 "GMBUS [%s] NAK on first message, retry\n", 733 adapter->name); 734 goto retry; 735 } 736 737 goto out; 738 739 timeout: 740 drm_dbg_kms(&i915->drm, 741 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 742 bus->adapter.name, bus->reg0 & 0xff); 743 intel_de_write_fw(i915, GMBUS0(i915), 0); 744 745 /* 746 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 747 * instead. Use EAGAIN to have i2c core retry. 748 */ 749 ret = -EAGAIN; 750 751 out: 752 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 753 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 754 bxt_gmbus_clock_gating(i915, true); 755 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 756 pch_gmbus_clock_gating(i915, true); 757 758 return ret; 759 } 760 761 static int 762 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 763 { 764 struct intel_gmbus *bus = to_intel_gmbus(adapter); 765 struct drm_i915_private *i915 = bus->i915; 766 intel_wakeref_t wakeref; 767 int ret; 768 769 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 770 771 if (bus->force_bit) { 772 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 773 if (ret < 0) 774 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 775 } else { 776 ret = do_gmbus_xfer(adapter, msgs, num, 0); 777 if (ret == -EAGAIN) 778 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 779 } 780 781 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 782 783 return ret; 784 } 785 786 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 787 { 788 struct intel_gmbus *bus = to_intel_gmbus(adapter); 789 struct drm_i915_private *i915 = bus->i915; 790 u8 cmd = DRM_HDCP_DDC_AKSV; 791 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 792 struct i2c_msg msgs[] = { 793 { 794 .addr = DRM_HDCP_DDC_ADDR, 795 .flags = 0, 796 .len = sizeof(cmd), 797 .buf = &cmd, 798 }, 799 { 800 .addr = DRM_HDCP_DDC_ADDR, 801 .flags = 0, 802 .len = sizeof(buf), 803 .buf = buf, 804 } 805 }; 806 intel_wakeref_t wakeref; 807 int ret; 808 809 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 810 mutex_lock(&i915->display.gmbus.mutex); 811 812 /* 813 * In order to output Aksv to the receiver, use an indexed write to 814 * pass the i2c command, and tell GMBUS to use the HW-provided value 815 * instead of sourcing GMBUS3 for the data. 816 */ 817 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 818 819 mutex_unlock(&i915->display.gmbus.mutex); 820 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 821 822 return ret; 823 } 824 825 static u32 gmbus_func(struct i2c_adapter *adapter) 826 { 827 return i2c_bit_algo.functionality(adapter) & 828 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 829 /* I2C_FUNC_10BIT_ADDR | */ 830 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 831 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 832 } 833 834 static const struct i2c_algorithm gmbus_algorithm = { 835 .master_xfer = gmbus_xfer, 836 .functionality = gmbus_func 837 }; 838 839 static void gmbus_lock_bus(struct i2c_adapter *adapter, 840 unsigned int flags) 841 { 842 struct intel_gmbus *bus = to_intel_gmbus(adapter); 843 struct drm_i915_private *i915 = bus->i915; 844 845 mutex_lock(&i915->display.gmbus.mutex); 846 } 847 848 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 849 unsigned int flags) 850 { 851 struct intel_gmbus *bus = to_intel_gmbus(adapter); 852 struct drm_i915_private *i915 = bus->i915; 853 854 return mutex_trylock(&i915->display.gmbus.mutex); 855 } 856 857 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 858 unsigned int flags) 859 { 860 struct intel_gmbus *bus = to_intel_gmbus(adapter); 861 struct drm_i915_private *i915 = bus->i915; 862 863 mutex_unlock(&i915->display.gmbus.mutex); 864 } 865 866 static const struct i2c_lock_operations gmbus_lock_ops = { 867 .lock_bus = gmbus_lock_bus, 868 .trylock_bus = gmbus_trylock_bus, 869 .unlock_bus = gmbus_unlock_bus, 870 }; 871 872 /** 873 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 874 * @i915: i915 device private 875 */ 876 int intel_gmbus_setup(struct drm_i915_private *i915) 877 { 878 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 879 unsigned int pin; 880 int ret; 881 882 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 883 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE; 884 else if (!HAS_GMCH(i915)) 885 /* 886 * Broxton uses the same PCH offsets for South Display Engine, 887 * even though it doesn't have a PCH. 888 */ 889 i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE; 890 891 mutex_init(&i915->display.gmbus.mutex); 892 init_waitqueue_head(&i915->display.gmbus.wait_queue); 893 894 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 895 const struct gmbus_pin *gmbus_pin; 896 struct intel_gmbus *bus; 897 898 gmbus_pin = get_gmbus_pin(i915, pin); 899 if (!gmbus_pin) 900 continue; 901 902 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 903 if (!bus) { 904 ret = -ENOMEM; 905 goto err; 906 } 907 908 bus->adapter.owner = THIS_MODULE; 909 bus->adapter.class = I2C_CLASS_DDC; 910 snprintf(bus->adapter.name, 911 sizeof(bus->adapter.name), 912 "i915 gmbus %s", gmbus_pin->name); 913 914 bus->adapter.dev.parent = &pdev->dev; 915 bus->i915 = i915; 916 917 bus->adapter.algo = &gmbus_algorithm; 918 bus->adapter.lock_ops = &gmbus_lock_ops; 919 920 /* 921 * We wish to retry with bit banging 922 * after a timed out GMBUS attempt. 923 */ 924 bus->adapter.retries = 1; 925 926 /* By default use a conservative clock rate */ 927 bus->reg0 = pin | GMBUS_RATE_100KHZ; 928 929 /* gmbus seems to be broken on i830 */ 930 if (IS_I830(i915)) 931 bus->force_bit = 1; 932 933 intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio)); 934 935 ret = i2c_add_adapter(&bus->adapter); 936 if (ret) { 937 kfree(bus); 938 goto err; 939 } 940 941 i915->display.gmbus.bus[pin] = bus; 942 } 943 944 intel_gmbus_reset(i915); 945 946 return 0; 947 948 err: 949 intel_gmbus_teardown(i915); 950 951 return ret; 952 } 953 954 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915, 955 unsigned int pin) 956 { 957 if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) || 958 !i915->display.gmbus.bus[pin])) 959 return NULL; 960 961 return &i915->display.gmbus.bus[pin]->adapter; 962 } 963 964 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 965 { 966 struct intel_gmbus *bus = to_intel_gmbus(adapter); 967 struct drm_i915_private *i915 = bus->i915; 968 969 mutex_lock(&i915->display.gmbus.mutex); 970 971 bus->force_bit += force_bit ? 1 : -1; 972 drm_dbg_kms(&i915->drm, 973 "%sabling bit-banging on %s. force bit now %d\n", 974 force_bit ? "en" : "dis", adapter->name, 975 bus->force_bit); 976 977 mutex_unlock(&i915->display.gmbus.mutex); 978 } 979 980 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 981 { 982 struct intel_gmbus *bus = to_intel_gmbus(adapter); 983 984 return bus->force_bit; 985 } 986 987 void intel_gmbus_teardown(struct drm_i915_private *i915) 988 { 989 unsigned int pin; 990 991 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 992 struct intel_gmbus *bus; 993 994 bus = i915->display.gmbus.bus[pin]; 995 if (!bus) 996 continue; 997 998 i2c_del_adapter(&bus->adapter); 999 1000 kfree(bus); 1001 i915->display.gmbus.bus[pin] = NULL; 1002 } 1003 } 1004