1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/drm_hdcp.h> 35 #include <drm/i915_drm.h> 36 37 #include "i915_drv.h" 38 #include "intel_display_types.h" 39 #include "intel_gmbus.h" 40 41 struct gmbus_pin { 42 const char *name; 43 enum i915_gpio gpio; 44 }; 45 46 /* Map gmbus pin pairs to names and registers. */ 47 static const struct gmbus_pin gmbus_pins[] = { 48 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 49 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 50 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 51 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 52 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 53 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 54 }; 55 56 static const struct gmbus_pin gmbus_pins_bdw[] = { 57 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 58 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 59 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 60 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 61 }; 62 63 static const struct gmbus_pin gmbus_pins_skl[] = { 64 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 65 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 66 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 67 }; 68 69 static const struct gmbus_pin gmbus_pins_bxt[] = { 70 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 71 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 72 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 73 }; 74 75 static const struct gmbus_pin gmbus_pins_cnp[] = { 76 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 77 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 78 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 79 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 80 }; 81 82 static const struct gmbus_pin gmbus_pins_icp[] = { 83 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 84 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 85 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 86 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 87 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 88 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 89 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 90 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 91 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 92 }; 93 94 /* pin is expected to be valid */ 95 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, 96 unsigned int pin) 97 { 98 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 99 return &gmbus_pins_icp[pin]; 100 else if (HAS_PCH_CNP(dev_priv)) 101 return &gmbus_pins_cnp[pin]; 102 else if (IS_GEN9_LP(dev_priv)) 103 return &gmbus_pins_bxt[pin]; 104 else if (IS_GEN9_BC(dev_priv)) 105 return &gmbus_pins_skl[pin]; 106 else if (IS_BROADWELL(dev_priv)) 107 return &gmbus_pins_bdw[pin]; 108 else 109 return &gmbus_pins[pin]; 110 } 111 112 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 113 unsigned int pin) 114 { 115 unsigned int size; 116 117 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 118 size = ARRAY_SIZE(gmbus_pins_icp); 119 else if (HAS_PCH_CNP(dev_priv)) 120 size = ARRAY_SIZE(gmbus_pins_cnp); 121 else if (IS_GEN9_LP(dev_priv)) 122 size = ARRAY_SIZE(gmbus_pins_bxt); 123 else if (IS_GEN9_BC(dev_priv)) 124 size = ARRAY_SIZE(gmbus_pins_skl); 125 else if (IS_BROADWELL(dev_priv)) 126 size = ARRAY_SIZE(gmbus_pins_bdw); 127 else 128 size = ARRAY_SIZE(gmbus_pins); 129 130 return pin < size && get_gmbus_pin(dev_priv, pin)->name; 131 } 132 133 /* Intel GPIO access functions */ 134 135 #define I2C_RISEFALL_TIME 10 136 137 static inline struct intel_gmbus * 138 to_intel_gmbus(struct i2c_adapter *i2c) 139 { 140 return container_of(i2c, struct intel_gmbus, adapter); 141 } 142 143 void 144 intel_gmbus_reset(struct drm_i915_private *dev_priv) 145 { 146 intel_de_write(dev_priv, GMBUS0, 0); 147 intel_de_write(dev_priv, GMBUS4, 0); 148 } 149 150 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, 151 bool enable) 152 { 153 u32 val; 154 155 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 156 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 157 if (!enable) 158 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 159 else 160 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 161 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 162 } 163 164 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, 165 bool enable) 166 { 167 u32 val; 168 169 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); 170 if (!enable) 171 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 172 else 173 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 174 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); 175 } 176 177 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, 178 bool enable) 179 { 180 u32 val; 181 182 val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); 183 if (!enable) 184 val |= BXT_GMBUS_GATING_DIS; 185 else 186 val &= ~BXT_GMBUS_GATING_DIS; 187 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); 188 } 189 190 static u32 get_reserved(struct intel_gmbus *bus) 191 { 192 struct drm_i915_private *i915 = bus->dev_priv; 193 struct intel_uncore *uncore = &i915->uncore; 194 u32 reserved = 0; 195 196 /* On most chips, these bits must be preserved in software. */ 197 if (!IS_I830(i915) && !IS_I845G(i915)) 198 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 199 (GPIO_DATA_PULLUP_DISABLE | 200 GPIO_CLOCK_PULLUP_DISABLE); 201 202 return reserved; 203 } 204 205 static int get_clock(void *data) 206 { 207 struct intel_gmbus *bus = data; 208 struct intel_uncore *uncore = &bus->dev_priv->uncore; 209 u32 reserved = get_reserved(bus); 210 211 intel_uncore_write_notrace(uncore, 212 bus->gpio_reg, 213 reserved | GPIO_CLOCK_DIR_MASK); 214 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 215 216 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 217 GPIO_CLOCK_VAL_IN) != 0; 218 } 219 220 static int get_data(void *data) 221 { 222 struct intel_gmbus *bus = data; 223 struct intel_uncore *uncore = &bus->dev_priv->uncore; 224 u32 reserved = get_reserved(bus); 225 226 intel_uncore_write_notrace(uncore, 227 bus->gpio_reg, 228 reserved | GPIO_DATA_DIR_MASK); 229 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 230 231 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 232 GPIO_DATA_VAL_IN) != 0; 233 } 234 235 static void set_clock(void *data, int state_high) 236 { 237 struct intel_gmbus *bus = data; 238 struct intel_uncore *uncore = &bus->dev_priv->uncore; 239 u32 reserved = get_reserved(bus); 240 u32 clock_bits; 241 242 if (state_high) 243 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 244 else 245 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 246 GPIO_CLOCK_VAL_MASK; 247 248 intel_uncore_write_notrace(uncore, 249 bus->gpio_reg, 250 reserved | clock_bits); 251 intel_uncore_posting_read(uncore, bus->gpio_reg); 252 } 253 254 static void set_data(void *data, int state_high) 255 { 256 struct intel_gmbus *bus = data; 257 struct intel_uncore *uncore = &bus->dev_priv->uncore; 258 u32 reserved = get_reserved(bus); 259 u32 data_bits; 260 261 if (state_high) 262 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 263 else 264 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 265 GPIO_DATA_VAL_MASK; 266 267 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 268 intel_uncore_posting_read(uncore, bus->gpio_reg); 269 } 270 271 static int 272 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 273 { 274 struct intel_gmbus *bus = container_of(adapter, 275 struct intel_gmbus, 276 adapter); 277 struct drm_i915_private *dev_priv = bus->dev_priv; 278 279 intel_gmbus_reset(dev_priv); 280 281 if (IS_PINEVIEW(dev_priv)) 282 pnv_gmbus_clock_gating(dev_priv, false); 283 284 set_data(bus, 1); 285 set_clock(bus, 1); 286 udelay(I2C_RISEFALL_TIME); 287 return 0; 288 } 289 290 static void 291 intel_gpio_post_xfer(struct i2c_adapter *adapter) 292 { 293 struct intel_gmbus *bus = container_of(adapter, 294 struct intel_gmbus, 295 adapter); 296 struct drm_i915_private *dev_priv = bus->dev_priv; 297 298 set_data(bus, 1); 299 set_clock(bus, 1); 300 301 if (IS_PINEVIEW(dev_priv)) 302 pnv_gmbus_clock_gating(dev_priv, true); 303 } 304 305 static void 306 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) 307 { 308 struct drm_i915_private *dev_priv = bus->dev_priv; 309 struct i2c_algo_bit_data *algo; 310 311 algo = &bus->bit_algo; 312 313 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); 314 bus->adapter.algo_data = algo; 315 algo->setsda = set_data; 316 algo->setscl = set_clock; 317 algo->getsda = get_data; 318 algo->getscl = get_clock; 319 algo->pre_xfer = intel_gpio_pre_xfer; 320 algo->post_xfer = intel_gpio_post_xfer; 321 algo->udelay = I2C_RISEFALL_TIME; 322 algo->timeout = usecs_to_jiffies(2200); 323 algo->data = bus; 324 } 325 326 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 327 { 328 DEFINE_WAIT(wait); 329 u32 gmbus2; 330 int ret; 331 332 /* Important: The hw handles only the first bit, so set only one! Since 333 * we also need to check for NAKs besides the hw ready/idle signal, we 334 * need to wake up periodically and check that ourselves. 335 */ 336 if (!HAS_GMBUS_IRQ(dev_priv)) 337 irq_en = 0; 338 339 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 340 intel_de_write_fw(dev_priv, GMBUS4, irq_en); 341 342 status |= GMBUS_SATOER; 343 ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, 344 2); 345 if (ret) 346 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, 347 50); 348 349 intel_de_write_fw(dev_priv, GMBUS4, 0); 350 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 351 352 if (gmbus2 & GMBUS_SATOER) 353 return -ENXIO; 354 355 return ret; 356 } 357 358 static int 359 gmbus_wait_idle(struct drm_i915_private *dev_priv) 360 { 361 DEFINE_WAIT(wait); 362 u32 irq_enable; 363 int ret; 364 365 /* Important: The hw handles only the first bit, so set only one! */ 366 irq_enable = 0; 367 if (HAS_GMBUS_IRQ(dev_priv)) 368 irq_enable = GMBUS_IDLE_EN; 369 370 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 371 intel_de_write_fw(dev_priv, GMBUS4, irq_enable); 372 373 ret = intel_wait_for_register_fw(&dev_priv->uncore, 374 GMBUS2, GMBUS_ACTIVE, 0, 375 10); 376 377 intel_de_write_fw(dev_priv, GMBUS4, 0); 378 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 379 380 return ret; 381 } 382 383 static inline 384 unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) 385 { 386 return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 387 GMBUS_BYTE_COUNT_MAX; 388 } 389 390 static int 391 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 392 unsigned short addr, u8 *buf, unsigned int len, 393 u32 gmbus0_reg, u32 gmbus1_index) 394 { 395 unsigned int size = len; 396 bool burst_read = len > gmbus_max_xfer_size(dev_priv); 397 bool extra_byte_added = false; 398 399 if (burst_read) { 400 /* 401 * As per HW Spec, for 512Bytes need to read extra Byte and 402 * Ignore the extra byte read. 403 */ 404 if (len == 512) { 405 extra_byte_added = true; 406 len++; 407 } 408 size = len % 256 + 256; 409 intel_de_write_fw(dev_priv, GMBUS0, 410 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 411 } 412 413 intel_de_write_fw(dev_priv, GMBUS1, 414 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 415 while (len) { 416 int ret; 417 u32 val, loop = 0; 418 419 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 420 if (ret) 421 return ret; 422 423 val = intel_de_read_fw(dev_priv, GMBUS3); 424 do { 425 if (extra_byte_added && len == 1) 426 break; 427 428 *buf++ = val & 0xff; 429 val >>= 8; 430 } while (--len && ++loop < 4); 431 432 if (burst_read && len == size - 4) 433 /* Reset the override bit */ 434 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); 435 } 436 437 return 0; 438 } 439 440 /* 441 * HW spec says that 512Bytes in Burst read need special treatment. 442 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 443 * an I2C slave, which supports such a lengthy burst read too for experiments. 444 * 445 * So until things get clarified on HW support, to avoid the burst read length 446 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 447 */ 448 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 449 450 static int 451 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 452 u32 gmbus0_reg, u32 gmbus1_index) 453 { 454 u8 *buf = msg->buf; 455 unsigned int rx_size = msg->len; 456 unsigned int len; 457 int ret; 458 459 do { 460 if (HAS_GMBUS_BURST_READ(dev_priv)) 461 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 462 else 463 len = min(rx_size, gmbus_max_xfer_size(dev_priv)); 464 465 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, 466 gmbus0_reg, gmbus1_index); 467 if (ret) 468 return ret; 469 470 rx_size -= len; 471 buf += len; 472 } while (rx_size != 0); 473 474 return 0; 475 } 476 477 static int 478 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 479 unsigned short addr, u8 *buf, unsigned int len, 480 u32 gmbus1_index) 481 { 482 unsigned int chunk_size = len; 483 u32 val, loop; 484 485 val = loop = 0; 486 while (len && loop < 4) { 487 val |= *buf++ << (8 * loop++); 488 len -= 1; 489 } 490 491 intel_de_write_fw(dev_priv, GMBUS3, val); 492 intel_de_write_fw(dev_priv, GMBUS1, 493 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 494 while (len) { 495 int ret; 496 497 val = loop = 0; 498 do { 499 val |= *buf++ << (8 * loop); 500 } while (--len && ++loop < 4); 501 502 intel_de_write_fw(dev_priv, GMBUS3, val); 503 504 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 505 if (ret) 506 return ret; 507 } 508 509 return 0; 510 } 511 512 static int 513 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 514 u32 gmbus1_index) 515 { 516 u8 *buf = msg->buf; 517 unsigned int tx_size = msg->len; 518 unsigned int len; 519 int ret; 520 521 do { 522 len = min(tx_size, gmbus_max_xfer_size(dev_priv)); 523 524 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, 525 gmbus1_index); 526 if (ret) 527 return ret; 528 529 buf += len; 530 tx_size -= len; 531 } while (tx_size != 0); 532 533 return 0; 534 } 535 536 /* 537 * The gmbus controller can combine a 1 or 2 byte write with another read/write 538 * that immediately follows it by using an "INDEX" cycle. 539 */ 540 static bool 541 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 542 { 543 return (i + 1 < num && 544 msgs[i].addr == msgs[i + 1].addr && 545 !(msgs[i].flags & I2C_M_RD) && 546 (msgs[i].len == 1 || msgs[i].len == 2) && 547 msgs[i + 1].len > 0); 548 } 549 550 static int 551 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, 552 u32 gmbus0_reg) 553 { 554 u32 gmbus1_index = 0; 555 u32 gmbus5 = 0; 556 int ret; 557 558 if (msgs[0].len == 2) 559 gmbus5 = GMBUS_2BYTE_INDEX_EN | 560 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 561 if (msgs[0].len == 1) 562 gmbus1_index = GMBUS_CYCLE_INDEX | 563 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 564 565 /* GMBUS5 holds 16-bit index */ 566 if (gmbus5) 567 intel_de_write_fw(dev_priv, GMBUS5, gmbus5); 568 569 if (msgs[1].flags & I2C_M_RD) 570 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, 571 gmbus1_index); 572 else 573 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); 574 575 /* Clear GMBUS5 after each index transfer */ 576 if (gmbus5) 577 intel_de_write_fw(dev_priv, GMBUS5, 0); 578 579 return ret; 580 } 581 582 static int 583 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 584 u32 gmbus0_source) 585 { 586 struct intel_gmbus *bus = container_of(adapter, 587 struct intel_gmbus, 588 adapter); 589 struct drm_i915_private *dev_priv = bus->dev_priv; 590 int i = 0, inc, try = 0; 591 int ret = 0; 592 593 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ 594 if (IS_GEN9_LP(dev_priv)) 595 bxt_gmbus_clock_gating(dev_priv, false); 596 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 597 pch_gmbus_clock_gating(dev_priv, false); 598 599 retry: 600 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); 601 602 for (; i < num; i += inc) { 603 inc = 1; 604 if (gmbus_is_index_xfer(msgs, i, num)) { 605 ret = gmbus_index_xfer(dev_priv, &msgs[i], 606 gmbus0_source | bus->reg0); 607 inc = 2; /* an index transmission is two msgs */ 608 } else if (msgs[i].flags & I2C_M_RD) { 609 ret = gmbus_xfer_read(dev_priv, &msgs[i], 610 gmbus0_source | bus->reg0, 0); 611 } else { 612 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); 613 } 614 615 if (!ret) 616 ret = gmbus_wait(dev_priv, 617 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 618 if (ret == -ETIMEDOUT) 619 goto timeout; 620 else if (ret) 621 goto clear_err; 622 } 623 624 /* Generate a STOP condition on the bus. Note that gmbus can't generata 625 * a STOP on the very first cycle. To simplify the code we 626 * unconditionally generate the STOP condition with an additional gmbus 627 * cycle. */ 628 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 629 630 /* Mark the GMBUS interface as disabled after waiting for idle. 631 * We will re-enable it at the start of the next xfer, 632 * till then let it sleep. 633 */ 634 if (gmbus_wait_idle(dev_priv)) { 635 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 636 adapter->name); 637 ret = -ETIMEDOUT; 638 } 639 intel_de_write_fw(dev_priv, GMBUS0, 0); 640 ret = ret ?: i; 641 goto out; 642 643 clear_err: 644 /* 645 * Wait for bus to IDLE before clearing NAK. 646 * If we clear the NAK while bus is still active, then it will stay 647 * active and the next transaction may fail. 648 * 649 * If no ACK is received during the address phase of a transaction, the 650 * adapter must report -ENXIO. It is not clear what to return if no ACK 651 * is received at other times. But we have to be careful to not return 652 * spurious -ENXIO because that will prevent i2c and drm edid functions 653 * from retrying. So return -ENXIO only when gmbus properly quiescents - 654 * timing out seems to happen when there _is_ a ddc chip present, but 655 * it's slow responding and only answers on the 2nd retry. 656 */ 657 ret = -ENXIO; 658 if (gmbus_wait_idle(dev_priv)) { 659 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 660 adapter->name); 661 ret = -ETIMEDOUT; 662 } 663 664 /* Toggle the Software Clear Interrupt bit. This has the effect 665 * of resetting the GMBUS controller and so clearing the 666 * BUS_ERROR raised by the slave's NAK. 667 */ 668 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); 669 intel_de_write_fw(dev_priv, GMBUS1, 0); 670 intel_de_write_fw(dev_priv, GMBUS0, 0); 671 672 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 673 adapter->name, msgs[i].addr, 674 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 675 676 /* 677 * Passive adapters sometimes NAK the first probe. Retry the first 678 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 679 * has retries internally. See also the retry loop in 680 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 681 */ 682 if (ret == -ENXIO && i == 0 && try++ == 0) { 683 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", 684 adapter->name); 685 goto retry; 686 } 687 688 goto out; 689 690 timeout: 691 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 692 bus->adapter.name, bus->reg0 & 0xff); 693 intel_de_write_fw(dev_priv, GMBUS0, 0); 694 695 /* 696 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 697 * instead. Use EAGAIN to have i2c core retry. 698 */ 699 ret = -EAGAIN; 700 701 out: 702 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ 703 if (IS_GEN9_LP(dev_priv)) 704 bxt_gmbus_clock_gating(dev_priv, true); 705 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 706 pch_gmbus_clock_gating(dev_priv, true); 707 708 return ret; 709 } 710 711 static int 712 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 713 { 714 struct intel_gmbus *bus = 715 container_of(adapter, struct intel_gmbus, adapter); 716 struct drm_i915_private *dev_priv = bus->dev_priv; 717 intel_wakeref_t wakeref; 718 int ret; 719 720 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 721 722 if (bus->force_bit) { 723 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 724 if (ret < 0) 725 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 726 } else { 727 ret = do_gmbus_xfer(adapter, msgs, num, 0); 728 if (ret == -EAGAIN) 729 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 730 } 731 732 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 733 734 return ret; 735 } 736 737 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 738 { 739 struct intel_gmbus *bus = 740 container_of(adapter, struct intel_gmbus, adapter); 741 struct drm_i915_private *dev_priv = bus->dev_priv; 742 u8 cmd = DRM_HDCP_DDC_AKSV; 743 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 744 struct i2c_msg msgs[] = { 745 { 746 .addr = DRM_HDCP_DDC_ADDR, 747 .flags = 0, 748 .len = sizeof(cmd), 749 .buf = &cmd, 750 }, 751 { 752 .addr = DRM_HDCP_DDC_ADDR, 753 .flags = 0, 754 .len = sizeof(buf), 755 .buf = buf, 756 } 757 }; 758 intel_wakeref_t wakeref; 759 int ret; 760 761 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 762 mutex_lock(&dev_priv->gmbus_mutex); 763 764 /* 765 * In order to output Aksv to the receiver, use an indexed write to 766 * pass the i2c command, and tell GMBUS to use the HW-provided value 767 * instead of sourcing GMBUS3 for the data. 768 */ 769 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 770 771 mutex_unlock(&dev_priv->gmbus_mutex); 772 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 773 774 return ret; 775 } 776 777 static u32 gmbus_func(struct i2c_adapter *adapter) 778 { 779 return i2c_bit_algo.functionality(adapter) & 780 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 781 /* I2C_FUNC_10BIT_ADDR | */ 782 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 783 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 784 } 785 786 static const struct i2c_algorithm gmbus_algorithm = { 787 .master_xfer = gmbus_xfer, 788 .functionality = gmbus_func 789 }; 790 791 static void gmbus_lock_bus(struct i2c_adapter *adapter, 792 unsigned int flags) 793 { 794 struct intel_gmbus *bus = to_intel_gmbus(adapter); 795 struct drm_i915_private *dev_priv = bus->dev_priv; 796 797 mutex_lock(&dev_priv->gmbus_mutex); 798 } 799 800 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 801 unsigned int flags) 802 { 803 struct intel_gmbus *bus = to_intel_gmbus(adapter); 804 struct drm_i915_private *dev_priv = bus->dev_priv; 805 806 return mutex_trylock(&dev_priv->gmbus_mutex); 807 } 808 809 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 810 unsigned int flags) 811 { 812 struct intel_gmbus *bus = to_intel_gmbus(adapter); 813 struct drm_i915_private *dev_priv = bus->dev_priv; 814 815 mutex_unlock(&dev_priv->gmbus_mutex); 816 } 817 818 static const struct i2c_lock_operations gmbus_lock_ops = { 819 .lock_bus = gmbus_lock_bus, 820 .trylock_bus = gmbus_trylock_bus, 821 .unlock_bus = gmbus_unlock_bus, 822 }; 823 824 /** 825 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 826 * @dev_priv: i915 device private 827 */ 828 int intel_gmbus_setup(struct drm_i915_private *dev_priv) 829 { 830 struct pci_dev *pdev = dev_priv->drm.pdev; 831 struct intel_gmbus *bus; 832 unsigned int pin; 833 int ret; 834 835 if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) 836 return 0; 837 838 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 839 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 840 else if (!HAS_GMCH(dev_priv)) 841 /* 842 * Broxton uses the same PCH offsets for South Display Engine, 843 * even though it doesn't have a PCH. 844 */ 845 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; 846 847 mutex_init(&dev_priv->gmbus_mutex); 848 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 849 850 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 851 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 852 continue; 853 854 bus = &dev_priv->gmbus[pin]; 855 856 bus->adapter.owner = THIS_MODULE; 857 bus->adapter.class = I2C_CLASS_DDC; 858 snprintf(bus->adapter.name, 859 sizeof(bus->adapter.name), 860 "i915 gmbus %s", 861 get_gmbus_pin(dev_priv, pin)->name); 862 863 bus->adapter.dev.parent = &pdev->dev; 864 bus->dev_priv = dev_priv; 865 866 bus->adapter.algo = &gmbus_algorithm; 867 bus->adapter.lock_ops = &gmbus_lock_ops; 868 869 /* 870 * We wish to retry with bit banging 871 * after a timed out GMBUS attempt. 872 */ 873 bus->adapter.retries = 1; 874 875 /* By default use a conservative clock rate */ 876 bus->reg0 = pin | GMBUS_RATE_100KHZ; 877 878 /* gmbus seems to be broken on i830 */ 879 if (IS_I830(dev_priv)) 880 bus->force_bit = 1; 881 882 intel_gpio_setup(bus, pin); 883 884 ret = i2c_add_adapter(&bus->adapter); 885 if (ret) 886 goto err; 887 } 888 889 intel_gmbus_reset(dev_priv); 890 891 return 0; 892 893 err: 894 while (pin--) { 895 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 896 continue; 897 898 bus = &dev_priv->gmbus[pin]; 899 i2c_del_adapter(&bus->adapter); 900 } 901 return ret; 902 } 903 904 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 905 unsigned int pin) 906 { 907 if (drm_WARN_ON(&dev_priv->drm, 908 !intel_gmbus_is_valid_pin(dev_priv, pin))) 909 return NULL; 910 911 return &dev_priv->gmbus[pin].adapter; 912 } 913 914 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) 915 { 916 struct intel_gmbus *bus = to_intel_gmbus(adapter); 917 918 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 919 } 920 921 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 922 { 923 struct intel_gmbus *bus = to_intel_gmbus(adapter); 924 struct drm_i915_private *dev_priv = bus->dev_priv; 925 926 mutex_lock(&dev_priv->gmbus_mutex); 927 928 bus->force_bit += force_bit ? 1 : -1; 929 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 930 force_bit ? "en" : "dis", adapter->name, 931 bus->force_bit); 932 933 mutex_unlock(&dev_priv->gmbus_mutex); 934 } 935 936 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 937 { 938 struct intel_gmbus *bus = to_intel_gmbus(adapter); 939 940 return bus->force_bit; 941 } 942 943 void intel_gmbus_teardown(struct drm_i915_private *dev_priv) 944 { 945 struct intel_gmbus *bus; 946 unsigned int pin; 947 948 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 949 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 950 continue; 951 952 bus = &dev_priv->gmbus[pin]; 953 i2c_del_adapter(&bus->adapter); 954 } 955 } 956