1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/display/drm_hdcp_helper.h> 35 36 #include "i915_drv.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_gmbus.h" 40 #include "intel_gmbus_regs.h" 41 42 struct intel_gmbus { 43 struct i2c_adapter adapter; 44 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 45 u32 force_bit; 46 u32 reg0; 47 i915_reg_t gpio_reg; 48 struct i2c_algo_bit_data bit_algo; 49 struct drm_i915_private *i915; 50 }; 51 52 struct gmbus_pin { 53 const char *name; 54 enum i915_gpio gpio; 55 }; 56 57 /* Map gmbus pin pairs to names and registers. */ 58 static const struct gmbus_pin gmbus_pins[] = { 59 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 60 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 61 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 62 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 63 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 64 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 65 }; 66 67 static const struct gmbus_pin gmbus_pins_bdw[] = { 68 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 69 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 70 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 71 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 72 }; 73 74 static const struct gmbus_pin gmbus_pins_skl[] = { 75 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 76 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 77 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 78 }; 79 80 static const struct gmbus_pin gmbus_pins_bxt[] = { 81 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 82 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 83 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 84 }; 85 86 static const struct gmbus_pin gmbus_pins_cnp[] = { 87 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 88 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 89 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 90 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 91 }; 92 93 static const struct gmbus_pin gmbus_pins_icp[] = { 94 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 95 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 96 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 97 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 98 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 99 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 100 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 101 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 102 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 103 }; 104 105 static const struct gmbus_pin gmbus_pins_dg1[] = { 106 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 107 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 108 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 109 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 110 }; 111 112 static const struct gmbus_pin gmbus_pins_dg2[] = { 113 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 114 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 115 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 116 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 117 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 118 }; 119 120 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 121 unsigned int pin) 122 { 123 const struct gmbus_pin *pins; 124 size_t size; 125 126 if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { 127 pins = gmbus_pins_dg2; 128 size = ARRAY_SIZE(gmbus_pins_dg2); 129 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 130 pins = gmbus_pins_dg1; 131 size = ARRAY_SIZE(gmbus_pins_dg1); 132 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 133 pins = gmbus_pins_icp; 134 size = ARRAY_SIZE(gmbus_pins_icp); 135 } else if (HAS_PCH_CNP(i915)) { 136 pins = gmbus_pins_cnp; 137 size = ARRAY_SIZE(gmbus_pins_cnp); 138 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 139 pins = gmbus_pins_bxt; 140 size = ARRAY_SIZE(gmbus_pins_bxt); 141 } else if (DISPLAY_VER(i915) == 9) { 142 pins = gmbus_pins_skl; 143 size = ARRAY_SIZE(gmbus_pins_skl); 144 } else if (IS_BROADWELL(i915)) { 145 pins = gmbus_pins_bdw; 146 size = ARRAY_SIZE(gmbus_pins_bdw); 147 } else { 148 pins = gmbus_pins; 149 size = ARRAY_SIZE(gmbus_pins); 150 } 151 152 if (pin >= size || !pins[pin].name) 153 return NULL; 154 155 return &pins[pin]; 156 } 157 158 bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin) 159 { 160 return get_gmbus_pin(i915, pin); 161 } 162 163 /* Intel GPIO access functions */ 164 165 #define I2C_RISEFALL_TIME 10 166 167 static inline struct intel_gmbus * 168 to_intel_gmbus(struct i2c_adapter *i2c) 169 { 170 return container_of(i2c, struct intel_gmbus, adapter); 171 } 172 173 void 174 intel_gmbus_reset(struct drm_i915_private *i915) 175 { 176 intel_de_write(i915, GMBUS0(i915), 0); 177 intel_de_write(i915, GMBUS4(i915), 0); 178 } 179 180 static void pnv_gmbus_clock_gating(struct drm_i915_private *i915, 181 bool enable) 182 { 183 u32 val; 184 185 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 186 val = intel_de_read(i915, DSPCLK_GATE_D(i915)); 187 if (!enable) 188 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 189 else 190 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 191 intel_de_write(i915, DSPCLK_GATE_D(i915), val); 192 } 193 194 static void pch_gmbus_clock_gating(struct drm_i915_private *i915, 195 bool enable) 196 { 197 u32 val; 198 199 val = intel_de_read(i915, SOUTH_DSPCLK_GATE_D); 200 if (!enable) 201 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 202 else 203 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 204 intel_de_write(i915, SOUTH_DSPCLK_GATE_D, val); 205 } 206 207 static void bxt_gmbus_clock_gating(struct drm_i915_private *i915, 208 bool enable) 209 { 210 u32 val; 211 212 val = intel_de_read(i915, GEN9_CLKGATE_DIS_4); 213 if (!enable) 214 val |= BXT_GMBUS_GATING_DIS; 215 else 216 val &= ~BXT_GMBUS_GATING_DIS; 217 intel_de_write(i915, GEN9_CLKGATE_DIS_4, val); 218 } 219 220 static u32 get_reserved(struct intel_gmbus *bus) 221 { 222 struct drm_i915_private *i915 = bus->i915; 223 struct intel_uncore *uncore = &i915->uncore; 224 u32 reserved = 0; 225 226 /* On most chips, these bits must be preserved in software. */ 227 if (!IS_I830(i915) && !IS_I845G(i915)) 228 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 229 (GPIO_DATA_PULLUP_DISABLE | 230 GPIO_CLOCK_PULLUP_DISABLE); 231 232 return reserved; 233 } 234 235 static int get_clock(void *data) 236 { 237 struct intel_gmbus *bus = data; 238 struct intel_uncore *uncore = &bus->i915->uncore; 239 u32 reserved = get_reserved(bus); 240 241 intel_uncore_write_notrace(uncore, 242 bus->gpio_reg, 243 reserved | GPIO_CLOCK_DIR_MASK); 244 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 245 246 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 247 GPIO_CLOCK_VAL_IN) != 0; 248 } 249 250 static int get_data(void *data) 251 { 252 struct intel_gmbus *bus = data; 253 struct intel_uncore *uncore = &bus->i915->uncore; 254 u32 reserved = get_reserved(bus); 255 256 intel_uncore_write_notrace(uncore, 257 bus->gpio_reg, 258 reserved | GPIO_DATA_DIR_MASK); 259 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 260 261 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 262 GPIO_DATA_VAL_IN) != 0; 263 } 264 265 static void set_clock(void *data, int state_high) 266 { 267 struct intel_gmbus *bus = data; 268 struct intel_uncore *uncore = &bus->i915->uncore; 269 u32 reserved = get_reserved(bus); 270 u32 clock_bits; 271 272 if (state_high) 273 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 274 else 275 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 276 GPIO_CLOCK_VAL_MASK; 277 278 intel_uncore_write_notrace(uncore, 279 bus->gpio_reg, 280 reserved | clock_bits); 281 intel_uncore_posting_read(uncore, bus->gpio_reg); 282 } 283 284 static void set_data(void *data, int state_high) 285 { 286 struct intel_gmbus *bus = data; 287 struct intel_uncore *uncore = &bus->i915->uncore; 288 u32 reserved = get_reserved(bus); 289 u32 data_bits; 290 291 if (state_high) 292 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 293 else 294 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 295 GPIO_DATA_VAL_MASK; 296 297 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 298 intel_uncore_posting_read(uncore, bus->gpio_reg); 299 } 300 301 static int 302 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 303 { 304 struct intel_gmbus *bus = to_intel_gmbus(adapter); 305 struct drm_i915_private *i915 = bus->i915; 306 307 intel_gmbus_reset(i915); 308 309 if (IS_PINEVIEW(i915)) 310 pnv_gmbus_clock_gating(i915, false); 311 312 set_data(bus, 1); 313 set_clock(bus, 1); 314 udelay(I2C_RISEFALL_TIME); 315 return 0; 316 } 317 318 static void 319 intel_gpio_post_xfer(struct i2c_adapter *adapter) 320 { 321 struct intel_gmbus *bus = to_intel_gmbus(adapter); 322 struct drm_i915_private *i915 = bus->i915; 323 324 set_data(bus, 1); 325 set_clock(bus, 1); 326 327 if (IS_PINEVIEW(i915)) 328 pnv_gmbus_clock_gating(i915, true); 329 } 330 331 static void 332 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 333 { 334 struct i2c_algo_bit_data *algo; 335 336 algo = &bus->bit_algo; 337 338 bus->gpio_reg = gpio_reg; 339 bus->adapter.algo_data = algo; 340 algo->setsda = set_data; 341 algo->setscl = set_clock; 342 algo->getsda = get_data; 343 algo->getscl = get_clock; 344 algo->pre_xfer = intel_gpio_pre_xfer; 345 algo->post_xfer = intel_gpio_post_xfer; 346 algo->udelay = I2C_RISEFALL_TIME; 347 algo->timeout = usecs_to_jiffies(2200); 348 algo->data = bus; 349 } 350 351 static bool has_gmbus_irq(struct drm_i915_private *i915) 352 { 353 /* 354 * encoder->shutdown() may want to use GMBUS 355 * after irqs have already been disabled. 356 */ 357 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); 358 } 359 360 static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en) 361 { 362 DEFINE_WAIT(wait); 363 u32 gmbus2; 364 int ret; 365 366 /* Important: The hw handles only the first bit, so set only one! Since 367 * we also need to check for NAKs besides the hw ready/idle signal, we 368 * need to wake up periodically and check that ourselves. 369 */ 370 if (!has_gmbus_irq(i915)) 371 irq_en = 0; 372 373 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 374 intel_de_write_fw(i915, GMBUS4(i915), irq_en); 375 376 status |= GMBUS_SATOER; 377 ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 378 2); 379 if (ret) 380 ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 381 50); 382 383 intel_de_write_fw(i915, GMBUS4(i915), 0); 384 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 385 386 if (gmbus2 & GMBUS_SATOER) 387 return -ENXIO; 388 389 return ret; 390 } 391 392 static int 393 gmbus_wait_idle(struct drm_i915_private *i915) 394 { 395 DEFINE_WAIT(wait); 396 u32 irq_enable; 397 int ret; 398 399 /* Important: The hw handles only the first bit, so set only one! */ 400 irq_enable = 0; 401 if (has_gmbus_irq(i915)) 402 irq_enable = GMBUS_IDLE_EN; 403 404 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 405 intel_de_write_fw(i915, GMBUS4(i915), irq_enable); 406 407 ret = intel_wait_for_register_fw(&i915->uncore, 408 GMBUS2(i915), GMBUS_ACTIVE, 0, 409 10); 410 411 intel_de_write_fw(i915, GMBUS4(i915), 0); 412 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 413 414 return ret; 415 } 416 417 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915) 418 { 419 return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 420 GMBUS_BYTE_COUNT_MAX; 421 } 422 423 static int 424 gmbus_xfer_read_chunk(struct drm_i915_private *i915, 425 unsigned short addr, u8 *buf, unsigned int len, 426 u32 gmbus0_reg, u32 gmbus1_index) 427 { 428 unsigned int size = len; 429 bool burst_read = len > gmbus_max_xfer_size(i915); 430 bool extra_byte_added = false; 431 432 if (burst_read) { 433 /* 434 * As per HW Spec, for 512Bytes need to read extra Byte and 435 * Ignore the extra byte read. 436 */ 437 if (len == 512) { 438 extra_byte_added = true; 439 len++; 440 } 441 size = len % 256 + 256; 442 intel_de_write_fw(i915, GMBUS0(i915), 443 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 444 } 445 446 intel_de_write_fw(i915, GMBUS1(i915), 447 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 448 while (len) { 449 int ret; 450 u32 val, loop = 0; 451 452 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 453 if (ret) 454 return ret; 455 456 val = intel_de_read_fw(i915, GMBUS3(i915)); 457 do { 458 if (extra_byte_added && len == 1) 459 break; 460 461 *buf++ = val & 0xff; 462 val >>= 8; 463 } while (--len && ++loop < 4); 464 465 if (burst_read && len == size - 4) 466 /* Reset the override bit */ 467 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg); 468 } 469 470 return 0; 471 } 472 473 /* 474 * HW spec says that 512Bytes in Burst read need special treatment. 475 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 476 * an I2C slave, which supports such a lengthy burst read too for experiments. 477 * 478 * So until things get clarified on HW support, to avoid the burst read length 479 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 480 */ 481 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 482 483 static int 484 gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg, 485 u32 gmbus0_reg, u32 gmbus1_index) 486 { 487 u8 *buf = msg->buf; 488 unsigned int rx_size = msg->len; 489 unsigned int len; 490 int ret; 491 492 do { 493 if (HAS_GMBUS_BURST_READ(i915)) 494 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 495 else 496 len = min(rx_size, gmbus_max_xfer_size(i915)); 497 498 ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len, 499 gmbus0_reg, gmbus1_index); 500 if (ret) 501 return ret; 502 503 rx_size -= len; 504 buf += len; 505 } while (rx_size != 0); 506 507 return 0; 508 } 509 510 static int 511 gmbus_xfer_write_chunk(struct drm_i915_private *i915, 512 unsigned short addr, u8 *buf, unsigned int len, 513 u32 gmbus1_index) 514 { 515 unsigned int chunk_size = len; 516 u32 val, loop; 517 518 val = loop = 0; 519 while (len && loop < 4) { 520 val |= *buf++ << (8 * loop++); 521 len -= 1; 522 } 523 524 intel_de_write_fw(i915, GMBUS3(i915), val); 525 intel_de_write_fw(i915, GMBUS1(i915), 526 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 527 while (len) { 528 int ret; 529 530 val = loop = 0; 531 do { 532 val |= *buf++ << (8 * loop); 533 } while (--len && ++loop < 4); 534 535 intel_de_write_fw(i915, GMBUS3(i915), val); 536 537 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 538 if (ret) 539 return ret; 540 } 541 542 return 0; 543 } 544 545 static int 546 gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg, 547 u32 gmbus1_index) 548 { 549 u8 *buf = msg->buf; 550 unsigned int tx_size = msg->len; 551 unsigned int len; 552 int ret; 553 554 do { 555 len = min(tx_size, gmbus_max_xfer_size(i915)); 556 557 ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len, 558 gmbus1_index); 559 if (ret) 560 return ret; 561 562 buf += len; 563 tx_size -= len; 564 } while (tx_size != 0); 565 566 return 0; 567 } 568 569 /* 570 * The gmbus controller can combine a 1 or 2 byte write with another read/write 571 * that immediately follows it by using an "INDEX" cycle. 572 */ 573 static bool 574 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 575 { 576 return (i + 1 < num && 577 msgs[i].addr == msgs[i + 1].addr && 578 !(msgs[i].flags & I2C_M_RD) && 579 (msgs[i].len == 1 || msgs[i].len == 2) && 580 msgs[i + 1].len > 0); 581 } 582 583 static int 584 gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs, 585 u32 gmbus0_reg) 586 { 587 u32 gmbus1_index = 0; 588 u32 gmbus5 = 0; 589 int ret; 590 591 if (msgs[0].len == 2) 592 gmbus5 = GMBUS_2BYTE_INDEX_EN | 593 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 594 if (msgs[0].len == 1) 595 gmbus1_index = GMBUS_CYCLE_INDEX | 596 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 597 598 /* GMBUS5 holds 16-bit index */ 599 if (gmbus5) 600 intel_de_write_fw(i915, GMBUS5(i915), gmbus5); 601 602 if (msgs[1].flags & I2C_M_RD) 603 ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg, 604 gmbus1_index); 605 else 606 ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index); 607 608 /* Clear GMBUS5 after each index transfer */ 609 if (gmbus5) 610 intel_de_write_fw(i915, GMBUS5(i915), 0); 611 612 return ret; 613 } 614 615 static int 616 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 617 u32 gmbus0_source) 618 { 619 struct intel_gmbus *bus = to_intel_gmbus(adapter); 620 struct drm_i915_private *i915 = bus->i915; 621 int i = 0, inc, try = 0; 622 int ret = 0; 623 624 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 625 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 626 bxt_gmbus_clock_gating(i915, false); 627 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 628 pch_gmbus_clock_gating(i915, false); 629 630 retry: 631 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0); 632 633 for (; i < num; i += inc) { 634 inc = 1; 635 if (gmbus_is_index_xfer(msgs, i, num)) { 636 ret = gmbus_index_xfer(i915, &msgs[i], 637 gmbus0_source | bus->reg0); 638 inc = 2; /* an index transmission is two msgs */ 639 } else if (msgs[i].flags & I2C_M_RD) { 640 ret = gmbus_xfer_read(i915, &msgs[i], 641 gmbus0_source | bus->reg0, 0); 642 } else { 643 ret = gmbus_xfer_write(i915, &msgs[i], 0); 644 } 645 646 if (!ret) 647 ret = gmbus_wait(i915, 648 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 649 if (ret == -ETIMEDOUT) 650 goto timeout; 651 else if (ret) 652 goto clear_err; 653 } 654 655 /* Generate a STOP condition on the bus. Note that gmbus can't generata 656 * a STOP on the very first cycle. To simplify the code we 657 * unconditionally generate the STOP condition with an additional gmbus 658 * cycle. */ 659 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 660 661 /* Mark the GMBUS interface as disabled after waiting for idle. 662 * We will re-enable it at the start of the next xfer, 663 * till then let it sleep. 664 */ 665 if (gmbus_wait_idle(i915)) { 666 drm_dbg_kms(&i915->drm, 667 "GMBUS [%s] timed out waiting for idle\n", 668 adapter->name); 669 ret = -ETIMEDOUT; 670 } 671 intel_de_write_fw(i915, GMBUS0(i915), 0); 672 ret = ret ?: i; 673 goto out; 674 675 clear_err: 676 /* 677 * Wait for bus to IDLE before clearing NAK. 678 * If we clear the NAK while bus is still active, then it will stay 679 * active and the next transaction may fail. 680 * 681 * If no ACK is received during the address phase of a transaction, the 682 * adapter must report -ENXIO. It is not clear what to return if no ACK 683 * is received at other times. But we have to be careful to not return 684 * spurious -ENXIO because that will prevent i2c and drm edid functions 685 * from retrying. So return -ENXIO only when gmbus properly quiescents - 686 * timing out seems to happen when there _is_ a ddc chip present, but 687 * it's slow responding and only answers on the 2nd retry. 688 */ 689 ret = -ENXIO; 690 if (gmbus_wait_idle(i915)) { 691 drm_dbg_kms(&i915->drm, 692 "GMBUS [%s] timed out after NAK\n", 693 adapter->name); 694 ret = -ETIMEDOUT; 695 } 696 697 /* Toggle the Software Clear Interrupt bit. This has the effect 698 * of resetting the GMBUS controller and so clearing the 699 * BUS_ERROR raised by the slave's NAK. 700 */ 701 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT); 702 intel_de_write_fw(i915, GMBUS1(i915), 0); 703 intel_de_write_fw(i915, GMBUS0(i915), 0); 704 705 drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 706 adapter->name, msgs[i].addr, 707 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 708 709 /* 710 * Passive adapters sometimes NAK the first probe. Retry the first 711 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 712 * has retries internally. See also the retry loop in 713 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 714 */ 715 if (ret == -ENXIO && i == 0 && try++ == 0) { 716 drm_dbg_kms(&i915->drm, 717 "GMBUS [%s] NAK on first message, retry\n", 718 adapter->name); 719 goto retry; 720 } 721 722 goto out; 723 724 timeout: 725 drm_dbg_kms(&i915->drm, 726 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 727 bus->adapter.name, bus->reg0 & 0xff); 728 intel_de_write_fw(i915, GMBUS0(i915), 0); 729 730 /* 731 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 732 * instead. Use EAGAIN to have i2c core retry. 733 */ 734 ret = -EAGAIN; 735 736 out: 737 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 738 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 739 bxt_gmbus_clock_gating(i915, true); 740 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 741 pch_gmbus_clock_gating(i915, true); 742 743 return ret; 744 } 745 746 static int 747 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 748 { 749 struct intel_gmbus *bus = to_intel_gmbus(adapter); 750 struct drm_i915_private *i915 = bus->i915; 751 intel_wakeref_t wakeref; 752 int ret; 753 754 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 755 756 if (bus->force_bit) { 757 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 758 if (ret < 0) 759 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 760 } else { 761 ret = do_gmbus_xfer(adapter, msgs, num, 0); 762 if (ret == -EAGAIN) 763 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 764 } 765 766 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 767 768 return ret; 769 } 770 771 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 772 { 773 struct intel_gmbus *bus = to_intel_gmbus(adapter); 774 struct drm_i915_private *i915 = bus->i915; 775 u8 cmd = DRM_HDCP_DDC_AKSV; 776 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 777 struct i2c_msg msgs[] = { 778 { 779 .addr = DRM_HDCP_DDC_ADDR, 780 .flags = 0, 781 .len = sizeof(cmd), 782 .buf = &cmd, 783 }, 784 { 785 .addr = DRM_HDCP_DDC_ADDR, 786 .flags = 0, 787 .len = sizeof(buf), 788 .buf = buf, 789 } 790 }; 791 intel_wakeref_t wakeref; 792 int ret; 793 794 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 795 mutex_lock(&i915->display.gmbus.mutex); 796 797 /* 798 * In order to output Aksv to the receiver, use an indexed write to 799 * pass the i2c command, and tell GMBUS to use the HW-provided value 800 * instead of sourcing GMBUS3 for the data. 801 */ 802 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 803 804 mutex_unlock(&i915->display.gmbus.mutex); 805 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 806 807 return ret; 808 } 809 810 static u32 gmbus_func(struct i2c_adapter *adapter) 811 { 812 return i2c_bit_algo.functionality(adapter) & 813 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 814 /* I2C_FUNC_10BIT_ADDR | */ 815 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 816 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 817 } 818 819 static const struct i2c_algorithm gmbus_algorithm = { 820 .master_xfer = gmbus_xfer, 821 .functionality = gmbus_func 822 }; 823 824 static void gmbus_lock_bus(struct i2c_adapter *adapter, 825 unsigned int flags) 826 { 827 struct intel_gmbus *bus = to_intel_gmbus(adapter); 828 struct drm_i915_private *i915 = bus->i915; 829 830 mutex_lock(&i915->display.gmbus.mutex); 831 } 832 833 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 834 unsigned int flags) 835 { 836 struct intel_gmbus *bus = to_intel_gmbus(adapter); 837 struct drm_i915_private *i915 = bus->i915; 838 839 return mutex_trylock(&i915->display.gmbus.mutex); 840 } 841 842 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 843 unsigned int flags) 844 { 845 struct intel_gmbus *bus = to_intel_gmbus(adapter); 846 struct drm_i915_private *i915 = bus->i915; 847 848 mutex_unlock(&i915->display.gmbus.mutex); 849 } 850 851 static const struct i2c_lock_operations gmbus_lock_ops = { 852 .lock_bus = gmbus_lock_bus, 853 .trylock_bus = gmbus_trylock_bus, 854 .unlock_bus = gmbus_unlock_bus, 855 }; 856 857 /** 858 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 859 * @i915: i915 device private 860 */ 861 int intel_gmbus_setup(struct drm_i915_private *i915) 862 { 863 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 864 unsigned int pin; 865 int ret; 866 867 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 868 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE; 869 else if (!HAS_GMCH(i915)) 870 /* 871 * Broxton uses the same PCH offsets for South Display Engine, 872 * even though it doesn't have a PCH. 873 */ 874 i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE; 875 876 mutex_init(&i915->display.gmbus.mutex); 877 init_waitqueue_head(&i915->display.gmbus.wait_queue); 878 879 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 880 const struct gmbus_pin *gmbus_pin; 881 struct intel_gmbus *bus; 882 883 gmbus_pin = get_gmbus_pin(i915, pin); 884 if (!gmbus_pin) 885 continue; 886 887 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 888 if (!bus) { 889 ret = -ENOMEM; 890 goto err; 891 } 892 893 bus->adapter.owner = THIS_MODULE; 894 bus->adapter.class = I2C_CLASS_DDC; 895 snprintf(bus->adapter.name, 896 sizeof(bus->adapter.name), 897 "i915 gmbus %s", gmbus_pin->name); 898 899 bus->adapter.dev.parent = &pdev->dev; 900 bus->i915 = i915; 901 902 bus->adapter.algo = &gmbus_algorithm; 903 bus->adapter.lock_ops = &gmbus_lock_ops; 904 905 /* 906 * We wish to retry with bit banging 907 * after a timed out GMBUS attempt. 908 */ 909 bus->adapter.retries = 1; 910 911 /* By default use a conservative clock rate */ 912 bus->reg0 = pin | GMBUS_RATE_100KHZ; 913 914 /* gmbus seems to be broken on i830 */ 915 if (IS_I830(i915)) 916 bus->force_bit = 1; 917 918 intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio)); 919 920 ret = i2c_add_adapter(&bus->adapter); 921 if (ret) { 922 kfree(bus); 923 goto err; 924 } 925 926 i915->display.gmbus.bus[pin] = bus; 927 } 928 929 intel_gmbus_reset(i915); 930 931 return 0; 932 933 err: 934 intel_gmbus_teardown(i915); 935 936 return ret; 937 } 938 939 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915, 940 unsigned int pin) 941 { 942 if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) || 943 !i915->display.gmbus.bus[pin])) 944 return NULL; 945 946 return &i915->display.gmbus.bus[pin]->adapter; 947 } 948 949 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 950 { 951 struct intel_gmbus *bus = to_intel_gmbus(adapter); 952 struct drm_i915_private *i915 = bus->i915; 953 954 mutex_lock(&i915->display.gmbus.mutex); 955 956 bus->force_bit += force_bit ? 1 : -1; 957 drm_dbg_kms(&i915->drm, 958 "%sabling bit-banging on %s. force bit now %d\n", 959 force_bit ? "en" : "dis", adapter->name, 960 bus->force_bit); 961 962 mutex_unlock(&i915->display.gmbus.mutex); 963 } 964 965 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 966 { 967 struct intel_gmbus *bus = to_intel_gmbus(adapter); 968 969 return bus->force_bit; 970 } 971 972 void intel_gmbus_teardown(struct drm_i915_private *i915) 973 { 974 unsigned int pin; 975 976 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 977 struct intel_gmbus *bus; 978 979 bus = i915->display.gmbus.bus[pin]; 980 if (!bus) 981 continue; 982 983 i2c_del_adapter(&bus->adapter); 984 985 kfree(bus); 986 i915->display.gmbus.bus[pin] = NULL; 987 } 988 } 989