1379bc100SJani Nikula /* 2379bc100SJani Nikula * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3379bc100SJani Nikula * Copyright © 2006-2008,2010 Intel Corporation 4379bc100SJani Nikula * Jesse Barnes <jesse.barnes@intel.com> 5379bc100SJani Nikula * 6379bc100SJani Nikula * Permission is hereby granted, free of charge, to any person obtaining a 7379bc100SJani Nikula * copy of this software and associated documentation files (the "Software"), 8379bc100SJani Nikula * to deal in the Software without restriction, including without limitation 9379bc100SJani Nikula * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10379bc100SJani Nikula * and/or sell copies of the Software, and to permit persons to whom the 11379bc100SJani Nikula * Software is furnished to do so, subject to the following conditions: 12379bc100SJani Nikula * 13379bc100SJani Nikula * The above copyright notice and this permission notice (including the next 14379bc100SJani Nikula * paragraph) shall be included in all copies or substantial portions of the 15379bc100SJani Nikula * Software. 16379bc100SJani Nikula * 17379bc100SJani Nikula * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18379bc100SJani Nikula * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19379bc100SJani Nikula * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20379bc100SJani Nikula * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21379bc100SJani Nikula * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22379bc100SJani Nikula * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23379bc100SJani Nikula * DEALINGS IN THE SOFTWARE. 24379bc100SJani Nikula * 25379bc100SJani Nikula * Authors: 26379bc100SJani Nikula * Eric Anholt <eric@anholt.net> 27379bc100SJani Nikula * Chris Wilson <chris@chris-wilson.co.uk> 28379bc100SJani Nikula */ 29379bc100SJani Nikula 30379bc100SJani Nikula #include <linux/export.h> 31379bc100SJani Nikula #include <linux/i2c-algo-bit.h> 32379bc100SJani Nikula #include <linux/i2c.h> 33379bc100SJani Nikula 346a99099fSThomas Zimmermann #include <drm/display/drm_hdcp_helper.h> 35379bc100SJani Nikula 36379bc100SJani Nikula #include "i915_drv.h" 37801543b2SJani Nikula #include "i915_irq.h" 38801543b2SJani Nikula #include "i915_reg.h" 397785ae0bSVille Syrjälä #include "intel_de.h" 401d455f8dSJani Nikula #include "intel_display_types.h" 41379bc100SJani Nikula #include "intel_gmbus.h" 4251b072deSJani Nikula #include "intel_gmbus_regs.h" 43379bc100SJani Nikula 4463a78bbbSJani Nikula struct intel_gmbus { 4563a78bbbSJani Nikula struct i2c_adapter adapter; 4663a78bbbSJani Nikula #define GMBUS_FORCE_BIT_RETRY (1U << 31) 4763a78bbbSJani Nikula u32 force_bit; 4863a78bbbSJani Nikula u32 reg0; 4963a78bbbSJani Nikula i915_reg_t gpio_reg; 5063a78bbbSJani Nikula struct i2c_algo_bit_data bit_algo; 510514b50cSJani Nikula struct drm_i915_private *i915; 5263a78bbbSJani Nikula }; 5363a78bbbSJani Nikula 54507d7c17SJani Nikula enum gmbus_gpio { 55507d7c17SJani Nikula GPIOA, 56507d7c17SJani Nikula GPIOB, 57507d7c17SJani Nikula GPIOC, 58507d7c17SJani Nikula GPIOD, 59507d7c17SJani Nikula GPIOE, 60507d7c17SJani Nikula GPIOF, 61507d7c17SJani Nikula GPIOG, 62507d7c17SJani Nikula GPIOH, 63507d7c17SJani Nikula __GPIOI_UNUSED, 64507d7c17SJani Nikula GPIOJ, 65507d7c17SJani Nikula GPIOK, 66507d7c17SJani Nikula GPIOL, 67507d7c17SJani Nikula GPIOM, 68507d7c17SJani Nikula GPION, 69507d7c17SJani Nikula GPIOO, 70507d7c17SJani Nikula }; 71507d7c17SJani Nikula 72379bc100SJani Nikula struct gmbus_pin { 73379bc100SJani Nikula const char *name; 74507d7c17SJani Nikula enum gmbus_gpio gpio; 75379bc100SJani Nikula }; 76379bc100SJani Nikula 77379bc100SJani Nikula /* Map gmbus pin pairs to names and registers. */ 78379bc100SJani Nikula static const struct gmbus_pin gmbus_pins[] = { 79379bc100SJani Nikula [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 80379bc100SJani Nikula [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 81379bc100SJani Nikula [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 82379bc100SJani Nikula [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 83379bc100SJani Nikula [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 84379bc100SJani Nikula [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 85379bc100SJani Nikula }; 86379bc100SJani Nikula 87379bc100SJani Nikula static const struct gmbus_pin gmbus_pins_bdw[] = { 88379bc100SJani Nikula [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 89379bc100SJani Nikula [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 90379bc100SJani Nikula [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 91379bc100SJani Nikula [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 92379bc100SJani Nikula }; 93379bc100SJani Nikula 94379bc100SJani Nikula static const struct gmbus_pin gmbus_pins_skl[] = { 95379bc100SJani Nikula [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 96379bc100SJani Nikula [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 97379bc100SJani Nikula [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 98379bc100SJani Nikula }; 99379bc100SJani Nikula 100379bc100SJani Nikula static const struct gmbus_pin gmbus_pins_bxt[] = { 101379bc100SJani Nikula [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 102379bc100SJani Nikula [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 103379bc100SJani Nikula [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 104379bc100SJani Nikula }; 105379bc100SJani Nikula 106379bc100SJani Nikula static const struct gmbus_pin gmbus_pins_cnp[] = { 107379bc100SJani Nikula [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 108379bc100SJani Nikula [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 109379bc100SJani Nikula [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 110379bc100SJani Nikula [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 111379bc100SJani Nikula }; 112379bc100SJani Nikula 113379bc100SJani Nikula static const struct gmbus_pin gmbus_pins_icp[] = { 114379bc100SJani Nikula [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 115379bc100SJani Nikula [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 1163fd53262SMahesh Kumar [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 1173fd53262SMahesh Kumar [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 1183fd53262SMahesh Kumar [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 1193fd53262SMahesh Kumar [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 1203fd53262SMahesh Kumar [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 1213fd53262SMahesh Kumar [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 1223fd53262SMahesh Kumar [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 1233fd53262SMahesh Kumar }; 1243fd53262SMahesh Kumar 125fb7318c3SLucas De Marchi static const struct gmbus_pin gmbus_pins_dg1[] = { 126fb7318c3SLucas De Marchi [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 127fb7318c3SLucas De Marchi [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 128fb7318c3SLucas De Marchi [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 129fb7318c3SLucas De Marchi [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 130fb7318c3SLucas De Marchi }; 131fb7318c3SLucas De Marchi 1322f8a6699SMatt Roper static const struct gmbus_pin gmbus_pins_dg2[] = { 1332f8a6699SMatt Roper [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 1342f8a6699SMatt Roper [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 1352f8a6699SMatt Roper [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 1362f8a6699SMatt Roper [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 1372f8a6699SMatt Roper [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 1382f8a6699SMatt Roper }; 1392f8a6699SMatt Roper 140e5d464d0SRadhakrishna Sripada static const struct gmbus_pin gmbus_pins_mtp[] = { 141e5d464d0SRadhakrishna Sripada [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 142e5d464d0SRadhakrishna Sripada [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 143e5d464d0SRadhakrishna Sripada [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 144e5d464d0SRadhakrishna Sripada [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 145e5d464d0SRadhakrishna Sripada [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 146e5d464d0SRadhakrishna Sripada [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 147e5d464d0SRadhakrishna Sripada [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 148e5d464d0SRadhakrishna Sripada [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 149e5d464d0SRadhakrishna Sripada [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 150e5d464d0SRadhakrishna Sripada }; 151e5d464d0SRadhakrishna Sripada 15269e807a5SJani Nikula static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 153379bc100SJani Nikula unsigned int pin) 154379bc100SJani Nikula { 15569e807a5SJani Nikula const struct gmbus_pin *pins; 15669e807a5SJani Nikula size_t size; 15769e807a5SJani Nikula 15869e807a5SJani Nikula if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { 15969e807a5SJani Nikula pins = gmbus_pins_dg2; 16069e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_dg2); 16169e807a5SJani Nikula } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 16269e807a5SJani Nikula pins = gmbus_pins_dg1; 16369e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_dg1); 164e5d464d0SRadhakrishna Sripada } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) { 165e5d464d0SRadhakrishna Sripada pins = gmbus_pins_mtp; 166e5d464d0SRadhakrishna Sripada size = ARRAY_SIZE(gmbus_pins_mtp); 16769e807a5SJani Nikula } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 16869e807a5SJani Nikula pins = gmbus_pins_icp; 16969e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_icp); 17069e807a5SJani Nikula } else if (HAS_PCH_CNP(i915)) { 17169e807a5SJani Nikula pins = gmbus_pins_cnp; 17269e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_cnp); 17369e807a5SJani Nikula } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 17469e807a5SJani Nikula pins = gmbus_pins_bxt; 17569e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_bxt); 17669e807a5SJani Nikula } else if (DISPLAY_VER(i915) == 9) { 17769e807a5SJani Nikula pins = gmbus_pins_skl; 17869e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_skl); 17969e807a5SJani Nikula } else if (IS_BROADWELL(i915)) { 18069e807a5SJani Nikula pins = gmbus_pins_bdw; 18169e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_bdw); 18269e807a5SJani Nikula } else { 18369e807a5SJani Nikula pins = gmbus_pins; 18469e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins); 185379bc100SJani Nikula } 186379bc100SJani Nikula 18769e807a5SJani Nikula if (pin >= size || !pins[pin].name) 18869e807a5SJani Nikula return NULL; 18969e807a5SJani Nikula 19069e807a5SJani Nikula return &pins[pin]; 19169e807a5SJani Nikula } 19269e807a5SJani Nikula 19369e807a5SJani Nikula bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin) 194379bc100SJani Nikula { 19569e807a5SJani Nikula return get_gmbus_pin(i915, pin); 196379bc100SJani Nikula } 197379bc100SJani Nikula 198379bc100SJani Nikula /* Intel GPIO access functions */ 199379bc100SJani Nikula 200379bc100SJani Nikula #define I2C_RISEFALL_TIME 10 201379bc100SJani Nikula 202379bc100SJani Nikula static inline struct intel_gmbus * 203379bc100SJani Nikula to_intel_gmbus(struct i2c_adapter *i2c) 204379bc100SJani Nikula { 205379bc100SJani Nikula return container_of(i2c, struct intel_gmbus, adapter); 206379bc100SJani Nikula } 207379bc100SJani Nikula 208379bc100SJani Nikula void 2096d737d9bSJani Nikula intel_gmbus_reset(struct drm_i915_private *i915) 210379bc100SJani Nikula { 2116d737d9bSJani Nikula intel_de_write(i915, GMBUS0(i915), 0); 2126d737d9bSJani Nikula intel_de_write(i915, GMBUS4(i915), 0); 213379bc100SJani Nikula } 214379bc100SJani Nikula 2150514b50cSJani Nikula static void pnv_gmbus_clock_gating(struct drm_i915_private *i915, 216379bc100SJani Nikula bool enable) 217379bc100SJani Nikula { 218379bc100SJani Nikula /* When using bit bashing for I2C, this bit needs to be set to 1 */ 219*8910d8b7SAndrzej Hajda intel_de_rmw(i915, DSPCLK_GATE_D(i915), PNV_GMBUSUNIT_CLOCK_GATE_DISABLE, 220*8910d8b7SAndrzej Hajda !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 221379bc100SJani Nikula } 222379bc100SJani Nikula 2230514b50cSJani Nikula static void pch_gmbus_clock_gating(struct drm_i915_private *i915, 224379bc100SJani Nikula bool enable) 225379bc100SJani Nikula { 226*8910d8b7SAndrzej Hajda intel_de_rmw(i915, SOUTH_DSPCLK_GATE_D, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 227*8910d8b7SAndrzej Hajda !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 228379bc100SJani Nikula } 229379bc100SJani Nikula 2300514b50cSJani Nikula static void bxt_gmbus_clock_gating(struct drm_i915_private *i915, 231379bc100SJani Nikula bool enable) 232379bc100SJani Nikula { 233*8910d8b7SAndrzej Hajda intel_de_rmw(i915, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, 234*8910d8b7SAndrzej Hajda !enable ? BXT_GMBUS_GATING_DIS : 0); 235379bc100SJani Nikula } 236379bc100SJani Nikula 237379bc100SJani Nikula static u32 get_reserved(struct intel_gmbus *bus) 238379bc100SJani Nikula { 2390514b50cSJani Nikula struct drm_i915_private *i915 = bus->i915; 240379bc100SJani Nikula u32 reserved = 0; 241379bc100SJani Nikula 242379bc100SJani Nikula /* On most chips, these bits must be preserved in software. */ 243379bc100SJani Nikula if (!IS_I830(i915) && !IS_I845G(i915)) 24401f84f74SJani Nikula reserved = intel_de_read_notrace(i915, bus->gpio_reg) & 24501f84f74SJani Nikula (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); 246379bc100SJani Nikula 247379bc100SJani Nikula return reserved; 248379bc100SJani Nikula } 249379bc100SJani Nikula 250379bc100SJani Nikula static int get_clock(void *data) 251379bc100SJani Nikula { 252379bc100SJani Nikula struct intel_gmbus *bus = data; 25301f84f74SJani Nikula struct drm_i915_private *i915 = bus->i915; 254379bc100SJani Nikula u32 reserved = get_reserved(bus); 255379bc100SJani Nikula 25601f84f74SJani Nikula intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 25701f84f74SJani Nikula intel_de_write_notrace(i915, bus->gpio_reg, reserved); 258379bc100SJani Nikula 25901f84f74SJani Nikula return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 260379bc100SJani Nikula } 261379bc100SJani Nikula 262379bc100SJani Nikula static int get_data(void *data) 263379bc100SJani Nikula { 264379bc100SJani Nikula struct intel_gmbus *bus = data; 26501f84f74SJani Nikula struct drm_i915_private *i915 = bus->i915; 266379bc100SJani Nikula u32 reserved = get_reserved(bus); 267379bc100SJani Nikula 26801f84f74SJani Nikula intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 26901f84f74SJani Nikula intel_de_write_notrace(i915, bus->gpio_reg, reserved); 270379bc100SJani Nikula 27101f84f74SJani Nikula return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 272379bc100SJani Nikula } 273379bc100SJani Nikula 274379bc100SJani Nikula static void set_clock(void *data, int state_high) 275379bc100SJani Nikula { 276379bc100SJani Nikula struct intel_gmbus *bus = data; 27701f84f74SJani Nikula struct drm_i915_private *i915 = bus->i915; 278379bc100SJani Nikula u32 reserved = get_reserved(bus); 279379bc100SJani Nikula u32 clock_bits; 280379bc100SJani Nikula 281379bc100SJani Nikula if (state_high) 282379bc100SJani Nikula clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 283379bc100SJani Nikula else 284379bc100SJani Nikula clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 285379bc100SJani Nikula GPIO_CLOCK_VAL_MASK; 286379bc100SJani Nikula 28701f84f74SJani Nikula intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits); 28801f84f74SJani Nikula intel_de_posting_read(i915, bus->gpio_reg); 289379bc100SJani Nikula } 290379bc100SJani Nikula 291379bc100SJani Nikula static void set_data(void *data, int state_high) 292379bc100SJani Nikula { 293379bc100SJani Nikula struct intel_gmbus *bus = data; 29401f84f74SJani Nikula struct drm_i915_private *i915 = bus->i915; 295379bc100SJani Nikula u32 reserved = get_reserved(bus); 296379bc100SJani Nikula u32 data_bits; 297379bc100SJani Nikula 298379bc100SJani Nikula if (state_high) 299379bc100SJani Nikula data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 300379bc100SJani Nikula else 301379bc100SJani Nikula data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 302379bc100SJani Nikula GPIO_DATA_VAL_MASK; 303379bc100SJani Nikula 30401f84f74SJani Nikula intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits); 30501f84f74SJani Nikula intel_de_posting_read(i915, bus->gpio_reg); 306379bc100SJani Nikula } 307379bc100SJani Nikula 308379bc100SJani Nikula static int 309379bc100SJani Nikula intel_gpio_pre_xfer(struct i2c_adapter *adapter) 310379bc100SJani Nikula { 31117e571feSJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 3120514b50cSJani Nikula struct drm_i915_private *i915 = bus->i915; 313379bc100SJani Nikula 3140514b50cSJani Nikula intel_gmbus_reset(i915); 315379bc100SJani Nikula 3160514b50cSJani Nikula if (IS_PINEVIEW(i915)) 3170514b50cSJani Nikula pnv_gmbus_clock_gating(i915, false); 318379bc100SJani Nikula 319379bc100SJani Nikula set_data(bus, 1); 320379bc100SJani Nikula set_clock(bus, 1); 321379bc100SJani Nikula udelay(I2C_RISEFALL_TIME); 322379bc100SJani Nikula return 0; 323379bc100SJani Nikula } 324379bc100SJani Nikula 325379bc100SJani Nikula static void 326379bc100SJani Nikula intel_gpio_post_xfer(struct i2c_adapter *adapter) 327379bc100SJani Nikula { 32817e571feSJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 3290514b50cSJani Nikula struct drm_i915_private *i915 = bus->i915; 330379bc100SJani Nikula 331379bc100SJani Nikula set_data(bus, 1); 332379bc100SJani Nikula set_clock(bus, 1); 333379bc100SJani Nikula 3340514b50cSJani Nikula if (IS_PINEVIEW(i915)) 3350514b50cSJani Nikula pnv_gmbus_clock_gating(i915, true); 336379bc100SJani Nikula } 337379bc100SJani Nikula 338379bc100SJani Nikula static void 33965cd963eSJani Nikula intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 340379bc100SJani Nikula { 341379bc100SJani Nikula struct i2c_algo_bit_data *algo; 342379bc100SJani Nikula 343379bc100SJani Nikula algo = &bus->bit_algo; 344379bc100SJani Nikula 34565cd963eSJani Nikula bus->gpio_reg = gpio_reg; 346379bc100SJani Nikula bus->adapter.algo_data = algo; 347379bc100SJani Nikula algo->setsda = set_data; 348379bc100SJani Nikula algo->setscl = set_clock; 349379bc100SJani Nikula algo->getsda = get_data; 350379bc100SJani Nikula algo->getscl = get_clock; 351379bc100SJani Nikula algo->pre_xfer = intel_gpio_pre_xfer; 352379bc100SJani Nikula algo->post_xfer = intel_gpio_post_xfer; 353379bc100SJani Nikula algo->udelay = I2C_RISEFALL_TIME; 354379bc100SJani Nikula algo->timeout = usecs_to_jiffies(2200); 355379bc100SJani Nikula algo->data = bus; 356379bc100SJani Nikula } 357379bc100SJani Nikula 358fa2a6c5bSVille Syrjälä static bool has_gmbus_irq(struct drm_i915_private *i915) 359fa2a6c5bSVille Syrjälä { 360fa2a6c5bSVille Syrjälä /* 361fa2a6c5bSVille Syrjälä * encoder->shutdown() may want to use GMBUS 362fa2a6c5bSVille Syrjälä * after irqs have already been disabled. 363fa2a6c5bSVille Syrjälä */ 364fa2a6c5bSVille Syrjälä return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); 365fa2a6c5bSVille Syrjälä } 366fa2a6c5bSVille Syrjälä 3670514b50cSJani Nikula static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en) 368379bc100SJani Nikula { 369379bc100SJani Nikula DEFINE_WAIT(wait); 370379bc100SJani Nikula u32 gmbus2; 371379bc100SJani Nikula int ret; 372379bc100SJani Nikula 373379bc100SJani Nikula /* Important: The hw handles only the first bit, so set only one! Since 374379bc100SJani Nikula * we also need to check for NAKs besides the hw ready/idle signal, we 375379bc100SJani Nikula * need to wake up periodically and check that ourselves. 376379bc100SJani Nikula */ 3770514b50cSJani Nikula if (!has_gmbus_irq(i915)) 378379bc100SJani Nikula irq_en = 0; 379379bc100SJani Nikula 3800514b50cSJani Nikula add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 3810514b50cSJani Nikula intel_de_write_fw(i915, GMBUS4(i915), irq_en); 382379bc100SJani Nikula 383379bc100SJani Nikula status |= GMBUS_SATOER; 3840514b50cSJani Nikula ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 385d9053b23SJani Nikula 2); 386379bc100SJani Nikula if (ret) 3870514b50cSJani Nikula ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 388d9053b23SJani Nikula 50); 389379bc100SJani Nikula 3900514b50cSJani Nikula intel_de_write_fw(i915, GMBUS4(i915), 0); 3910514b50cSJani Nikula remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 392379bc100SJani Nikula 393379bc100SJani Nikula if (gmbus2 & GMBUS_SATOER) 394379bc100SJani Nikula return -ENXIO; 395379bc100SJani Nikula 396379bc100SJani Nikula return ret; 397379bc100SJani Nikula } 398379bc100SJani Nikula 399379bc100SJani Nikula static int 4000514b50cSJani Nikula gmbus_wait_idle(struct drm_i915_private *i915) 401379bc100SJani Nikula { 402379bc100SJani Nikula DEFINE_WAIT(wait); 403379bc100SJani Nikula u32 irq_enable; 404379bc100SJani Nikula int ret; 405379bc100SJani Nikula 406379bc100SJani Nikula /* Important: The hw handles only the first bit, so set only one! */ 407379bc100SJani Nikula irq_enable = 0; 4080514b50cSJani Nikula if (has_gmbus_irq(i915)) 409379bc100SJani Nikula irq_enable = GMBUS_IDLE_EN; 410379bc100SJani Nikula 4110514b50cSJani Nikula add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 4120514b50cSJani Nikula intel_de_write_fw(i915, GMBUS4(i915), irq_enable); 413379bc100SJani Nikula 41401f84f74SJani Nikula ret = intel_de_wait_for_register_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10); 415379bc100SJani Nikula 4160514b50cSJani Nikula intel_de_write_fw(i915, GMBUS4(i915), 0); 4170514b50cSJani Nikula remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 418379bc100SJani Nikula 419379bc100SJani Nikula return ret; 420379bc100SJani Nikula } 421379bc100SJani Nikula 4220514b50cSJani Nikula static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915) 423379bc100SJani Nikula { 4240514b50cSJani Nikula return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 425379bc100SJani Nikula GMBUS_BYTE_COUNT_MAX; 426379bc100SJani Nikula } 427379bc100SJani Nikula 428379bc100SJani Nikula static int 4290514b50cSJani Nikula gmbus_xfer_read_chunk(struct drm_i915_private *i915, 430379bc100SJani Nikula unsigned short addr, u8 *buf, unsigned int len, 431379bc100SJani Nikula u32 gmbus0_reg, u32 gmbus1_index) 432379bc100SJani Nikula { 433379bc100SJani Nikula unsigned int size = len; 4340514b50cSJani Nikula bool burst_read = len > gmbus_max_xfer_size(i915); 435379bc100SJani Nikula bool extra_byte_added = false; 436379bc100SJani Nikula 437379bc100SJani Nikula if (burst_read) { 438379bc100SJani Nikula /* 439379bc100SJani Nikula * As per HW Spec, for 512Bytes need to read extra Byte and 440379bc100SJani Nikula * Ignore the extra byte read. 441379bc100SJani Nikula */ 442379bc100SJani Nikula if (len == 512) { 443379bc100SJani Nikula extra_byte_added = true; 444379bc100SJani Nikula len++; 445379bc100SJani Nikula } 446379bc100SJani Nikula size = len % 256 + 256; 4470514b50cSJani Nikula intel_de_write_fw(i915, GMBUS0(i915), 448d9053b23SJani Nikula gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 449379bc100SJani Nikula } 450379bc100SJani Nikula 4510514b50cSJani Nikula intel_de_write_fw(i915, GMBUS1(i915), 452d9053b23SJani Nikula gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 453379bc100SJani Nikula while (len) { 454379bc100SJani Nikula int ret; 455379bc100SJani Nikula u32 val, loop = 0; 456379bc100SJani Nikula 4570514b50cSJani Nikula ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 458379bc100SJani Nikula if (ret) 459379bc100SJani Nikula return ret; 460379bc100SJani Nikula 4610514b50cSJani Nikula val = intel_de_read_fw(i915, GMBUS3(i915)); 462379bc100SJani Nikula do { 463379bc100SJani Nikula if (extra_byte_added && len == 1) 464379bc100SJani Nikula break; 465379bc100SJani Nikula 466379bc100SJani Nikula *buf++ = val & 0xff; 467379bc100SJani Nikula val >>= 8; 468379bc100SJani Nikula } while (--len && ++loop < 4); 469379bc100SJani Nikula 470379bc100SJani Nikula if (burst_read && len == size - 4) 471379bc100SJani Nikula /* Reset the override bit */ 4720514b50cSJani Nikula intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg); 473379bc100SJani Nikula } 474379bc100SJani Nikula 475379bc100SJani Nikula return 0; 476379bc100SJani Nikula } 477379bc100SJani Nikula 478379bc100SJani Nikula /* 479379bc100SJani Nikula * HW spec says that 512Bytes in Burst read need special treatment. 480379bc100SJani Nikula * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 481379bc100SJani Nikula * an I2C slave, which supports such a lengthy burst read too for experiments. 482379bc100SJani Nikula * 483379bc100SJani Nikula * So until things get clarified on HW support, to avoid the burst read length 484379bc100SJani Nikula * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 485379bc100SJani Nikula */ 486379bc100SJani Nikula #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 487379bc100SJani Nikula 488379bc100SJani Nikula static int 4890514b50cSJani Nikula gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg, 490379bc100SJani Nikula u32 gmbus0_reg, u32 gmbus1_index) 491379bc100SJani Nikula { 492379bc100SJani Nikula u8 *buf = msg->buf; 493379bc100SJani Nikula unsigned int rx_size = msg->len; 494379bc100SJani Nikula unsigned int len; 495379bc100SJani Nikula int ret; 496379bc100SJani Nikula 497379bc100SJani Nikula do { 4980514b50cSJani Nikula if (HAS_GMBUS_BURST_READ(i915)) 499379bc100SJani Nikula len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 500379bc100SJani Nikula else 5010514b50cSJani Nikula len = min(rx_size, gmbus_max_xfer_size(i915)); 502379bc100SJani Nikula 5030514b50cSJani Nikula ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len, 504379bc100SJani Nikula gmbus0_reg, gmbus1_index); 505379bc100SJani Nikula if (ret) 506379bc100SJani Nikula return ret; 507379bc100SJani Nikula 508379bc100SJani Nikula rx_size -= len; 509379bc100SJani Nikula buf += len; 510379bc100SJani Nikula } while (rx_size != 0); 511379bc100SJani Nikula 512379bc100SJani Nikula return 0; 513379bc100SJani Nikula } 514379bc100SJani Nikula 515379bc100SJani Nikula static int 5160514b50cSJani Nikula gmbus_xfer_write_chunk(struct drm_i915_private *i915, 517379bc100SJani Nikula unsigned short addr, u8 *buf, unsigned int len, 518379bc100SJani Nikula u32 gmbus1_index) 519379bc100SJani Nikula { 520379bc100SJani Nikula unsigned int chunk_size = len; 521379bc100SJani Nikula u32 val, loop; 522379bc100SJani Nikula 523379bc100SJani Nikula val = loop = 0; 524379bc100SJani Nikula while (len && loop < 4) { 525379bc100SJani Nikula val |= *buf++ << (8 * loop++); 526379bc100SJani Nikula len -= 1; 527379bc100SJani Nikula } 528379bc100SJani Nikula 5290514b50cSJani Nikula intel_de_write_fw(i915, GMBUS3(i915), val); 5300514b50cSJani Nikula intel_de_write_fw(i915, GMBUS1(i915), 531d9053b23SJani Nikula gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 532379bc100SJani Nikula while (len) { 533379bc100SJani Nikula int ret; 534379bc100SJani Nikula 535379bc100SJani Nikula val = loop = 0; 536379bc100SJani Nikula do { 537379bc100SJani Nikula val |= *buf++ << (8 * loop); 538379bc100SJani Nikula } while (--len && ++loop < 4); 539379bc100SJani Nikula 5400514b50cSJani Nikula intel_de_write_fw(i915, GMBUS3(i915), val); 541379bc100SJani Nikula 5420514b50cSJani Nikula ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 543379bc100SJani Nikula if (ret) 544379bc100SJani Nikula return ret; 545379bc100SJani Nikula } 546379bc100SJani Nikula 547379bc100SJani Nikula return 0; 548379bc100SJani Nikula } 549379bc100SJani Nikula 550379bc100SJani Nikula static int 5510514b50cSJani Nikula gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg, 552379bc100SJani Nikula u32 gmbus1_index) 553379bc100SJani Nikula { 554379bc100SJani Nikula u8 *buf = msg->buf; 555379bc100SJani Nikula unsigned int tx_size = msg->len; 556379bc100SJani Nikula unsigned int len; 557379bc100SJani Nikula int ret; 558379bc100SJani Nikula 559379bc100SJani Nikula do { 5600514b50cSJani Nikula len = min(tx_size, gmbus_max_xfer_size(i915)); 561379bc100SJani Nikula 5620514b50cSJani Nikula ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len, 563379bc100SJani Nikula gmbus1_index); 564379bc100SJani Nikula if (ret) 565379bc100SJani Nikula return ret; 566379bc100SJani Nikula 567379bc100SJani Nikula buf += len; 568379bc100SJani Nikula tx_size -= len; 569379bc100SJani Nikula } while (tx_size != 0); 570379bc100SJani Nikula 571379bc100SJani Nikula return 0; 572379bc100SJani Nikula } 573379bc100SJani Nikula 574379bc100SJani Nikula /* 575379bc100SJani Nikula * The gmbus controller can combine a 1 or 2 byte write with another read/write 576379bc100SJani Nikula * that immediately follows it by using an "INDEX" cycle. 577379bc100SJani Nikula */ 578379bc100SJani Nikula static bool 579379bc100SJani Nikula gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 580379bc100SJani Nikula { 581379bc100SJani Nikula return (i + 1 < num && 582379bc100SJani Nikula msgs[i].addr == msgs[i + 1].addr && 583379bc100SJani Nikula !(msgs[i].flags & I2C_M_RD) && 584379bc100SJani Nikula (msgs[i].len == 1 || msgs[i].len == 2) && 585379bc100SJani Nikula msgs[i + 1].len > 0); 586379bc100SJani Nikula } 587379bc100SJani Nikula 588379bc100SJani Nikula static int 5890514b50cSJani Nikula gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs, 590379bc100SJani Nikula u32 gmbus0_reg) 591379bc100SJani Nikula { 592379bc100SJani Nikula u32 gmbus1_index = 0; 593379bc100SJani Nikula u32 gmbus5 = 0; 594379bc100SJani Nikula int ret; 595379bc100SJani Nikula 596379bc100SJani Nikula if (msgs[0].len == 2) 597379bc100SJani Nikula gmbus5 = GMBUS_2BYTE_INDEX_EN | 598379bc100SJani Nikula msgs[0].buf[1] | (msgs[0].buf[0] << 8); 599379bc100SJani Nikula if (msgs[0].len == 1) 600379bc100SJani Nikula gmbus1_index = GMBUS_CYCLE_INDEX | 601379bc100SJani Nikula (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 602379bc100SJani Nikula 603379bc100SJani Nikula /* GMBUS5 holds 16-bit index */ 604379bc100SJani Nikula if (gmbus5) 6050514b50cSJani Nikula intel_de_write_fw(i915, GMBUS5(i915), gmbus5); 606379bc100SJani Nikula 607379bc100SJani Nikula if (msgs[1].flags & I2C_M_RD) 6080514b50cSJani Nikula ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg, 609379bc100SJani Nikula gmbus1_index); 610379bc100SJani Nikula else 6110514b50cSJani Nikula ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index); 612379bc100SJani Nikula 613379bc100SJani Nikula /* Clear GMBUS5 after each index transfer */ 614379bc100SJani Nikula if (gmbus5) 6150514b50cSJani Nikula intel_de_write_fw(i915, GMBUS5(i915), 0); 616379bc100SJani Nikula 617379bc100SJani Nikula return ret; 618379bc100SJani Nikula } 619379bc100SJani Nikula 620379bc100SJani Nikula static int 621379bc100SJani Nikula do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 622379bc100SJani Nikula u32 gmbus0_source) 623379bc100SJani Nikula { 62417e571feSJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 6250514b50cSJani Nikula struct drm_i915_private *i915 = bus->i915; 626379bc100SJani Nikula int i = 0, inc, try = 0; 627379bc100SJani Nikula int ret = 0; 628379bc100SJani Nikula 629244dba4cSLucas De Marchi /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 6300514b50cSJani Nikula if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 6310514b50cSJani Nikula bxt_gmbus_clock_gating(i915, false); 6320514b50cSJani Nikula else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 6330514b50cSJani Nikula pch_gmbus_clock_gating(i915, false); 634379bc100SJani Nikula 635379bc100SJani Nikula retry: 6360514b50cSJani Nikula intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0); 637379bc100SJani Nikula 638379bc100SJani Nikula for (; i < num; i += inc) { 639379bc100SJani Nikula inc = 1; 640379bc100SJani Nikula if (gmbus_is_index_xfer(msgs, i, num)) { 6410514b50cSJani Nikula ret = gmbus_index_xfer(i915, &msgs[i], 642379bc100SJani Nikula gmbus0_source | bus->reg0); 643379bc100SJani Nikula inc = 2; /* an index transmission is two msgs */ 644379bc100SJani Nikula } else if (msgs[i].flags & I2C_M_RD) { 6450514b50cSJani Nikula ret = gmbus_xfer_read(i915, &msgs[i], 646379bc100SJani Nikula gmbus0_source | bus->reg0, 0); 647379bc100SJani Nikula } else { 6480514b50cSJani Nikula ret = gmbus_xfer_write(i915, &msgs[i], 0); 649379bc100SJani Nikula } 650379bc100SJani Nikula 651379bc100SJani Nikula if (!ret) 6520514b50cSJani Nikula ret = gmbus_wait(i915, 653379bc100SJani Nikula GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 654379bc100SJani Nikula if (ret == -ETIMEDOUT) 655379bc100SJani Nikula goto timeout; 656379bc100SJani Nikula else if (ret) 657379bc100SJani Nikula goto clear_err; 658379bc100SJani Nikula } 659379bc100SJani Nikula 660379bc100SJani Nikula /* Generate a STOP condition on the bus. Note that gmbus can't generata 661379bc100SJani Nikula * a STOP on the very first cycle. To simplify the code we 662379bc100SJani Nikula * unconditionally generate the STOP condition with an additional gmbus 663379bc100SJani Nikula * cycle. */ 6640514b50cSJani Nikula intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 665379bc100SJani Nikula 666379bc100SJani Nikula /* Mark the GMBUS interface as disabled after waiting for idle. 667379bc100SJani Nikula * We will re-enable it at the start of the next xfer, 668379bc100SJani Nikula * till then let it sleep. 669379bc100SJani Nikula */ 6700514b50cSJani Nikula if (gmbus_wait_idle(i915)) { 6710514b50cSJani Nikula drm_dbg_kms(&i915->drm, 6726a9cc4bfSWambui Karuga "GMBUS [%s] timed out waiting for idle\n", 673379bc100SJani Nikula adapter->name); 674379bc100SJani Nikula ret = -ETIMEDOUT; 675379bc100SJani Nikula } 6760514b50cSJani Nikula intel_de_write_fw(i915, GMBUS0(i915), 0); 677379bc100SJani Nikula ret = ret ?: i; 678379bc100SJani Nikula goto out; 679379bc100SJani Nikula 680379bc100SJani Nikula clear_err: 681379bc100SJani Nikula /* 682379bc100SJani Nikula * Wait for bus to IDLE before clearing NAK. 683379bc100SJani Nikula * If we clear the NAK while bus is still active, then it will stay 684379bc100SJani Nikula * active and the next transaction may fail. 685379bc100SJani Nikula * 686379bc100SJani Nikula * If no ACK is received during the address phase of a transaction, the 687379bc100SJani Nikula * adapter must report -ENXIO. It is not clear what to return if no ACK 688379bc100SJani Nikula * is received at other times. But we have to be careful to not return 689379bc100SJani Nikula * spurious -ENXIO because that will prevent i2c and drm edid functions 690379bc100SJani Nikula * from retrying. So return -ENXIO only when gmbus properly quiescents - 691379bc100SJani Nikula * timing out seems to happen when there _is_ a ddc chip present, but 692379bc100SJani Nikula * it's slow responding and only answers on the 2nd retry. 693379bc100SJani Nikula */ 694379bc100SJani Nikula ret = -ENXIO; 6950514b50cSJani Nikula if (gmbus_wait_idle(i915)) { 6960514b50cSJani Nikula drm_dbg_kms(&i915->drm, 6976a9cc4bfSWambui Karuga "GMBUS [%s] timed out after NAK\n", 698379bc100SJani Nikula adapter->name); 699379bc100SJani Nikula ret = -ETIMEDOUT; 700379bc100SJani Nikula } 701379bc100SJani Nikula 702379bc100SJani Nikula /* Toggle the Software Clear Interrupt bit. This has the effect 703379bc100SJani Nikula * of resetting the GMBUS controller and so clearing the 704379bc100SJani Nikula * BUS_ERROR raised by the slave's NAK. 705379bc100SJani Nikula */ 7060514b50cSJani Nikula intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT); 7070514b50cSJani Nikula intel_de_write_fw(i915, GMBUS1(i915), 0); 7080514b50cSJani Nikula intel_de_write_fw(i915, GMBUS0(i915), 0); 709379bc100SJani Nikula 7100514b50cSJani Nikula drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 711379bc100SJani Nikula adapter->name, msgs[i].addr, 712379bc100SJani Nikula (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 713379bc100SJani Nikula 714379bc100SJani Nikula /* 715379bc100SJani Nikula * Passive adapters sometimes NAK the first probe. Retry the first 716379bc100SJani Nikula * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 717379bc100SJani Nikula * has retries internally. See also the retry loop in 718379bc100SJani Nikula * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 719379bc100SJani Nikula */ 720379bc100SJani Nikula if (ret == -ENXIO && i == 0 && try++ == 0) { 7210514b50cSJani Nikula drm_dbg_kms(&i915->drm, 7226a9cc4bfSWambui Karuga "GMBUS [%s] NAK on first message, retry\n", 723379bc100SJani Nikula adapter->name); 724379bc100SJani Nikula goto retry; 725379bc100SJani Nikula } 726379bc100SJani Nikula 727379bc100SJani Nikula goto out; 728379bc100SJani Nikula 729379bc100SJani Nikula timeout: 7300514b50cSJani Nikula drm_dbg_kms(&i915->drm, 7316a9cc4bfSWambui Karuga "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 732379bc100SJani Nikula bus->adapter.name, bus->reg0 & 0xff); 7330514b50cSJani Nikula intel_de_write_fw(i915, GMBUS0(i915), 0); 734379bc100SJani Nikula 735379bc100SJani Nikula /* 736379bc100SJani Nikula * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 737379bc100SJani Nikula * instead. Use EAGAIN to have i2c core retry. 738379bc100SJani Nikula */ 739379bc100SJani Nikula ret = -EAGAIN; 740379bc100SJani Nikula 741379bc100SJani Nikula out: 742244dba4cSLucas De Marchi /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 7430514b50cSJani Nikula if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 7440514b50cSJani Nikula bxt_gmbus_clock_gating(i915, true); 7450514b50cSJani Nikula else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 7460514b50cSJani Nikula pch_gmbus_clock_gating(i915, true); 747379bc100SJani Nikula 748379bc100SJani Nikula return ret; 749379bc100SJani Nikula } 750379bc100SJani Nikula 751379bc100SJani Nikula static int 752379bc100SJani Nikula gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 753379bc100SJani Nikula { 75417e571feSJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 7550514b50cSJani Nikula struct drm_i915_private *i915 = bus->i915; 756379bc100SJani Nikula intel_wakeref_t wakeref; 757379bc100SJani Nikula int ret; 758379bc100SJani Nikula 7590514b50cSJani Nikula wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 760379bc100SJani Nikula 761379bc100SJani Nikula if (bus->force_bit) { 762379bc100SJani Nikula ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 763379bc100SJani Nikula if (ret < 0) 764379bc100SJani Nikula bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 765379bc100SJani Nikula } else { 766379bc100SJani Nikula ret = do_gmbus_xfer(adapter, msgs, num, 0); 767379bc100SJani Nikula if (ret == -EAGAIN) 768379bc100SJani Nikula bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 769379bc100SJani Nikula } 770379bc100SJani Nikula 7710514b50cSJani Nikula intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 772379bc100SJani Nikula 773379bc100SJani Nikula return ret; 774379bc100SJani Nikula } 775379bc100SJani Nikula 776379bc100SJani Nikula int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 777379bc100SJani Nikula { 77817e571feSJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 7790514b50cSJani Nikula struct drm_i915_private *i915 = bus->i915; 780379bc100SJani Nikula u8 cmd = DRM_HDCP_DDC_AKSV; 781379bc100SJani Nikula u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 782379bc100SJani Nikula struct i2c_msg msgs[] = { 783379bc100SJani Nikula { 784379bc100SJani Nikula .addr = DRM_HDCP_DDC_ADDR, 785379bc100SJani Nikula .flags = 0, 786379bc100SJani Nikula .len = sizeof(cmd), 787379bc100SJani Nikula .buf = &cmd, 788379bc100SJani Nikula }, 789379bc100SJani Nikula { 790379bc100SJani Nikula .addr = DRM_HDCP_DDC_ADDR, 791379bc100SJani Nikula .flags = 0, 792379bc100SJani Nikula .len = sizeof(buf), 793379bc100SJani Nikula .buf = buf, 794379bc100SJani Nikula } 795379bc100SJani Nikula }; 796379bc100SJani Nikula intel_wakeref_t wakeref; 797379bc100SJani Nikula int ret; 798379bc100SJani Nikula 7990514b50cSJani Nikula wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 8000514b50cSJani Nikula mutex_lock(&i915->display.gmbus.mutex); 801379bc100SJani Nikula 802379bc100SJani Nikula /* 803379bc100SJani Nikula * In order to output Aksv to the receiver, use an indexed write to 804379bc100SJani Nikula * pass the i2c command, and tell GMBUS to use the HW-provided value 805379bc100SJani Nikula * instead of sourcing GMBUS3 for the data. 806379bc100SJani Nikula */ 807379bc100SJani Nikula ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 808379bc100SJani Nikula 8090514b50cSJani Nikula mutex_unlock(&i915->display.gmbus.mutex); 8100514b50cSJani Nikula intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 811379bc100SJani Nikula 812379bc100SJani Nikula return ret; 813379bc100SJani Nikula } 814379bc100SJani Nikula 815379bc100SJani Nikula static u32 gmbus_func(struct i2c_adapter *adapter) 816379bc100SJani Nikula { 817379bc100SJani Nikula return i2c_bit_algo.functionality(adapter) & 818379bc100SJani Nikula (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 819379bc100SJani Nikula /* I2C_FUNC_10BIT_ADDR | */ 820379bc100SJani Nikula I2C_FUNC_SMBUS_READ_BLOCK_DATA | 821379bc100SJani Nikula I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 822379bc100SJani Nikula } 823379bc100SJani Nikula 824379bc100SJani Nikula static const struct i2c_algorithm gmbus_algorithm = { 825379bc100SJani Nikula .master_xfer = gmbus_xfer, 826379bc100SJani Nikula .functionality = gmbus_func 827379bc100SJani Nikula }; 828379bc100SJani Nikula 829379bc100SJani Nikula static void gmbus_lock_bus(struct i2c_adapter *adapter, 830379bc100SJani Nikula unsigned int flags) 831379bc100SJani Nikula { 832379bc100SJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 8330514b50cSJani Nikula struct drm_i915_private *i915 = bus->i915; 834379bc100SJani Nikula 8350514b50cSJani Nikula mutex_lock(&i915->display.gmbus.mutex); 836379bc100SJani Nikula } 837379bc100SJani Nikula 838379bc100SJani Nikula static int gmbus_trylock_bus(struct i2c_adapter *adapter, 839379bc100SJani Nikula unsigned int flags) 840379bc100SJani Nikula { 841379bc100SJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 8420514b50cSJani Nikula struct drm_i915_private *i915 = bus->i915; 843379bc100SJani Nikula 8440514b50cSJani Nikula return mutex_trylock(&i915->display.gmbus.mutex); 845379bc100SJani Nikula } 846379bc100SJani Nikula 847379bc100SJani Nikula static void gmbus_unlock_bus(struct i2c_adapter *adapter, 848379bc100SJani Nikula unsigned int flags) 849379bc100SJani Nikula { 850379bc100SJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 8510514b50cSJani Nikula struct drm_i915_private *i915 = bus->i915; 852379bc100SJani Nikula 8530514b50cSJani Nikula mutex_unlock(&i915->display.gmbus.mutex); 854379bc100SJani Nikula } 855379bc100SJani Nikula 856379bc100SJani Nikula static const struct i2c_lock_operations gmbus_lock_ops = { 857379bc100SJani Nikula .lock_bus = gmbus_lock_bus, 858379bc100SJani Nikula .trylock_bus = gmbus_trylock_bus, 859379bc100SJani Nikula .unlock_bus = gmbus_unlock_bus, 860379bc100SJani Nikula }; 861379bc100SJani Nikula 862379bc100SJani Nikula /** 863379bc100SJani Nikula * intel_gmbus_setup - instantiate all Intel i2c GMBuses 8640514b50cSJani Nikula * @i915: i915 device private 865379bc100SJani Nikula */ 8660514b50cSJani Nikula int intel_gmbus_setup(struct drm_i915_private *i915) 867379bc100SJani Nikula { 8680514b50cSJani Nikula struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 869379bc100SJani Nikula unsigned int pin; 870379bc100SJani Nikula int ret; 871379bc100SJani Nikula 8720514b50cSJani Nikula if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 8730514b50cSJani Nikula i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE; 8740514b50cSJani Nikula else if (!HAS_GMCH(i915)) 875379bc100SJani Nikula /* 876379bc100SJani Nikula * Broxton uses the same PCH offsets for South Display Engine, 877379bc100SJani Nikula * even though it doesn't have a PCH. 878379bc100SJani Nikula */ 8790514b50cSJani Nikula i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE; 880379bc100SJani Nikula 8810514b50cSJani Nikula mutex_init(&i915->display.gmbus.mutex); 8820514b50cSJani Nikula init_waitqueue_head(&i915->display.gmbus.wait_queue); 883379bc100SJani Nikula 8840514b50cSJani Nikula for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 88539a8c428SJani Nikula const struct gmbus_pin *gmbus_pin; 88671abfcbeSJani Nikula struct intel_gmbus *bus; 88739a8c428SJani Nikula 8880514b50cSJani Nikula gmbus_pin = get_gmbus_pin(i915, pin); 88939a8c428SJani Nikula if (!gmbus_pin) 890379bc100SJani Nikula continue; 891379bc100SJani Nikula 89263a78bbbSJani Nikula bus = kzalloc(sizeof(*bus), GFP_KERNEL); 89363a78bbbSJani Nikula if (!bus) { 89463a78bbbSJani Nikula ret = -ENOMEM; 89563a78bbbSJani Nikula goto err; 89663a78bbbSJani Nikula } 897379bc100SJani Nikula 898379bc100SJani Nikula bus->adapter.owner = THIS_MODULE; 899379bc100SJani Nikula bus->adapter.class = I2C_CLASS_DDC; 900379bc100SJani Nikula snprintf(bus->adapter.name, 901379bc100SJani Nikula sizeof(bus->adapter.name), 90239a8c428SJani Nikula "i915 gmbus %s", gmbus_pin->name); 903379bc100SJani Nikula 904379bc100SJani Nikula bus->adapter.dev.parent = &pdev->dev; 9050514b50cSJani Nikula bus->i915 = i915; 906379bc100SJani Nikula 907379bc100SJani Nikula bus->adapter.algo = &gmbus_algorithm; 908379bc100SJani Nikula bus->adapter.lock_ops = &gmbus_lock_ops; 909379bc100SJani Nikula 910379bc100SJani Nikula /* 911379bc100SJani Nikula * We wish to retry with bit banging 912379bc100SJani Nikula * after a timed out GMBUS attempt. 913379bc100SJani Nikula */ 914379bc100SJani Nikula bus->adapter.retries = 1; 915379bc100SJani Nikula 916379bc100SJani Nikula /* By default use a conservative clock rate */ 917379bc100SJani Nikula bus->reg0 = pin | GMBUS_RATE_100KHZ; 918379bc100SJani Nikula 919379bc100SJani Nikula /* gmbus seems to be broken on i830 */ 9200514b50cSJani Nikula if (IS_I830(i915)) 921379bc100SJani Nikula bus->force_bit = 1; 922379bc100SJani Nikula 9230514b50cSJani Nikula intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio)); 924379bc100SJani Nikula 925379bc100SJani Nikula ret = i2c_add_adapter(&bus->adapter); 92663a78bbbSJani Nikula if (ret) { 92763a78bbbSJani Nikula kfree(bus); 928379bc100SJani Nikula goto err; 929379bc100SJani Nikula } 930379bc100SJani Nikula 9310514b50cSJani Nikula i915->display.gmbus.bus[pin] = bus; 93263a78bbbSJani Nikula } 93363a78bbbSJani Nikula 9340514b50cSJani Nikula intel_gmbus_reset(i915); 935379bc100SJani Nikula 936379bc100SJani Nikula return 0; 937379bc100SJani Nikula 938379bc100SJani Nikula err: 9390514b50cSJani Nikula intel_gmbus_teardown(i915); 940379bc100SJani Nikula 941379bc100SJani Nikula return ret; 942379bc100SJani Nikula } 943379bc100SJani Nikula 9440514b50cSJani Nikula struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915, 945379bc100SJani Nikula unsigned int pin) 946379bc100SJani Nikula { 9470514b50cSJani Nikula if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) || 9480514b50cSJani Nikula !i915->display.gmbus.bus[pin])) 949379bc100SJani Nikula return NULL; 950379bc100SJani Nikula 9510514b50cSJani Nikula return &i915->display.gmbus.bus[pin]->adapter; 952379bc100SJani Nikula } 953379bc100SJani Nikula 954379bc100SJani Nikula void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 955379bc100SJani Nikula { 956379bc100SJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 9570514b50cSJani Nikula struct drm_i915_private *i915 = bus->i915; 958379bc100SJani Nikula 9590514b50cSJani Nikula mutex_lock(&i915->display.gmbus.mutex); 960379bc100SJani Nikula 961379bc100SJani Nikula bus->force_bit += force_bit ? 1 : -1; 9620514b50cSJani Nikula drm_dbg_kms(&i915->drm, 9636a9cc4bfSWambui Karuga "%sabling bit-banging on %s. force bit now %d\n", 964379bc100SJani Nikula force_bit ? "en" : "dis", adapter->name, 965379bc100SJani Nikula bus->force_bit); 966379bc100SJani Nikula 9670514b50cSJani Nikula mutex_unlock(&i915->display.gmbus.mutex); 968379bc100SJani Nikula } 969379bc100SJani Nikula 970379bc100SJani Nikula bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 971379bc100SJani Nikula { 972379bc100SJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 973379bc100SJani Nikula 974379bc100SJani Nikula return bus->force_bit; 975379bc100SJani Nikula } 976379bc100SJani Nikula 9770514b50cSJani Nikula void intel_gmbus_teardown(struct drm_i915_private *i915) 978379bc100SJani Nikula { 979379bc100SJani Nikula unsigned int pin; 980379bc100SJani Nikula 9810514b50cSJani Nikula for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 98271abfcbeSJani Nikula struct intel_gmbus *bus; 98371abfcbeSJani Nikula 9840514b50cSJani Nikula bus = i915->display.gmbus.bus[pin]; 98563a78bbbSJani Nikula if (!bus) 986379bc100SJani Nikula continue; 987379bc100SJani Nikula 988379bc100SJani Nikula i2c_del_adapter(&bus->adapter); 98963a78bbbSJani Nikula 99063a78bbbSJani Nikula kfree(bus); 9910514b50cSJani Nikula i915->display.gmbus.bus[pin] = NULL; 992379bc100SJani Nikula } 993379bc100SJani Nikula } 994