1379bc100SJani Nikula /* 2379bc100SJani Nikula * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3379bc100SJani Nikula * Copyright © 2006-2008,2010 Intel Corporation 4379bc100SJani Nikula * Jesse Barnes <jesse.barnes@intel.com> 5379bc100SJani Nikula * 6379bc100SJani Nikula * Permission is hereby granted, free of charge, to any person obtaining a 7379bc100SJani Nikula * copy of this software and associated documentation files (the "Software"), 8379bc100SJani Nikula * to deal in the Software without restriction, including without limitation 9379bc100SJani Nikula * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10379bc100SJani Nikula * and/or sell copies of the Software, and to permit persons to whom the 11379bc100SJani Nikula * Software is furnished to do so, subject to the following conditions: 12379bc100SJani Nikula * 13379bc100SJani Nikula * The above copyright notice and this permission notice (including the next 14379bc100SJani Nikula * paragraph) shall be included in all copies or substantial portions of the 15379bc100SJani Nikula * Software. 16379bc100SJani Nikula * 17379bc100SJani Nikula * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18379bc100SJani Nikula * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19379bc100SJani Nikula * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20379bc100SJani Nikula * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21379bc100SJani Nikula * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22379bc100SJani Nikula * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23379bc100SJani Nikula * DEALINGS IN THE SOFTWARE. 24379bc100SJani Nikula * 25379bc100SJani Nikula * Authors: 26379bc100SJani Nikula * Eric Anholt <eric@anholt.net> 27379bc100SJani Nikula * Chris Wilson <chris@chris-wilson.co.uk> 28379bc100SJani Nikula */ 29379bc100SJani Nikula 30379bc100SJani Nikula #include <linux/export.h> 31379bc100SJani Nikula #include <linux/i2c-algo-bit.h> 32379bc100SJani Nikula #include <linux/i2c.h> 33379bc100SJani Nikula 346a99099fSThomas Zimmermann #include <drm/display/drm_hdcp_helper.h> 35379bc100SJani Nikula 36379bc100SJani Nikula #include "i915_drv.h" 377785ae0bSVille Syrjälä #include "intel_de.h" 381d455f8dSJani Nikula #include "intel_display_types.h" 39379bc100SJani Nikula #include "intel_gmbus.h" 4051b072deSJani Nikula #include "intel_gmbus_regs.h" 41379bc100SJani Nikula 4263a78bbbSJani Nikula struct intel_gmbus { 4363a78bbbSJani Nikula struct i2c_adapter adapter; 4463a78bbbSJani Nikula #define GMBUS_FORCE_BIT_RETRY (1U << 31) 4563a78bbbSJani Nikula u32 force_bit; 4663a78bbbSJani Nikula u32 reg0; 4763a78bbbSJani Nikula i915_reg_t gpio_reg; 4863a78bbbSJani Nikula struct i2c_algo_bit_data bit_algo; 4963a78bbbSJani Nikula struct drm_i915_private *dev_priv; 5063a78bbbSJani Nikula }; 5163a78bbbSJani Nikula 52379bc100SJani Nikula struct gmbus_pin { 53379bc100SJani Nikula const char *name; 54379bc100SJani Nikula enum i915_gpio gpio; 55379bc100SJani Nikula }; 56379bc100SJani Nikula 57379bc100SJani Nikula /* Map gmbus pin pairs to names and registers. */ 58379bc100SJani Nikula static const struct gmbus_pin gmbus_pins[] = { 59379bc100SJani Nikula [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 60379bc100SJani Nikula [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 61379bc100SJani Nikula [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 62379bc100SJani Nikula [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 63379bc100SJani Nikula [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 64379bc100SJani Nikula [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 65379bc100SJani Nikula }; 66379bc100SJani Nikula 67379bc100SJani Nikula static const struct gmbus_pin gmbus_pins_bdw[] = { 68379bc100SJani Nikula [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 69379bc100SJani Nikula [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 70379bc100SJani Nikula [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 71379bc100SJani Nikula [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 72379bc100SJani Nikula }; 73379bc100SJani Nikula 74379bc100SJani Nikula static const struct gmbus_pin gmbus_pins_skl[] = { 75379bc100SJani Nikula [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 76379bc100SJani Nikula [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 77379bc100SJani Nikula [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 78379bc100SJani Nikula }; 79379bc100SJani Nikula 80379bc100SJani Nikula static const struct gmbus_pin gmbus_pins_bxt[] = { 81379bc100SJani Nikula [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 82379bc100SJani Nikula [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 83379bc100SJani Nikula [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 84379bc100SJani Nikula }; 85379bc100SJani Nikula 86379bc100SJani Nikula static const struct gmbus_pin gmbus_pins_cnp[] = { 87379bc100SJani Nikula [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 88379bc100SJani Nikula [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 89379bc100SJani Nikula [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 90379bc100SJani Nikula [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 91379bc100SJani Nikula }; 92379bc100SJani Nikula 93379bc100SJani Nikula static const struct gmbus_pin gmbus_pins_icp[] = { 94379bc100SJani Nikula [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 95379bc100SJani Nikula [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 963fd53262SMahesh Kumar [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 973fd53262SMahesh Kumar [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 983fd53262SMahesh Kumar [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 993fd53262SMahesh Kumar [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 1003fd53262SMahesh Kumar [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 1013fd53262SMahesh Kumar [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 1023fd53262SMahesh Kumar [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 1033fd53262SMahesh Kumar }; 1043fd53262SMahesh Kumar 105fb7318c3SLucas De Marchi static const struct gmbus_pin gmbus_pins_dg1[] = { 106fb7318c3SLucas De Marchi [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 107fb7318c3SLucas De Marchi [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 108fb7318c3SLucas De Marchi [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 109fb7318c3SLucas De Marchi [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 110fb7318c3SLucas De Marchi }; 111fb7318c3SLucas De Marchi 1122f8a6699SMatt Roper static const struct gmbus_pin gmbus_pins_dg2[] = { 1132f8a6699SMatt Roper [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 1142f8a6699SMatt Roper [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 1152f8a6699SMatt Roper [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 1162f8a6699SMatt Roper [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 1172f8a6699SMatt Roper [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 1182f8a6699SMatt Roper }; 1192f8a6699SMatt Roper 12069e807a5SJani Nikula static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 121379bc100SJani Nikula unsigned int pin) 122379bc100SJani Nikula { 12369e807a5SJani Nikula const struct gmbus_pin *pins; 12469e807a5SJani Nikula size_t size; 12569e807a5SJani Nikula 12669e807a5SJani Nikula if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { 12769e807a5SJani Nikula pins = gmbus_pins_dg2; 12869e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_dg2); 12969e807a5SJani Nikula } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 13069e807a5SJani Nikula pins = gmbus_pins_dg1; 13169e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_dg1); 13269e807a5SJani Nikula } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 13369e807a5SJani Nikula pins = gmbus_pins_icp; 13469e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_icp); 13569e807a5SJani Nikula } else if (HAS_PCH_CNP(i915)) { 13669e807a5SJani Nikula pins = gmbus_pins_cnp; 13769e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_cnp); 13869e807a5SJani Nikula } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 13969e807a5SJani Nikula pins = gmbus_pins_bxt; 14069e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_bxt); 14169e807a5SJani Nikula } else if (DISPLAY_VER(i915) == 9) { 14269e807a5SJani Nikula pins = gmbus_pins_skl; 14369e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_skl); 14469e807a5SJani Nikula } else if (IS_BROADWELL(i915)) { 14569e807a5SJani Nikula pins = gmbus_pins_bdw; 14669e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins_bdw); 14769e807a5SJani Nikula } else { 14869e807a5SJani Nikula pins = gmbus_pins; 14969e807a5SJani Nikula size = ARRAY_SIZE(gmbus_pins); 150379bc100SJani Nikula } 151379bc100SJani Nikula 15269e807a5SJani Nikula if (pin >= size || !pins[pin].name) 15369e807a5SJani Nikula return NULL; 15469e807a5SJani Nikula 15569e807a5SJani Nikula return &pins[pin]; 15669e807a5SJani Nikula } 15769e807a5SJani Nikula 15869e807a5SJani Nikula bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin) 159379bc100SJani Nikula { 16069e807a5SJani Nikula return get_gmbus_pin(i915, pin); 161379bc100SJani Nikula } 162379bc100SJani Nikula 163379bc100SJani Nikula /* Intel GPIO access functions */ 164379bc100SJani Nikula 165379bc100SJani Nikula #define I2C_RISEFALL_TIME 10 166379bc100SJani Nikula 167379bc100SJani Nikula static inline struct intel_gmbus * 168379bc100SJani Nikula to_intel_gmbus(struct i2c_adapter *i2c) 169379bc100SJani Nikula { 170379bc100SJani Nikula return container_of(i2c, struct intel_gmbus, adapter); 171379bc100SJani Nikula } 172379bc100SJani Nikula 173379bc100SJani Nikula void 174*6d737d9bSJani Nikula intel_gmbus_reset(struct drm_i915_private *i915) 175379bc100SJani Nikula { 176*6d737d9bSJani Nikula intel_de_write(i915, GMBUS0(i915), 0); 177*6d737d9bSJani Nikula intel_de_write(i915, GMBUS4(i915), 0); 178379bc100SJani Nikula } 179379bc100SJani Nikula 180379bc100SJani Nikula static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, 181379bc100SJani Nikula bool enable) 182379bc100SJani Nikula { 183379bc100SJani Nikula u32 val; 184379bc100SJani Nikula 185379bc100SJani Nikula /* When using bit bashing for I2C, this bit needs to be set to 1 */ 186d9053b23SJani Nikula val = intel_de_read(dev_priv, DSPCLK_GATE_D); 187379bc100SJani Nikula if (!enable) 188379bc100SJani Nikula val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 189379bc100SJani Nikula else 190379bc100SJani Nikula val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 191d9053b23SJani Nikula intel_de_write(dev_priv, DSPCLK_GATE_D, val); 192379bc100SJani Nikula } 193379bc100SJani Nikula 194379bc100SJani Nikula static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, 195379bc100SJani Nikula bool enable) 196379bc100SJani Nikula { 197379bc100SJani Nikula u32 val; 198379bc100SJani Nikula 199d9053b23SJani Nikula val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); 200379bc100SJani Nikula if (!enable) 201379bc100SJani Nikula val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 202379bc100SJani Nikula else 203379bc100SJani Nikula val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 204d9053b23SJani Nikula intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); 205379bc100SJani Nikula } 206379bc100SJani Nikula 207379bc100SJani Nikula static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, 208379bc100SJani Nikula bool enable) 209379bc100SJani Nikula { 210379bc100SJani Nikula u32 val; 211379bc100SJani Nikula 212d9053b23SJani Nikula val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); 213379bc100SJani Nikula if (!enable) 214379bc100SJani Nikula val |= BXT_GMBUS_GATING_DIS; 215379bc100SJani Nikula else 216379bc100SJani Nikula val &= ~BXT_GMBUS_GATING_DIS; 217d9053b23SJani Nikula intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); 218379bc100SJani Nikula } 219379bc100SJani Nikula 220379bc100SJani Nikula static u32 get_reserved(struct intel_gmbus *bus) 221379bc100SJani Nikula { 222379bc100SJani Nikula struct drm_i915_private *i915 = bus->dev_priv; 223379bc100SJani Nikula struct intel_uncore *uncore = &i915->uncore; 224379bc100SJani Nikula u32 reserved = 0; 225379bc100SJani Nikula 226379bc100SJani Nikula /* On most chips, these bits must be preserved in software. */ 227379bc100SJani Nikula if (!IS_I830(i915) && !IS_I845G(i915)) 228379bc100SJani Nikula reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 229379bc100SJani Nikula (GPIO_DATA_PULLUP_DISABLE | 230379bc100SJani Nikula GPIO_CLOCK_PULLUP_DISABLE); 231379bc100SJani Nikula 232379bc100SJani Nikula return reserved; 233379bc100SJani Nikula } 234379bc100SJani Nikula 235379bc100SJani Nikula static int get_clock(void *data) 236379bc100SJani Nikula { 237379bc100SJani Nikula struct intel_gmbus *bus = data; 238379bc100SJani Nikula struct intel_uncore *uncore = &bus->dev_priv->uncore; 239379bc100SJani Nikula u32 reserved = get_reserved(bus); 240379bc100SJani Nikula 241379bc100SJani Nikula intel_uncore_write_notrace(uncore, 242379bc100SJani Nikula bus->gpio_reg, 243379bc100SJani Nikula reserved | GPIO_CLOCK_DIR_MASK); 244379bc100SJani Nikula intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 245379bc100SJani Nikula 246379bc100SJani Nikula return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 247379bc100SJani Nikula GPIO_CLOCK_VAL_IN) != 0; 248379bc100SJani Nikula } 249379bc100SJani Nikula 250379bc100SJani Nikula static int get_data(void *data) 251379bc100SJani Nikula { 252379bc100SJani Nikula struct intel_gmbus *bus = data; 253379bc100SJani Nikula struct intel_uncore *uncore = &bus->dev_priv->uncore; 254379bc100SJani Nikula u32 reserved = get_reserved(bus); 255379bc100SJani Nikula 256379bc100SJani Nikula intel_uncore_write_notrace(uncore, 257379bc100SJani Nikula bus->gpio_reg, 258379bc100SJani Nikula reserved | GPIO_DATA_DIR_MASK); 259379bc100SJani Nikula intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 260379bc100SJani Nikula 261379bc100SJani Nikula return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 262379bc100SJani Nikula GPIO_DATA_VAL_IN) != 0; 263379bc100SJani Nikula } 264379bc100SJani Nikula 265379bc100SJani Nikula static void set_clock(void *data, int state_high) 266379bc100SJani Nikula { 267379bc100SJani Nikula struct intel_gmbus *bus = data; 268379bc100SJani Nikula struct intel_uncore *uncore = &bus->dev_priv->uncore; 269379bc100SJani Nikula u32 reserved = get_reserved(bus); 270379bc100SJani Nikula u32 clock_bits; 271379bc100SJani Nikula 272379bc100SJani Nikula if (state_high) 273379bc100SJani Nikula clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 274379bc100SJani Nikula else 275379bc100SJani Nikula clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 276379bc100SJani Nikula GPIO_CLOCK_VAL_MASK; 277379bc100SJani Nikula 278379bc100SJani Nikula intel_uncore_write_notrace(uncore, 279379bc100SJani Nikula bus->gpio_reg, 280379bc100SJani Nikula reserved | clock_bits); 281379bc100SJani Nikula intel_uncore_posting_read(uncore, bus->gpio_reg); 282379bc100SJani Nikula } 283379bc100SJani Nikula 284379bc100SJani Nikula static void set_data(void *data, int state_high) 285379bc100SJani Nikula { 286379bc100SJani Nikula struct intel_gmbus *bus = data; 287379bc100SJani Nikula struct intel_uncore *uncore = &bus->dev_priv->uncore; 288379bc100SJani Nikula u32 reserved = get_reserved(bus); 289379bc100SJani Nikula u32 data_bits; 290379bc100SJani Nikula 291379bc100SJani Nikula if (state_high) 292379bc100SJani Nikula data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 293379bc100SJani Nikula else 294379bc100SJani Nikula data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 295379bc100SJani Nikula GPIO_DATA_VAL_MASK; 296379bc100SJani Nikula 297379bc100SJani Nikula intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 298379bc100SJani Nikula intel_uncore_posting_read(uncore, bus->gpio_reg); 299379bc100SJani Nikula } 300379bc100SJani Nikula 301379bc100SJani Nikula static int 302379bc100SJani Nikula intel_gpio_pre_xfer(struct i2c_adapter *adapter) 303379bc100SJani Nikula { 30417e571feSJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 305379bc100SJani Nikula struct drm_i915_private *dev_priv = bus->dev_priv; 306379bc100SJani Nikula 307379bc100SJani Nikula intel_gmbus_reset(dev_priv); 308379bc100SJani Nikula 309379bc100SJani Nikula if (IS_PINEVIEW(dev_priv)) 310379bc100SJani Nikula pnv_gmbus_clock_gating(dev_priv, false); 311379bc100SJani Nikula 312379bc100SJani Nikula set_data(bus, 1); 313379bc100SJani Nikula set_clock(bus, 1); 314379bc100SJani Nikula udelay(I2C_RISEFALL_TIME); 315379bc100SJani Nikula return 0; 316379bc100SJani Nikula } 317379bc100SJani Nikula 318379bc100SJani Nikula static void 319379bc100SJani Nikula intel_gpio_post_xfer(struct i2c_adapter *adapter) 320379bc100SJani Nikula { 32117e571feSJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 322379bc100SJani Nikula struct drm_i915_private *dev_priv = bus->dev_priv; 323379bc100SJani Nikula 324379bc100SJani Nikula set_data(bus, 1); 325379bc100SJani Nikula set_clock(bus, 1); 326379bc100SJani Nikula 327379bc100SJani Nikula if (IS_PINEVIEW(dev_priv)) 328379bc100SJani Nikula pnv_gmbus_clock_gating(dev_priv, true); 329379bc100SJani Nikula } 330379bc100SJani Nikula 331379bc100SJani Nikula static void 33265cd963eSJani Nikula intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 333379bc100SJani Nikula { 334379bc100SJani Nikula struct i2c_algo_bit_data *algo; 335379bc100SJani Nikula 336379bc100SJani Nikula algo = &bus->bit_algo; 337379bc100SJani Nikula 33865cd963eSJani Nikula bus->gpio_reg = gpio_reg; 339379bc100SJani Nikula bus->adapter.algo_data = algo; 340379bc100SJani Nikula algo->setsda = set_data; 341379bc100SJani Nikula algo->setscl = set_clock; 342379bc100SJani Nikula algo->getsda = get_data; 343379bc100SJani Nikula algo->getscl = get_clock; 344379bc100SJani Nikula algo->pre_xfer = intel_gpio_pre_xfer; 345379bc100SJani Nikula algo->post_xfer = intel_gpio_post_xfer; 346379bc100SJani Nikula algo->udelay = I2C_RISEFALL_TIME; 347379bc100SJani Nikula algo->timeout = usecs_to_jiffies(2200); 348379bc100SJani Nikula algo->data = bus; 349379bc100SJani Nikula } 350379bc100SJani Nikula 351fa2a6c5bSVille Syrjälä static bool has_gmbus_irq(struct drm_i915_private *i915) 352fa2a6c5bSVille Syrjälä { 353fa2a6c5bSVille Syrjälä /* 354fa2a6c5bSVille Syrjälä * encoder->shutdown() may want to use GMBUS 355fa2a6c5bSVille Syrjälä * after irqs have already been disabled. 356fa2a6c5bSVille Syrjälä */ 357fa2a6c5bSVille Syrjälä return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); 358fa2a6c5bSVille Syrjälä } 359fa2a6c5bSVille Syrjälä 360379bc100SJani Nikula static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 361379bc100SJani Nikula { 362379bc100SJani Nikula DEFINE_WAIT(wait); 363379bc100SJani Nikula u32 gmbus2; 364379bc100SJani Nikula int ret; 365379bc100SJani Nikula 366379bc100SJani Nikula /* Important: The hw handles only the first bit, so set only one! Since 367379bc100SJani Nikula * we also need to check for NAKs besides the hw ready/idle signal, we 368379bc100SJani Nikula * need to wake up periodically and check that ourselves. 369379bc100SJani Nikula */ 370fa2a6c5bSVille Syrjälä if (!has_gmbus_irq(dev_priv)) 371379bc100SJani Nikula irq_en = 0; 372379bc100SJani Nikula 373203eb5a9SJani Nikula add_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait); 374*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS4(dev_priv), irq_en); 375379bc100SJani Nikula 376379bc100SJani Nikula status |= GMBUS_SATOER; 377*6d737d9bSJani Nikula ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2(dev_priv))) & status, 378d9053b23SJani Nikula 2); 379379bc100SJani Nikula if (ret) 380*6d737d9bSJani Nikula ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2(dev_priv))) & status, 381d9053b23SJani Nikula 50); 382379bc100SJani Nikula 383*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS4(dev_priv), 0); 384203eb5a9SJani Nikula remove_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait); 385379bc100SJani Nikula 386379bc100SJani Nikula if (gmbus2 & GMBUS_SATOER) 387379bc100SJani Nikula return -ENXIO; 388379bc100SJani Nikula 389379bc100SJani Nikula return ret; 390379bc100SJani Nikula } 391379bc100SJani Nikula 392379bc100SJani Nikula static int 393379bc100SJani Nikula gmbus_wait_idle(struct drm_i915_private *dev_priv) 394379bc100SJani Nikula { 395379bc100SJani Nikula DEFINE_WAIT(wait); 396379bc100SJani Nikula u32 irq_enable; 397379bc100SJani Nikula int ret; 398379bc100SJani Nikula 399379bc100SJani Nikula /* Important: The hw handles only the first bit, so set only one! */ 400379bc100SJani Nikula irq_enable = 0; 401fa2a6c5bSVille Syrjälä if (has_gmbus_irq(dev_priv)) 402379bc100SJani Nikula irq_enable = GMBUS_IDLE_EN; 403379bc100SJani Nikula 404203eb5a9SJani Nikula add_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait); 405*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS4(dev_priv), irq_enable); 406379bc100SJani Nikula 407379bc100SJani Nikula ret = intel_wait_for_register_fw(&dev_priv->uncore, 408*6d737d9bSJani Nikula GMBUS2(dev_priv), GMBUS_ACTIVE, 0, 409379bc100SJani Nikula 10); 410379bc100SJani Nikula 411*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS4(dev_priv), 0); 412203eb5a9SJani Nikula remove_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait); 413379bc100SJani Nikula 414379bc100SJani Nikula return ret; 415379bc100SJani Nikula } 416379bc100SJani Nikula 41781b55ef1SJani Nikula static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) 418379bc100SJani Nikula { 419005e9537SMatt Roper return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 420379bc100SJani Nikula GMBUS_BYTE_COUNT_MAX; 421379bc100SJani Nikula } 422379bc100SJani Nikula 423379bc100SJani Nikula static int 424379bc100SJani Nikula gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 425379bc100SJani Nikula unsigned short addr, u8 *buf, unsigned int len, 426379bc100SJani Nikula u32 gmbus0_reg, u32 gmbus1_index) 427379bc100SJani Nikula { 428379bc100SJani Nikula unsigned int size = len; 429379bc100SJani Nikula bool burst_read = len > gmbus_max_xfer_size(dev_priv); 430379bc100SJani Nikula bool extra_byte_added = false; 431379bc100SJani Nikula 432379bc100SJani Nikula if (burst_read) { 433379bc100SJani Nikula /* 434379bc100SJani Nikula * As per HW Spec, for 512Bytes need to read extra Byte and 435379bc100SJani Nikula * Ignore the extra byte read. 436379bc100SJani Nikula */ 437379bc100SJani Nikula if (len == 512) { 438379bc100SJani Nikula extra_byte_added = true; 439379bc100SJani Nikula len++; 440379bc100SJani Nikula } 441379bc100SJani Nikula size = len % 256 + 256; 442*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS0(dev_priv), 443d9053b23SJani Nikula gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 444379bc100SJani Nikula } 445379bc100SJani Nikula 446*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS1(dev_priv), 447d9053b23SJani Nikula gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 448379bc100SJani Nikula while (len) { 449379bc100SJani Nikula int ret; 450379bc100SJani Nikula u32 val, loop = 0; 451379bc100SJani Nikula 452379bc100SJani Nikula ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 453379bc100SJani Nikula if (ret) 454379bc100SJani Nikula return ret; 455379bc100SJani Nikula 456*6d737d9bSJani Nikula val = intel_de_read_fw(dev_priv, GMBUS3(dev_priv)); 457379bc100SJani Nikula do { 458379bc100SJani Nikula if (extra_byte_added && len == 1) 459379bc100SJani Nikula break; 460379bc100SJani Nikula 461379bc100SJani Nikula *buf++ = val & 0xff; 462379bc100SJani Nikula val >>= 8; 463379bc100SJani Nikula } while (--len && ++loop < 4); 464379bc100SJani Nikula 465379bc100SJani Nikula if (burst_read && len == size - 4) 466379bc100SJani Nikula /* Reset the override bit */ 467*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS0(dev_priv), gmbus0_reg); 468379bc100SJani Nikula } 469379bc100SJani Nikula 470379bc100SJani Nikula return 0; 471379bc100SJani Nikula } 472379bc100SJani Nikula 473379bc100SJani Nikula /* 474379bc100SJani Nikula * HW spec says that 512Bytes in Burst read need special treatment. 475379bc100SJani Nikula * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 476379bc100SJani Nikula * an I2C slave, which supports such a lengthy burst read too for experiments. 477379bc100SJani Nikula * 478379bc100SJani Nikula * So until things get clarified on HW support, to avoid the burst read length 479379bc100SJani Nikula * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 480379bc100SJani Nikula */ 481379bc100SJani Nikula #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 482379bc100SJani Nikula 483379bc100SJani Nikula static int 484379bc100SJani Nikula gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 485379bc100SJani Nikula u32 gmbus0_reg, u32 gmbus1_index) 486379bc100SJani Nikula { 487379bc100SJani Nikula u8 *buf = msg->buf; 488379bc100SJani Nikula unsigned int rx_size = msg->len; 489379bc100SJani Nikula unsigned int len; 490379bc100SJani Nikula int ret; 491379bc100SJani Nikula 492379bc100SJani Nikula do { 493379bc100SJani Nikula if (HAS_GMBUS_BURST_READ(dev_priv)) 494379bc100SJani Nikula len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 495379bc100SJani Nikula else 496379bc100SJani Nikula len = min(rx_size, gmbus_max_xfer_size(dev_priv)); 497379bc100SJani Nikula 498379bc100SJani Nikula ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, 499379bc100SJani Nikula gmbus0_reg, gmbus1_index); 500379bc100SJani Nikula if (ret) 501379bc100SJani Nikula return ret; 502379bc100SJani Nikula 503379bc100SJani Nikula rx_size -= len; 504379bc100SJani Nikula buf += len; 505379bc100SJani Nikula } while (rx_size != 0); 506379bc100SJani Nikula 507379bc100SJani Nikula return 0; 508379bc100SJani Nikula } 509379bc100SJani Nikula 510379bc100SJani Nikula static int 511379bc100SJani Nikula gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 512379bc100SJani Nikula unsigned short addr, u8 *buf, unsigned int len, 513379bc100SJani Nikula u32 gmbus1_index) 514379bc100SJani Nikula { 515379bc100SJani Nikula unsigned int chunk_size = len; 516379bc100SJani Nikula u32 val, loop; 517379bc100SJani Nikula 518379bc100SJani Nikula val = loop = 0; 519379bc100SJani Nikula while (len && loop < 4) { 520379bc100SJani Nikula val |= *buf++ << (8 * loop++); 521379bc100SJani Nikula len -= 1; 522379bc100SJani Nikula } 523379bc100SJani Nikula 524*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS3(dev_priv), val); 525*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS1(dev_priv), 526d9053b23SJani Nikula gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 527379bc100SJani Nikula while (len) { 528379bc100SJani Nikula int ret; 529379bc100SJani Nikula 530379bc100SJani Nikula val = loop = 0; 531379bc100SJani Nikula do { 532379bc100SJani Nikula val |= *buf++ << (8 * loop); 533379bc100SJani Nikula } while (--len && ++loop < 4); 534379bc100SJani Nikula 535*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS3(dev_priv), val); 536379bc100SJani Nikula 537379bc100SJani Nikula ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 538379bc100SJani Nikula if (ret) 539379bc100SJani Nikula return ret; 540379bc100SJani Nikula } 541379bc100SJani Nikula 542379bc100SJani Nikula return 0; 543379bc100SJani Nikula } 544379bc100SJani Nikula 545379bc100SJani Nikula static int 546379bc100SJani Nikula gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 547379bc100SJani Nikula u32 gmbus1_index) 548379bc100SJani Nikula { 549379bc100SJani Nikula u8 *buf = msg->buf; 550379bc100SJani Nikula unsigned int tx_size = msg->len; 551379bc100SJani Nikula unsigned int len; 552379bc100SJani Nikula int ret; 553379bc100SJani Nikula 554379bc100SJani Nikula do { 555379bc100SJani Nikula len = min(tx_size, gmbus_max_xfer_size(dev_priv)); 556379bc100SJani Nikula 557379bc100SJani Nikula ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, 558379bc100SJani Nikula gmbus1_index); 559379bc100SJani Nikula if (ret) 560379bc100SJani Nikula return ret; 561379bc100SJani Nikula 562379bc100SJani Nikula buf += len; 563379bc100SJani Nikula tx_size -= len; 564379bc100SJani Nikula } while (tx_size != 0); 565379bc100SJani Nikula 566379bc100SJani Nikula return 0; 567379bc100SJani Nikula } 568379bc100SJani Nikula 569379bc100SJani Nikula /* 570379bc100SJani Nikula * The gmbus controller can combine a 1 or 2 byte write with another read/write 571379bc100SJani Nikula * that immediately follows it by using an "INDEX" cycle. 572379bc100SJani Nikula */ 573379bc100SJani Nikula static bool 574379bc100SJani Nikula gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 575379bc100SJani Nikula { 576379bc100SJani Nikula return (i + 1 < num && 577379bc100SJani Nikula msgs[i].addr == msgs[i + 1].addr && 578379bc100SJani Nikula !(msgs[i].flags & I2C_M_RD) && 579379bc100SJani Nikula (msgs[i].len == 1 || msgs[i].len == 2) && 580379bc100SJani Nikula msgs[i + 1].len > 0); 581379bc100SJani Nikula } 582379bc100SJani Nikula 583379bc100SJani Nikula static int 584379bc100SJani Nikula gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, 585379bc100SJani Nikula u32 gmbus0_reg) 586379bc100SJani Nikula { 587379bc100SJani Nikula u32 gmbus1_index = 0; 588379bc100SJani Nikula u32 gmbus5 = 0; 589379bc100SJani Nikula int ret; 590379bc100SJani Nikula 591379bc100SJani Nikula if (msgs[0].len == 2) 592379bc100SJani Nikula gmbus5 = GMBUS_2BYTE_INDEX_EN | 593379bc100SJani Nikula msgs[0].buf[1] | (msgs[0].buf[0] << 8); 594379bc100SJani Nikula if (msgs[0].len == 1) 595379bc100SJani Nikula gmbus1_index = GMBUS_CYCLE_INDEX | 596379bc100SJani Nikula (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 597379bc100SJani Nikula 598379bc100SJani Nikula /* GMBUS5 holds 16-bit index */ 599379bc100SJani Nikula if (gmbus5) 600*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS5(dev_priv), gmbus5); 601379bc100SJani Nikula 602379bc100SJani Nikula if (msgs[1].flags & I2C_M_RD) 603379bc100SJani Nikula ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, 604379bc100SJani Nikula gmbus1_index); 605379bc100SJani Nikula else 606379bc100SJani Nikula ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); 607379bc100SJani Nikula 608379bc100SJani Nikula /* Clear GMBUS5 after each index transfer */ 609379bc100SJani Nikula if (gmbus5) 610*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS5(dev_priv), 0); 611379bc100SJani Nikula 612379bc100SJani Nikula return ret; 613379bc100SJani Nikula } 614379bc100SJani Nikula 615379bc100SJani Nikula static int 616379bc100SJani Nikula do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 617379bc100SJani Nikula u32 gmbus0_source) 618379bc100SJani Nikula { 61917e571feSJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 620379bc100SJani Nikula struct drm_i915_private *dev_priv = bus->dev_priv; 621379bc100SJani Nikula int i = 0, inc, try = 0; 622379bc100SJani Nikula int ret = 0; 623379bc100SJani Nikula 624244dba4cSLucas De Marchi /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 62570bfb307SMatt Roper if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 626379bc100SJani Nikula bxt_gmbus_clock_gating(dev_priv, false); 627379bc100SJani Nikula else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 628379bc100SJani Nikula pch_gmbus_clock_gating(dev_priv, false); 629379bc100SJani Nikula 630379bc100SJani Nikula retry: 631*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS0(dev_priv), gmbus0_source | bus->reg0); 632379bc100SJani Nikula 633379bc100SJani Nikula for (; i < num; i += inc) { 634379bc100SJani Nikula inc = 1; 635379bc100SJani Nikula if (gmbus_is_index_xfer(msgs, i, num)) { 636379bc100SJani Nikula ret = gmbus_index_xfer(dev_priv, &msgs[i], 637379bc100SJani Nikula gmbus0_source | bus->reg0); 638379bc100SJani Nikula inc = 2; /* an index transmission is two msgs */ 639379bc100SJani Nikula } else if (msgs[i].flags & I2C_M_RD) { 640379bc100SJani Nikula ret = gmbus_xfer_read(dev_priv, &msgs[i], 641379bc100SJani Nikula gmbus0_source | bus->reg0, 0); 642379bc100SJani Nikula } else { 643379bc100SJani Nikula ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); 644379bc100SJani Nikula } 645379bc100SJani Nikula 646379bc100SJani Nikula if (!ret) 647379bc100SJani Nikula ret = gmbus_wait(dev_priv, 648379bc100SJani Nikula GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 649379bc100SJani Nikula if (ret == -ETIMEDOUT) 650379bc100SJani Nikula goto timeout; 651379bc100SJani Nikula else if (ret) 652379bc100SJani Nikula goto clear_err; 653379bc100SJani Nikula } 654379bc100SJani Nikula 655379bc100SJani Nikula /* Generate a STOP condition on the bus. Note that gmbus can't generata 656379bc100SJani Nikula * a STOP on the very first cycle. To simplify the code we 657379bc100SJani Nikula * unconditionally generate the STOP condition with an additional gmbus 658379bc100SJani Nikula * cycle. */ 659*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS1(dev_priv), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 660379bc100SJani Nikula 661379bc100SJani Nikula /* Mark the GMBUS interface as disabled after waiting for idle. 662379bc100SJani Nikula * We will re-enable it at the start of the next xfer, 663379bc100SJani Nikula * till then let it sleep. 664379bc100SJani Nikula */ 665379bc100SJani Nikula if (gmbus_wait_idle(dev_priv)) { 6666a9cc4bfSWambui Karuga drm_dbg_kms(&dev_priv->drm, 6676a9cc4bfSWambui Karuga "GMBUS [%s] timed out waiting for idle\n", 668379bc100SJani Nikula adapter->name); 669379bc100SJani Nikula ret = -ETIMEDOUT; 670379bc100SJani Nikula } 671*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS0(dev_priv), 0); 672379bc100SJani Nikula ret = ret ?: i; 673379bc100SJani Nikula goto out; 674379bc100SJani Nikula 675379bc100SJani Nikula clear_err: 676379bc100SJani Nikula /* 677379bc100SJani Nikula * Wait for bus to IDLE before clearing NAK. 678379bc100SJani Nikula * If we clear the NAK while bus is still active, then it will stay 679379bc100SJani Nikula * active and the next transaction may fail. 680379bc100SJani Nikula * 681379bc100SJani Nikula * If no ACK is received during the address phase of a transaction, the 682379bc100SJani Nikula * adapter must report -ENXIO. It is not clear what to return if no ACK 683379bc100SJani Nikula * is received at other times. But we have to be careful to not return 684379bc100SJani Nikula * spurious -ENXIO because that will prevent i2c and drm edid functions 685379bc100SJani Nikula * from retrying. So return -ENXIO only when gmbus properly quiescents - 686379bc100SJani Nikula * timing out seems to happen when there _is_ a ddc chip present, but 687379bc100SJani Nikula * it's slow responding and only answers on the 2nd retry. 688379bc100SJani Nikula */ 689379bc100SJani Nikula ret = -ENXIO; 690379bc100SJani Nikula if (gmbus_wait_idle(dev_priv)) { 6916a9cc4bfSWambui Karuga drm_dbg_kms(&dev_priv->drm, 6926a9cc4bfSWambui Karuga "GMBUS [%s] timed out after NAK\n", 693379bc100SJani Nikula adapter->name); 694379bc100SJani Nikula ret = -ETIMEDOUT; 695379bc100SJani Nikula } 696379bc100SJani Nikula 697379bc100SJani Nikula /* Toggle the Software Clear Interrupt bit. This has the effect 698379bc100SJani Nikula * of resetting the GMBUS controller and so clearing the 699379bc100SJani Nikula * BUS_ERROR raised by the slave's NAK. 700379bc100SJani Nikula */ 701*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS1(dev_priv), GMBUS_SW_CLR_INT); 702*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS1(dev_priv), 0); 703*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS0(dev_priv), 0); 704379bc100SJani Nikula 7056a9cc4bfSWambui Karuga drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 706379bc100SJani Nikula adapter->name, msgs[i].addr, 707379bc100SJani Nikula (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 708379bc100SJani Nikula 709379bc100SJani Nikula /* 710379bc100SJani Nikula * Passive adapters sometimes NAK the first probe. Retry the first 711379bc100SJani Nikula * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 712379bc100SJani Nikula * has retries internally. See also the retry loop in 713379bc100SJani Nikula * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 714379bc100SJani Nikula */ 715379bc100SJani Nikula if (ret == -ENXIO && i == 0 && try++ == 0) { 7166a9cc4bfSWambui Karuga drm_dbg_kms(&dev_priv->drm, 7176a9cc4bfSWambui Karuga "GMBUS [%s] NAK on first message, retry\n", 718379bc100SJani Nikula adapter->name); 719379bc100SJani Nikula goto retry; 720379bc100SJani Nikula } 721379bc100SJani Nikula 722379bc100SJani Nikula goto out; 723379bc100SJani Nikula 724379bc100SJani Nikula timeout: 7256a9cc4bfSWambui Karuga drm_dbg_kms(&dev_priv->drm, 7266a9cc4bfSWambui Karuga "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 727379bc100SJani Nikula bus->adapter.name, bus->reg0 & 0xff); 728*6d737d9bSJani Nikula intel_de_write_fw(dev_priv, GMBUS0(dev_priv), 0); 729379bc100SJani Nikula 730379bc100SJani Nikula /* 731379bc100SJani Nikula * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 732379bc100SJani Nikula * instead. Use EAGAIN to have i2c core retry. 733379bc100SJani Nikula */ 734379bc100SJani Nikula ret = -EAGAIN; 735379bc100SJani Nikula 736379bc100SJani Nikula out: 737244dba4cSLucas De Marchi /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 73870bfb307SMatt Roper if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 739379bc100SJani Nikula bxt_gmbus_clock_gating(dev_priv, true); 740379bc100SJani Nikula else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 741379bc100SJani Nikula pch_gmbus_clock_gating(dev_priv, true); 742379bc100SJani Nikula 743379bc100SJani Nikula return ret; 744379bc100SJani Nikula } 745379bc100SJani Nikula 746379bc100SJani Nikula static int 747379bc100SJani Nikula gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 748379bc100SJani Nikula { 74917e571feSJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 750379bc100SJani Nikula struct drm_i915_private *dev_priv = bus->dev_priv; 751379bc100SJani Nikula intel_wakeref_t wakeref; 752379bc100SJani Nikula int ret; 753379bc100SJani Nikula 754379bc100SJani Nikula wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 755379bc100SJani Nikula 756379bc100SJani Nikula if (bus->force_bit) { 757379bc100SJani Nikula ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 758379bc100SJani Nikula if (ret < 0) 759379bc100SJani Nikula bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 760379bc100SJani Nikula } else { 761379bc100SJani Nikula ret = do_gmbus_xfer(adapter, msgs, num, 0); 762379bc100SJani Nikula if (ret == -EAGAIN) 763379bc100SJani Nikula bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 764379bc100SJani Nikula } 765379bc100SJani Nikula 766379bc100SJani Nikula intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 767379bc100SJani Nikula 768379bc100SJani Nikula return ret; 769379bc100SJani Nikula } 770379bc100SJani Nikula 771379bc100SJani Nikula int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 772379bc100SJani Nikula { 77317e571feSJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 774379bc100SJani Nikula struct drm_i915_private *dev_priv = bus->dev_priv; 775379bc100SJani Nikula u8 cmd = DRM_HDCP_DDC_AKSV; 776379bc100SJani Nikula u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 777379bc100SJani Nikula struct i2c_msg msgs[] = { 778379bc100SJani Nikula { 779379bc100SJani Nikula .addr = DRM_HDCP_DDC_ADDR, 780379bc100SJani Nikula .flags = 0, 781379bc100SJani Nikula .len = sizeof(cmd), 782379bc100SJani Nikula .buf = &cmd, 783379bc100SJani Nikula }, 784379bc100SJani Nikula { 785379bc100SJani Nikula .addr = DRM_HDCP_DDC_ADDR, 786379bc100SJani Nikula .flags = 0, 787379bc100SJani Nikula .len = sizeof(buf), 788379bc100SJani Nikula .buf = buf, 789379bc100SJani Nikula } 790379bc100SJani Nikula }; 791379bc100SJani Nikula intel_wakeref_t wakeref; 792379bc100SJani Nikula int ret; 793379bc100SJani Nikula 794379bc100SJani Nikula wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 795203eb5a9SJani Nikula mutex_lock(&dev_priv->display.gmbus.mutex); 796379bc100SJani Nikula 797379bc100SJani Nikula /* 798379bc100SJani Nikula * In order to output Aksv to the receiver, use an indexed write to 799379bc100SJani Nikula * pass the i2c command, and tell GMBUS to use the HW-provided value 800379bc100SJani Nikula * instead of sourcing GMBUS3 for the data. 801379bc100SJani Nikula */ 802379bc100SJani Nikula ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 803379bc100SJani Nikula 804203eb5a9SJani Nikula mutex_unlock(&dev_priv->display.gmbus.mutex); 805379bc100SJani Nikula intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 806379bc100SJani Nikula 807379bc100SJani Nikula return ret; 808379bc100SJani Nikula } 809379bc100SJani Nikula 810379bc100SJani Nikula static u32 gmbus_func(struct i2c_adapter *adapter) 811379bc100SJani Nikula { 812379bc100SJani Nikula return i2c_bit_algo.functionality(adapter) & 813379bc100SJani Nikula (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 814379bc100SJani Nikula /* I2C_FUNC_10BIT_ADDR | */ 815379bc100SJani Nikula I2C_FUNC_SMBUS_READ_BLOCK_DATA | 816379bc100SJani Nikula I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 817379bc100SJani Nikula } 818379bc100SJani Nikula 819379bc100SJani Nikula static const struct i2c_algorithm gmbus_algorithm = { 820379bc100SJani Nikula .master_xfer = gmbus_xfer, 821379bc100SJani Nikula .functionality = gmbus_func 822379bc100SJani Nikula }; 823379bc100SJani Nikula 824379bc100SJani Nikula static void gmbus_lock_bus(struct i2c_adapter *adapter, 825379bc100SJani Nikula unsigned int flags) 826379bc100SJani Nikula { 827379bc100SJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 828379bc100SJani Nikula struct drm_i915_private *dev_priv = bus->dev_priv; 829379bc100SJani Nikula 830203eb5a9SJani Nikula mutex_lock(&dev_priv->display.gmbus.mutex); 831379bc100SJani Nikula } 832379bc100SJani Nikula 833379bc100SJani Nikula static int gmbus_trylock_bus(struct i2c_adapter *adapter, 834379bc100SJani Nikula unsigned int flags) 835379bc100SJani Nikula { 836379bc100SJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 837379bc100SJani Nikula struct drm_i915_private *dev_priv = bus->dev_priv; 838379bc100SJani Nikula 839203eb5a9SJani Nikula return mutex_trylock(&dev_priv->display.gmbus.mutex); 840379bc100SJani Nikula } 841379bc100SJani Nikula 842379bc100SJani Nikula static void gmbus_unlock_bus(struct i2c_adapter *adapter, 843379bc100SJani Nikula unsigned int flags) 844379bc100SJani Nikula { 845379bc100SJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 846379bc100SJani Nikula struct drm_i915_private *dev_priv = bus->dev_priv; 847379bc100SJani Nikula 848203eb5a9SJani Nikula mutex_unlock(&dev_priv->display.gmbus.mutex); 849379bc100SJani Nikula } 850379bc100SJani Nikula 851379bc100SJani Nikula static const struct i2c_lock_operations gmbus_lock_ops = { 852379bc100SJani Nikula .lock_bus = gmbus_lock_bus, 853379bc100SJani Nikula .trylock_bus = gmbus_trylock_bus, 854379bc100SJani Nikula .unlock_bus = gmbus_unlock_bus, 855379bc100SJani Nikula }; 856379bc100SJani Nikula 857379bc100SJani Nikula /** 858379bc100SJani Nikula * intel_gmbus_setup - instantiate all Intel i2c GMBuses 859379bc100SJani Nikula * @dev_priv: i915 device private 860379bc100SJani Nikula */ 861379bc100SJani Nikula int intel_gmbus_setup(struct drm_i915_private *dev_priv) 862379bc100SJani Nikula { 8638ff5446aSThomas Zimmermann struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 864379bc100SJani Nikula unsigned int pin; 865379bc100SJani Nikula int ret; 866379bc100SJani Nikula 867379bc100SJani Nikula if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 868203eb5a9SJani Nikula dev_priv->display.gmbus.mmio_base = VLV_DISPLAY_BASE; 869379bc100SJani Nikula else if (!HAS_GMCH(dev_priv)) 870379bc100SJani Nikula /* 871379bc100SJani Nikula * Broxton uses the same PCH offsets for South Display Engine, 872379bc100SJani Nikula * even though it doesn't have a PCH. 873379bc100SJani Nikula */ 874203eb5a9SJani Nikula dev_priv->display.gmbus.mmio_base = PCH_DISPLAY_BASE; 875379bc100SJani Nikula 876203eb5a9SJani Nikula mutex_init(&dev_priv->display.gmbus.mutex); 877203eb5a9SJani Nikula init_waitqueue_head(&dev_priv->display.gmbus.wait_queue); 878379bc100SJani Nikula 879203eb5a9SJani Nikula for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus.bus); pin++) { 88039a8c428SJani Nikula const struct gmbus_pin *gmbus_pin; 88171abfcbeSJani Nikula struct intel_gmbus *bus; 88239a8c428SJani Nikula 88339a8c428SJani Nikula gmbus_pin = get_gmbus_pin(dev_priv, pin); 88439a8c428SJani Nikula if (!gmbus_pin) 885379bc100SJani Nikula continue; 886379bc100SJani Nikula 88763a78bbbSJani Nikula bus = kzalloc(sizeof(*bus), GFP_KERNEL); 88863a78bbbSJani Nikula if (!bus) { 88963a78bbbSJani Nikula ret = -ENOMEM; 89063a78bbbSJani Nikula goto err; 89163a78bbbSJani Nikula } 892379bc100SJani Nikula 893379bc100SJani Nikula bus->adapter.owner = THIS_MODULE; 894379bc100SJani Nikula bus->adapter.class = I2C_CLASS_DDC; 895379bc100SJani Nikula snprintf(bus->adapter.name, 896379bc100SJani Nikula sizeof(bus->adapter.name), 89739a8c428SJani Nikula "i915 gmbus %s", gmbus_pin->name); 898379bc100SJani Nikula 899379bc100SJani Nikula bus->adapter.dev.parent = &pdev->dev; 900379bc100SJani Nikula bus->dev_priv = dev_priv; 901379bc100SJani Nikula 902379bc100SJani Nikula bus->adapter.algo = &gmbus_algorithm; 903379bc100SJani Nikula bus->adapter.lock_ops = &gmbus_lock_ops; 904379bc100SJani Nikula 905379bc100SJani Nikula /* 906379bc100SJani Nikula * We wish to retry with bit banging 907379bc100SJani Nikula * after a timed out GMBUS attempt. 908379bc100SJani Nikula */ 909379bc100SJani Nikula bus->adapter.retries = 1; 910379bc100SJani Nikula 911379bc100SJani Nikula /* By default use a conservative clock rate */ 912379bc100SJani Nikula bus->reg0 = pin | GMBUS_RATE_100KHZ; 913379bc100SJani Nikula 914379bc100SJani Nikula /* gmbus seems to be broken on i830 */ 915379bc100SJani Nikula if (IS_I830(dev_priv)) 916379bc100SJani Nikula bus->force_bit = 1; 917379bc100SJani Nikula 918*6d737d9bSJani Nikula intel_gpio_setup(bus, GPIO(dev_priv, gmbus_pin->gpio)); 919379bc100SJani Nikula 920379bc100SJani Nikula ret = i2c_add_adapter(&bus->adapter); 92163a78bbbSJani Nikula if (ret) { 92263a78bbbSJani Nikula kfree(bus); 923379bc100SJani Nikula goto err; 924379bc100SJani Nikula } 925379bc100SJani Nikula 926203eb5a9SJani Nikula dev_priv->display.gmbus.bus[pin] = bus; 92763a78bbbSJani Nikula } 92863a78bbbSJani Nikula 929379bc100SJani Nikula intel_gmbus_reset(dev_priv); 930379bc100SJani Nikula 931379bc100SJani Nikula return 0; 932379bc100SJani Nikula 933379bc100SJani Nikula err: 93463a78bbbSJani Nikula intel_gmbus_teardown(dev_priv); 935379bc100SJani Nikula 936379bc100SJani Nikula return ret; 937379bc100SJani Nikula } 938379bc100SJani Nikula 939379bc100SJani Nikula struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 940379bc100SJani Nikula unsigned int pin) 941379bc100SJani Nikula { 942203eb5a9SJani Nikula if (drm_WARN_ON(&dev_priv->drm, pin >= ARRAY_SIZE(dev_priv->display.gmbus.bus) || 943203eb5a9SJani Nikula !dev_priv->display.gmbus.bus[pin])) 944379bc100SJani Nikula return NULL; 945379bc100SJani Nikula 946203eb5a9SJani Nikula return &dev_priv->display.gmbus.bus[pin]->adapter; 947379bc100SJani Nikula } 948379bc100SJani Nikula 949379bc100SJani Nikula void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 950379bc100SJani Nikula { 951379bc100SJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 952379bc100SJani Nikula struct drm_i915_private *dev_priv = bus->dev_priv; 953379bc100SJani Nikula 954203eb5a9SJani Nikula mutex_lock(&dev_priv->display.gmbus.mutex); 955379bc100SJani Nikula 956379bc100SJani Nikula bus->force_bit += force_bit ? 1 : -1; 9576a9cc4bfSWambui Karuga drm_dbg_kms(&dev_priv->drm, 9586a9cc4bfSWambui Karuga "%sabling bit-banging on %s. force bit now %d\n", 959379bc100SJani Nikula force_bit ? "en" : "dis", adapter->name, 960379bc100SJani Nikula bus->force_bit); 961379bc100SJani Nikula 962203eb5a9SJani Nikula mutex_unlock(&dev_priv->display.gmbus.mutex); 963379bc100SJani Nikula } 964379bc100SJani Nikula 965379bc100SJani Nikula bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 966379bc100SJani Nikula { 967379bc100SJani Nikula struct intel_gmbus *bus = to_intel_gmbus(adapter); 968379bc100SJani Nikula 969379bc100SJani Nikula return bus->force_bit; 970379bc100SJani Nikula } 971379bc100SJani Nikula 972379bc100SJani Nikula void intel_gmbus_teardown(struct drm_i915_private *dev_priv) 973379bc100SJani Nikula { 974379bc100SJani Nikula unsigned int pin; 975379bc100SJani Nikula 976203eb5a9SJani Nikula for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus.bus); pin++) { 97771abfcbeSJani Nikula struct intel_gmbus *bus; 97871abfcbeSJani Nikula 979203eb5a9SJani Nikula bus = dev_priv->display.gmbus.bus[pin]; 98063a78bbbSJani Nikula if (!bus) 981379bc100SJani Nikula continue; 982379bc100SJani Nikula 983379bc100SJani Nikula i2c_del_adapter(&bus->adapter); 98463a78bbbSJani Nikula 98563a78bbbSJani Nikula kfree(bus); 986203eb5a9SJani Nikula dev_priv->display.gmbus.bus[pin] = NULL; 987379bc100SJani Nikula } 988379bc100SJani Nikula } 989