1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel.vetter@ffwll.ch> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include "intel_fbc.h" 31 #include "intel_fifo_underrun.h" 32 33 /** 34 * DOC: fifo underrun handling 35 * 36 * The i915 driver checks for display fifo underruns using the interrupt signals 37 * provided by the hardware. This is enabled by default and fairly useful to 38 * debug display issues, especially watermark settings. 39 * 40 * If an underrun is detected this is logged into dmesg. To avoid flooding logs 41 * and occupying the cpu underrun interrupts are disabled after the first 42 * occurrence until the next modeset on a given pipe. 43 * 44 * Note that underrun detection on gmch platforms is a bit more ugly since there 45 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe 46 * interrupt register). Also on some other platforms underrun interrupts are 47 * shared, which means that if we detect an underrun we need to disable underrun 48 * reporting on all pipes. 49 * 50 * The code also supports underrun detection on the PCH transcoder. 51 */ 52 53 static bool ivb_can_enable_err_int(struct drm_device *dev) 54 { 55 struct drm_i915_private *dev_priv = to_i915(dev); 56 struct intel_crtc *crtc; 57 enum pipe pipe; 58 59 lockdep_assert_held(&dev_priv->irq_lock); 60 61 for_each_pipe(dev_priv, pipe) { 62 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 63 64 if (crtc->cpu_fifo_underrun_disabled) 65 return false; 66 } 67 68 return true; 69 } 70 71 static bool cpt_can_enable_serr_int(struct drm_device *dev) 72 { 73 struct drm_i915_private *dev_priv = to_i915(dev); 74 enum pipe pipe; 75 struct intel_crtc *crtc; 76 77 lockdep_assert_held(&dev_priv->irq_lock); 78 79 for_each_pipe(dev_priv, pipe) { 80 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 81 82 if (crtc->pch_fifo_underrun_disabled) 83 return false; 84 } 85 86 return true; 87 } 88 89 static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) 90 { 91 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 92 i915_reg_t reg = PIPESTAT(crtc->pipe); 93 u32 enable_mask; 94 95 lockdep_assert_held(&dev_priv->irq_lock); 96 97 if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) 98 return; 99 100 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); 101 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 102 POSTING_READ(reg); 103 104 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); 105 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); 106 } 107 108 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, 109 enum pipe pipe, 110 bool enable, bool old) 111 { 112 struct drm_i915_private *dev_priv = to_i915(dev); 113 i915_reg_t reg = PIPESTAT(pipe); 114 115 lockdep_assert_held(&dev_priv->irq_lock); 116 117 if (enable) { 118 u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 119 120 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 121 POSTING_READ(reg); 122 } else { 123 if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) 124 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 125 } 126 } 127 128 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, 129 enum pipe pipe, bool enable) 130 { 131 struct drm_i915_private *dev_priv = to_i915(dev); 132 u32 bit = (pipe == PIPE_A) ? 133 DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN; 134 135 if (enable) 136 ilk_enable_display_irq(dev_priv, bit); 137 else 138 ilk_disable_display_irq(dev_priv, bit); 139 } 140 141 static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc) 142 { 143 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 144 enum pipe pipe = crtc->pipe; 145 u32 err_int = I915_READ(GEN7_ERR_INT); 146 147 lockdep_assert_held(&dev_priv->irq_lock); 148 149 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) 150 return; 151 152 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 153 POSTING_READ(GEN7_ERR_INT); 154 155 trace_intel_cpu_fifo_underrun(dev_priv, pipe); 156 DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe)); 157 } 158 159 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, 160 enum pipe pipe, 161 bool enable, bool old) 162 { 163 struct drm_i915_private *dev_priv = to_i915(dev); 164 if (enable) { 165 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 166 167 if (!ivb_can_enable_err_int(dev)) 168 return; 169 170 ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); 171 } else { 172 ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); 173 174 if (old && 175 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { 176 DRM_ERROR("uncleared fifo underrun on pipe %c\n", 177 pipe_name(pipe)); 178 } 179 } 180 } 181 182 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, 183 enum pipe pipe, bool enable) 184 { 185 struct drm_i915_private *dev_priv = to_i915(dev); 186 187 if (enable) 188 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); 189 else 190 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); 191 } 192 193 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, 194 enum pipe pch_transcoder, 195 bool enable) 196 { 197 struct drm_i915_private *dev_priv = to_i915(dev); 198 u32 bit = (pch_transcoder == PIPE_A) ? 199 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; 200 201 if (enable) 202 ibx_enable_display_interrupt(dev_priv, bit); 203 else 204 ibx_disable_display_interrupt(dev_priv, bit); 205 } 206 207 static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) 208 { 209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 210 enum pipe pch_transcoder = crtc->pipe; 211 u32 serr_int = I915_READ(SERR_INT); 212 213 lockdep_assert_held(&dev_priv->irq_lock); 214 215 if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) 216 return; 217 218 I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 219 POSTING_READ(SERR_INT); 220 221 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); 222 DRM_ERROR("pch fifo underrun on pch transcoder %c\n", 223 pipe_name(pch_transcoder)); 224 } 225 226 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 227 enum pipe pch_transcoder, 228 bool enable, bool old) 229 { 230 struct drm_i915_private *dev_priv = to_i915(dev); 231 232 if (enable) { 233 I915_WRITE(SERR_INT, 234 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 235 236 if (!cpt_can_enable_serr_int(dev)) 237 return; 238 239 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); 240 } else { 241 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); 242 243 if (old && I915_READ(SERR_INT) & 244 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { 245 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", 246 pipe_name(pch_transcoder)); 247 } 248 } 249 } 250 251 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 252 enum pipe pipe, bool enable) 253 { 254 struct drm_i915_private *dev_priv = to_i915(dev); 255 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 256 bool old; 257 258 lockdep_assert_held(&dev_priv->irq_lock); 259 260 old = !crtc->cpu_fifo_underrun_disabled; 261 crtc->cpu_fifo_underrun_disabled = !enable; 262 263 if (HAS_GMCH(dev_priv)) 264 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); 265 else if (IS_GEN_RANGE(dev_priv, 5, 6)) 266 ironlake_set_fifo_underrun_reporting(dev, pipe, enable); 267 else if (IS_GEN(dev_priv, 7)) 268 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); 269 else if (INTEL_GEN(dev_priv) >= 8) 270 broadwell_set_fifo_underrun_reporting(dev, pipe, enable); 271 272 return old; 273 } 274 275 /** 276 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state 277 * @dev_priv: i915 device instance 278 * @pipe: (CPU) pipe to set state for 279 * @enable: whether underruns should be reported or not 280 * 281 * This function sets the fifo underrun state for @pipe. It is used in the 282 * modeset code to avoid false positives since on many platforms underruns are 283 * expected when disabling or enabling the pipe. 284 * 285 * Notice that on some platforms disabling underrun reports for one pipe 286 * disables for all due to shared interrupts. Actual reporting is still per-pipe 287 * though. 288 * 289 * Returns the previous state of underrun reporting. 290 */ 291 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 292 enum pipe pipe, bool enable) 293 { 294 unsigned long flags; 295 bool ret; 296 297 spin_lock_irqsave(&dev_priv->irq_lock, flags); 298 ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, 299 enable); 300 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 301 302 return ret; 303 } 304 305 /** 306 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state 307 * @dev_priv: i915 device instance 308 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 309 * @enable: whether underruns should be reported or not 310 * 311 * This function makes us disable or enable PCH fifo underruns for a specific 312 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO 313 * underrun reporting for one transcoder may also disable all the other PCH 314 * error interruts for the other transcoders, due to the fact that there's just 315 * one interrupt mask/enable bit for all the transcoders. 316 * 317 * Returns the previous state of underrun reporting. 318 */ 319 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 320 enum pipe pch_transcoder, 321 bool enable) 322 { 323 struct intel_crtc *crtc = 324 intel_get_crtc_for_pipe(dev_priv, pch_transcoder); 325 unsigned long flags; 326 bool old; 327 328 /* 329 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT 330 * has only one pch transcoder A that all pipes can use. To avoid racy 331 * pch transcoder -> pipe lookups from interrupt code simply store the 332 * underrun statistics in crtc A. Since we never expose this anywhere 333 * nor use it outside of the fifo underrun code here using the "wrong" 334 * crtc on LPT won't cause issues. 335 */ 336 337 spin_lock_irqsave(&dev_priv->irq_lock, flags); 338 339 old = !crtc->pch_fifo_underrun_disabled; 340 crtc->pch_fifo_underrun_disabled = !enable; 341 342 if (HAS_PCH_IBX(dev_priv)) 343 ibx_set_fifo_underrun_reporting(&dev_priv->drm, 344 pch_transcoder, 345 enable); 346 else 347 cpt_set_fifo_underrun_reporting(&dev_priv->drm, 348 pch_transcoder, 349 enable, old); 350 351 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 352 return old; 353 } 354 355 /** 356 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt 357 * @dev_priv: i915 device instance 358 * @pipe: (CPU) pipe to set state for 359 * 360 * This handles a CPU fifo underrun interrupt, generating an underrun warning 361 * into dmesg if underrun reporting is enabled and then disables the underrun 362 * interrupt to avoid an irq storm. 363 */ 364 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 365 enum pipe pipe) 366 { 367 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 368 369 /* We may be called too early in init, thanks BIOS! */ 370 if (crtc == NULL) 371 return; 372 373 /* GMCH can't disable fifo underruns, filter them. */ 374 if (HAS_GMCH(dev_priv) && 375 crtc->cpu_fifo_underrun_disabled) 376 return; 377 378 if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { 379 trace_intel_cpu_fifo_underrun(dev_priv, pipe); 380 DRM_ERROR("CPU pipe %c FIFO underrun\n", 381 pipe_name(pipe)); 382 } 383 384 intel_fbc_handle_fifo_underrun_irq(dev_priv); 385 } 386 387 /** 388 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt 389 * @dev_priv: i915 device instance 390 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 391 * 392 * This handles a PCH fifo underrun interrupt, generating an underrun warning 393 * into dmesg if underrun reporting is enabled and then disables the underrun 394 * interrupt to avoid an irq storm. 395 */ 396 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 397 enum pipe pch_transcoder) 398 { 399 if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, 400 false)) { 401 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); 402 DRM_ERROR("PCH transcoder %c FIFO underrun\n", 403 pipe_name(pch_transcoder)); 404 } 405 } 406 407 /** 408 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately 409 * @dev_priv: i915 device instance 410 * 411 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared 412 * error interrupt may have been disabled, and so CPU fifo underruns won't 413 * necessarily raise an interrupt, and on GMCH platforms where underruns never 414 * raise an interrupt. 415 */ 416 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) 417 { 418 struct intel_crtc *crtc; 419 420 spin_lock_irq(&dev_priv->irq_lock); 421 422 for_each_intel_crtc(&dev_priv->drm, crtc) { 423 if (crtc->cpu_fifo_underrun_disabled) 424 continue; 425 426 if (HAS_GMCH(dev_priv)) 427 i9xx_check_fifo_underruns(crtc); 428 else if (IS_GEN(dev_priv, 7)) 429 ivybridge_check_fifo_underruns(crtc); 430 } 431 432 spin_unlock_irq(&dev_priv->irq_lock); 433 } 434 435 /** 436 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately 437 * @dev_priv: i915 device instance 438 * 439 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared 440 * error interrupt may have been disabled, and so PCH fifo underruns won't 441 * necessarily raise an interrupt. 442 */ 443 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) 444 { 445 struct intel_crtc *crtc; 446 447 spin_lock_irq(&dev_priv->irq_lock); 448 449 for_each_intel_crtc(&dev_priv->drm, crtc) { 450 if (crtc->pch_fifo_underrun_disabled) 451 continue; 452 453 if (HAS_PCH_CPT(dev_priv)) 454 cpt_check_pch_fifo_underruns(crtc); 455 } 456 457 spin_unlock_irq(&dev_priv->irq_lock); 458 } 459