1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel.vetter@ffwll.ch> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_de.h" 30 #include "intel_display_trace.h" 31 #include "intel_display_types.h" 32 #include "intel_fbc.h" 33 #include "intel_fifo_underrun.h" 34 #include "intel_pch_display.h" 35 36 /** 37 * DOC: fifo underrun handling 38 * 39 * The i915 driver checks for display fifo underruns using the interrupt signals 40 * provided by the hardware. This is enabled by default and fairly useful to 41 * debug display issues, especially watermark settings. 42 * 43 * If an underrun is detected this is logged into dmesg. To avoid flooding logs 44 * and occupying the cpu underrun interrupts are disabled after the first 45 * occurrence until the next modeset on a given pipe. 46 * 47 * Note that underrun detection on gmch platforms is a bit more ugly since there 48 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe 49 * interrupt register). Also on some other platforms underrun interrupts are 50 * shared, which means that if we detect an underrun we need to disable underrun 51 * reporting on all pipes. 52 * 53 * The code also supports underrun detection on the PCH transcoder. 54 */ 55 56 static bool ivb_can_enable_err_int(struct drm_device *dev) 57 { 58 struct drm_i915_private *dev_priv = to_i915(dev); 59 struct intel_crtc *crtc; 60 enum pipe pipe; 61 62 lockdep_assert_held(&dev_priv->irq_lock); 63 64 for_each_pipe(dev_priv, pipe) { 65 crtc = intel_crtc_for_pipe(dev_priv, pipe); 66 67 if (crtc->cpu_fifo_underrun_disabled) 68 return false; 69 } 70 71 return true; 72 } 73 74 static bool cpt_can_enable_serr_int(struct drm_device *dev) 75 { 76 struct drm_i915_private *dev_priv = to_i915(dev); 77 enum pipe pipe; 78 struct intel_crtc *crtc; 79 80 lockdep_assert_held(&dev_priv->irq_lock); 81 82 for_each_pipe(dev_priv, pipe) { 83 crtc = intel_crtc_for_pipe(dev_priv, pipe); 84 85 if (crtc->pch_fifo_underrun_disabled) 86 return false; 87 } 88 89 return true; 90 } 91 92 static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) 93 { 94 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 95 i915_reg_t reg = PIPESTAT(crtc->pipe); 96 u32 enable_mask; 97 98 lockdep_assert_held(&dev_priv->irq_lock); 99 100 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) 101 return; 102 103 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); 104 intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 105 intel_de_posting_read(dev_priv, reg); 106 107 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); 108 drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); 109 } 110 111 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, 112 enum pipe pipe, 113 bool enable, bool old) 114 { 115 struct drm_i915_private *dev_priv = to_i915(dev); 116 i915_reg_t reg = PIPESTAT(pipe); 117 118 lockdep_assert_held(&dev_priv->irq_lock); 119 120 if (enable) { 121 u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 122 123 intel_de_write(dev_priv, reg, 124 enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 125 intel_de_posting_read(dev_priv, reg); 126 } else { 127 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) 128 drm_err(&dev_priv->drm, "pipe %c underrun\n", 129 pipe_name(pipe)); 130 } 131 } 132 133 static void ilk_set_fifo_underrun_reporting(struct drm_device *dev, 134 enum pipe pipe, bool enable) 135 { 136 struct drm_i915_private *dev_priv = to_i915(dev); 137 u32 bit = (pipe == PIPE_A) ? 138 DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN; 139 140 if (enable) 141 ilk_enable_display_irq(dev_priv, bit); 142 else 143 ilk_disable_display_irq(dev_priv, bit); 144 } 145 146 static void ivb_check_fifo_underruns(struct intel_crtc *crtc) 147 { 148 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 149 enum pipe pipe = crtc->pipe; 150 u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); 151 152 lockdep_assert_held(&dev_priv->irq_lock); 153 154 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) 155 return; 156 157 intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 158 intel_de_posting_read(dev_priv, GEN7_ERR_INT); 159 160 trace_intel_cpu_fifo_underrun(dev_priv, pipe); 161 drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe)); 162 } 163 164 static void ivb_set_fifo_underrun_reporting(struct drm_device *dev, 165 enum pipe pipe, bool enable, 166 bool old) 167 { 168 struct drm_i915_private *dev_priv = to_i915(dev); 169 if (enable) { 170 intel_de_write(dev_priv, GEN7_ERR_INT, 171 ERR_INT_FIFO_UNDERRUN(pipe)); 172 173 if (!ivb_can_enable_err_int(dev)) 174 return; 175 176 ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); 177 } else { 178 ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); 179 180 if (old && 181 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { 182 drm_err(&dev_priv->drm, 183 "uncleared fifo underrun on pipe %c\n", 184 pipe_name(pipe)); 185 } 186 } 187 } 188 189 static u32 190 icl_pipe_status_underrun_mask(struct drm_i915_private *dev_priv) 191 { 192 u32 mask = PIPE_STATUS_UNDERRUN; 193 194 if (DISPLAY_VER(dev_priv) >= 13) 195 mask |= PIPE_STATUS_SOFT_UNDERRUN_XELPD | 196 PIPE_STATUS_HARD_UNDERRUN_XELPD | 197 PIPE_STATUS_PORT_UNDERRUN_XELPD; 198 199 return mask; 200 } 201 202 static void bdw_set_fifo_underrun_reporting(struct drm_device *dev, 203 enum pipe pipe, bool enable) 204 { 205 struct drm_i915_private *dev_priv = to_i915(dev); 206 u32 mask = gen8_de_pipe_underrun_mask(dev_priv); 207 208 if (enable) { 209 if (DISPLAY_VER(dev_priv) >= 11) 210 intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), 211 icl_pipe_status_underrun_mask(dev_priv)); 212 213 bdw_enable_pipe_irq(dev_priv, pipe, mask); 214 } else { 215 bdw_disable_pipe_irq(dev_priv, pipe, mask); 216 } 217 } 218 219 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, 220 enum pipe pch_transcoder, 221 bool enable) 222 { 223 struct drm_i915_private *dev_priv = to_i915(dev); 224 u32 bit = (pch_transcoder == PIPE_A) ? 225 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; 226 227 if (enable) 228 ibx_enable_display_interrupt(dev_priv, bit); 229 else 230 ibx_disable_display_interrupt(dev_priv, bit); 231 } 232 233 static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) 234 { 235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 236 enum pipe pch_transcoder = crtc->pipe; 237 u32 serr_int = intel_de_read(dev_priv, SERR_INT); 238 239 lockdep_assert_held(&dev_priv->irq_lock); 240 241 if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) 242 return; 243 244 intel_de_write(dev_priv, SERR_INT, 245 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 246 intel_de_posting_read(dev_priv, SERR_INT); 247 248 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); 249 drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n", 250 pipe_name(pch_transcoder)); 251 } 252 253 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 254 enum pipe pch_transcoder, 255 bool enable, bool old) 256 { 257 struct drm_i915_private *dev_priv = to_i915(dev); 258 259 if (enable) { 260 intel_de_write(dev_priv, SERR_INT, 261 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 262 263 if (!cpt_can_enable_serr_int(dev)) 264 return; 265 266 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); 267 } else { 268 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); 269 270 if (old && intel_de_read(dev_priv, SERR_INT) & 271 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { 272 drm_err(&dev_priv->drm, 273 "uncleared pch fifo underrun on pch transcoder %c\n", 274 pipe_name(pch_transcoder)); 275 } 276 } 277 } 278 279 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 280 enum pipe pipe, bool enable) 281 { 282 struct drm_i915_private *dev_priv = to_i915(dev); 283 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 284 bool old; 285 286 lockdep_assert_held(&dev_priv->irq_lock); 287 288 old = !crtc->cpu_fifo_underrun_disabled; 289 crtc->cpu_fifo_underrun_disabled = !enable; 290 291 if (HAS_GMCH(dev_priv)) 292 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); 293 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) 294 ilk_set_fifo_underrun_reporting(dev, pipe, enable); 295 else if (DISPLAY_VER(dev_priv) == 7) 296 ivb_set_fifo_underrun_reporting(dev, pipe, enable, old); 297 else if (DISPLAY_VER(dev_priv) >= 8) 298 bdw_set_fifo_underrun_reporting(dev, pipe, enable); 299 300 return old; 301 } 302 303 /** 304 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state 305 * @dev_priv: i915 device instance 306 * @pipe: (CPU) pipe to set state for 307 * @enable: whether underruns should be reported or not 308 * 309 * This function sets the fifo underrun state for @pipe. It is used in the 310 * modeset code to avoid false positives since on many platforms underruns are 311 * expected when disabling or enabling the pipe. 312 * 313 * Notice that on some platforms disabling underrun reports for one pipe 314 * disables for all due to shared interrupts. Actual reporting is still per-pipe 315 * though. 316 * 317 * Returns the previous state of underrun reporting. 318 */ 319 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 320 enum pipe pipe, bool enable) 321 { 322 unsigned long flags; 323 bool ret; 324 325 spin_lock_irqsave(&dev_priv->irq_lock, flags); 326 ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, 327 enable); 328 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 329 330 return ret; 331 } 332 333 /** 334 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state 335 * @dev_priv: i915 device instance 336 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 337 * @enable: whether underruns should be reported or not 338 * 339 * This function makes us disable or enable PCH fifo underruns for a specific 340 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO 341 * underrun reporting for one transcoder may also disable all the other PCH 342 * error interruts for the other transcoders, due to the fact that there's just 343 * one interrupt mask/enable bit for all the transcoders. 344 * 345 * Returns the previous state of underrun reporting. 346 */ 347 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 348 enum pipe pch_transcoder, 349 bool enable) 350 { 351 struct intel_crtc *crtc = 352 intel_crtc_for_pipe(dev_priv, pch_transcoder); 353 unsigned long flags; 354 bool old; 355 356 /* 357 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT 358 * has only one pch transcoder A that all pipes can use. To avoid racy 359 * pch transcoder -> pipe lookups from interrupt code simply store the 360 * underrun statistics in crtc A. Since we never expose this anywhere 361 * nor use it outside of the fifo underrun code here using the "wrong" 362 * crtc on LPT won't cause issues. 363 */ 364 365 spin_lock_irqsave(&dev_priv->irq_lock, flags); 366 367 old = !crtc->pch_fifo_underrun_disabled; 368 crtc->pch_fifo_underrun_disabled = !enable; 369 370 if (HAS_PCH_IBX(dev_priv)) 371 ibx_set_fifo_underrun_reporting(&dev_priv->drm, 372 pch_transcoder, 373 enable); 374 else 375 cpt_set_fifo_underrun_reporting(&dev_priv->drm, 376 pch_transcoder, 377 enable, old); 378 379 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 380 return old; 381 } 382 383 /** 384 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt 385 * @dev_priv: i915 device instance 386 * @pipe: (CPU) pipe to set state for 387 * 388 * This handles a CPU fifo underrun interrupt, generating an underrun warning 389 * into dmesg if underrun reporting is enabled and then disables the underrun 390 * interrupt to avoid an irq storm. 391 */ 392 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 393 enum pipe pipe) 394 { 395 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 396 u32 underruns = 0; 397 398 /* We may be called too early in init, thanks BIOS! */ 399 if (crtc == NULL) 400 return; 401 402 /* GMCH can't disable fifo underruns, filter them. */ 403 if (HAS_GMCH(dev_priv) && 404 crtc->cpu_fifo_underrun_disabled) 405 return; 406 407 /* 408 * Starting with display version 11, the PIPE_STAT register records 409 * whether an underrun has happened, and on XELPD+, it will also record 410 * whether the underrun was soft/hard and whether it was triggered by 411 * the downstream port logic. We should clear these bits (which use 412 * write-1-to-clear logic) too. 413 * 414 * Note that although the IIR gives us the same underrun and soft/hard 415 * information, PIPE_STAT is the only place we can find out whether 416 * the underrun was caused by the downstream port. 417 */ 418 if (DISPLAY_VER(dev_priv) >= 11) { 419 underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) & 420 icl_pipe_status_underrun_mask(dev_priv); 421 intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns); 422 } 423 424 if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { 425 trace_intel_cpu_fifo_underrun(dev_priv, pipe); 426 427 if (DISPLAY_VER(dev_priv) >= 11) 428 drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun: %s%s%s%s\n", 429 pipe_name(pipe), 430 underruns & PIPE_STATUS_SOFT_UNDERRUN_XELPD ? "soft," : "", 431 underruns & PIPE_STATUS_HARD_UNDERRUN_XELPD ? "hard," : "", 432 underruns & PIPE_STATUS_PORT_UNDERRUN_XELPD ? "port," : "", 433 underruns & PIPE_STATUS_UNDERRUN ? "transcoder," : ""); 434 else 435 drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); 436 } 437 438 intel_fbc_handle_fifo_underrun_irq(dev_priv); 439 } 440 441 /** 442 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt 443 * @dev_priv: i915 device instance 444 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 445 * 446 * This handles a PCH fifo underrun interrupt, generating an underrun warning 447 * into dmesg if underrun reporting is enabled and then disables the underrun 448 * interrupt to avoid an irq storm. 449 */ 450 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 451 enum pipe pch_transcoder) 452 { 453 if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, 454 false)) { 455 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); 456 drm_err(&dev_priv->drm, "PCH transcoder %c FIFO underrun\n", 457 pipe_name(pch_transcoder)); 458 } 459 } 460 461 /** 462 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately 463 * @dev_priv: i915 device instance 464 * 465 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared 466 * error interrupt may have been disabled, and so CPU fifo underruns won't 467 * necessarily raise an interrupt, and on GMCH platforms where underruns never 468 * raise an interrupt. 469 */ 470 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) 471 { 472 struct intel_crtc *crtc; 473 474 spin_lock_irq(&dev_priv->irq_lock); 475 476 for_each_intel_crtc(&dev_priv->drm, crtc) { 477 if (crtc->cpu_fifo_underrun_disabled) 478 continue; 479 480 if (HAS_GMCH(dev_priv)) 481 i9xx_check_fifo_underruns(crtc); 482 else if (DISPLAY_VER(dev_priv) == 7) 483 ivb_check_fifo_underruns(crtc); 484 } 485 486 spin_unlock_irq(&dev_priv->irq_lock); 487 } 488 489 /** 490 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately 491 * @dev_priv: i915 device instance 492 * 493 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared 494 * error interrupt may have been disabled, and so PCH fifo underruns won't 495 * necessarily raise an interrupt. 496 */ 497 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) 498 { 499 struct intel_crtc *crtc; 500 501 spin_lock_irq(&dev_priv->irq_lock); 502 503 for_each_intel_crtc(&dev_priv->drm, crtc) { 504 if (crtc->pch_fifo_underrun_disabled) 505 continue; 506 507 if (HAS_PCH_CPT(dev_priv)) 508 cpt_check_pch_fifo_underruns(crtc); 509 } 510 511 spin_unlock_irq(&dev_priv->irq_lock); 512 } 513 514 void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915, 515 struct intel_crtc *crtc, 516 bool enable) 517 { 518 crtc->cpu_fifo_underrun_disabled = !enable; 519 520 /* 521 * We track the PCH trancoder underrun reporting state 522 * within the crtc. With crtc for pipe A housing the underrun 523 * reporting state for PCH transcoder A, crtc for pipe B housing 524 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 525 * and marking underrun reporting as disabled for the non-existing 526 * PCH transcoders B and C would prevent enabling the south 527 * error interrupt (see cpt_can_enable_serr_int()). 528 */ 529 if (intel_has_pch_trancoder(i915, crtc->pipe)) 530 crtc->pch_fifo_underrun_disabled = !enable; 531 } 532