1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Frame Buffer Compression (FBC) 26 * 27 * FBC tries to save memory bandwidth (and so power consumption) by 28 * compressing the amount of memory used by the display. It is total 29 * transparent to user space and completely handled in the kernel. 30 * 31 * The benefits of FBC are mostly visible with solid backgrounds and 32 * variation-less patterns. It comes from keeping the memory footprint small 33 * and having fewer memory pages opened and accessed for refreshing the display. 34 * 35 * i915 is responsible to reserve stolen memory for FBC and configure its 36 * offset on proper registers. The hardware takes care of all 37 * compress/decompress. However there are many known cases where we have to 38 * forcibly disable it to allow proper screen updates. 39 */ 40 41 #include <drm/drm_fourcc.h> 42 43 #include "i915_drv.h" 44 #include "i915_vgpu.h" 45 #include "intel_cdclk.h" 46 #include "intel_de.h" 47 #include "intel_display_trace.h" 48 #include "intel_display_types.h" 49 #include "intel_fbc.h" 50 #include "intel_frontbuffer.h" 51 52 struct intel_fbc_funcs { 53 void (*activate)(struct intel_fbc *fbc); 54 void (*deactivate)(struct intel_fbc *fbc); 55 bool (*is_active)(struct intel_fbc *fbc); 56 bool (*is_compressing)(struct intel_fbc *fbc); 57 void (*nuke)(struct intel_fbc *fbc); 58 void (*program_cfb)(struct intel_fbc *fbc); 59 void (*set_false_color)(struct intel_fbc *fbc, bool enable); 60 }; 61 62 struct intel_fbc_state { 63 struct intel_plane *plane; 64 unsigned int cfb_stride; 65 unsigned int cfb_size; 66 unsigned int fence_y_offset; 67 u16 override_cfb_stride; 68 u16 interval; 69 s8 fence_id; 70 }; 71 72 struct intel_fbc { 73 struct drm_i915_private *i915; 74 const struct intel_fbc_funcs *funcs; 75 76 /* 77 * This is always the inner lock when overlapping with 78 * struct_mutex and it's the outer lock when overlapping 79 * with stolen_lock. 80 */ 81 struct mutex lock; 82 unsigned int possible_framebuffer_bits; 83 unsigned int busy_bits; 84 85 struct drm_mm_node compressed_fb; 86 struct drm_mm_node compressed_llb; 87 88 u8 limit; 89 90 bool false_color; 91 92 bool active; 93 bool activated; 94 bool flip_pending; 95 96 bool underrun_detected; 97 struct work_struct underrun_work; 98 99 /* 100 * This structure contains everything that's relevant to program the 101 * hardware registers. When we want to figure out if we need to disable 102 * and re-enable FBC for a new configuration we just check if there's 103 * something different in the struct. The genx_fbc_activate functions 104 * are supposed to read from it in order to program the registers. 105 */ 106 struct intel_fbc_state state; 107 const char *no_fbc_reason; 108 }; 109 110 /* plane stride in pixels */ 111 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state) 112 { 113 const struct drm_framebuffer *fb = plane_state->hw.fb; 114 unsigned int stride; 115 116 stride = plane_state->view.color_plane[0].mapping_stride; 117 if (!drm_rotation_90_or_270(plane_state->hw.rotation)) 118 stride /= fb->format->cpp[0]; 119 120 return stride; 121 } 122 123 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */ 124 static unsigned int _intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) 125 { 126 unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ 127 128 return intel_fbc_plane_stride(plane_state) * cpp; 129 } 130 131 /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */ 132 static unsigned int skl_fbc_min_cfb_stride(const struct intel_plane_state *plane_state) 133 { 134 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 135 unsigned int limit = 4; /* 1:4 compression limit is the worst case */ 136 unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ 137 unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; 138 unsigned int height = 4; /* FBC segment is 4 lines */ 139 unsigned int stride; 140 141 /* minimum segment stride we can use */ 142 stride = width * cpp * height / limit; 143 144 /* 145 * Wa_16011863758: icl+ 146 * Avoid some hardware segment address miscalculation. 147 */ 148 if (DISPLAY_VER(i915) >= 11) 149 stride += 64; 150 151 /* 152 * At least some of the platforms require each 4 line segment to 153 * be 512 byte aligned. Just do it always for simplicity. 154 */ 155 stride = ALIGN(stride, 512); 156 157 /* convert back to single line equivalent with 1:1 compression limit */ 158 return stride * limit / height; 159 } 160 161 /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */ 162 static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) 163 { 164 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 165 unsigned int stride = _intel_fbc_cfb_stride(plane_state); 166 167 /* 168 * At least some of the platforms require each 4 line segment to 169 * be 512 byte aligned. Aligning each line to 512 bytes guarantees 170 * that regardless of the compression limit we choose later. 171 */ 172 if (DISPLAY_VER(i915) >= 9) 173 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(plane_state)); 174 else 175 return stride; 176 } 177 178 static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state) 179 { 180 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 181 int lines = drm_rect_height(&plane_state->uapi.src) >> 16; 182 183 if (DISPLAY_VER(i915) == 7) 184 lines = min(lines, 2048); 185 else if (DISPLAY_VER(i915) >= 8) 186 lines = min(lines, 2560); 187 188 return lines * intel_fbc_cfb_stride(plane_state); 189 } 190 191 static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state) 192 { 193 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 194 unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state); 195 unsigned int stride = _intel_fbc_cfb_stride(plane_state); 196 const struct drm_framebuffer *fb = plane_state->hw.fb; 197 198 /* 199 * Override stride in 64 byte units per 4 line segment. 200 * 201 * Gen9 hw miscalculates cfb stride for linear as 202 * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so 203 * we always need to use the override there. 204 */ 205 if (stride != stride_aligned || 206 (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) 207 return stride_aligned * 4 / 64; 208 209 return 0; 210 } 211 212 static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) 213 { 214 const struct intel_fbc_state *fbc_state = &fbc->state; 215 struct drm_i915_private *i915 = fbc->i915; 216 unsigned int cfb_stride; 217 u32 fbc_ctl; 218 219 cfb_stride = fbc_state->cfb_stride / fbc->limit; 220 221 /* FBC_CTL wants 32B or 64B units */ 222 if (DISPLAY_VER(i915) == 2) 223 cfb_stride = (cfb_stride / 32) - 1; 224 else 225 cfb_stride = (cfb_stride / 64) - 1; 226 227 fbc_ctl = FBC_CTL_PERIODIC | 228 FBC_CTL_INTERVAL(fbc_state->interval) | 229 FBC_CTL_STRIDE(cfb_stride); 230 231 if (IS_I945GM(i915)) 232 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 233 234 if (fbc_state->fence_id >= 0) 235 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id); 236 237 return fbc_ctl; 238 } 239 240 static u32 i965_fbc_ctl2(struct intel_fbc *fbc) 241 { 242 const struct intel_fbc_state *fbc_state = &fbc->state; 243 u32 fbc_ctl2; 244 245 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | 246 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane); 247 248 if (fbc_state->fence_id >= 0) 249 fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN; 250 251 return fbc_ctl2; 252 } 253 254 static void i8xx_fbc_deactivate(struct intel_fbc *fbc) 255 { 256 struct drm_i915_private *i915 = fbc->i915; 257 u32 fbc_ctl; 258 259 /* Disable compression */ 260 fbc_ctl = intel_de_read(i915, FBC_CONTROL); 261 if ((fbc_ctl & FBC_CTL_EN) == 0) 262 return; 263 264 fbc_ctl &= ~FBC_CTL_EN; 265 intel_de_write(i915, FBC_CONTROL, fbc_ctl); 266 267 /* Wait for compressing bit to clear */ 268 if (intel_de_wait_for_clear(i915, FBC_STATUS, 269 FBC_STAT_COMPRESSING, 10)) { 270 drm_dbg_kms(&i915->drm, "FBC idle timed out\n"); 271 return; 272 } 273 } 274 275 static void i8xx_fbc_activate(struct intel_fbc *fbc) 276 { 277 const struct intel_fbc_state *fbc_state = &fbc->state; 278 struct drm_i915_private *i915 = fbc->i915; 279 int i; 280 281 /* Clear old tags */ 282 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 283 intel_de_write(i915, FBC_TAG(i), 0); 284 285 if (DISPLAY_VER(i915) == 4) { 286 intel_de_write(i915, FBC_CONTROL2, 287 i965_fbc_ctl2(fbc)); 288 intel_de_write(i915, FBC_FENCE_OFF, 289 fbc_state->fence_y_offset); 290 } 291 292 intel_de_write(i915, FBC_CONTROL, 293 FBC_CTL_EN | i8xx_fbc_ctl(fbc)); 294 } 295 296 static bool i8xx_fbc_is_active(struct intel_fbc *fbc) 297 { 298 return intel_de_read(fbc->i915, FBC_CONTROL) & FBC_CTL_EN; 299 } 300 301 static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc) 302 { 303 return intel_de_read(fbc->i915, FBC_STATUS) & 304 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); 305 } 306 307 static void i8xx_fbc_nuke(struct intel_fbc *fbc) 308 { 309 struct intel_fbc_state *fbc_state = &fbc->state; 310 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; 311 struct drm_i915_private *dev_priv = fbc->i915; 312 313 spin_lock_irq(&dev_priv->uncore.lock); 314 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 315 intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane))); 316 spin_unlock_irq(&dev_priv->uncore.lock); 317 } 318 319 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) 320 { 321 struct drm_i915_private *i915 = fbc->i915; 322 323 GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start, 324 fbc->compressed_fb.start, U32_MAX)); 325 GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start, 326 fbc->compressed_llb.start, U32_MAX)); 327 328 intel_de_write(i915, FBC_CFB_BASE, 329 i915->dsm.start + fbc->compressed_fb.start); 330 intel_de_write(i915, FBC_LL_BASE, 331 i915->dsm.start + fbc->compressed_llb.start); 332 } 333 334 static const struct intel_fbc_funcs i8xx_fbc_funcs = { 335 .activate = i8xx_fbc_activate, 336 .deactivate = i8xx_fbc_deactivate, 337 .is_active = i8xx_fbc_is_active, 338 .is_compressing = i8xx_fbc_is_compressing, 339 .nuke = i8xx_fbc_nuke, 340 .program_cfb = i8xx_fbc_program_cfb, 341 }; 342 343 static void i965_fbc_nuke(struct intel_fbc *fbc) 344 { 345 struct intel_fbc_state *fbc_state = &fbc->state; 346 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; 347 struct drm_i915_private *dev_priv = fbc->i915; 348 349 spin_lock_irq(&dev_priv->uncore.lock); 350 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 351 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); 352 spin_unlock_irq(&dev_priv->uncore.lock); 353 } 354 355 static const struct intel_fbc_funcs i965_fbc_funcs = { 356 .activate = i8xx_fbc_activate, 357 .deactivate = i8xx_fbc_deactivate, 358 .is_active = i8xx_fbc_is_active, 359 .is_compressing = i8xx_fbc_is_compressing, 360 .nuke = i965_fbc_nuke, 361 .program_cfb = i8xx_fbc_program_cfb, 362 }; 363 364 static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc) 365 { 366 switch (fbc->limit) { 367 default: 368 MISSING_CASE(fbc->limit); 369 fallthrough; 370 case 1: 371 return DPFC_CTL_LIMIT_1X; 372 case 2: 373 return DPFC_CTL_LIMIT_2X; 374 case 4: 375 return DPFC_CTL_LIMIT_4X; 376 } 377 } 378 379 static u32 g4x_dpfc_ctl(struct intel_fbc *fbc) 380 { 381 const struct intel_fbc_state *fbc_state = &fbc->state; 382 struct drm_i915_private *i915 = fbc->i915; 383 u32 dpfc_ctl; 384 385 dpfc_ctl = g4x_dpfc_ctl_limit(fbc) | 386 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane); 387 388 if (IS_G4X(i915)) 389 dpfc_ctl |= DPFC_CTL_SR_EN; 390 391 if (fbc_state->fence_id >= 0) { 392 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X; 393 394 if (DISPLAY_VER(i915) < 6) 395 dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id); 396 } 397 398 return dpfc_ctl; 399 } 400 401 static void g4x_fbc_activate(struct intel_fbc *fbc) 402 { 403 const struct intel_fbc_state *fbc_state = &fbc->state; 404 struct drm_i915_private *i915 = fbc->i915; 405 406 intel_de_write(i915, DPFC_FENCE_YOFF, 407 fbc_state->fence_y_offset); 408 409 intel_de_write(i915, DPFC_CONTROL, 410 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 411 } 412 413 static void g4x_fbc_deactivate(struct intel_fbc *fbc) 414 { 415 struct drm_i915_private *i915 = fbc->i915; 416 u32 dpfc_ctl; 417 418 /* Disable compression */ 419 dpfc_ctl = intel_de_read(i915, DPFC_CONTROL); 420 if (dpfc_ctl & DPFC_CTL_EN) { 421 dpfc_ctl &= ~DPFC_CTL_EN; 422 intel_de_write(i915, DPFC_CONTROL, dpfc_ctl); 423 } 424 } 425 426 static bool g4x_fbc_is_active(struct intel_fbc *fbc) 427 { 428 return intel_de_read(fbc->i915, DPFC_CONTROL) & DPFC_CTL_EN; 429 } 430 431 static bool g4x_fbc_is_compressing(struct intel_fbc *fbc) 432 { 433 return intel_de_read(fbc->i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK; 434 } 435 436 static void g4x_fbc_program_cfb(struct intel_fbc *fbc) 437 { 438 struct drm_i915_private *i915 = fbc->i915; 439 440 intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start); 441 } 442 443 static const struct intel_fbc_funcs g4x_fbc_funcs = { 444 .activate = g4x_fbc_activate, 445 .deactivate = g4x_fbc_deactivate, 446 .is_active = g4x_fbc_is_active, 447 .is_compressing = g4x_fbc_is_compressing, 448 .nuke = i965_fbc_nuke, 449 .program_cfb = g4x_fbc_program_cfb, 450 }; 451 452 static void ilk_fbc_activate(struct intel_fbc *fbc) 453 { 454 struct intel_fbc_state *fbc_state = &fbc->state; 455 struct drm_i915_private *i915 = fbc->i915; 456 457 intel_de_write(i915, ILK_DPFC_FENCE_YOFF, 458 fbc_state->fence_y_offset); 459 460 intel_de_write(i915, ILK_DPFC_CONTROL, 461 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 462 } 463 464 static void ilk_fbc_deactivate(struct intel_fbc *fbc) 465 { 466 struct drm_i915_private *i915 = fbc->i915; 467 u32 dpfc_ctl; 468 469 /* Disable compression */ 470 dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL); 471 if (dpfc_ctl & DPFC_CTL_EN) { 472 dpfc_ctl &= ~DPFC_CTL_EN; 473 intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl); 474 } 475 } 476 477 static bool ilk_fbc_is_active(struct intel_fbc *fbc) 478 { 479 return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN; 480 } 481 482 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc) 483 { 484 return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK; 485 } 486 487 static void ilk_fbc_program_cfb(struct intel_fbc *fbc) 488 { 489 struct drm_i915_private *i915 = fbc->i915; 490 491 intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start); 492 } 493 494 static const struct intel_fbc_funcs ilk_fbc_funcs = { 495 .activate = ilk_fbc_activate, 496 .deactivate = ilk_fbc_deactivate, 497 .is_active = ilk_fbc_is_active, 498 .is_compressing = ilk_fbc_is_compressing, 499 .nuke = i965_fbc_nuke, 500 .program_cfb = ilk_fbc_program_cfb, 501 }; 502 503 static void snb_fbc_program_fence(struct intel_fbc *fbc) 504 { 505 const struct intel_fbc_state *fbc_state = &fbc->state; 506 struct drm_i915_private *i915 = fbc->i915; 507 u32 ctl = 0; 508 509 if (fbc_state->fence_id >= 0) 510 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id); 511 512 intel_de_write(i915, SNB_DPFC_CTL_SA, ctl); 513 intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset); 514 } 515 516 static void snb_fbc_activate(struct intel_fbc *fbc) 517 { 518 snb_fbc_program_fence(fbc); 519 520 ilk_fbc_activate(fbc); 521 } 522 523 static void snb_fbc_nuke(struct intel_fbc *fbc) 524 { 525 struct drm_i915_private *i915 = fbc->i915; 526 527 intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE); 528 intel_de_posting_read(i915, MSG_FBC_REND_STATE); 529 } 530 531 static const struct intel_fbc_funcs snb_fbc_funcs = { 532 .activate = snb_fbc_activate, 533 .deactivate = ilk_fbc_deactivate, 534 .is_active = ilk_fbc_is_active, 535 .is_compressing = ilk_fbc_is_compressing, 536 .nuke = snb_fbc_nuke, 537 .program_cfb = ilk_fbc_program_cfb, 538 }; 539 540 static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) 541 { 542 const struct intel_fbc_state *fbc_state = &fbc->state; 543 struct drm_i915_private *i915 = fbc->i915; 544 u32 val = 0; 545 546 if (fbc_state->override_cfb_stride) 547 val |= FBC_STRIDE_OVERRIDE | 548 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); 549 550 intel_de_write(i915, GLK_FBC_STRIDE, val); 551 } 552 553 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc) 554 { 555 const struct intel_fbc_state *fbc_state = &fbc->state; 556 struct drm_i915_private *i915 = fbc->i915; 557 u32 val = 0; 558 559 /* Display WA #0529: skl, kbl, bxt. */ 560 if (fbc_state->override_cfb_stride) 561 val |= CHICKEN_FBC_STRIDE_OVERRIDE | 562 CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); 563 564 intel_de_rmw(i915, CHICKEN_MISC_4, 565 CHICKEN_FBC_STRIDE_OVERRIDE | 566 CHICKEN_FBC_STRIDE_MASK, val); 567 } 568 569 static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) 570 { 571 const struct intel_fbc_state *fbc_state = &fbc->state; 572 struct drm_i915_private *i915 = fbc->i915; 573 u32 dpfc_ctl; 574 575 dpfc_ctl = g4x_dpfc_ctl_limit(fbc); 576 577 if (IS_IVYBRIDGE(i915)) 578 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane); 579 580 if (fbc_state->fence_id >= 0) 581 dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB; 582 583 if (fbc->false_color) 584 dpfc_ctl |= DPFC_CTL_FALSE_COLOR; 585 586 return dpfc_ctl; 587 } 588 589 static void ivb_fbc_activate(struct intel_fbc *fbc) 590 { 591 struct drm_i915_private *i915 = fbc->i915; 592 593 if (DISPLAY_VER(i915) >= 10) 594 glk_fbc_program_cfb_stride(fbc); 595 else if (DISPLAY_VER(i915) == 9) 596 skl_fbc_program_cfb_stride(fbc); 597 598 if (i915->ggtt.num_fences) 599 snb_fbc_program_fence(fbc); 600 601 intel_de_write(i915, ILK_DPFC_CONTROL, 602 DPFC_CTL_EN | ivb_dpfc_ctl(fbc)); 603 } 604 605 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc) 606 { 607 return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB; 608 } 609 610 static void ivb_fbc_set_false_color(struct intel_fbc *fbc, 611 bool enable) 612 { 613 intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL, 614 DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0); 615 } 616 617 static const struct intel_fbc_funcs ivb_fbc_funcs = { 618 .activate = ivb_fbc_activate, 619 .deactivate = ilk_fbc_deactivate, 620 .is_active = ilk_fbc_is_active, 621 .is_compressing = ivb_fbc_is_compressing, 622 .nuke = snb_fbc_nuke, 623 .program_cfb = ilk_fbc_program_cfb, 624 .set_false_color = ivb_fbc_set_false_color, 625 }; 626 627 static bool intel_fbc_hw_is_active(struct intel_fbc *fbc) 628 { 629 return fbc->funcs->is_active(fbc); 630 } 631 632 static void intel_fbc_hw_activate(struct intel_fbc *fbc) 633 { 634 trace_intel_fbc_activate(fbc->state.plane); 635 636 fbc->active = true; 637 fbc->activated = true; 638 639 fbc->funcs->activate(fbc); 640 } 641 642 static void intel_fbc_hw_deactivate(struct intel_fbc *fbc) 643 { 644 trace_intel_fbc_deactivate(fbc->state.plane); 645 646 fbc->active = false; 647 648 fbc->funcs->deactivate(fbc); 649 } 650 651 static bool intel_fbc_is_compressing(struct intel_fbc *fbc) 652 { 653 return fbc->funcs->is_compressing(fbc); 654 } 655 656 static void intel_fbc_nuke(struct intel_fbc *fbc) 657 { 658 trace_intel_fbc_nuke(fbc->state.plane); 659 660 fbc->funcs->nuke(fbc); 661 } 662 663 static void intel_fbc_activate(struct intel_fbc *fbc) 664 { 665 intel_fbc_hw_activate(fbc); 666 intel_fbc_nuke(fbc); 667 668 fbc->no_fbc_reason = NULL; 669 } 670 671 static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason) 672 { 673 struct drm_i915_private *i915 = fbc->i915; 674 675 drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); 676 677 if (fbc->active) 678 intel_fbc_hw_deactivate(fbc); 679 680 fbc->no_fbc_reason = reason; 681 } 682 683 static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915) 684 { 685 if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) 686 return BIT_ULL(28); 687 else 688 return BIT_ULL(32); 689 } 690 691 static u64 intel_fbc_stolen_end(struct drm_i915_private *i915) 692 { 693 u64 end; 694 695 /* The FBC hardware for BDW/SKL doesn't have access to the stolen 696 * reserved range size, so it always assumes the maximum (8mb) is used. 697 * If we enable FBC using a CFB on that memory range we'll get FIFO 698 * underruns, even if that range is not reserved by the BIOS. */ 699 if (IS_BROADWELL(i915) || 700 (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915))) 701 end = resource_size(&i915->dsm) - 8 * 1024 * 1024; 702 else 703 end = U64_MAX; 704 705 return min(end, intel_fbc_cfb_base_max(i915)); 706 } 707 708 static int intel_fbc_min_limit(const struct intel_plane_state *plane_state) 709 { 710 return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1; 711 } 712 713 static int intel_fbc_max_limit(struct drm_i915_private *i915) 714 { 715 /* WaFbcOnly1to1Ratio:ctg */ 716 if (IS_G4X(i915)) 717 return 1; 718 719 /* 720 * FBC2 can only do 1:1, 1:2, 1:4, we limit 721 * FBC1 to the same out of convenience. 722 */ 723 return 4; 724 } 725 726 static int find_compression_limit(struct intel_fbc *fbc, 727 unsigned int size, int min_limit) 728 { 729 struct drm_i915_private *i915 = fbc->i915; 730 u64 end = intel_fbc_stolen_end(i915); 731 int ret, limit = min_limit; 732 733 size /= limit; 734 735 /* Try to over-allocate to reduce reallocations and fragmentation. */ 736 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb, 737 size <<= 1, 4096, 0, end); 738 if (ret == 0) 739 return limit; 740 741 for (; limit <= intel_fbc_max_limit(i915); limit <<= 1) { 742 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb, 743 size >>= 1, 4096, 0, end); 744 if (ret == 0) 745 return limit; 746 } 747 748 return 0; 749 } 750 751 static int intel_fbc_alloc_cfb(struct intel_fbc *fbc, 752 unsigned int size, int min_limit) 753 { 754 struct drm_i915_private *i915 = fbc->i915; 755 int ret; 756 757 drm_WARN_ON(&i915->drm, 758 drm_mm_node_allocated(&fbc->compressed_fb)); 759 drm_WARN_ON(&i915->drm, 760 drm_mm_node_allocated(&fbc->compressed_llb)); 761 762 if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) { 763 ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb, 764 4096, 4096); 765 if (ret) 766 goto err; 767 } 768 769 ret = find_compression_limit(fbc, size, min_limit); 770 if (!ret) 771 goto err_llb; 772 else if (ret > min_limit) 773 drm_info_once(&i915->drm, 774 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); 775 776 fbc->limit = ret; 777 778 drm_dbg_kms(&i915->drm, 779 "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n", 780 fbc->compressed_fb.size, fbc->limit); 781 782 return 0; 783 784 err_llb: 785 if (drm_mm_node_allocated(&fbc->compressed_llb)) 786 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb); 787 err: 788 if (drm_mm_initialized(&i915->mm.stolen)) 789 drm_info_once(&i915->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); 790 return -ENOSPC; 791 } 792 793 static void intel_fbc_program_cfb(struct intel_fbc *fbc) 794 { 795 fbc->funcs->program_cfb(fbc); 796 } 797 798 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) 799 { 800 struct drm_i915_private *i915 = fbc->i915; 801 802 if (WARN_ON(intel_fbc_hw_is_active(fbc))) 803 return; 804 805 if (drm_mm_node_allocated(&fbc->compressed_llb)) 806 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb); 807 if (drm_mm_node_allocated(&fbc->compressed_fb)) 808 i915_gem_stolen_remove_node(i915, &fbc->compressed_fb); 809 } 810 811 void intel_fbc_cleanup(struct drm_i915_private *i915) 812 { 813 struct intel_fbc *fbc = i915->fbc; 814 815 if (!fbc) 816 return; 817 818 mutex_lock(&fbc->lock); 819 __intel_fbc_cleanup_cfb(fbc); 820 mutex_unlock(&fbc->lock); 821 822 kfree(fbc); 823 } 824 825 static bool stride_is_valid(const struct intel_plane_state *plane_state) 826 { 827 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 828 const struct drm_framebuffer *fb = plane_state->hw.fb; 829 unsigned int stride = intel_fbc_plane_stride(plane_state) * 830 fb->format->cpp[0]; 831 832 /* This should have been caught earlier. */ 833 if (drm_WARN_ON_ONCE(&i915->drm, (stride & (64 - 1)) != 0)) 834 return false; 835 836 /* Below are the additional FBC restrictions. */ 837 if (stride < 512) 838 return false; 839 840 if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3) 841 return stride == 4096 || stride == 8192; 842 843 if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && stride < 2048) 844 return false; 845 846 /* Display WA #1105: skl,bxt,kbl,cfl,glk */ 847 if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) && 848 fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) 849 return false; 850 851 if (stride > 16384) 852 return false; 853 854 return true; 855 } 856 857 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) 858 { 859 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 860 const struct drm_framebuffer *fb = plane_state->hw.fb; 861 862 switch (fb->format->format) { 863 case DRM_FORMAT_XRGB8888: 864 case DRM_FORMAT_XBGR8888: 865 return true; 866 case DRM_FORMAT_XRGB1555: 867 case DRM_FORMAT_RGB565: 868 /* 16bpp not supported on gen2 */ 869 if (DISPLAY_VER(i915) == 2) 870 return false; 871 /* WaFbcOnly1to1Ratio:ctg */ 872 if (IS_G4X(i915)) 873 return false; 874 return true; 875 default: 876 return false; 877 } 878 } 879 880 static bool rotation_is_valid(const struct intel_plane_state *plane_state) 881 { 882 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 883 const struct drm_framebuffer *fb = plane_state->hw.fb; 884 unsigned int rotation = plane_state->hw.rotation; 885 886 if (DISPLAY_VER(i915) >= 9 && fb->format->format == DRM_FORMAT_RGB565 && 887 drm_rotation_90_or_270(rotation)) 888 return false; 889 else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) && 890 rotation != DRM_MODE_ROTATE_0) 891 return false; 892 893 return true; 894 } 895 896 /* 897 * For some reason, the hardware tracking starts looking at whatever we 898 * programmed as the display plane base address register. It does not look at 899 * the X and Y offset registers. That's why we include the src x/y offsets 900 * instead of just looking at the plane size. 901 */ 902 static bool intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state *plane_state) 903 { 904 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 905 unsigned int effective_w, effective_h, max_w, max_h; 906 907 if (DISPLAY_VER(i915) >= 10) { 908 max_w = 5120; 909 max_h = 4096; 910 } else if (DISPLAY_VER(i915) >= 8 || IS_HASWELL(i915)) { 911 max_w = 4096; 912 max_h = 4096; 913 } else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) { 914 max_w = 4096; 915 max_h = 2048; 916 } else { 917 max_w = 2048; 918 max_h = 1536; 919 } 920 921 effective_w = plane_state->view.color_plane[0].x + 922 (drm_rect_width(&plane_state->uapi.src) >> 16); 923 effective_h = plane_state->view.color_plane[0].y + 924 (drm_rect_height(&plane_state->uapi.src) >> 16); 925 926 return effective_w <= max_w && effective_h <= max_h; 927 } 928 929 static bool tiling_is_valid(const struct intel_plane_state *plane_state) 930 { 931 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 932 const struct drm_framebuffer *fb = plane_state->hw.fb; 933 934 switch (fb->modifier) { 935 case DRM_FORMAT_MOD_LINEAR: 936 case I915_FORMAT_MOD_Y_TILED: 937 case I915_FORMAT_MOD_Yf_TILED: 938 return DISPLAY_VER(i915) >= 9; 939 case I915_FORMAT_MOD_X_TILED: 940 return true; 941 default: 942 return false; 943 } 944 } 945 946 static void intel_fbc_update_state(struct intel_atomic_state *state, 947 struct intel_crtc *crtc, 948 struct intel_plane *plane) 949 { 950 struct drm_i915_private *i915 = to_i915(state->base.dev); 951 const struct intel_crtc_state *crtc_state = 952 intel_atomic_get_new_crtc_state(state, crtc); 953 const struct intel_plane_state *plane_state = 954 intel_atomic_get_new_plane_state(state, plane); 955 struct intel_fbc *fbc = plane->fbc; 956 struct intel_fbc_state *fbc_state = &fbc->state; 957 958 WARN_ON(plane_state->no_fbc_reason); 959 960 fbc_state->plane = plane; 961 962 /* FBC1 compression interval: arbitrary choice of 1 second */ 963 fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); 964 965 fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state); 966 967 drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE && 968 !plane_state->ggtt_vma->fence); 969 970 if (plane_state->flags & PLANE_HAS_FENCE && 971 plane_state->ggtt_vma->fence) 972 fbc_state->fence_id = plane_state->ggtt_vma->fence->id; 973 else 974 fbc_state->fence_id = -1; 975 976 fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state); 977 fbc_state->cfb_size = intel_fbc_cfb_size(plane_state); 978 fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state); 979 } 980 981 static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) 982 { 983 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 984 985 /* The use of a CPU fence is one of two ways to detect writes by the 986 * CPU to the scanout and trigger updates to the FBC. 987 * 988 * The other method is by software tracking (see 989 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke 990 * the current compressed buffer and recompress it. 991 * 992 * Note that is possible for a tiled surface to be unmappable (and 993 * so have no fence associated with it) due to aperture constraints 994 * at the time of pinning. 995 * 996 * FIXME with 90/270 degree rotation we should use the fence on 997 * the normal GTT view (the rotated view doesn't even have a 998 * fence). Would need changes to the FBC fence Y offset as well. 999 * For now this will effectively disable FBC with 90/270 degree 1000 * rotation. 1001 */ 1002 return DISPLAY_VER(i915) >= 9 || 1003 (plane_state->flags & PLANE_HAS_FENCE && 1004 plane_state->ggtt_vma->fence); 1005 } 1006 1007 static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state) 1008 { 1009 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1010 struct intel_fbc *fbc = plane->fbc; 1011 1012 return intel_fbc_min_limit(plane_state) <= fbc->limit && 1013 intel_fbc_cfb_size(plane_state) <= fbc->compressed_fb.size * fbc->limit; 1014 } 1015 1016 static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state) 1017 { 1018 return !plane_state->no_fbc_reason && 1019 intel_fbc_is_fence_ok(plane_state) && 1020 intel_fbc_is_cfb_ok(plane_state); 1021 } 1022 1023 static int intel_fbc_check_plane(struct intel_atomic_state *state, 1024 struct intel_plane *plane) 1025 { 1026 struct drm_i915_private *i915 = to_i915(state->base.dev); 1027 struct intel_plane_state *plane_state = 1028 intel_atomic_get_new_plane_state(state, plane); 1029 const struct drm_framebuffer *fb = plane_state->hw.fb; 1030 struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc); 1031 const struct intel_crtc_state *crtc_state; 1032 struct intel_fbc *fbc = plane->fbc; 1033 1034 if (!fbc) 1035 return 0; 1036 1037 if (intel_vgpu_active(i915)) { 1038 plane_state->no_fbc_reason = "VGPU active"; 1039 return 0; 1040 } 1041 1042 if (!i915->params.enable_fbc) { 1043 plane_state->no_fbc_reason = "disabled per module param or by default"; 1044 return 0; 1045 } 1046 1047 if (!plane_state->uapi.visible) { 1048 plane_state->no_fbc_reason = "plane not visible"; 1049 return 0; 1050 } 1051 1052 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1053 1054 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1055 plane_state->no_fbc_reason = "interlaced mode not supported"; 1056 return 0; 1057 } 1058 1059 if (crtc_state->double_wide) { 1060 plane_state->no_fbc_reason = "double wide pipe not supported"; 1061 return 0; 1062 } 1063 1064 /* 1065 * Display 12+ is not supporting FBC with PSR2. 1066 * Recommendation is to keep this combination disabled 1067 * Bspec: 50422 HSD: 14010260002 1068 */ 1069 if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) { 1070 plane_state->no_fbc_reason = "PSR2 enabled"; 1071 return false; 1072 } 1073 1074 if (!pixel_format_is_valid(plane_state)) { 1075 plane_state->no_fbc_reason = "pixel format not supported"; 1076 return 0; 1077 } 1078 1079 if (!tiling_is_valid(plane_state)) { 1080 plane_state->no_fbc_reason = "tiling not supported"; 1081 return 0; 1082 } 1083 1084 if (!rotation_is_valid(plane_state)) { 1085 plane_state->no_fbc_reason = "rotation not supported"; 1086 return 0; 1087 } 1088 1089 if (!stride_is_valid(plane_state)) { 1090 plane_state->no_fbc_reason = "stride not supported"; 1091 return 0; 1092 } 1093 1094 if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && 1095 fb->format->has_alpha) { 1096 plane_state->no_fbc_reason = "per-pixel alpha not supported"; 1097 return false; 1098 } 1099 1100 if (!intel_fbc_hw_tracking_covers_screen(plane_state)) { 1101 plane_state->no_fbc_reason = "plane size too big"; 1102 return 0; 1103 } 1104 1105 /* 1106 * Work around a problem on GEN9+ HW, where enabling FBC on a plane 1107 * having a Y offset that isn't divisible by 4 causes FIFO underrun 1108 * and screen flicker. 1109 */ 1110 if (DISPLAY_VER(i915) >= 9 && 1111 plane_state->view.color_plane[0].y & 3) { 1112 plane_state->no_fbc_reason = "plane start Y offset misaligned"; 1113 return false; 1114 } 1115 1116 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ 1117 if (DISPLAY_VER(i915) >= 11 && 1118 (plane_state->view.color_plane[0].y + drm_rect_height(&plane_state->uapi.src)) & 3) { 1119 plane_state->no_fbc_reason = "plane end Y offset misaligned"; 1120 return false; 1121 } 1122 1123 /* WaFbcExceedCdClockThreshold:hsw,bdw */ 1124 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 1125 const struct intel_cdclk_state *cdclk_state; 1126 1127 cdclk_state = intel_atomic_get_cdclk_state(state); 1128 if (IS_ERR(cdclk_state)) 1129 return PTR_ERR(cdclk_state); 1130 1131 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { 1132 plane_state->no_fbc_reason = "pixel rate too high"; 1133 return 0; 1134 } 1135 } 1136 1137 plane_state->no_fbc_reason = NULL; 1138 1139 return 0; 1140 } 1141 1142 1143 static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state, 1144 struct intel_crtc *crtc, 1145 struct intel_plane *plane) 1146 { 1147 const struct intel_crtc_state *new_crtc_state = 1148 intel_atomic_get_new_crtc_state(state, crtc); 1149 const struct intel_plane_state *old_plane_state = 1150 intel_atomic_get_old_plane_state(state, plane); 1151 const struct intel_plane_state *new_plane_state = 1152 intel_atomic_get_new_plane_state(state, plane); 1153 const struct drm_framebuffer *old_fb = old_plane_state->hw.fb; 1154 const struct drm_framebuffer *new_fb = new_plane_state->hw.fb; 1155 1156 if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) 1157 return false; 1158 1159 if (!intel_fbc_is_ok(old_plane_state) || 1160 !intel_fbc_is_ok(new_plane_state)) 1161 return false; 1162 1163 if (old_fb->format->format != new_fb->format->format) 1164 return false; 1165 1166 if (old_fb->modifier != new_fb->modifier) 1167 return false; 1168 1169 if (intel_fbc_plane_stride(old_plane_state) != 1170 intel_fbc_plane_stride(new_plane_state)) 1171 return false; 1172 1173 if (intel_fbc_cfb_stride(old_plane_state) != 1174 intel_fbc_cfb_stride(new_plane_state)) 1175 return false; 1176 1177 if (intel_fbc_cfb_size(old_plane_state) != 1178 intel_fbc_cfb_size(new_plane_state)) 1179 return false; 1180 1181 if (intel_fbc_override_cfb_stride(old_plane_state) != 1182 intel_fbc_override_cfb_stride(new_plane_state)) 1183 return false; 1184 1185 return true; 1186 } 1187 1188 static bool __intel_fbc_pre_update(struct intel_atomic_state *state, 1189 struct intel_crtc *crtc, 1190 struct intel_plane *plane) 1191 { 1192 struct drm_i915_private *i915 = to_i915(state->base.dev); 1193 struct intel_fbc *fbc = plane->fbc; 1194 bool need_vblank_wait = false; 1195 1196 fbc->flip_pending = true; 1197 1198 if (intel_fbc_can_flip_nuke(state, crtc, plane)) 1199 return need_vblank_wait; 1200 1201 intel_fbc_deactivate(fbc, "update pending"); 1202 1203 /* 1204 * Display WA #1198: glk+ 1205 * Need an extra vblank wait between FBC disable and most plane 1206 * updates. Bspec says this is only needed for plane disable, but 1207 * that is not true. Touching most plane registers will cause the 1208 * corruption to appear. Also SKL/derivatives do not seem to be 1209 * affected. 1210 * 1211 * TODO: could optimize this a bit by sampling the frame 1212 * counter when we disable FBC (if it was already done earlier) 1213 * and skipping the extra vblank wait before the plane update 1214 * if at least one frame has already passed. 1215 */ 1216 if (fbc->activated && DISPLAY_VER(i915) >= 10) 1217 need_vblank_wait = true; 1218 fbc->activated = false; 1219 1220 return need_vblank_wait; 1221 } 1222 1223 bool intel_fbc_pre_update(struct intel_atomic_state *state, 1224 struct intel_crtc *crtc) 1225 { 1226 const struct intel_plane_state *plane_state; 1227 bool need_vblank_wait = false; 1228 struct intel_plane *plane; 1229 int i; 1230 1231 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1232 struct intel_fbc *fbc = plane->fbc; 1233 1234 if (!fbc || plane->pipe != crtc->pipe) 1235 continue; 1236 1237 mutex_lock(&fbc->lock); 1238 1239 if (fbc->state.plane == plane) 1240 need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane); 1241 1242 mutex_unlock(&fbc->lock); 1243 } 1244 1245 return need_vblank_wait; 1246 } 1247 1248 static void __intel_fbc_disable(struct intel_fbc *fbc) 1249 { 1250 struct drm_i915_private *i915 = fbc->i915; 1251 struct intel_plane *plane = fbc->state.plane; 1252 1253 drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); 1254 drm_WARN_ON(&i915->drm, fbc->active); 1255 1256 drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n", 1257 plane->base.base.id, plane->base.name); 1258 1259 __intel_fbc_cleanup_cfb(fbc); 1260 1261 fbc->state.plane = NULL; 1262 } 1263 1264 static void __intel_fbc_post_update(struct intel_fbc *fbc) 1265 { 1266 struct drm_i915_private *i915 = fbc->i915; 1267 1268 drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); 1269 1270 if (!fbc->busy_bits) 1271 intel_fbc_activate(fbc); 1272 else 1273 intel_fbc_deactivate(fbc, "frontbuffer write"); 1274 } 1275 1276 void intel_fbc_post_update(struct intel_atomic_state *state, 1277 struct intel_crtc *crtc) 1278 { 1279 const struct intel_plane_state *plane_state; 1280 struct intel_plane *plane; 1281 int i; 1282 1283 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1284 struct intel_fbc *fbc = plane->fbc; 1285 1286 if (!fbc || plane->pipe != crtc->pipe) 1287 continue; 1288 1289 mutex_lock(&fbc->lock); 1290 1291 if (fbc->state.plane == plane) { 1292 fbc->flip_pending = false; 1293 __intel_fbc_post_update(fbc); 1294 } 1295 1296 mutex_unlock(&fbc->lock); 1297 } 1298 } 1299 1300 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) 1301 { 1302 if (fbc->state.plane) 1303 return fbc->state.plane->frontbuffer_bit; 1304 else 1305 return fbc->possible_framebuffer_bits; 1306 } 1307 1308 void intel_fbc_invalidate(struct drm_i915_private *i915, 1309 unsigned int frontbuffer_bits, 1310 enum fb_op_origin origin) 1311 { 1312 struct intel_fbc *fbc = i915->fbc; 1313 1314 if (!fbc) 1315 return; 1316 1317 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE) 1318 return; 1319 1320 mutex_lock(&fbc->lock); 1321 1322 fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits; 1323 1324 if (fbc->state.plane && fbc->busy_bits) 1325 intel_fbc_deactivate(fbc, "frontbuffer write"); 1326 1327 mutex_unlock(&fbc->lock); 1328 } 1329 1330 void intel_fbc_flush(struct drm_i915_private *i915, 1331 unsigned int frontbuffer_bits, enum fb_op_origin origin) 1332 { 1333 struct intel_fbc *fbc = i915->fbc; 1334 1335 if (!fbc) 1336 return; 1337 1338 mutex_lock(&fbc->lock); 1339 1340 fbc->busy_bits &= ~frontbuffer_bits; 1341 1342 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE) 1343 goto out; 1344 1345 if (!fbc->busy_bits && fbc->state.plane && 1346 (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) { 1347 if (fbc->active) 1348 intel_fbc_nuke(fbc); 1349 else if (!fbc->flip_pending) 1350 __intel_fbc_post_update(fbc); 1351 } 1352 1353 out: 1354 mutex_unlock(&fbc->lock); 1355 } 1356 1357 int intel_fbc_atomic_check(struct intel_atomic_state *state) 1358 { 1359 struct intel_plane_state *plane_state; 1360 struct intel_plane *plane; 1361 int i; 1362 1363 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1364 int ret; 1365 1366 ret = intel_fbc_check_plane(state, plane); 1367 if (ret) 1368 return ret; 1369 } 1370 1371 return 0; 1372 } 1373 1374 static void __intel_fbc_enable(struct intel_atomic_state *state, 1375 struct intel_crtc *crtc, 1376 struct intel_plane *plane) 1377 { 1378 struct drm_i915_private *i915 = to_i915(state->base.dev); 1379 const struct intel_plane_state *plane_state = 1380 intel_atomic_get_new_plane_state(state, plane); 1381 struct intel_fbc *fbc = plane->fbc; 1382 1383 if (fbc->state.plane) { 1384 if (fbc->state.plane != plane) 1385 return; 1386 1387 if (intel_fbc_is_ok(plane_state)) { 1388 intel_fbc_update_state(state, crtc, plane); 1389 return; 1390 } 1391 1392 __intel_fbc_disable(fbc); 1393 } 1394 1395 drm_WARN_ON(&i915->drm, fbc->active); 1396 1397 fbc->no_fbc_reason = plane_state->no_fbc_reason; 1398 if (fbc->no_fbc_reason) 1399 return; 1400 1401 if (!intel_fbc_is_fence_ok(plane_state)) { 1402 fbc->no_fbc_reason = "framebuffer not fenced"; 1403 return; 1404 } 1405 1406 if (fbc->underrun_detected) { 1407 fbc->no_fbc_reason = "FIFO underrun"; 1408 return; 1409 } 1410 1411 if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), 1412 intel_fbc_min_limit(plane_state))) { 1413 fbc->no_fbc_reason = "not enough stolen memory"; 1414 return; 1415 } 1416 1417 drm_dbg_kms(&i915->drm, "Enabling FBC on [PLANE:%d:%s]\n", 1418 plane->base.base.id, plane->base.name); 1419 fbc->no_fbc_reason = "FBC enabled but not active yet\n"; 1420 1421 intel_fbc_update_state(state, crtc, plane); 1422 1423 intel_fbc_program_cfb(fbc); 1424 } 1425 1426 /** 1427 * intel_fbc_disable - disable FBC if it's associated with crtc 1428 * @crtc: the CRTC 1429 * 1430 * This function disables FBC if it's associated with the provided CRTC. 1431 */ 1432 void intel_fbc_disable(struct intel_crtc *crtc) 1433 { 1434 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1435 struct intel_plane *plane; 1436 1437 for_each_intel_plane(&i915->drm, plane) { 1438 struct intel_fbc *fbc = plane->fbc; 1439 1440 if (!fbc || plane->pipe != crtc->pipe) 1441 continue; 1442 1443 mutex_lock(&fbc->lock); 1444 if (fbc->state.plane == plane) 1445 __intel_fbc_disable(fbc); 1446 mutex_unlock(&fbc->lock); 1447 } 1448 } 1449 1450 void intel_fbc_update(struct intel_atomic_state *state, 1451 struct intel_crtc *crtc) 1452 { 1453 const struct intel_crtc_state *crtc_state = 1454 intel_atomic_get_new_crtc_state(state, crtc); 1455 const struct intel_plane_state *plane_state; 1456 struct intel_plane *plane; 1457 int i; 1458 1459 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1460 struct intel_fbc *fbc = plane->fbc; 1461 1462 if (!fbc || plane->pipe != crtc->pipe) 1463 continue; 1464 1465 mutex_lock(&fbc->lock); 1466 1467 if (crtc_state->update_pipe && plane_state->no_fbc_reason) { 1468 if (fbc->state.plane == plane) 1469 __intel_fbc_disable(fbc); 1470 } else { 1471 __intel_fbc_enable(state, crtc, plane); 1472 } 1473 1474 mutex_unlock(&fbc->lock); 1475 } 1476 } 1477 1478 /** 1479 * intel_fbc_global_disable - globally disable FBC 1480 * @i915: i915 device instance 1481 * 1482 * This function disables FBC regardless of which CRTC is associated with it. 1483 */ 1484 void intel_fbc_global_disable(struct drm_i915_private *i915) 1485 { 1486 struct intel_fbc *fbc = i915->fbc; 1487 1488 if (!fbc) 1489 return; 1490 1491 mutex_lock(&fbc->lock); 1492 if (fbc->state.plane) 1493 __intel_fbc_disable(fbc); 1494 mutex_unlock(&fbc->lock); 1495 } 1496 1497 static void intel_fbc_underrun_work_fn(struct work_struct *work) 1498 { 1499 struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work); 1500 struct drm_i915_private *i915 = fbc->i915; 1501 1502 mutex_lock(&fbc->lock); 1503 1504 /* Maybe we were scheduled twice. */ 1505 if (fbc->underrun_detected || !fbc->state.plane) 1506 goto out; 1507 1508 drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n"); 1509 fbc->underrun_detected = true; 1510 1511 intel_fbc_deactivate(fbc, "FIFO underrun"); 1512 if (!fbc->flip_pending) 1513 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(i915, fbc->state.plane->pipe)); 1514 __intel_fbc_disable(fbc); 1515 out: 1516 mutex_unlock(&fbc->lock); 1517 } 1518 1519 /* 1520 * intel_fbc_reset_underrun - reset FBC fifo underrun status. 1521 * @i915: the i915 device 1522 * 1523 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we 1524 * want to re-enable FBC after an underrun to increase test coverage. 1525 */ 1526 void intel_fbc_reset_underrun(struct drm_i915_private *i915) 1527 { 1528 struct intel_fbc *fbc = i915->fbc; 1529 1530 if (!fbc) 1531 return; 1532 1533 cancel_work_sync(&fbc->underrun_work); 1534 1535 mutex_lock(&fbc->lock); 1536 1537 if (fbc->underrun_detected) { 1538 drm_dbg_kms(&i915->drm, 1539 "Re-allowing FBC after fifo underrun\n"); 1540 fbc->no_fbc_reason = "FIFO underrun cleared"; 1541 } 1542 1543 fbc->underrun_detected = false; 1544 mutex_unlock(&fbc->lock); 1545 } 1546 1547 /** 1548 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun 1549 * @i915: i915 device 1550 * 1551 * Without FBC, most underruns are harmless and don't really cause too many 1552 * problems, except for an annoying message on dmesg. With FBC, underruns can 1553 * become black screens or even worse, especially when paired with bad 1554 * watermarks. So in order for us to be on the safe side, completely disable FBC 1555 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe 1556 * already suggests that watermarks may be bad, so try to be as safe as 1557 * possible. 1558 * 1559 * This function is called from the IRQ handler. 1560 */ 1561 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915) 1562 { 1563 struct intel_fbc *fbc = i915->fbc; 1564 1565 if (!fbc) 1566 return; 1567 1568 /* There's no guarantee that underrun_detected won't be set to true 1569 * right after this check and before the work is scheduled, but that's 1570 * not a problem since we'll check it again under the work function 1571 * while FBC is locked. This check here is just to prevent us from 1572 * unnecessarily scheduling the work, and it relies on the fact that we 1573 * never switch underrun_detect back to false after it's true. */ 1574 if (READ_ONCE(fbc->underrun_detected)) 1575 return; 1576 1577 schedule_work(&fbc->underrun_work); 1578 } 1579 1580 /* 1581 * The DDX driver changes its behavior depending on the value it reads from 1582 * i915.enable_fbc, so sanitize it by translating the default value into either 1583 * 0 or 1 in order to allow it to know what's going on. 1584 * 1585 * Notice that this is done at driver initialization and we still allow user 1586 * space to change the value during runtime without sanitizing it again. IGT 1587 * relies on being able to change i915.enable_fbc at runtime. 1588 */ 1589 static int intel_sanitize_fbc_option(struct drm_i915_private *i915) 1590 { 1591 if (i915->params.enable_fbc >= 0) 1592 return !!i915->params.enable_fbc; 1593 1594 if (!HAS_FBC(i915)) 1595 return 0; 1596 1597 if (IS_BROADWELL(i915) || DISPLAY_VER(i915) >= 9) 1598 return 1; 1599 1600 return 0; 1601 } 1602 1603 static bool need_fbc_vtd_wa(struct drm_i915_private *i915) 1604 { 1605 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ 1606 if (intel_vtd_active(i915) && 1607 (IS_SKYLAKE(i915) || IS_BROXTON(i915))) { 1608 drm_info(&i915->drm, 1609 "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n"); 1610 return true; 1611 } 1612 1613 return false; 1614 } 1615 1616 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane) 1617 { 1618 if (!fbc) 1619 return; 1620 1621 plane->fbc = fbc; 1622 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; 1623 } 1624 1625 static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915) 1626 { 1627 struct intel_fbc *fbc; 1628 1629 fbc = kzalloc(sizeof(*fbc), GFP_KERNEL); 1630 if (!fbc) 1631 return NULL; 1632 1633 fbc->i915 = i915; 1634 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); 1635 mutex_init(&fbc->lock); 1636 1637 if (DISPLAY_VER(i915) >= 7) 1638 fbc->funcs = &ivb_fbc_funcs; 1639 else if (DISPLAY_VER(i915) == 6) 1640 fbc->funcs = &snb_fbc_funcs; 1641 else if (DISPLAY_VER(i915) == 5) 1642 fbc->funcs = &ilk_fbc_funcs; 1643 else if (IS_G4X(i915)) 1644 fbc->funcs = &g4x_fbc_funcs; 1645 else if (DISPLAY_VER(i915) == 4) 1646 fbc->funcs = &i965_fbc_funcs; 1647 else 1648 fbc->funcs = &i8xx_fbc_funcs; 1649 1650 return fbc; 1651 } 1652 1653 /** 1654 * intel_fbc_init - Initialize FBC 1655 * @i915: the i915 device 1656 * 1657 * This function might be called during PM init process. 1658 */ 1659 void intel_fbc_init(struct drm_i915_private *i915) 1660 { 1661 struct intel_fbc *fbc; 1662 1663 if (!drm_mm_initialized(&i915->mm.stolen)) 1664 mkwrite_device_info(i915)->display.has_fbc = false; 1665 1666 if (need_fbc_vtd_wa(i915)) 1667 mkwrite_device_info(i915)->display.has_fbc = false; 1668 1669 i915->params.enable_fbc = intel_sanitize_fbc_option(i915); 1670 drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n", 1671 i915->params.enable_fbc); 1672 1673 if (!HAS_FBC(i915)) 1674 return; 1675 1676 fbc = intel_fbc_create(i915); 1677 if (!fbc) 1678 return; 1679 1680 /* We still don't have any sort of hardware state readout for FBC, so 1681 * deactivate it in case the BIOS activated it to make sure software 1682 * matches the hardware state. */ 1683 if (intel_fbc_hw_is_active(fbc)) 1684 intel_fbc_hw_deactivate(fbc); 1685 1686 i915->fbc = fbc; 1687 } 1688 1689 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused) 1690 { 1691 struct intel_fbc *fbc = m->private; 1692 struct drm_i915_private *i915 = fbc->i915; 1693 struct intel_plane *plane; 1694 intel_wakeref_t wakeref; 1695 1696 drm_modeset_lock_all(&i915->drm); 1697 1698 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1699 mutex_lock(&fbc->lock); 1700 1701 if (fbc->active) { 1702 seq_puts(m, "FBC enabled\n"); 1703 seq_printf(m, "Compressing: %s\n", 1704 yesno(intel_fbc_is_compressing(fbc))); 1705 } else { 1706 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); 1707 } 1708 1709 for_each_intel_plane(&i915->drm, plane) { 1710 const struct intel_plane_state *plane_state = 1711 to_intel_plane_state(plane->base.state); 1712 1713 if (plane->fbc != fbc) 1714 continue; 1715 1716 seq_printf(m, "%c [PLANE:%d:%s]: %s\n", 1717 fbc->state.plane == plane ? '*' : ' ', 1718 plane->base.base.id, plane->base.name, 1719 plane_state->no_fbc_reason ?: "FBC possible"); 1720 } 1721 1722 mutex_unlock(&fbc->lock); 1723 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1724 1725 drm_modeset_unlock_all(&i915->drm); 1726 1727 return 0; 1728 } 1729 1730 DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status); 1731 1732 static int intel_fbc_debugfs_false_color_get(void *data, u64 *val) 1733 { 1734 struct intel_fbc *fbc = data; 1735 1736 *val = fbc->false_color; 1737 1738 return 0; 1739 } 1740 1741 static int intel_fbc_debugfs_false_color_set(void *data, u64 val) 1742 { 1743 struct intel_fbc *fbc = data; 1744 1745 mutex_lock(&fbc->lock); 1746 1747 fbc->false_color = val; 1748 1749 if (fbc->active) 1750 fbc->funcs->set_false_color(fbc, fbc->false_color); 1751 1752 mutex_unlock(&fbc->lock); 1753 1754 return 0; 1755 } 1756 1757 DEFINE_SIMPLE_ATTRIBUTE(intel_fbc_debugfs_false_color_fops, 1758 intel_fbc_debugfs_false_color_get, 1759 intel_fbc_debugfs_false_color_set, 1760 "%llu\n"); 1761 1762 static void intel_fbc_debugfs_add(struct intel_fbc *fbc) 1763 { 1764 struct drm_i915_private *i915 = fbc->i915; 1765 struct drm_minor *minor = i915->drm.primary; 1766 1767 debugfs_create_file("i915_fbc_status", 0444, 1768 minor->debugfs_root, fbc, 1769 &intel_fbc_debugfs_status_fops); 1770 1771 if (fbc->funcs->set_false_color) 1772 debugfs_create_file("i915_fbc_false_color", 0644, 1773 minor->debugfs_root, fbc, 1774 &intel_fbc_debugfs_false_color_fops); 1775 } 1776 1777 void intel_fbc_debugfs_register(struct drm_i915_private *i915) 1778 { 1779 struct intel_fbc *fbc = i915->fbc; 1780 1781 if (fbc) 1782 intel_fbc_debugfs_add(fbc); 1783 } 1784