1 /*
2  * Copyright © 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 /**
25  * DOC: Frame Buffer Compression (FBC)
26  *
27  * FBC tries to save memory bandwidth (and so power consumption) by
28  * compressing the amount of memory used by the display. It is total
29  * transparent to user space and completely handled in the kernel.
30  *
31  * The benefits of FBC are mostly visible with solid backgrounds and
32  * variation-less patterns. It comes from keeping the memory footprint small
33  * and having fewer memory pages opened and accessed for refreshing the display.
34  *
35  * i915 is responsible to reserve stolen memory for FBC and configure its
36  * offset on proper registers. The hardware takes care of all
37  * compress/decompress. However there are many known cases where we have to
38  * forcibly disable it to allow proper screen updates.
39  */
40 
41 #include <linux/string_helpers.h>
42 
43 #include <drm/drm_blend.h>
44 #include <drm/drm_fourcc.h>
45 
46 #include "i915_drv.h"
47 #include "i915_reg.h"
48 #include "i915_utils.h"
49 #include "i915_vgpu.h"
50 #include "i915_vma.h"
51 #include "intel_cdclk.h"
52 #include "intel_de.h"
53 #include "intel_display_trace.h"
54 #include "intel_display_types.h"
55 #include "intel_fbc.h"
56 #include "intel_frontbuffer.h"
57 
58 #define for_each_fbc_id(__dev_priv, __fbc_id) \
59 	for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
60 		for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
61 
62 #define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
63 	for_each_fbc_id((__dev_priv), (__fbc_id)) \
64 		for_each_if((__fbc) = (__dev_priv)->display.fbc[(__fbc_id)])
65 
66 struct intel_fbc_funcs {
67 	void (*activate)(struct intel_fbc *fbc);
68 	void (*deactivate)(struct intel_fbc *fbc);
69 	bool (*is_active)(struct intel_fbc *fbc);
70 	bool (*is_compressing)(struct intel_fbc *fbc);
71 	void (*nuke)(struct intel_fbc *fbc);
72 	void (*program_cfb)(struct intel_fbc *fbc);
73 	void (*set_false_color)(struct intel_fbc *fbc, bool enable);
74 };
75 
76 struct intel_fbc_state {
77 	struct intel_plane *plane;
78 	unsigned int cfb_stride;
79 	unsigned int cfb_size;
80 	unsigned int fence_y_offset;
81 	u16 override_cfb_stride;
82 	u16 interval;
83 	s8 fence_id;
84 };
85 
86 struct intel_fbc {
87 	struct drm_i915_private *i915;
88 	const struct intel_fbc_funcs *funcs;
89 
90 	/*
91 	 * This is always the inner lock when overlapping with
92 	 * struct_mutex and it's the outer lock when overlapping
93 	 * with stolen_lock.
94 	 */
95 	struct mutex lock;
96 	unsigned int busy_bits;
97 
98 	struct i915_stolen_fb compressed_fb, compressed_llb;
99 
100 	enum intel_fbc_id id;
101 
102 	u8 limit;
103 
104 	bool false_color;
105 
106 	bool active;
107 	bool activated;
108 	bool flip_pending;
109 
110 	bool underrun_detected;
111 	struct work_struct underrun_work;
112 
113 	/*
114 	 * This structure contains everything that's relevant to program the
115 	 * hardware registers. When we want to figure out if we need to disable
116 	 * and re-enable FBC for a new configuration we just check if there's
117 	 * something different in the struct. The genx_fbc_activate functions
118 	 * are supposed to read from it in order to program the registers.
119 	 */
120 	struct intel_fbc_state state;
121 	const char *no_fbc_reason;
122 };
123 
124 /* plane stride in pixels */
125 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
126 {
127 	const struct drm_framebuffer *fb = plane_state->hw.fb;
128 	unsigned int stride;
129 
130 	stride = plane_state->view.color_plane[0].mapping_stride;
131 	if (!drm_rotation_90_or_270(plane_state->hw.rotation))
132 		stride /= fb->format->cpp[0];
133 
134 	return stride;
135 }
136 
137 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
138 static unsigned int _intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
139 {
140 	unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
141 
142 	return intel_fbc_plane_stride(plane_state) * cpp;
143 }
144 
145 /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */
146 static unsigned int skl_fbc_min_cfb_stride(const struct intel_plane_state *plane_state)
147 {
148 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
149 	unsigned int limit = 4; /* 1:4 compression limit is the worst case */
150 	unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
151 	unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;
152 	unsigned int height = 4; /* FBC segment is 4 lines */
153 	unsigned int stride;
154 
155 	/* minimum segment stride we can use */
156 	stride = width * cpp * height / limit;
157 
158 	/*
159 	 * Wa_16011863758: icl+
160 	 * Avoid some hardware segment address miscalculation.
161 	 */
162 	if (DISPLAY_VER(i915) >= 11)
163 		stride += 64;
164 
165 	/*
166 	 * At least some of the platforms require each 4 line segment to
167 	 * be 512 byte aligned. Just do it always for simplicity.
168 	 */
169 	stride = ALIGN(stride, 512);
170 
171 	/* convert back to single line equivalent with 1:1 compression limit */
172 	return stride * limit / height;
173 }
174 
175 /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */
176 static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
177 {
178 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
179 	unsigned int stride = _intel_fbc_cfb_stride(plane_state);
180 
181 	/*
182 	 * At least some of the platforms require each 4 line segment to
183 	 * be 512 byte aligned. Aligning each line to 512 bytes guarantees
184 	 * that regardless of the compression limit we choose later.
185 	 */
186 	if (DISPLAY_VER(i915) >= 9)
187 		return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(plane_state));
188 	else
189 		return stride;
190 }
191 
192 static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state)
193 {
194 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
195 	int lines = drm_rect_height(&plane_state->uapi.src) >> 16;
196 
197 	if (DISPLAY_VER(i915) == 7)
198 		lines = min(lines, 2048);
199 	else if (DISPLAY_VER(i915) >= 8)
200 		lines = min(lines, 2560);
201 
202 	return lines * intel_fbc_cfb_stride(plane_state);
203 }
204 
205 static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state)
206 {
207 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
208 	unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);
209 	unsigned int stride = _intel_fbc_cfb_stride(plane_state);
210 	const struct drm_framebuffer *fb = plane_state->hw.fb;
211 
212 	/*
213 	 * Override stride in 64 byte units per 4 line segment.
214 	 *
215 	 * Gen9 hw miscalculates cfb stride for linear as
216 	 * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
217 	 * we always need to use the override there.
218 	 */
219 	if (stride != stride_aligned ||
220 	    (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR))
221 		return stride_aligned * 4 / 64;
222 
223 	return 0;
224 }
225 
226 static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
227 {
228 	const struct intel_fbc_state *fbc_state = &fbc->state;
229 	struct drm_i915_private *i915 = fbc->i915;
230 	unsigned int cfb_stride;
231 	u32 fbc_ctl;
232 
233 	cfb_stride = fbc_state->cfb_stride / fbc->limit;
234 
235 	/* FBC_CTL wants 32B or 64B units */
236 	if (DISPLAY_VER(i915) == 2)
237 		cfb_stride = (cfb_stride / 32) - 1;
238 	else
239 		cfb_stride = (cfb_stride / 64) - 1;
240 
241 	fbc_ctl = FBC_CTL_PERIODIC |
242 		FBC_CTL_INTERVAL(fbc_state->interval) |
243 		FBC_CTL_STRIDE(cfb_stride);
244 
245 	if (IS_I945GM(i915))
246 		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
247 
248 	if (fbc_state->fence_id >= 0)
249 		fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id);
250 
251 	return fbc_ctl;
252 }
253 
254 static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
255 {
256 	const struct intel_fbc_state *fbc_state = &fbc->state;
257 	u32 fbc_ctl2;
258 
259 	fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
260 		FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);
261 
262 	if (fbc_state->fence_id >= 0)
263 		fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
264 
265 	return fbc_ctl2;
266 }
267 
268 static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
269 {
270 	struct drm_i915_private *i915 = fbc->i915;
271 	u32 fbc_ctl;
272 
273 	/* Disable compression */
274 	fbc_ctl = intel_de_read(i915, FBC_CONTROL);
275 	if ((fbc_ctl & FBC_CTL_EN) == 0)
276 		return;
277 
278 	fbc_ctl &= ~FBC_CTL_EN;
279 	intel_de_write(i915, FBC_CONTROL, fbc_ctl);
280 
281 	/* Wait for compressing bit to clear */
282 	if (intel_de_wait_for_clear(i915, FBC_STATUS,
283 				    FBC_STAT_COMPRESSING, 10)) {
284 		drm_dbg_kms(&i915->drm, "FBC idle timed out\n");
285 		return;
286 	}
287 }
288 
289 static void i8xx_fbc_activate(struct intel_fbc *fbc)
290 {
291 	const struct intel_fbc_state *fbc_state = &fbc->state;
292 	struct drm_i915_private *i915 = fbc->i915;
293 	int i;
294 
295 	/* Clear old tags */
296 	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
297 		intel_de_write(i915, FBC_TAG(i), 0);
298 
299 	if (DISPLAY_VER(i915) == 4) {
300 		intel_de_write(i915, FBC_CONTROL2,
301 			       i965_fbc_ctl2(fbc));
302 		intel_de_write(i915, FBC_FENCE_OFF,
303 			       fbc_state->fence_y_offset);
304 	}
305 
306 	intel_de_write(i915, FBC_CONTROL,
307 		       FBC_CTL_EN | i8xx_fbc_ctl(fbc));
308 }
309 
310 static bool i8xx_fbc_is_active(struct intel_fbc *fbc)
311 {
312 	return intel_de_read(fbc->i915, FBC_CONTROL) & FBC_CTL_EN;
313 }
314 
315 static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
316 {
317 	return intel_de_read(fbc->i915, FBC_STATUS) &
318 		(FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
319 }
320 
321 static void i8xx_fbc_nuke(struct intel_fbc *fbc)
322 {
323 	struct intel_fbc_state *fbc_state = &fbc->state;
324 	enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
325 	struct drm_i915_private *dev_priv = fbc->i915;
326 
327 	intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
328 			  intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
329 }
330 
331 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
332 {
333 	struct drm_i915_private *i915 = fbc->i915;
334 
335 	GEM_BUG_ON(range_overflows_end_t(u64, i915_gem_stolen_area_address(i915),
336 					 i915_gem_stolen_node_offset(&fbc->compressed_fb),
337 					 U32_MAX));
338 	GEM_BUG_ON(range_overflows_end_t(u64, i915_gem_stolen_area_address(i915),
339 					 i915_gem_stolen_node_offset(&fbc->compressed_llb),
340 					 U32_MAX));
341 	intel_de_write(i915, FBC_CFB_BASE,
342 		       i915_gem_stolen_node_address(i915, &fbc->compressed_fb));
343 	intel_de_write(i915, FBC_LL_BASE,
344 		       i915_gem_stolen_node_address(i915, &fbc->compressed_llb));
345 }
346 
347 static const struct intel_fbc_funcs i8xx_fbc_funcs = {
348 	.activate = i8xx_fbc_activate,
349 	.deactivate = i8xx_fbc_deactivate,
350 	.is_active = i8xx_fbc_is_active,
351 	.is_compressing = i8xx_fbc_is_compressing,
352 	.nuke = i8xx_fbc_nuke,
353 	.program_cfb = i8xx_fbc_program_cfb,
354 };
355 
356 static void i965_fbc_nuke(struct intel_fbc *fbc)
357 {
358 	struct intel_fbc_state *fbc_state = &fbc->state;
359 	enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
360 	struct drm_i915_private *dev_priv = fbc->i915;
361 
362 	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
363 			  intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
364 }
365 
366 static const struct intel_fbc_funcs i965_fbc_funcs = {
367 	.activate = i8xx_fbc_activate,
368 	.deactivate = i8xx_fbc_deactivate,
369 	.is_active = i8xx_fbc_is_active,
370 	.is_compressing = i8xx_fbc_is_compressing,
371 	.nuke = i965_fbc_nuke,
372 	.program_cfb = i8xx_fbc_program_cfb,
373 };
374 
375 static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
376 {
377 	switch (fbc->limit) {
378 	default:
379 		MISSING_CASE(fbc->limit);
380 		fallthrough;
381 	case 1:
382 		return DPFC_CTL_LIMIT_1X;
383 	case 2:
384 		return DPFC_CTL_LIMIT_2X;
385 	case 4:
386 		return DPFC_CTL_LIMIT_4X;
387 	}
388 }
389 
390 static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
391 {
392 	const struct intel_fbc_state *fbc_state = &fbc->state;
393 	struct drm_i915_private *i915 = fbc->i915;
394 	u32 dpfc_ctl;
395 
396 	dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
397 		DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);
398 
399 	if (IS_G4X(i915))
400 		dpfc_ctl |= DPFC_CTL_SR_EN;
401 
402 	if (fbc_state->fence_id >= 0) {
403 		dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X;
404 
405 		if (DISPLAY_VER(i915) < 6)
406 			dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id);
407 	}
408 
409 	return dpfc_ctl;
410 }
411 
412 static void g4x_fbc_activate(struct intel_fbc *fbc)
413 {
414 	const struct intel_fbc_state *fbc_state = &fbc->state;
415 	struct drm_i915_private *i915 = fbc->i915;
416 
417 	intel_de_write(i915, DPFC_FENCE_YOFF,
418 		       fbc_state->fence_y_offset);
419 
420 	intel_de_write(i915, DPFC_CONTROL,
421 		       DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
422 }
423 
424 static void g4x_fbc_deactivate(struct intel_fbc *fbc)
425 {
426 	struct drm_i915_private *i915 = fbc->i915;
427 	u32 dpfc_ctl;
428 
429 	/* Disable compression */
430 	dpfc_ctl = intel_de_read(i915, DPFC_CONTROL);
431 	if (dpfc_ctl & DPFC_CTL_EN) {
432 		dpfc_ctl &= ~DPFC_CTL_EN;
433 		intel_de_write(i915, DPFC_CONTROL, dpfc_ctl);
434 	}
435 }
436 
437 static bool g4x_fbc_is_active(struct intel_fbc *fbc)
438 {
439 	return intel_de_read(fbc->i915, DPFC_CONTROL) & DPFC_CTL_EN;
440 }
441 
442 static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
443 {
444 	return intel_de_read(fbc->i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
445 }
446 
447 static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
448 {
449 	struct drm_i915_private *i915 = fbc->i915;
450 
451 	intel_de_write(i915, DPFC_CB_BASE,
452 		       i915_gem_stolen_node_offset(&fbc->compressed_fb));
453 }
454 
455 static const struct intel_fbc_funcs g4x_fbc_funcs = {
456 	.activate = g4x_fbc_activate,
457 	.deactivate = g4x_fbc_deactivate,
458 	.is_active = g4x_fbc_is_active,
459 	.is_compressing = g4x_fbc_is_compressing,
460 	.nuke = i965_fbc_nuke,
461 	.program_cfb = g4x_fbc_program_cfb,
462 };
463 
464 static void ilk_fbc_activate(struct intel_fbc *fbc)
465 {
466 	struct intel_fbc_state *fbc_state = &fbc->state;
467 	struct drm_i915_private *i915 = fbc->i915;
468 
469 	intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
470 		       fbc_state->fence_y_offset);
471 
472 	intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
473 		       DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
474 }
475 
476 static void ilk_fbc_deactivate(struct intel_fbc *fbc)
477 {
478 	struct drm_i915_private *i915 = fbc->i915;
479 	u32 dpfc_ctl;
480 
481 	/* Disable compression */
482 	dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
483 	if (dpfc_ctl & DPFC_CTL_EN) {
484 		dpfc_ctl &= ~DPFC_CTL_EN;
485 		intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
486 	}
487 }
488 
489 static bool ilk_fbc_is_active(struct intel_fbc *fbc)
490 {
491 	return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
492 }
493 
494 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
495 {
496 	return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
497 }
498 
499 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
500 {
501 	struct drm_i915_private *i915 = fbc->i915;
502 
503 	intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id),
504 		       i915_gem_stolen_node_offset(&fbc->compressed_fb));
505 }
506 
507 static const struct intel_fbc_funcs ilk_fbc_funcs = {
508 	.activate = ilk_fbc_activate,
509 	.deactivate = ilk_fbc_deactivate,
510 	.is_active = ilk_fbc_is_active,
511 	.is_compressing = ilk_fbc_is_compressing,
512 	.nuke = i965_fbc_nuke,
513 	.program_cfb = ilk_fbc_program_cfb,
514 };
515 
516 static void snb_fbc_program_fence(struct intel_fbc *fbc)
517 {
518 	const struct intel_fbc_state *fbc_state = &fbc->state;
519 	struct drm_i915_private *i915 = fbc->i915;
520 	u32 ctl = 0;
521 
522 	if (fbc_state->fence_id >= 0)
523 		ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id);
524 
525 	intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
526 	intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset);
527 }
528 
529 static void snb_fbc_activate(struct intel_fbc *fbc)
530 {
531 	snb_fbc_program_fence(fbc);
532 
533 	ilk_fbc_activate(fbc);
534 }
535 
536 static void snb_fbc_nuke(struct intel_fbc *fbc)
537 {
538 	struct drm_i915_private *i915 = fbc->i915;
539 
540 	intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
541 	intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
542 }
543 
544 static const struct intel_fbc_funcs snb_fbc_funcs = {
545 	.activate = snb_fbc_activate,
546 	.deactivate = ilk_fbc_deactivate,
547 	.is_active = ilk_fbc_is_active,
548 	.is_compressing = ilk_fbc_is_compressing,
549 	.nuke = snb_fbc_nuke,
550 	.program_cfb = ilk_fbc_program_cfb,
551 };
552 
553 static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
554 {
555 	const struct intel_fbc_state *fbc_state = &fbc->state;
556 	struct drm_i915_private *i915 = fbc->i915;
557 	u32 val = 0;
558 
559 	if (fbc_state->override_cfb_stride)
560 		val |= FBC_STRIDE_OVERRIDE |
561 			FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
562 
563 	intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
564 }
565 
566 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
567 {
568 	const struct intel_fbc_state *fbc_state = &fbc->state;
569 	struct drm_i915_private *i915 = fbc->i915;
570 	u32 val = 0;
571 
572 	/* Display WA #0529: skl, kbl, bxt. */
573 	if (fbc_state->override_cfb_stride)
574 		val |= CHICKEN_FBC_STRIDE_OVERRIDE |
575 			CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
576 
577 	intel_de_rmw(i915, CHICKEN_MISC_4,
578 		     CHICKEN_FBC_STRIDE_OVERRIDE |
579 		     CHICKEN_FBC_STRIDE_MASK, val);
580 }
581 
582 static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
583 {
584 	const struct intel_fbc_state *fbc_state = &fbc->state;
585 	struct drm_i915_private *i915 = fbc->i915;
586 	u32 dpfc_ctl;
587 
588 	dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
589 
590 	if (IS_IVYBRIDGE(i915))
591 		dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane);
592 
593 	if (fbc_state->fence_id >= 0)
594 		dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
595 
596 	if (fbc->false_color)
597 		dpfc_ctl |= DPFC_CTL_FALSE_COLOR;
598 
599 	return dpfc_ctl;
600 }
601 
602 static void ivb_fbc_activate(struct intel_fbc *fbc)
603 {
604 	struct drm_i915_private *i915 = fbc->i915;
605 
606 	if (DISPLAY_VER(i915) >= 10)
607 		glk_fbc_program_cfb_stride(fbc);
608 	else if (DISPLAY_VER(i915) == 9)
609 		skl_fbc_program_cfb_stride(fbc);
610 
611 	if (intel_gt_support_legacy_fencing(to_gt(i915)))
612 		snb_fbc_program_fence(fbc);
613 
614 	intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
615 		       DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
616 }
617 
618 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
619 {
620 	return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
621 }
622 
623 static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
624 				    bool enable)
625 {
626 	intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
627 		     DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
628 }
629 
630 static const struct intel_fbc_funcs ivb_fbc_funcs = {
631 	.activate = ivb_fbc_activate,
632 	.deactivate = ilk_fbc_deactivate,
633 	.is_active = ilk_fbc_is_active,
634 	.is_compressing = ivb_fbc_is_compressing,
635 	.nuke = snb_fbc_nuke,
636 	.program_cfb = ilk_fbc_program_cfb,
637 	.set_false_color = ivb_fbc_set_false_color,
638 };
639 
640 static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
641 {
642 	return fbc->funcs->is_active(fbc);
643 }
644 
645 static void intel_fbc_hw_activate(struct intel_fbc *fbc)
646 {
647 	trace_intel_fbc_activate(fbc->state.plane);
648 
649 	fbc->active = true;
650 	fbc->activated = true;
651 
652 	fbc->funcs->activate(fbc);
653 }
654 
655 static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
656 {
657 	trace_intel_fbc_deactivate(fbc->state.plane);
658 
659 	fbc->active = false;
660 
661 	fbc->funcs->deactivate(fbc);
662 }
663 
664 static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
665 {
666 	return fbc->funcs->is_compressing(fbc);
667 }
668 
669 static void intel_fbc_nuke(struct intel_fbc *fbc)
670 {
671 	struct drm_i915_private *i915 = fbc->i915;
672 
673 	lockdep_assert_held(&fbc->lock);
674 	drm_WARN_ON(&i915->drm, fbc->flip_pending);
675 
676 	trace_intel_fbc_nuke(fbc->state.plane);
677 
678 	fbc->funcs->nuke(fbc);
679 }
680 
681 static void intel_fbc_activate(struct intel_fbc *fbc)
682 {
683 	lockdep_assert_held(&fbc->lock);
684 
685 	intel_fbc_hw_activate(fbc);
686 	intel_fbc_nuke(fbc);
687 
688 	fbc->no_fbc_reason = NULL;
689 }
690 
691 static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason)
692 {
693 	lockdep_assert_held(&fbc->lock);
694 
695 	if (fbc->active)
696 		intel_fbc_hw_deactivate(fbc);
697 
698 	fbc->no_fbc_reason = reason;
699 }
700 
701 static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
702 {
703 	if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
704 		return BIT_ULL(28);
705 	else
706 		return BIT_ULL(32);
707 }
708 
709 static u64 intel_fbc_stolen_end(struct drm_i915_private *i915)
710 {
711 	u64 end;
712 
713 	/* The FBC hardware for BDW/SKL doesn't have access to the stolen
714 	 * reserved range size, so it always assumes the maximum (8mb) is used.
715 	 * If we enable FBC using a CFB on that memory range we'll get FIFO
716 	 * underruns, even if that range is not reserved by the BIOS. */
717 	if (IS_BROADWELL(i915) ||
718 	    (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915)))
719 		end = i915_gem_stolen_area_size(i915) - 8 * 1024 * 1024;
720 	else
721 		end = U64_MAX;
722 
723 	return min(end, intel_fbc_cfb_base_max(i915));
724 }
725 
726 static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)
727 {
728 	return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;
729 }
730 
731 static int intel_fbc_max_limit(struct drm_i915_private *i915)
732 {
733 	/* WaFbcOnly1to1Ratio:ctg */
734 	if (IS_G4X(i915))
735 		return 1;
736 
737 	/*
738 	 * FBC2 can only do 1:1, 1:2, 1:4, we limit
739 	 * FBC1 to the same out of convenience.
740 	 */
741 	return 4;
742 }
743 
744 static int find_compression_limit(struct intel_fbc *fbc,
745 				  unsigned int size, int min_limit)
746 {
747 	struct drm_i915_private *i915 = fbc->i915;
748 	u64 end = intel_fbc_stolen_end(i915);
749 	int ret, limit = min_limit;
750 
751 	size /= limit;
752 
753 	/* Try to over-allocate to reduce reallocations and fragmentation. */
754 	ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
755 						   size <<= 1, 4096, 0, end);
756 	if (ret == 0)
757 		return limit;
758 
759 	for (; limit <= intel_fbc_max_limit(i915); limit <<= 1) {
760 		ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
761 							   size >>= 1, 4096, 0, end);
762 		if (ret == 0)
763 			return limit;
764 	}
765 
766 	return 0;
767 }
768 
769 static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
770 			       unsigned int size, int min_limit)
771 {
772 	struct drm_i915_private *i915 = fbc->i915;
773 	int ret;
774 
775 	drm_WARN_ON(&i915->drm,
776 		    i915_gem_stolen_node_allocated(&fbc->compressed_fb));
777 	drm_WARN_ON(&i915->drm,
778 		    i915_gem_stolen_node_allocated(&fbc->compressed_llb));
779 
780 	if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) {
781 		ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb,
782 						  4096, 4096);
783 		if (ret)
784 			goto err;
785 	}
786 
787 	ret = find_compression_limit(fbc, size, min_limit);
788 	if (!ret)
789 		goto err_llb;
790 	else if (ret > min_limit)
791 		drm_info_once(&i915->drm,
792 			      "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
793 
794 	fbc->limit = ret;
795 
796 	drm_dbg_kms(&i915->drm,
797 		    "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n",
798 		    i915_gem_stolen_node_size(&fbc->compressed_fb), fbc->limit);
799 	return 0;
800 
801 err_llb:
802 	if (i915_gem_stolen_node_allocated(&fbc->compressed_llb))
803 		i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
804 err:
805 	if (i915_gem_stolen_initialized(i915))
806 		drm_info_once(&i915->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
807 	return -ENOSPC;
808 }
809 
810 static void intel_fbc_program_cfb(struct intel_fbc *fbc)
811 {
812 	fbc->funcs->program_cfb(fbc);
813 }
814 
815 static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
816 {
817 	/* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp,mtl */
818 	if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915))
819 		intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0,
820 			     DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
821 }
822 
823 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
824 {
825 	struct drm_i915_private *i915 = fbc->i915;
826 
827 	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
828 		return;
829 
830 	if (i915_gem_stolen_node_allocated(&fbc->compressed_llb))
831 		i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
832 	if (i915_gem_stolen_node_allocated(&fbc->compressed_fb))
833 		i915_gem_stolen_remove_node(i915, &fbc->compressed_fb);
834 }
835 
836 void intel_fbc_cleanup(struct drm_i915_private *i915)
837 {
838 	struct intel_fbc *fbc;
839 	enum intel_fbc_id fbc_id;
840 
841 	for_each_intel_fbc(i915, fbc, fbc_id) {
842 		mutex_lock(&fbc->lock);
843 		__intel_fbc_cleanup_cfb(fbc);
844 		mutex_unlock(&fbc->lock);
845 
846 		kfree(fbc);
847 	}
848 }
849 
850 static bool stride_is_valid(const struct intel_plane_state *plane_state)
851 {
852 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
853 	const struct drm_framebuffer *fb = plane_state->hw.fb;
854 	unsigned int stride = intel_fbc_plane_stride(plane_state) *
855 		fb->format->cpp[0];
856 
857 	/* This should have been caught earlier. */
858 	if (drm_WARN_ON_ONCE(&i915->drm, (stride & (64 - 1)) != 0))
859 		return false;
860 
861 	/* Below are the additional FBC restrictions. */
862 	if (stride < 512)
863 		return false;
864 
865 	if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3)
866 		return stride == 4096 || stride == 8192;
867 
868 	if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && stride < 2048)
869 		return false;
870 
871 	/* Display WA #1105: skl,bxt,kbl,cfl,glk */
872 	if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) &&
873 	    fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
874 		return false;
875 
876 	if (stride > 16384)
877 		return false;
878 
879 	return true;
880 }
881 
882 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
883 {
884 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
885 	const struct drm_framebuffer *fb = plane_state->hw.fb;
886 
887 	switch (fb->format->format) {
888 	case DRM_FORMAT_XRGB8888:
889 	case DRM_FORMAT_XBGR8888:
890 		return true;
891 	case DRM_FORMAT_XRGB1555:
892 	case DRM_FORMAT_RGB565:
893 		/* 16bpp not supported on gen2 */
894 		if (DISPLAY_VER(i915) == 2)
895 			return false;
896 		/* WaFbcOnly1to1Ratio:ctg */
897 		if (IS_G4X(i915))
898 			return false;
899 		return true;
900 	default:
901 		return false;
902 	}
903 }
904 
905 static bool rotation_is_valid(const struct intel_plane_state *plane_state)
906 {
907 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
908 	const struct drm_framebuffer *fb = plane_state->hw.fb;
909 	unsigned int rotation = plane_state->hw.rotation;
910 
911 	if (DISPLAY_VER(i915) >= 9 && fb->format->format == DRM_FORMAT_RGB565 &&
912 	    drm_rotation_90_or_270(rotation))
913 		return false;
914 	else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) &&
915 		 rotation != DRM_MODE_ROTATE_0)
916 		return false;
917 
918 	return true;
919 }
920 
921 /*
922  * For some reason, the hardware tracking starts looking at whatever we
923  * programmed as the display plane base address register. It does not look at
924  * the X and Y offset registers. That's why we include the src x/y offsets
925  * instead of just looking at the plane size.
926  */
927 static bool intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state *plane_state)
928 {
929 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
930 	unsigned int effective_w, effective_h, max_w, max_h;
931 
932 	if (DISPLAY_VER(i915) >= 10) {
933 		max_w = 5120;
934 		max_h = 4096;
935 	} else if (DISPLAY_VER(i915) >= 8 || IS_HASWELL(i915)) {
936 		max_w = 4096;
937 		max_h = 4096;
938 	} else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) {
939 		max_w = 4096;
940 		max_h = 2048;
941 	} else {
942 		max_w = 2048;
943 		max_h = 1536;
944 	}
945 
946 	effective_w = plane_state->view.color_plane[0].x +
947 		(drm_rect_width(&plane_state->uapi.src) >> 16);
948 	effective_h = plane_state->view.color_plane[0].y +
949 		(drm_rect_height(&plane_state->uapi.src) >> 16);
950 
951 	return effective_w <= max_w && effective_h <= max_h;
952 }
953 
954 static bool tiling_is_valid(const struct intel_plane_state *plane_state)
955 {
956 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
957 	const struct drm_framebuffer *fb = plane_state->hw.fb;
958 
959 	switch (fb->modifier) {
960 	case DRM_FORMAT_MOD_LINEAR:
961 	case I915_FORMAT_MOD_Y_TILED:
962 	case I915_FORMAT_MOD_Yf_TILED:
963 		return DISPLAY_VER(i915) >= 9;
964 	case I915_FORMAT_MOD_4_TILED:
965 	case I915_FORMAT_MOD_X_TILED:
966 		return true;
967 	default:
968 		return false;
969 	}
970 }
971 
972 static void intel_fbc_update_state(struct intel_atomic_state *state,
973 				   struct intel_crtc *crtc,
974 				   struct intel_plane *plane)
975 {
976 	struct drm_i915_private *i915 = to_i915(state->base.dev);
977 	const struct intel_crtc_state *crtc_state =
978 		intel_atomic_get_new_crtc_state(state, crtc);
979 	const struct intel_plane_state *plane_state =
980 		intel_atomic_get_new_plane_state(state, plane);
981 	struct intel_fbc *fbc = plane->fbc;
982 	struct intel_fbc_state *fbc_state = &fbc->state;
983 
984 	WARN_ON(plane_state->no_fbc_reason);
985 	WARN_ON(fbc_state->plane && fbc_state->plane != plane);
986 
987 	fbc_state->plane = plane;
988 
989 	/* FBC1 compression interval: arbitrary choice of 1 second */
990 	fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
991 
992 	fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);
993 
994 	drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE &&
995 		    !intel_gt_support_legacy_fencing(to_gt(i915)));
996 
997 	if (plane_state->flags & PLANE_HAS_FENCE)
998 		fbc_state->fence_id =  i915_vma_fence_id(plane_state->ggtt_vma);
999 	else
1000 		fbc_state->fence_id = -1;
1001 
1002 	fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);
1003 	fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);
1004 	fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
1005 }
1006 
1007 static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
1008 {
1009 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1010 
1011 	/*
1012 	 * The use of a CPU fence is one of two ways to detect writes by the
1013 	 * CPU to the scanout and trigger updates to the FBC.
1014 	 *
1015 	 * The other method is by software tracking (see
1016 	 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
1017 	 * the current compressed buffer and recompress it.
1018 	 *
1019 	 * Note that is possible for a tiled surface to be unmappable (and
1020 	 * so have no fence associated with it) due to aperture constraints
1021 	 * at the time of pinning.
1022 	 */
1023 	return DISPLAY_VER(i915) >= 9 ||
1024 		(plane_state->flags & PLANE_HAS_FENCE &&
1025 		 i915_vma_fence_id(plane_state->ggtt_vma) != -1);
1026 }
1027 
1028 static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)
1029 {
1030 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1031 	struct intel_fbc *fbc = plane->fbc;
1032 
1033 	return intel_fbc_min_limit(plane_state) <= fbc->limit &&
1034 		intel_fbc_cfb_size(plane_state) <= fbc->limit *
1035 			i915_gem_stolen_node_size(&fbc->compressed_fb);
1036 }
1037 
1038 static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)
1039 {
1040 	return !plane_state->no_fbc_reason &&
1041 		intel_fbc_is_fence_ok(plane_state) &&
1042 		intel_fbc_is_cfb_ok(plane_state);
1043 }
1044 
1045 static int intel_fbc_check_plane(struct intel_atomic_state *state,
1046 				 struct intel_plane *plane)
1047 {
1048 	struct drm_i915_private *i915 = to_i915(state->base.dev);
1049 	struct intel_plane_state *plane_state =
1050 		intel_atomic_get_new_plane_state(state, plane);
1051 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1052 	struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1053 	const struct intel_crtc_state *crtc_state;
1054 	struct intel_fbc *fbc = plane->fbc;
1055 
1056 	if (!fbc)
1057 		return 0;
1058 
1059 	if (!i915_gem_stolen_initialized(i915)) {
1060 		plane_state->no_fbc_reason = "stolen memory not initialised";
1061 		return 0;
1062 	}
1063 
1064 	if (intel_vgpu_active(i915)) {
1065 		plane_state->no_fbc_reason = "VGPU active";
1066 		return 0;
1067 	}
1068 
1069 	if (!i915->params.enable_fbc) {
1070 		plane_state->no_fbc_reason = "disabled per module param or by default";
1071 		return 0;
1072 	}
1073 
1074 	if (!plane_state->uapi.visible) {
1075 		plane_state->no_fbc_reason = "plane not visible";
1076 		return 0;
1077 	}
1078 
1079 	crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1080 
1081 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1082 		plane_state->no_fbc_reason = "interlaced mode not supported";
1083 		return 0;
1084 	}
1085 
1086 	if (crtc_state->double_wide) {
1087 		plane_state->no_fbc_reason = "double wide pipe not supported";
1088 		return 0;
1089 	}
1090 
1091 	/*
1092 	 * Display 12+ is not supporting FBC with PSR2.
1093 	 * Recommendation is to keep this combination disabled
1094 	 * Bspec: 50422 HSD: 14010260002
1095 	 */
1096 	if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) {
1097 		plane_state->no_fbc_reason = "PSR2 enabled";
1098 		return 0;
1099 	}
1100 
1101 	/* Wa_14016291713 */
1102 	if ((IS_DISPLAY_VER(i915, 12, 13) ||
1103 	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
1104 	    crtc_state->has_psr) {
1105 		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
1106 		return 0;
1107 	}
1108 
1109 	if (!pixel_format_is_valid(plane_state)) {
1110 		plane_state->no_fbc_reason = "pixel format not supported";
1111 		return 0;
1112 	}
1113 
1114 	if (!tiling_is_valid(plane_state)) {
1115 		plane_state->no_fbc_reason = "tiling not supported";
1116 		return 0;
1117 	}
1118 
1119 	if (!rotation_is_valid(plane_state)) {
1120 		plane_state->no_fbc_reason = "rotation not supported";
1121 		return 0;
1122 	}
1123 
1124 	if (!stride_is_valid(plane_state)) {
1125 		plane_state->no_fbc_reason = "stride not supported";
1126 		return 0;
1127 	}
1128 
1129 	if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
1130 	    fb->format->has_alpha) {
1131 		plane_state->no_fbc_reason = "per-pixel alpha not supported";
1132 		return 0;
1133 	}
1134 
1135 	if (!intel_fbc_hw_tracking_covers_screen(plane_state)) {
1136 		plane_state->no_fbc_reason = "plane size too big";
1137 		return 0;
1138 	}
1139 
1140 	/*
1141 	 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
1142 	 * having a Y offset that isn't divisible by 4 causes FIFO underrun
1143 	 * and screen flicker.
1144 	 */
1145 	if (DISPLAY_VER(i915) >= 9 &&
1146 	    plane_state->view.color_plane[0].y & 3) {
1147 		plane_state->no_fbc_reason = "plane start Y offset misaligned";
1148 		return 0;
1149 	}
1150 
1151 	/* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
1152 	if (DISPLAY_VER(i915) >= 11 &&
1153 	    (plane_state->view.color_plane[0].y +
1154 	     (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
1155 		plane_state->no_fbc_reason = "plane end Y offset misaligned";
1156 		return 0;
1157 	}
1158 
1159 	/* WaFbcExceedCdClockThreshold:hsw,bdw */
1160 	if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1161 		const struct intel_cdclk_state *cdclk_state;
1162 
1163 		cdclk_state = intel_atomic_get_cdclk_state(state);
1164 		if (IS_ERR(cdclk_state))
1165 			return PTR_ERR(cdclk_state);
1166 
1167 		if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
1168 			plane_state->no_fbc_reason = "pixel rate too high";
1169 			return 0;
1170 		}
1171 	}
1172 
1173 	plane_state->no_fbc_reason = NULL;
1174 
1175 	return 0;
1176 }
1177 
1178 
1179 static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
1180 				    struct intel_crtc *crtc,
1181 				    struct intel_plane *plane)
1182 {
1183 	const struct intel_crtc_state *new_crtc_state =
1184 		intel_atomic_get_new_crtc_state(state, crtc);
1185 	const struct intel_plane_state *old_plane_state =
1186 		intel_atomic_get_old_plane_state(state, plane);
1187 	const struct intel_plane_state *new_plane_state =
1188 		intel_atomic_get_new_plane_state(state, plane);
1189 	const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
1190 	const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
1191 
1192 	if (intel_crtc_needs_modeset(new_crtc_state))
1193 		return false;
1194 
1195 	if (!intel_fbc_is_ok(old_plane_state) ||
1196 	    !intel_fbc_is_ok(new_plane_state))
1197 		return false;
1198 
1199 	if (old_fb->format->format != new_fb->format->format)
1200 		return false;
1201 
1202 	if (old_fb->modifier != new_fb->modifier)
1203 		return false;
1204 
1205 	if (intel_fbc_plane_stride(old_plane_state) !=
1206 	    intel_fbc_plane_stride(new_plane_state))
1207 		return false;
1208 
1209 	if (intel_fbc_cfb_stride(old_plane_state) !=
1210 	    intel_fbc_cfb_stride(new_plane_state))
1211 		return false;
1212 
1213 	if (intel_fbc_cfb_size(old_plane_state) !=
1214 	    intel_fbc_cfb_size(new_plane_state))
1215 		return false;
1216 
1217 	if (intel_fbc_override_cfb_stride(old_plane_state) !=
1218 	    intel_fbc_override_cfb_stride(new_plane_state))
1219 		return false;
1220 
1221 	return true;
1222 }
1223 
1224 static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
1225 				   struct intel_crtc *crtc,
1226 				   struct intel_plane *plane)
1227 {
1228 	struct drm_i915_private *i915 = to_i915(state->base.dev);
1229 	struct intel_fbc *fbc = plane->fbc;
1230 	bool need_vblank_wait = false;
1231 
1232 	lockdep_assert_held(&fbc->lock);
1233 
1234 	fbc->flip_pending = true;
1235 
1236 	if (intel_fbc_can_flip_nuke(state, crtc, plane))
1237 		return need_vblank_wait;
1238 
1239 	intel_fbc_deactivate(fbc, "update pending");
1240 
1241 	/*
1242 	 * Display WA #1198: glk+
1243 	 * Need an extra vblank wait between FBC disable and most plane
1244 	 * updates. Bspec says this is only needed for plane disable, but
1245 	 * that is not true. Touching most plane registers will cause the
1246 	 * corruption to appear. Also SKL/derivatives do not seem to be
1247 	 * affected.
1248 	 *
1249 	 * TODO: could optimize this a bit by sampling the frame
1250 	 * counter when we disable FBC (if it was already done earlier)
1251 	 * and skipping the extra vblank wait before the plane update
1252 	 * if at least one frame has already passed.
1253 	 */
1254 	if (fbc->activated && DISPLAY_VER(i915) >= 10)
1255 		need_vblank_wait = true;
1256 	fbc->activated = false;
1257 
1258 	return need_vblank_wait;
1259 }
1260 
1261 bool intel_fbc_pre_update(struct intel_atomic_state *state,
1262 			  struct intel_crtc *crtc)
1263 {
1264 	const struct intel_plane_state __maybe_unused *plane_state;
1265 	bool need_vblank_wait = false;
1266 	struct intel_plane *plane;
1267 	int i;
1268 
1269 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1270 		struct intel_fbc *fbc = plane->fbc;
1271 
1272 		if (!fbc || plane->pipe != crtc->pipe)
1273 			continue;
1274 
1275 		mutex_lock(&fbc->lock);
1276 
1277 		if (fbc->state.plane == plane)
1278 			need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);
1279 
1280 		mutex_unlock(&fbc->lock);
1281 	}
1282 
1283 	return need_vblank_wait;
1284 }
1285 
1286 static void __intel_fbc_disable(struct intel_fbc *fbc)
1287 {
1288 	struct drm_i915_private *i915 = fbc->i915;
1289 	struct intel_plane *plane = fbc->state.plane;
1290 
1291 	lockdep_assert_held(&fbc->lock);
1292 	drm_WARN_ON(&i915->drm, fbc->active);
1293 
1294 	drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n",
1295 		    plane->base.base.id, plane->base.name);
1296 
1297 	__intel_fbc_cleanup_cfb(fbc);
1298 
1299 	fbc->state.plane = NULL;
1300 	fbc->flip_pending = false;
1301 	fbc->busy_bits = 0;
1302 }
1303 
1304 static void __intel_fbc_post_update(struct intel_fbc *fbc)
1305 {
1306 	lockdep_assert_held(&fbc->lock);
1307 
1308 	fbc->flip_pending = false;
1309 
1310 	if (!fbc->busy_bits)
1311 		intel_fbc_activate(fbc);
1312 	else
1313 		intel_fbc_deactivate(fbc, "frontbuffer write");
1314 }
1315 
1316 void intel_fbc_post_update(struct intel_atomic_state *state,
1317 			   struct intel_crtc *crtc)
1318 {
1319 	const struct intel_plane_state __maybe_unused *plane_state;
1320 	struct intel_plane *plane;
1321 	int i;
1322 
1323 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1324 		struct intel_fbc *fbc = plane->fbc;
1325 
1326 		if (!fbc || plane->pipe != crtc->pipe)
1327 			continue;
1328 
1329 		mutex_lock(&fbc->lock);
1330 
1331 		if (fbc->state.plane == plane)
1332 			__intel_fbc_post_update(fbc);
1333 
1334 		mutex_unlock(&fbc->lock);
1335 	}
1336 }
1337 
1338 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1339 {
1340 	if (fbc->state.plane)
1341 		return fbc->state.plane->frontbuffer_bit;
1342 	else
1343 		return 0;
1344 }
1345 
1346 static void __intel_fbc_invalidate(struct intel_fbc *fbc,
1347 				   unsigned int frontbuffer_bits,
1348 				   enum fb_op_origin origin)
1349 {
1350 	if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1351 		return;
1352 
1353 	mutex_lock(&fbc->lock);
1354 
1355 	frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1356 	if (!frontbuffer_bits)
1357 		goto out;
1358 
1359 	fbc->busy_bits |= frontbuffer_bits;
1360 	intel_fbc_deactivate(fbc, "frontbuffer write");
1361 
1362 out:
1363 	mutex_unlock(&fbc->lock);
1364 }
1365 
1366 void intel_fbc_invalidate(struct drm_i915_private *i915,
1367 			  unsigned int frontbuffer_bits,
1368 			  enum fb_op_origin origin)
1369 {
1370 	struct intel_fbc *fbc;
1371 	enum intel_fbc_id fbc_id;
1372 
1373 	for_each_intel_fbc(i915, fbc, fbc_id)
1374 		__intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
1375 
1376 }
1377 
1378 static void __intel_fbc_flush(struct intel_fbc *fbc,
1379 			      unsigned int frontbuffer_bits,
1380 			      enum fb_op_origin origin)
1381 {
1382 	mutex_lock(&fbc->lock);
1383 
1384 	frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1385 	if (!frontbuffer_bits)
1386 		goto out;
1387 
1388 	fbc->busy_bits &= ~frontbuffer_bits;
1389 
1390 	if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1391 		goto out;
1392 
1393 	if (fbc->busy_bits || fbc->flip_pending)
1394 		goto out;
1395 
1396 	if (fbc->active)
1397 		intel_fbc_nuke(fbc);
1398 	else
1399 		intel_fbc_activate(fbc);
1400 
1401 out:
1402 	mutex_unlock(&fbc->lock);
1403 }
1404 
1405 void intel_fbc_flush(struct drm_i915_private *i915,
1406 		     unsigned int frontbuffer_bits,
1407 		     enum fb_op_origin origin)
1408 {
1409 	struct intel_fbc *fbc;
1410 	enum intel_fbc_id fbc_id;
1411 
1412 	for_each_intel_fbc(i915, fbc, fbc_id)
1413 		__intel_fbc_flush(fbc, frontbuffer_bits, origin);
1414 }
1415 
1416 int intel_fbc_atomic_check(struct intel_atomic_state *state)
1417 {
1418 	struct intel_plane_state __maybe_unused *plane_state;
1419 	struct intel_plane *plane;
1420 	int i;
1421 
1422 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1423 		int ret;
1424 
1425 		ret = intel_fbc_check_plane(state, plane);
1426 		if (ret)
1427 			return ret;
1428 	}
1429 
1430 	return 0;
1431 }
1432 
1433 static void __intel_fbc_enable(struct intel_atomic_state *state,
1434 			       struct intel_crtc *crtc,
1435 			       struct intel_plane *plane)
1436 {
1437 	struct drm_i915_private *i915 = to_i915(state->base.dev);
1438 	const struct intel_plane_state *plane_state =
1439 		intel_atomic_get_new_plane_state(state, plane);
1440 	struct intel_fbc *fbc = plane->fbc;
1441 
1442 	lockdep_assert_held(&fbc->lock);
1443 
1444 	if (fbc->state.plane) {
1445 		if (fbc->state.plane != plane)
1446 			return;
1447 
1448 		if (intel_fbc_is_ok(plane_state)) {
1449 			intel_fbc_update_state(state, crtc, plane);
1450 			return;
1451 		}
1452 
1453 		__intel_fbc_disable(fbc);
1454 	}
1455 
1456 	drm_WARN_ON(&i915->drm, fbc->active);
1457 
1458 	fbc->no_fbc_reason = plane_state->no_fbc_reason;
1459 	if (fbc->no_fbc_reason)
1460 		return;
1461 
1462 	if (!intel_fbc_is_fence_ok(plane_state)) {
1463 		fbc->no_fbc_reason = "framebuffer not fenced";
1464 		return;
1465 	}
1466 
1467 	if (fbc->underrun_detected) {
1468 		fbc->no_fbc_reason = "FIFO underrun";
1469 		return;
1470 	}
1471 
1472 	if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),
1473 				intel_fbc_min_limit(plane_state))) {
1474 		fbc->no_fbc_reason = "not enough stolen memory";
1475 		return;
1476 	}
1477 
1478 	drm_dbg_kms(&i915->drm, "Enabling FBC on [PLANE:%d:%s]\n",
1479 		    plane->base.base.id, plane->base.name);
1480 	fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1481 
1482 	intel_fbc_update_state(state, crtc, plane);
1483 
1484 	intel_fbc_program_workarounds(fbc);
1485 	intel_fbc_program_cfb(fbc);
1486 }
1487 
1488 /**
1489  * intel_fbc_disable - disable FBC if it's associated with crtc
1490  * @crtc: the CRTC
1491  *
1492  * This function disables FBC if it's associated with the provided CRTC.
1493  */
1494 void intel_fbc_disable(struct intel_crtc *crtc)
1495 {
1496 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1497 	struct intel_plane *plane;
1498 
1499 	for_each_intel_plane(&i915->drm, plane) {
1500 		struct intel_fbc *fbc = plane->fbc;
1501 
1502 		if (!fbc || plane->pipe != crtc->pipe)
1503 			continue;
1504 
1505 		mutex_lock(&fbc->lock);
1506 		if (fbc->state.plane == plane)
1507 			__intel_fbc_disable(fbc);
1508 		mutex_unlock(&fbc->lock);
1509 	}
1510 }
1511 
1512 void intel_fbc_update(struct intel_atomic_state *state,
1513 		      struct intel_crtc *crtc)
1514 {
1515 	const struct intel_crtc_state *crtc_state =
1516 		intel_atomic_get_new_crtc_state(state, crtc);
1517 	const struct intel_plane_state *plane_state;
1518 	struct intel_plane *plane;
1519 	int i;
1520 
1521 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1522 		struct intel_fbc *fbc = plane->fbc;
1523 
1524 		if (!fbc || plane->pipe != crtc->pipe)
1525 			continue;
1526 
1527 		mutex_lock(&fbc->lock);
1528 
1529 		if (intel_crtc_needs_fastset(crtc_state) &&
1530 		    plane_state->no_fbc_reason) {
1531 			if (fbc->state.plane == plane)
1532 				__intel_fbc_disable(fbc);
1533 		} else {
1534 			__intel_fbc_enable(state, crtc, plane);
1535 		}
1536 
1537 		mutex_unlock(&fbc->lock);
1538 	}
1539 }
1540 
1541 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1542 {
1543 	struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work);
1544 	struct drm_i915_private *i915 = fbc->i915;
1545 
1546 	mutex_lock(&fbc->lock);
1547 
1548 	/* Maybe we were scheduled twice. */
1549 	if (fbc->underrun_detected || !fbc->state.plane)
1550 		goto out;
1551 
1552 	drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
1553 	fbc->underrun_detected = true;
1554 
1555 	intel_fbc_deactivate(fbc, "FIFO underrun");
1556 	if (!fbc->flip_pending)
1557 		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(i915, fbc->state.plane->pipe));
1558 	__intel_fbc_disable(fbc);
1559 out:
1560 	mutex_unlock(&fbc->lock);
1561 }
1562 
1563 static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
1564 {
1565 	struct drm_i915_private *i915 = fbc->i915;
1566 
1567 	cancel_work_sync(&fbc->underrun_work);
1568 
1569 	mutex_lock(&fbc->lock);
1570 
1571 	if (fbc->underrun_detected) {
1572 		drm_dbg_kms(&i915->drm,
1573 			    "Re-allowing FBC after fifo underrun\n");
1574 		fbc->no_fbc_reason = "FIFO underrun cleared";
1575 	}
1576 
1577 	fbc->underrun_detected = false;
1578 	mutex_unlock(&fbc->lock);
1579 }
1580 
1581 /*
1582  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1583  * @i915: the i915 device
1584  *
1585  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1586  * want to re-enable FBC after an underrun to increase test coverage.
1587  */
1588 void intel_fbc_reset_underrun(struct drm_i915_private *i915)
1589 {
1590 	struct intel_fbc *fbc;
1591 	enum intel_fbc_id fbc_id;
1592 
1593 	for_each_intel_fbc(i915, fbc, fbc_id)
1594 		__intel_fbc_reset_underrun(fbc);
1595 }
1596 
1597 static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
1598 {
1599 	/*
1600 	 * There's no guarantee that underrun_detected won't be set to true
1601 	 * right after this check and before the work is scheduled, but that's
1602 	 * not a problem since we'll check it again under the work function
1603 	 * while FBC is locked. This check here is just to prevent us from
1604 	 * unnecessarily scheduling the work, and it relies on the fact that we
1605 	 * never switch underrun_detect back to false after it's true.
1606 	 */
1607 	if (READ_ONCE(fbc->underrun_detected))
1608 		return;
1609 
1610 	queue_work(fbc->i915->unordered_wq, &fbc->underrun_work);
1611 }
1612 
1613 /**
1614  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1615  * @i915: i915 device
1616  *
1617  * Without FBC, most underruns are harmless and don't really cause too many
1618  * problems, except for an annoying message on dmesg. With FBC, underruns can
1619  * become black screens or even worse, especially when paired with bad
1620  * watermarks. So in order for us to be on the safe side, completely disable FBC
1621  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1622  * already suggests that watermarks may be bad, so try to be as safe as
1623  * possible.
1624  *
1625  * This function is called from the IRQ handler.
1626  */
1627 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
1628 {
1629 	struct intel_fbc *fbc;
1630 	enum intel_fbc_id fbc_id;
1631 
1632 	for_each_intel_fbc(i915, fbc, fbc_id)
1633 		__intel_fbc_handle_fifo_underrun_irq(fbc);
1634 }
1635 
1636 /*
1637  * The DDX driver changes its behavior depending on the value it reads from
1638  * i915.enable_fbc, so sanitize it by translating the default value into either
1639  * 0 or 1 in order to allow it to know what's going on.
1640  *
1641  * Notice that this is done at driver initialization and we still allow user
1642  * space to change the value during runtime without sanitizing it again. IGT
1643  * relies on being able to change i915.enable_fbc at runtime.
1644  */
1645 static int intel_sanitize_fbc_option(struct drm_i915_private *i915)
1646 {
1647 	if (i915->params.enable_fbc >= 0)
1648 		return !!i915->params.enable_fbc;
1649 
1650 	if (!HAS_FBC(i915))
1651 		return 0;
1652 
1653 	if (IS_BROADWELL(i915) || DISPLAY_VER(i915) >= 9)
1654 		return 1;
1655 
1656 	return 0;
1657 }
1658 
1659 static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
1660 {
1661 	/* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1662 	if (i915_vtd_active(i915) &&
1663 	    (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
1664 		drm_info(&i915->drm,
1665 			 "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1666 		return true;
1667 	}
1668 
1669 	return false;
1670 }
1671 
1672 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
1673 {
1674 	plane->fbc = fbc;
1675 }
1676 
1677 static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
1678 					  enum intel_fbc_id fbc_id)
1679 {
1680 	struct intel_fbc *fbc;
1681 
1682 	fbc = kzalloc(sizeof(*fbc), GFP_KERNEL);
1683 	if (!fbc)
1684 		return NULL;
1685 
1686 	fbc->id = fbc_id;
1687 	fbc->i915 = i915;
1688 	INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1689 	mutex_init(&fbc->lock);
1690 
1691 	if (DISPLAY_VER(i915) >= 7)
1692 		fbc->funcs = &ivb_fbc_funcs;
1693 	else if (DISPLAY_VER(i915) == 6)
1694 		fbc->funcs = &snb_fbc_funcs;
1695 	else if (DISPLAY_VER(i915) == 5)
1696 		fbc->funcs = &ilk_fbc_funcs;
1697 	else if (IS_G4X(i915))
1698 		fbc->funcs = &g4x_fbc_funcs;
1699 	else if (DISPLAY_VER(i915) == 4)
1700 		fbc->funcs = &i965_fbc_funcs;
1701 	else
1702 		fbc->funcs = &i8xx_fbc_funcs;
1703 
1704 	return fbc;
1705 }
1706 
1707 /**
1708  * intel_fbc_init - Initialize FBC
1709  * @i915: the i915 device
1710  *
1711  * This function might be called during PM init process.
1712  */
1713 void intel_fbc_init(struct drm_i915_private *i915)
1714 {
1715 	enum intel_fbc_id fbc_id;
1716 
1717 	if (need_fbc_vtd_wa(i915))
1718 		DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
1719 
1720 	i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
1721 	drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
1722 		    i915->params.enable_fbc);
1723 
1724 	for_each_fbc_id(i915, fbc_id)
1725 		i915->display.fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
1726 }
1727 
1728 /**
1729  * intel_fbc_sanitize - Sanitize FBC
1730  * @i915: the i915 device
1731  *
1732  * Make sure FBC is initially disabled since we have no
1733  * idea eg. into which parts of stolen it might be scribbling
1734  * into.
1735  */
1736 void intel_fbc_sanitize(struct drm_i915_private *i915)
1737 {
1738 	struct intel_fbc *fbc;
1739 	enum intel_fbc_id fbc_id;
1740 
1741 	for_each_intel_fbc(i915, fbc, fbc_id) {
1742 		if (intel_fbc_hw_is_active(fbc))
1743 			intel_fbc_hw_deactivate(fbc);
1744 	}
1745 }
1746 
1747 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
1748 {
1749 	struct intel_fbc *fbc = m->private;
1750 	struct drm_i915_private *i915 = fbc->i915;
1751 	struct intel_plane *plane;
1752 	intel_wakeref_t wakeref;
1753 
1754 	drm_modeset_lock_all(&i915->drm);
1755 
1756 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1757 	mutex_lock(&fbc->lock);
1758 
1759 	if (fbc->active) {
1760 		seq_puts(m, "FBC enabled\n");
1761 		seq_printf(m, "Compressing: %s\n",
1762 			   str_yes_no(intel_fbc_is_compressing(fbc)));
1763 	} else {
1764 		seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1765 	}
1766 
1767 	for_each_intel_plane(&i915->drm, plane) {
1768 		const struct intel_plane_state *plane_state =
1769 			to_intel_plane_state(plane->base.state);
1770 
1771 		if (plane->fbc != fbc)
1772 			continue;
1773 
1774 		seq_printf(m, "%c [PLANE:%d:%s]: %s\n",
1775 			   fbc->state.plane == plane ? '*' : ' ',
1776 			   plane->base.base.id, plane->base.name,
1777 			   plane_state->no_fbc_reason ?: "FBC possible");
1778 	}
1779 
1780 	mutex_unlock(&fbc->lock);
1781 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1782 
1783 	drm_modeset_unlock_all(&i915->drm);
1784 
1785 	return 0;
1786 }
1787 
1788 DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status);
1789 
1790 static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
1791 {
1792 	struct intel_fbc *fbc = data;
1793 
1794 	*val = fbc->false_color;
1795 
1796 	return 0;
1797 }
1798 
1799 static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
1800 {
1801 	struct intel_fbc *fbc = data;
1802 
1803 	mutex_lock(&fbc->lock);
1804 
1805 	fbc->false_color = val;
1806 
1807 	if (fbc->active)
1808 		fbc->funcs->set_false_color(fbc, fbc->false_color);
1809 
1810 	mutex_unlock(&fbc->lock);
1811 
1812 	return 0;
1813 }
1814 
1815 DEFINE_DEBUGFS_ATTRIBUTE(intel_fbc_debugfs_false_color_fops,
1816 			 intel_fbc_debugfs_false_color_get,
1817 			 intel_fbc_debugfs_false_color_set,
1818 			 "%llu\n");
1819 
1820 static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
1821 				  struct dentry *parent)
1822 {
1823 	debugfs_create_file("i915_fbc_status", 0444, parent,
1824 			    fbc, &intel_fbc_debugfs_status_fops);
1825 
1826 	if (fbc->funcs->set_false_color)
1827 		debugfs_create_file_unsafe("i915_fbc_false_color", 0644, parent,
1828 					   fbc, &intel_fbc_debugfs_false_color_fops);
1829 }
1830 
1831 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
1832 {
1833 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1834 
1835 	if (plane->fbc)
1836 		intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);
1837 }
1838 
1839 /* FIXME: remove this once igt is on board with per-crtc stuff */
1840 void intel_fbc_debugfs_register(struct drm_i915_private *i915)
1841 {
1842 	struct drm_minor *minor = i915->drm.primary;
1843 	struct intel_fbc *fbc;
1844 
1845 	fbc = i915->display.fbc[INTEL_FBC_A];
1846 	if (fbc)
1847 		intel_fbc_debugfs_add(fbc, minor->debugfs_root);
1848 }
1849