1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Frame Buffer Compression (FBC) 26 * 27 * FBC tries to save memory bandwidth (and so power consumption) by 28 * compressing the amount of memory used by the display. It is total 29 * transparent to user space and completely handled in the kernel. 30 * 31 * The benefits of FBC are mostly visible with solid backgrounds and 32 * variation-less patterns. It comes from keeping the memory footprint small 33 * and having fewer memory pages opened and accessed for refreshing the display. 34 * 35 * i915 is responsible to reserve stolen memory for FBC and configure its 36 * offset on proper registers. The hardware takes care of all 37 * compress/decompress. However there are many known cases where we have to 38 * forcibly disable it to allow proper screen updates. 39 */ 40 41 #include <drm/drm_fourcc.h> 42 43 #include "i915_drv.h" 44 #include "i915_vgpu.h" 45 #include "intel_cdclk.h" 46 #include "intel_de.h" 47 #include "intel_display_trace.h" 48 #include "intel_display_types.h" 49 #include "intel_fbc.h" 50 #include "intel_frontbuffer.h" 51 52 #define for_each_fbc_id(__dev_priv, __fbc_id) \ 53 for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \ 54 for_each_if(INTEL_INFO(__dev_priv)->display.fbc_mask & BIT(__fbc_id)) 55 56 #define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \ 57 for_each_fbc_id((__dev_priv), (__fbc_id)) \ 58 for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)]) 59 60 struct intel_fbc_funcs { 61 void (*activate)(struct intel_fbc *fbc); 62 void (*deactivate)(struct intel_fbc *fbc); 63 bool (*is_active)(struct intel_fbc *fbc); 64 bool (*is_compressing)(struct intel_fbc *fbc); 65 void (*nuke)(struct intel_fbc *fbc); 66 void (*program_cfb)(struct intel_fbc *fbc); 67 void (*set_false_color)(struct intel_fbc *fbc, bool enable); 68 }; 69 70 struct intel_fbc_state { 71 struct intel_plane *plane; 72 unsigned int cfb_stride; 73 unsigned int cfb_size; 74 unsigned int fence_y_offset; 75 u16 override_cfb_stride; 76 u16 interval; 77 s8 fence_id; 78 }; 79 80 struct intel_fbc { 81 struct drm_i915_private *i915; 82 const struct intel_fbc_funcs *funcs; 83 84 /* 85 * This is always the inner lock when overlapping with 86 * struct_mutex and it's the outer lock when overlapping 87 * with stolen_lock. 88 */ 89 struct mutex lock; 90 unsigned int possible_framebuffer_bits; 91 unsigned int busy_bits; 92 93 struct drm_mm_node compressed_fb; 94 struct drm_mm_node compressed_llb; 95 96 enum intel_fbc_id id; 97 98 u8 limit; 99 100 bool false_color; 101 102 bool active; 103 bool activated; 104 bool flip_pending; 105 106 bool underrun_detected; 107 struct work_struct underrun_work; 108 109 /* 110 * This structure contains everything that's relevant to program the 111 * hardware registers. When we want to figure out if we need to disable 112 * and re-enable FBC for a new configuration we just check if there's 113 * something different in the struct. The genx_fbc_activate functions 114 * are supposed to read from it in order to program the registers. 115 */ 116 struct intel_fbc_state state; 117 const char *no_fbc_reason; 118 }; 119 120 /* plane stride in pixels */ 121 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state) 122 { 123 const struct drm_framebuffer *fb = plane_state->hw.fb; 124 unsigned int stride; 125 126 stride = plane_state->view.color_plane[0].mapping_stride; 127 if (!drm_rotation_90_or_270(plane_state->hw.rotation)) 128 stride /= fb->format->cpp[0]; 129 130 return stride; 131 } 132 133 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */ 134 static unsigned int _intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) 135 { 136 unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ 137 138 return intel_fbc_plane_stride(plane_state) * cpp; 139 } 140 141 /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */ 142 static unsigned int skl_fbc_min_cfb_stride(const struct intel_plane_state *plane_state) 143 { 144 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 145 unsigned int limit = 4; /* 1:4 compression limit is the worst case */ 146 unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ 147 unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; 148 unsigned int height = 4; /* FBC segment is 4 lines */ 149 unsigned int stride; 150 151 /* minimum segment stride we can use */ 152 stride = width * cpp * height / limit; 153 154 /* 155 * Wa_16011863758: icl+ 156 * Avoid some hardware segment address miscalculation. 157 */ 158 if (DISPLAY_VER(i915) >= 11) 159 stride += 64; 160 161 /* 162 * At least some of the platforms require each 4 line segment to 163 * be 512 byte aligned. Just do it always for simplicity. 164 */ 165 stride = ALIGN(stride, 512); 166 167 /* convert back to single line equivalent with 1:1 compression limit */ 168 return stride * limit / height; 169 } 170 171 /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */ 172 static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) 173 { 174 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 175 unsigned int stride = _intel_fbc_cfb_stride(plane_state); 176 177 /* 178 * At least some of the platforms require each 4 line segment to 179 * be 512 byte aligned. Aligning each line to 512 bytes guarantees 180 * that regardless of the compression limit we choose later. 181 */ 182 if (DISPLAY_VER(i915) >= 9) 183 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(plane_state)); 184 else 185 return stride; 186 } 187 188 static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state) 189 { 190 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 191 int lines = drm_rect_height(&plane_state->uapi.src) >> 16; 192 193 if (DISPLAY_VER(i915) == 7) 194 lines = min(lines, 2048); 195 else if (DISPLAY_VER(i915) >= 8) 196 lines = min(lines, 2560); 197 198 return lines * intel_fbc_cfb_stride(plane_state); 199 } 200 201 static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state) 202 { 203 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 204 unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state); 205 unsigned int stride = _intel_fbc_cfb_stride(plane_state); 206 const struct drm_framebuffer *fb = plane_state->hw.fb; 207 208 /* 209 * Override stride in 64 byte units per 4 line segment. 210 * 211 * Gen9 hw miscalculates cfb stride for linear as 212 * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so 213 * we always need to use the override there. 214 */ 215 if (stride != stride_aligned || 216 (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) 217 return stride_aligned * 4 / 64; 218 219 return 0; 220 } 221 222 static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) 223 { 224 const struct intel_fbc_state *fbc_state = &fbc->state; 225 struct drm_i915_private *i915 = fbc->i915; 226 unsigned int cfb_stride; 227 u32 fbc_ctl; 228 229 cfb_stride = fbc_state->cfb_stride / fbc->limit; 230 231 /* FBC_CTL wants 32B or 64B units */ 232 if (DISPLAY_VER(i915) == 2) 233 cfb_stride = (cfb_stride / 32) - 1; 234 else 235 cfb_stride = (cfb_stride / 64) - 1; 236 237 fbc_ctl = FBC_CTL_PERIODIC | 238 FBC_CTL_INTERVAL(fbc_state->interval) | 239 FBC_CTL_STRIDE(cfb_stride); 240 241 if (IS_I945GM(i915)) 242 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 243 244 if (fbc_state->fence_id >= 0) 245 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id); 246 247 return fbc_ctl; 248 } 249 250 static u32 i965_fbc_ctl2(struct intel_fbc *fbc) 251 { 252 const struct intel_fbc_state *fbc_state = &fbc->state; 253 u32 fbc_ctl2; 254 255 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | 256 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane); 257 258 if (fbc_state->fence_id >= 0) 259 fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN; 260 261 return fbc_ctl2; 262 } 263 264 static void i8xx_fbc_deactivate(struct intel_fbc *fbc) 265 { 266 struct drm_i915_private *i915 = fbc->i915; 267 u32 fbc_ctl; 268 269 /* Disable compression */ 270 fbc_ctl = intel_de_read(i915, FBC_CONTROL); 271 if ((fbc_ctl & FBC_CTL_EN) == 0) 272 return; 273 274 fbc_ctl &= ~FBC_CTL_EN; 275 intel_de_write(i915, FBC_CONTROL, fbc_ctl); 276 277 /* Wait for compressing bit to clear */ 278 if (intel_de_wait_for_clear(i915, FBC_STATUS, 279 FBC_STAT_COMPRESSING, 10)) { 280 drm_dbg_kms(&i915->drm, "FBC idle timed out\n"); 281 return; 282 } 283 } 284 285 static void i8xx_fbc_activate(struct intel_fbc *fbc) 286 { 287 const struct intel_fbc_state *fbc_state = &fbc->state; 288 struct drm_i915_private *i915 = fbc->i915; 289 int i; 290 291 /* Clear old tags */ 292 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 293 intel_de_write(i915, FBC_TAG(i), 0); 294 295 if (DISPLAY_VER(i915) == 4) { 296 intel_de_write(i915, FBC_CONTROL2, 297 i965_fbc_ctl2(fbc)); 298 intel_de_write(i915, FBC_FENCE_OFF, 299 fbc_state->fence_y_offset); 300 } 301 302 intel_de_write(i915, FBC_CONTROL, 303 FBC_CTL_EN | i8xx_fbc_ctl(fbc)); 304 } 305 306 static bool i8xx_fbc_is_active(struct intel_fbc *fbc) 307 { 308 return intel_de_read(fbc->i915, FBC_CONTROL) & FBC_CTL_EN; 309 } 310 311 static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc) 312 { 313 return intel_de_read(fbc->i915, FBC_STATUS) & 314 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); 315 } 316 317 static void i8xx_fbc_nuke(struct intel_fbc *fbc) 318 { 319 struct intel_fbc_state *fbc_state = &fbc->state; 320 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; 321 struct drm_i915_private *dev_priv = fbc->i915; 322 323 spin_lock_irq(&dev_priv->uncore.lock); 324 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 325 intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane))); 326 spin_unlock_irq(&dev_priv->uncore.lock); 327 } 328 329 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) 330 { 331 struct drm_i915_private *i915 = fbc->i915; 332 333 GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start, 334 fbc->compressed_fb.start, U32_MAX)); 335 GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start, 336 fbc->compressed_llb.start, U32_MAX)); 337 338 intel_de_write(i915, FBC_CFB_BASE, 339 i915->dsm.start + fbc->compressed_fb.start); 340 intel_de_write(i915, FBC_LL_BASE, 341 i915->dsm.start + fbc->compressed_llb.start); 342 } 343 344 static const struct intel_fbc_funcs i8xx_fbc_funcs = { 345 .activate = i8xx_fbc_activate, 346 .deactivate = i8xx_fbc_deactivate, 347 .is_active = i8xx_fbc_is_active, 348 .is_compressing = i8xx_fbc_is_compressing, 349 .nuke = i8xx_fbc_nuke, 350 .program_cfb = i8xx_fbc_program_cfb, 351 }; 352 353 static void i965_fbc_nuke(struct intel_fbc *fbc) 354 { 355 struct intel_fbc_state *fbc_state = &fbc->state; 356 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; 357 struct drm_i915_private *dev_priv = fbc->i915; 358 359 spin_lock_irq(&dev_priv->uncore.lock); 360 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 361 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); 362 spin_unlock_irq(&dev_priv->uncore.lock); 363 } 364 365 static const struct intel_fbc_funcs i965_fbc_funcs = { 366 .activate = i8xx_fbc_activate, 367 .deactivate = i8xx_fbc_deactivate, 368 .is_active = i8xx_fbc_is_active, 369 .is_compressing = i8xx_fbc_is_compressing, 370 .nuke = i965_fbc_nuke, 371 .program_cfb = i8xx_fbc_program_cfb, 372 }; 373 374 static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc) 375 { 376 switch (fbc->limit) { 377 default: 378 MISSING_CASE(fbc->limit); 379 fallthrough; 380 case 1: 381 return DPFC_CTL_LIMIT_1X; 382 case 2: 383 return DPFC_CTL_LIMIT_2X; 384 case 4: 385 return DPFC_CTL_LIMIT_4X; 386 } 387 } 388 389 static u32 g4x_dpfc_ctl(struct intel_fbc *fbc) 390 { 391 const struct intel_fbc_state *fbc_state = &fbc->state; 392 struct drm_i915_private *i915 = fbc->i915; 393 u32 dpfc_ctl; 394 395 dpfc_ctl = g4x_dpfc_ctl_limit(fbc) | 396 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane); 397 398 if (IS_G4X(i915)) 399 dpfc_ctl |= DPFC_CTL_SR_EN; 400 401 if (fbc_state->fence_id >= 0) { 402 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X; 403 404 if (DISPLAY_VER(i915) < 6) 405 dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id); 406 } 407 408 return dpfc_ctl; 409 } 410 411 static void g4x_fbc_activate(struct intel_fbc *fbc) 412 { 413 const struct intel_fbc_state *fbc_state = &fbc->state; 414 struct drm_i915_private *i915 = fbc->i915; 415 416 intel_de_write(i915, DPFC_FENCE_YOFF, 417 fbc_state->fence_y_offset); 418 419 intel_de_write(i915, DPFC_CONTROL, 420 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 421 } 422 423 static void g4x_fbc_deactivate(struct intel_fbc *fbc) 424 { 425 struct drm_i915_private *i915 = fbc->i915; 426 u32 dpfc_ctl; 427 428 /* Disable compression */ 429 dpfc_ctl = intel_de_read(i915, DPFC_CONTROL); 430 if (dpfc_ctl & DPFC_CTL_EN) { 431 dpfc_ctl &= ~DPFC_CTL_EN; 432 intel_de_write(i915, DPFC_CONTROL, dpfc_ctl); 433 } 434 } 435 436 static bool g4x_fbc_is_active(struct intel_fbc *fbc) 437 { 438 return intel_de_read(fbc->i915, DPFC_CONTROL) & DPFC_CTL_EN; 439 } 440 441 static bool g4x_fbc_is_compressing(struct intel_fbc *fbc) 442 { 443 return intel_de_read(fbc->i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK; 444 } 445 446 static void g4x_fbc_program_cfb(struct intel_fbc *fbc) 447 { 448 struct drm_i915_private *i915 = fbc->i915; 449 450 intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start); 451 } 452 453 static const struct intel_fbc_funcs g4x_fbc_funcs = { 454 .activate = g4x_fbc_activate, 455 .deactivate = g4x_fbc_deactivate, 456 .is_active = g4x_fbc_is_active, 457 .is_compressing = g4x_fbc_is_compressing, 458 .nuke = i965_fbc_nuke, 459 .program_cfb = g4x_fbc_program_cfb, 460 }; 461 462 static void ilk_fbc_activate(struct intel_fbc *fbc) 463 { 464 struct intel_fbc_state *fbc_state = &fbc->state; 465 struct drm_i915_private *i915 = fbc->i915; 466 467 intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id), 468 fbc_state->fence_y_offset); 469 470 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), 471 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 472 } 473 474 static void ilk_fbc_deactivate(struct intel_fbc *fbc) 475 { 476 struct drm_i915_private *i915 = fbc->i915; 477 u32 dpfc_ctl; 478 479 /* Disable compression */ 480 dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id)); 481 if (dpfc_ctl & DPFC_CTL_EN) { 482 dpfc_ctl &= ~DPFC_CTL_EN; 483 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 484 } 485 } 486 487 static bool ilk_fbc_is_active(struct intel_fbc *fbc) 488 { 489 return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN; 490 } 491 492 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc) 493 { 494 return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK; 495 } 496 497 static void ilk_fbc_program_cfb(struct intel_fbc *fbc) 498 { 499 struct drm_i915_private *i915 = fbc->i915; 500 501 intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start); 502 } 503 504 static const struct intel_fbc_funcs ilk_fbc_funcs = { 505 .activate = ilk_fbc_activate, 506 .deactivate = ilk_fbc_deactivate, 507 .is_active = ilk_fbc_is_active, 508 .is_compressing = ilk_fbc_is_compressing, 509 .nuke = i965_fbc_nuke, 510 .program_cfb = ilk_fbc_program_cfb, 511 }; 512 513 static void snb_fbc_program_fence(struct intel_fbc *fbc) 514 { 515 const struct intel_fbc_state *fbc_state = &fbc->state; 516 struct drm_i915_private *i915 = fbc->i915; 517 u32 ctl = 0; 518 519 if (fbc_state->fence_id >= 0) 520 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id); 521 522 intel_de_write(i915, SNB_DPFC_CTL_SA, ctl); 523 intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset); 524 } 525 526 static void snb_fbc_activate(struct intel_fbc *fbc) 527 { 528 snb_fbc_program_fence(fbc); 529 530 ilk_fbc_activate(fbc); 531 } 532 533 static void snb_fbc_nuke(struct intel_fbc *fbc) 534 { 535 struct drm_i915_private *i915 = fbc->i915; 536 537 intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE); 538 intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id)); 539 } 540 541 static const struct intel_fbc_funcs snb_fbc_funcs = { 542 .activate = snb_fbc_activate, 543 .deactivate = ilk_fbc_deactivate, 544 .is_active = ilk_fbc_is_active, 545 .is_compressing = ilk_fbc_is_compressing, 546 .nuke = snb_fbc_nuke, 547 .program_cfb = ilk_fbc_program_cfb, 548 }; 549 550 static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) 551 { 552 const struct intel_fbc_state *fbc_state = &fbc->state; 553 struct drm_i915_private *i915 = fbc->i915; 554 u32 val = 0; 555 556 if (fbc_state->override_cfb_stride) 557 val |= FBC_STRIDE_OVERRIDE | 558 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); 559 560 intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val); 561 } 562 563 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc) 564 { 565 const struct intel_fbc_state *fbc_state = &fbc->state; 566 struct drm_i915_private *i915 = fbc->i915; 567 u32 val = 0; 568 569 /* Display WA #0529: skl, kbl, bxt. */ 570 if (fbc_state->override_cfb_stride) 571 val |= CHICKEN_FBC_STRIDE_OVERRIDE | 572 CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); 573 574 intel_de_rmw(i915, CHICKEN_MISC_4, 575 CHICKEN_FBC_STRIDE_OVERRIDE | 576 CHICKEN_FBC_STRIDE_MASK, val); 577 } 578 579 static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) 580 { 581 const struct intel_fbc_state *fbc_state = &fbc->state; 582 struct drm_i915_private *i915 = fbc->i915; 583 u32 dpfc_ctl; 584 585 dpfc_ctl = g4x_dpfc_ctl_limit(fbc); 586 587 if (IS_IVYBRIDGE(i915)) 588 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane); 589 590 if (fbc_state->fence_id >= 0) 591 dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB; 592 593 if (fbc->false_color) 594 dpfc_ctl |= DPFC_CTL_FALSE_COLOR; 595 596 return dpfc_ctl; 597 } 598 599 static void ivb_fbc_activate(struct intel_fbc *fbc) 600 { 601 struct drm_i915_private *i915 = fbc->i915; 602 603 if (DISPLAY_VER(i915) >= 10) 604 glk_fbc_program_cfb_stride(fbc); 605 else if (DISPLAY_VER(i915) == 9) 606 skl_fbc_program_cfb_stride(fbc); 607 608 if (i915->ggtt.num_fences) 609 snb_fbc_program_fence(fbc); 610 611 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), 612 DPFC_CTL_EN | ivb_dpfc_ctl(fbc)); 613 } 614 615 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc) 616 { 617 return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB; 618 } 619 620 static void ivb_fbc_set_false_color(struct intel_fbc *fbc, 621 bool enable) 622 { 623 intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id), 624 DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0); 625 } 626 627 static const struct intel_fbc_funcs ivb_fbc_funcs = { 628 .activate = ivb_fbc_activate, 629 .deactivate = ilk_fbc_deactivate, 630 .is_active = ilk_fbc_is_active, 631 .is_compressing = ivb_fbc_is_compressing, 632 .nuke = snb_fbc_nuke, 633 .program_cfb = ilk_fbc_program_cfb, 634 .set_false_color = ivb_fbc_set_false_color, 635 }; 636 637 static bool intel_fbc_hw_is_active(struct intel_fbc *fbc) 638 { 639 return fbc->funcs->is_active(fbc); 640 } 641 642 static void intel_fbc_hw_activate(struct intel_fbc *fbc) 643 { 644 trace_intel_fbc_activate(fbc->state.plane); 645 646 fbc->active = true; 647 fbc->activated = true; 648 649 fbc->funcs->activate(fbc); 650 } 651 652 static void intel_fbc_hw_deactivate(struct intel_fbc *fbc) 653 { 654 trace_intel_fbc_deactivate(fbc->state.plane); 655 656 fbc->active = false; 657 658 fbc->funcs->deactivate(fbc); 659 } 660 661 static bool intel_fbc_is_compressing(struct intel_fbc *fbc) 662 { 663 return fbc->funcs->is_compressing(fbc); 664 } 665 666 static void intel_fbc_nuke(struct intel_fbc *fbc) 667 { 668 trace_intel_fbc_nuke(fbc->state.plane); 669 670 fbc->funcs->nuke(fbc); 671 } 672 673 static void intel_fbc_activate(struct intel_fbc *fbc) 674 { 675 intel_fbc_hw_activate(fbc); 676 intel_fbc_nuke(fbc); 677 678 fbc->no_fbc_reason = NULL; 679 } 680 681 static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason) 682 { 683 struct drm_i915_private *i915 = fbc->i915; 684 685 drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); 686 687 if (fbc->active) 688 intel_fbc_hw_deactivate(fbc); 689 690 fbc->no_fbc_reason = reason; 691 } 692 693 static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915) 694 { 695 if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) 696 return BIT_ULL(28); 697 else 698 return BIT_ULL(32); 699 } 700 701 static u64 intel_fbc_stolen_end(struct drm_i915_private *i915) 702 { 703 u64 end; 704 705 /* The FBC hardware for BDW/SKL doesn't have access to the stolen 706 * reserved range size, so it always assumes the maximum (8mb) is used. 707 * If we enable FBC using a CFB on that memory range we'll get FIFO 708 * underruns, even if that range is not reserved by the BIOS. */ 709 if (IS_BROADWELL(i915) || 710 (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915))) 711 end = resource_size(&i915->dsm) - 8 * 1024 * 1024; 712 else 713 end = U64_MAX; 714 715 return min(end, intel_fbc_cfb_base_max(i915)); 716 } 717 718 static int intel_fbc_min_limit(const struct intel_plane_state *plane_state) 719 { 720 return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1; 721 } 722 723 static int intel_fbc_max_limit(struct drm_i915_private *i915) 724 { 725 /* WaFbcOnly1to1Ratio:ctg */ 726 if (IS_G4X(i915)) 727 return 1; 728 729 /* 730 * FBC2 can only do 1:1, 1:2, 1:4, we limit 731 * FBC1 to the same out of convenience. 732 */ 733 return 4; 734 } 735 736 static int find_compression_limit(struct intel_fbc *fbc, 737 unsigned int size, int min_limit) 738 { 739 struct drm_i915_private *i915 = fbc->i915; 740 u64 end = intel_fbc_stolen_end(i915); 741 int ret, limit = min_limit; 742 743 size /= limit; 744 745 /* Try to over-allocate to reduce reallocations and fragmentation. */ 746 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb, 747 size <<= 1, 4096, 0, end); 748 if (ret == 0) 749 return limit; 750 751 for (; limit <= intel_fbc_max_limit(i915); limit <<= 1) { 752 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb, 753 size >>= 1, 4096, 0, end); 754 if (ret == 0) 755 return limit; 756 } 757 758 return 0; 759 } 760 761 static int intel_fbc_alloc_cfb(struct intel_fbc *fbc, 762 unsigned int size, int min_limit) 763 { 764 struct drm_i915_private *i915 = fbc->i915; 765 int ret; 766 767 drm_WARN_ON(&i915->drm, 768 drm_mm_node_allocated(&fbc->compressed_fb)); 769 drm_WARN_ON(&i915->drm, 770 drm_mm_node_allocated(&fbc->compressed_llb)); 771 772 if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) { 773 ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb, 774 4096, 4096); 775 if (ret) 776 goto err; 777 } 778 779 ret = find_compression_limit(fbc, size, min_limit); 780 if (!ret) 781 goto err_llb; 782 else if (ret > min_limit) 783 drm_info_once(&i915->drm, 784 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); 785 786 fbc->limit = ret; 787 788 drm_dbg_kms(&i915->drm, 789 "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n", 790 fbc->compressed_fb.size, fbc->limit); 791 792 return 0; 793 794 err_llb: 795 if (drm_mm_node_allocated(&fbc->compressed_llb)) 796 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb); 797 err: 798 if (drm_mm_initialized(&i915->mm.stolen)) 799 drm_info_once(&i915->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); 800 return -ENOSPC; 801 } 802 803 static void intel_fbc_program_cfb(struct intel_fbc *fbc) 804 { 805 fbc->funcs->program_cfb(fbc); 806 } 807 808 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) 809 { 810 struct drm_i915_private *i915 = fbc->i915; 811 812 if (WARN_ON(intel_fbc_hw_is_active(fbc))) 813 return; 814 815 if (drm_mm_node_allocated(&fbc->compressed_llb)) 816 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb); 817 if (drm_mm_node_allocated(&fbc->compressed_fb)) 818 i915_gem_stolen_remove_node(i915, &fbc->compressed_fb); 819 } 820 821 void intel_fbc_cleanup(struct drm_i915_private *i915) 822 { 823 struct intel_fbc *fbc; 824 enum intel_fbc_id fbc_id; 825 826 for_each_intel_fbc(i915, fbc, fbc_id) { 827 mutex_lock(&fbc->lock); 828 __intel_fbc_cleanup_cfb(fbc); 829 mutex_unlock(&fbc->lock); 830 831 kfree(fbc); 832 } 833 } 834 835 static bool stride_is_valid(const struct intel_plane_state *plane_state) 836 { 837 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 838 const struct drm_framebuffer *fb = plane_state->hw.fb; 839 unsigned int stride = intel_fbc_plane_stride(plane_state) * 840 fb->format->cpp[0]; 841 842 /* This should have been caught earlier. */ 843 if (drm_WARN_ON_ONCE(&i915->drm, (stride & (64 - 1)) != 0)) 844 return false; 845 846 /* Below are the additional FBC restrictions. */ 847 if (stride < 512) 848 return false; 849 850 if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3) 851 return stride == 4096 || stride == 8192; 852 853 if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && stride < 2048) 854 return false; 855 856 /* Display WA #1105: skl,bxt,kbl,cfl,glk */ 857 if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) && 858 fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) 859 return false; 860 861 if (stride > 16384) 862 return false; 863 864 return true; 865 } 866 867 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) 868 { 869 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 870 const struct drm_framebuffer *fb = plane_state->hw.fb; 871 872 switch (fb->format->format) { 873 case DRM_FORMAT_XRGB8888: 874 case DRM_FORMAT_XBGR8888: 875 return true; 876 case DRM_FORMAT_XRGB1555: 877 case DRM_FORMAT_RGB565: 878 /* 16bpp not supported on gen2 */ 879 if (DISPLAY_VER(i915) == 2) 880 return false; 881 /* WaFbcOnly1to1Ratio:ctg */ 882 if (IS_G4X(i915)) 883 return false; 884 return true; 885 default: 886 return false; 887 } 888 } 889 890 static bool rotation_is_valid(const struct intel_plane_state *plane_state) 891 { 892 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 893 const struct drm_framebuffer *fb = plane_state->hw.fb; 894 unsigned int rotation = plane_state->hw.rotation; 895 896 if (DISPLAY_VER(i915) >= 9 && fb->format->format == DRM_FORMAT_RGB565 && 897 drm_rotation_90_or_270(rotation)) 898 return false; 899 else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) && 900 rotation != DRM_MODE_ROTATE_0) 901 return false; 902 903 return true; 904 } 905 906 /* 907 * For some reason, the hardware tracking starts looking at whatever we 908 * programmed as the display plane base address register. It does not look at 909 * the X and Y offset registers. That's why we include the src x/y offsets 910 * instead of just looking at the plane size. 911 */ 912 static bool intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state *plane_state) 913 { 914 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 915 unsigned int effective_w, effective_h, max_w, max_h; 916 917 if (DISPLAY_VER(i915) >= 10) { 918 max_w = 5120; 919 max_h = 4096; 920 } else if (DISPLAY_VER(i915) >= 8 || IS_HASWELL(i915)) { 921 max_w = 4096; 922 max_h = 4096; 923 } else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) { 924 max_w = 4096; 925 max_h = 2048; 926 } else { 927 max_w = 2048; 928 max_h = 1536; 929 } 930 931 effective_w = plane_state->view.color_plane[0].x + 932 (drm_rect_width(&plane_state->uapi.src) >> 16); 933 effective_h = plane_state->view.color_plane[0].y + 934 (drm_rect_height(&plane_state->uapi.src) >> 16); 935 936 return effective_w <= max_w && effective_h <= max_h; 937 } 938 939 static bool tiling_is_valid(const struct intel_plane_state *plane_state) 940 { 941 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 942 const struct drm_framebuffer *fb = plane_state->hw.fb; 943 944 switch (fb->modifier) { 945 case DRM_FORMAT_MOD_LINEAR: 946 case I915_FORMAT_MOD_Y_TILED: 947 case I915_FORMAT_MOD_Yf_TILED: 948 return DISPLAY_VER(i915) >= 9; 949 case I915_FORMAT_MOD_X_TILED: 950 return true; 951 default: 952 return false; 953 } 954 } 955 956 static void intel_fbc_update_state(struct intel_atomic_state *state, 957 struct intel_crtc *crtc, 958 struct intel_plane *plane) 959 { 960 struct drm_i915_private *i915 = to_i915(state->base.dev); 961 const struct intel_crtc_state *crtc_state = 962 intel_atomic_get_new_crtc_state(state, crtc); 963 const struct intel_plane_state *plane_state = 964 intel_atomic_get_new_plane_state(state, plane); 965 struct intel_fbc *fbc = plane->fbc; 966 struct intel_fbc_state *fbc_state = &fbc->state; 967 968 WARN_ON(plane_state->no_fbc_reason); 969 970 fbc_state->plane = plane; 971 972 /* FBC1 compression interval: arbitrary choice of 1 second */ 973 fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); 974 975 fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state); 976 977 drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE && 978 !plane_state->ggtt_vma->fence); 979 980 if (plane_state->flags & PLANE_HAS_FENCE && 981 plane_state->ggtt_vma->fence) 982 fbc_state->fence_id = plane_state->ggtt_vma->fence->id; 983 else 984 fbc_state->fence_id = -1; 985 986 fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state); 987 fbc_state->cfb_size = intel_fbc_cfb_size(plane_state); 988 fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state); 989 } 990 991 static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) 992 { 993 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 994 995 /* The use of a CPU fence is one of two ways to detect writes by the 996 * CPU to the scanout and trigger updates to the FBC. 997 * 998 * The other method is by software tracking (see 999 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke 1000 * the current compressed buffer and recompress it. 1001 * 1002 * Note that is possible for a tiled surface to be unmappable (and 1003 * so have no fence associated with it) due to aperture constraints 1004 * at the time of pinning. 1005 * 1006 * FIXME with 90/270 degree rotation we should use the fence on 1007 * the normal GTT view (the rotated view doesn't even have a 1008 * fence). Would need changes to the FBC fence Y offset as well. 1009 * For now this will effectively disable FBC with 90/270 degree 1010 * rotation. 1011 */ 1012 return DISPLAY_VER(i915) >= 9 || 1013 (plane_state->flags & PLANE_HAS_FENCE && 1014 plane_state->ggtt_vma->fence); 1015 } 1016 1017 static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state) 1018 { 1019 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1020 struct intel_fbc *fbc = plane->fbc; 1021 1022 return intel_fbc_min_limit(plane_state) <= fbc->limit && 1023 intel_fbc_cfb_size(plane_state) <= fbc->compressed_fb.size * fbc->limit; 1024 } 1025 1026 static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state) 1027 { 1028 return !plane_state->no_fbc_reason && 1029 intel_fbc_is_fence_ok(plane_state) && 1030 intel_fbc_is_cfb_ok(plane_state); 1031 } 1032 1033 static int intel_fbc_check_plane(struct intel_atomic_state *state, 1034 struct intel_plane *plane) 1035 { 1036 struct drm_i915_private *i915 = to_i915(state->base.dev); 1037 struct intel_plane_state *plane_state = 1038 intel_atomic_get_new_plane_state(state, plane); 1039 const struct drm_framebuffer *fb = plane_state->hw.fb; 1040 struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc); 1041 const struct intel_crtc_state *crtc_state; 1042 struct intel_fbc *fbc = plane->fbc; 1043 1044 if (!fbc) 1045 return 0; 1046 1047 if (intel_vgpu_active(i915)) { 1048 plane_state->no_fbc_reason = "VGPU active"; 1049 return 0; 1050 } 1051 1052 if (!i915->params.enable_fbc) { 1053 plane_state->no_fbc_reason = "disabled per module param or by default"; 1054 return 0; 1055 } 1056 1057 if (!plane_state->uapi.visible) { 1058 plane_state->no_fbc_reason = "plane not visible"; 1059 return 0; 1060 } 1061 1062 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1063 1064 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1065 plane_state->no_fbc_reason = "interlaced mode not supported"; 1066 return 0; 1067 } 1068 1069 if (crtc_state->double_wide) { 1070 plane_state->no_fbc_reason = "double wide pipe not supported"; 1071 return 0; 1072 } 1073 1074 /* 1075 * Display 12+ is not supporting FBC with PSR2. 1076 * Recommendation is to keep this combination disabled 1077 * Bspec: 50422 HSD: 14010260002 1078 */ 1079 if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) { 1080 plane_state->no_fbc_reason = "PSR2 enabled"; 1081 return false; 1082 } 1083 1084 if (!pixel_format_is_valid(plane_state)) { 1085 plane_state->no_fbc_reason = "pixel format not supported"; 1086 return 0; 1087 } 1088 1089 if (!tiling_is_valid(plane_state)) { 1090 plane_state->no_fbc_reason = "tiling not supported"; 1091 return 0; 1092 } 1093 1094 if (!rotation_is_valid(plane_state)) { 1095 plane_state->no_fbc_reason = "rotation not supported"; 1096 return 0; 1097 } 1098 1099 if (!stride_is_valid(plane_state)) { 1100 plane_state->no_fbc_reason = "stride not supported"; 1101 return 0; 1102 } 1103 1104 if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && 1105 fb->format->has_alpha) { 1106 plane_state->no_fbc_reason = "per-pixel alpha not supported"; 1107 return false; 1108 } 1109 1110 if (!intel_fbc_hw_tracking_covers_screen(plane_state)) { 1111 plane_state->no_fbc_reason = "plane size too big"; 1112 return 0; 1113 } 1114 1115 /* 1116 * Work around a problem on GEN9+ HW, where enabling FBC on a plane 1117 * having a Y offset that isn't divisible by 4 causes FIFO underrun 1118 * and screen flicker. 1119 */ 1120 if (DISPLAY_VER(i915) >= 9 && 1121 plane_state->view.color_plane[0].y & 3) { 1122 plane_state->no_fbc_reason = "plane start Y offset misaligned"; 1123 return false; 1124 } 1125 1126 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ 1127 if (DISPLAY_VER(i915) >= 11 && 1128 (plane_state->view.color_plane[0].y + drm_rect_height(&plane_state->uapi.src)) & 3) { 1129 plane_state->no_fbc_reason = "plane end Y offset misaligned"; 1130 return false; 1131 } 1132 1133 /* WaFbcExceedCdClockThreshold:hsw,bdw */ 1134 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 1135 const struct intel_cdclk_state *cdclk_state; 1136 1137 cdclk_state = intel_atomic_get_cdclk_state(state); 1138 if (IS_ERR(cdclk_state)) 1139 return PTR_ERR(cdclk_state); 1140 1141 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { 1142 plane_state->no_fbc_reason = "pixel rate too high"; 1143 return 0; 1144 } 1145 } 1146 1147 plane_state->no_fbc_reason = NULL; 1148 1149 return 0; 1150 } 1151 1152 1153 static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state, 1154 struct intel_crtc *crtc, 1155 struct intel_plane *plane) 1156 { 1157 const struct intel_crtc_state *new_crtc_state = 1158 intel_atomic_get_new_crtc_state(state, crtc); 1159 const struct intel_plane_state *old_plane_state = 1160 intel_atomic_get_old_plane_state(state, plane); 1161 const struct intel_plane_state *new_plane_state = 1162 intel_atomic_get_new_plane_state(state, plane); 1163 const struct drm_framebuffer *old_fb = old_plane_state->hw.fb; 1164 const struct drm_framebuffer *new_fb = new_plane_state->hw.fb; 1165 1166 if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) 1167 return false; 1168 1169 if (!intel_fbc_is_ok(old_plane_state) || 1170 !intel_fbc_is_ok(new_plane_state)) 1171 return false; 1172 1173 if (old_fb->format->format != new_fb->format->format) 1174 return false; 1175 1176 if (old_fb->modifier != new_fb->modifier) 1177 return false; 1178 1179 if (intel_fbc_plane_stride(old_plane_state) != 1180 intel_fbc_plane_stride(new_plane_state)) 1181 return false; 1182 1183 if (intel_fbc_cfb_stride(old_plane_state) != 1184 intel_fbc_cfb_stride(new_plane_state)) 1185 return false; 1186 1187 if (intel_fbc_cfb_size(old_plane_state) != 1188 intel_fbc_cfb_size(new_plane_state)) 1189 return false; 1190 1191 if (intel_fbc_override_cfb_stride(old_plane_state) != 1192 intel_fbc_override_cfb_stride(new_plane_state)) 1193 return false; 1194 1195 return true; 1196 } 1197 1198 static bool __intel_fbc_pre_update(struct intel_atomic_state *state, 1199 struct intel_crtc *crtc, 1200 struct intel_plane *plane) 1201 { 1202 struct drm_i915_private *i915 = to_i915(state->base.dev); 1203 struct intel_fbc *fbc = plane->fbc; 1204 bool need_vblank_wait = false; 1205 1206 fbc->flip_pending = true; 1207 1208 if (intel_fbc_can_flip_nuke(state, crtc, plane)) 1209 return need_vblank_wait; 1210 1211 intel_fbc_deactivate(fbc, "update pending"); 1212 1213 /* 1214 * Display WA #1198: glk+ 1215 * Need an extra vblank wait between FBC disable and most plane 1216 * updates. Bspec says this is only needed for plane disable, but 1217 * that is not true. Touching most plane registers will cause the 1218 * corruption to appear. Also SKL/derivatives do not seem to be 1219 * affected. 1220 * 1221 * TODO: could optimize this a bit by sampling the frame 1222 * counter when we disable FBC (if it was already done earlier) 1223 * and skipping the extra vblank wait before the plane update 1224 * if at least one frame has already passed. 1225 */ 1226 if (fbc->activated && DISPLAY_VER(i915) >= 10) 1227 need_vblank_wait = true; 1228 fbc->activated = false; 1229 1230 return need_vblank_wait; 1231 } 1232 1233 bool intel_fbc_pre_update(struct intel_atomic_state *state, 1234 struct intel_crtc *crtc) 1235 { 1236 const struct intel_plane_state *plane_state; 1237 bool need_vblank_wait = false; 1238 struct intel_plane *plane; 1239 int i; 1240 1241 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1242 struct intel_fbc *fbc = plane->fbc; 1243 1244 if (!fbc || plane->pipe != crtc->pipe) 1245 continue; 1246 1247 mutex_lock(&fbc->lock); 1248 1249 if (fbc->state.plane == plane) 1250 need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane); 1251 1252 mutex_unlock(&fbc->lock); 1253 } 1254 1255 return need_vblank_wait; 1256 } 1257 1258 static void __intel_fbc_disable(struct intel_fbc *fbc) 1259 { 1260 struct drm_i915_private *i915 = fbc->i915; 1261 struct intel_plane *plane = fbc->state.plane; 1262 1263 drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); 1264 drm_WARN_ON(&i915->drm, fbc->active); 1265 1266 drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n", 1267 plane->base.base.id, plane->base.name); 1268 1269 __intel_fbc_cleanup_cfb(fbc); 1270 1271 fbc->state.plane = NULL; 1272 } 1273 1274 static void __intel_fbc_post_update(struct intel_fbc *fbc) 1275 { 1276 struct drm_i915_private *i915 = fbc->i915; 1277 1278 drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock)); 1279 1280 if (!fbc->busy_bits) 1281 intel_fbc_activate(fbc); 1282 else 1283 intel_fbc_deactivate(fbc, "frontbuffer write"); 1284 } 1285 1286 void intel_fbc_post_update(struct intel_atomic_state *state, 1287 struct intel_crtc *crtc) 1288 { 1289 const struct intel_plane_state *plane_state; 1290 struct intel_plane *plane; 1291 int i; 1292 1293 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1294 struct intel_fbc *fbc = plane->fbc; 1295 1296 if (!fbc || plane->pipe != crtc->pipe) 1297 continue; 1298 1299 mutex_lock(&fbc->lock); 1300 1301 if (fbc->state.plane == plane) { 1302 fbc->flip_pending = false; 1303 __intel_fbc_post_update(fbc); 1304 } 1305 1306 mutex_unlock(&fbc->lock); 1307 } 1308 } 1309 1310 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) 1311 { 1312 if (fbc->state.plane) 1313 return fbc->state.plane->frontbuffer_bit; 1314 else 1315 return fbc->possible_framebuffer_bits; 1316 } 1317 1318 static void __intel_fbc_invalidate(struct intel_fbc *fbc, 1319 unsigned int frontbuffer_bits, 1320 enum fb_op_origin origin) 1321 { 1322 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE) 1323 return; 1324 1325 mutex_lock(&fbc->lock); 1326 1327 fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits; 1328 1329 if (fbc->state.plane && fbc->busy_bits) 1330 intel_fbc_deactivate(fbc, "frontbuffer write"); 1331 1332 mutex_unlock(&fbc->lock); 1333 } 1334 1335 void intel_fbc_invalidate(struct drm_i915_private *i915, 1336 unsigned int frontbuffer_bits, 1337 enum fb_op_origin origin) 1338 { 1339 struct intel_fbc *fbc; 1340 enum intel_fbc_id fbc_id; 1341 1342 for_each_intel_fbc(i915, fbc, fbc_id) 1343 __intel_fbc_invalidate(fbc, frontbuffer_bits, origin); 1344 1345 } 1346 1347 static void __intel_fbc_flush(struct intel_fbc *fbc, 1348 unsigned int frontbuffer_bits, 1349 enum fb_op_origin origin) 1350 { 1351 mutex_lock(&fbc->lock); 1352 1353 fbc->busy_bits &= ~frontbuffer_bits; 1354 1355 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE) 1356 goto out; 1357 1358 if (!fbc->busy_bits && fbc->state.plane && 1359 (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) { 1360 if (fbc->active) 1361 intel_fbc_nuke(fbc); 1362 else if (!fbc->flip_pending) 1363 __intel_fbc_post_update(fbc); 1364 } 1365 1366 out: 1367 mutex_unlock(&fbc->lock); 1368 } 1369 1370 void intel_fbc_flush(struct drm_i915_private *i915, 1371 unsigned int frontbuffer_bits, 1372 enum fb_op_origin origin) 1373 { 1374 struct intel_fbc *fbc; 1375 enum intel_fbc_id fbc_id; 1376 1377 for_each_intel_fbc(i915, fbc, fbc_id) 1378 __intel_fbc_flush(fbc, frontbuffer_bits, origin); 1379 } 1380 1381 int intel_fbc_atomic_check(struct intel_atomic_state *state) 1382 { 1383 struct intel_plane_state *plane_state; 1384 struct intel_plane *plane; 1385 int i; 1386 1387 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1388 int ret; 1389 1390 ret = intel_fbc_check_plane(state, plane); 1391 if (ret) 1392 return ret; 1393 } 1394 1395 return 0; 1396 } 1397 1398 static void __intel_fbc_enable(struct intel_atomic_state *state, 1399 struct intel_crtc *crtc, 1400 struct intel_plane *plane) 1401 { 1402 struct drm_i915_private *i915 = to_i915(state->base.dev); 1403 const struct intel_plane_state *plane_state = 1404 intel_atomic_get_new_plane_state(state, plane); 1405 struct intel_fbc *fbc = plane->fbc; 1406 1407 if (fbc->state.plane) { 1408 if (fbc->state.plane != plane) 1409 return; 1410 1411 if (intel_fbc_is_ok(plane_state)) { 1412 intel_fbc_update_state(state, crtc, plane); 1413 return; 1414 } 1415 1416 __intel_fbc_disable(fbc); 1417 } 1418 1419 drm_WARN_ON(&i915->drm, fbc->active); 1420 1421 fbc->no_fbc_reason = plane_state->no_fbc_reason; 1422 if (fbc->no_fbc_reason) 1423 return; 1424 1425 if (!intel_fbc_is_fence_ok(plane_state)) { 1426 fbc->no_fbc_reason = "framebuffer not fenced"; 1427 return; 1428 } 1429 1430 if (fbc->underrun_detected) { 1431 fbc->no_fbc_reason = "FIFO underrun"; 1432 return; 1433 } 1434 1435 if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), 1436 intel_fbc_min_limit(plane_state))) { 1437 fbc->no_fbc_reason = "not enough stolen memory"; 1438 return; 1439 } 1440 1441 drm_dbg_kms(&i915->drm, "Enabling FBC on [PLANE:%d:%s]\n", 1442 plane->base.base.id, plane->base.name); 1443 fbc->no_fbc_reason = "FBC enabled but not active yet\n"; 1444 1445 intel_fbc_update_state(state, crtc, plane); 1446 1447 intel_fbc_program_cfb(fbc); 1448 } 1449 1450 /** 1451 * intel_fbc_disable - disable FBC if it's associated with crtc 1452 * @crtc: the CRTC 1453 * 1454 * This function disables FBC if it's associated with the provided CRTC. 1455 */ 1456 void intel_fbc_disable(struct intel_crtc *crtc) 1457 { 1458 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1459 struct intel_plane *plane; 1460 1461 for_each_intel_plane(&i915->drm, plane) { 1462 struct intel_fbc *fbc = plane->fbc; 1463 1464 if (!fbc || plane->pipe != crtc->pipe) 1465 continue; 1466 1467 mutex_lock(&fbc->lock); 1468 if (fbc->state.plane == plane) 1469 __intel_fbc_disable(fbc); 1470 mutex_unlock(&fbc->lock); 1471 } 1472 } 1473 1474 void intel_fbc_update(struct intel_atomic_state *state, 1475 struct intel_crtc *crtc) 1476 { 1477 const struct intel_crtc_state *crtc_state = 1478 intel_atomic_get_new_crtc_state(state, crtc); 1479 const struct intel_plane_state *plane_state; 1480 struct intel_plane *plane; 1481 int i; 1482 1483 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1484 struct intel_fbc *fbc = plane->fbc; 1485 1486 if (!fbc || plane->pipe != crtc->pipe) 1487 continue; 1488 1489 mutex_lock(&fbc->lock); 1490 1491 if (crtc_state->update_pipe && plane_state->no_fbc_reason) { 1492 if (fbc->state.plane == plane) 1493 __intel_fbc_disable(fbc); 1494 } else { 1495 __intel_fbc_enable(state, crtc, plane); 1496 } 1497 1498 mutex_unlock(&fbc->lock); 1499 } 1500 } 1501 1502 /** 1503 * intel_fbc_global_disable - globally disable FBC 1504 * @i915: i915 device instance 1505 * 1506 * This function disables FBC regardless of which CRTC is associated with it. 1507 */ 1508 void intel_fbc_global_disable(struct drm_i915_private *i915) 1509 { 1510 struct intel_fbc *fbc; 1511 enum intel_fbc_id fbc_id; 1512 1513 for_each_intel_fbc(i915, fbc, fbc_id) { 1514 mutex_lock(&fbc->lock); 1515 if (fbc->state.plane) 1516 __intel_fbc_disable(fbc); 1517 mutex_unlock(&fbc->lock); 1518 } 1519 } 1520 1521 static void intel_fbc_underrun_work_fn(struct work_struct *work) 1522 { 1523 struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work); 1524 struct drm_i915_private *i915 = fbc->i915; 1525 1526 mutex_lock(&fbc->lock); 1527 1528 /* Maybe we were scheduled twice. */ 1529 if (fbc->underrun_detected || !fbc->state.plane) 1530 goto out; 1531 1532 drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n"); 1533 fbc->underrun_detected = true; 1534 1535 intel_fbc_deactivate(fbc, "FIFO underrun"); 1536 if (!fbc->flip_pending) 1537 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(i915, fbc->state.plane->pipe)); 1538 __intel_fbc_disable(fbc); 1539 out: 1540 mutex_unlock(&fbc->lock); 1541 } 1542 1543 static void __intel_fbc_reset_underrun(struct intel_fbc *fbc) 1544 { 1545 struct drm_i915_private *i915 = fbc->i915; 1546 1547 cancel_work_sync(&fbc->underrun_work); 1548 1549 mutex_lock(&fbc->lock); 1550 1551 if (fbc->underrun_detected) { 1552 drm_dbg_kms(&i915->drm, 1553 "Re-allowing FBC after fifo underrun\n"); 1554 fbc->no_fbc_reason = "FIFO underrun cleared"; 1555 } 1556 1557 fbc->underrun_detected = false; 1558 mutex_unlock(&fbc->lock); 1559 } 1560 1561 /* 1562 * intel_fbc_reset_underrun - reset FBC fifo underrun status. 1563 * @i915: the i915 device 1564 * 1565 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we 1566 * want to re-enable FBC after an underrun to increase test coverage. 1567 */ 1568 void intel_fbc_reset_underrun(struct drm_i915_private *i915) 1569 { 1570 struct intel_fbc *fbc; 1571 enum intel_fbc_id fbc_id; 1572 1573 for_each_intel_fbc(i915, fbc, fbc_id) 1574 __intel_fbc_reset_underrun(fbc); 1575 } 1576 1577 static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc) 1578 { 1579 /* 1580 * There's no guarantee that underrun_detected won't be set to true 1581 * right after this check and before the work is scheduled, but that's 1582 * not a problem since we'll check it again under the work function 1583 * while FBC is locked. This check here is just to prevent us from 1584 * unnecessarily scheduling the work, and it relies on the fact that we 1585 * never switch underrun_detect back to false after it's true. 1586 */ 1587 if (READ_ONCE(fbc->underrun_detected)) 1588 return; 1589 1590 schedule_work(&fbc->underrun_work); 1591 } 1592 1593 /** 1594 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun 1595 * @i915: i915 device 1596 * 1597 * Without FBC, most underruns are harmless and don't really cause too many 1598 * problems, except for an annoying message on dmesg. With FBC, underruns can 1599 * become black screens or even worse, especially when paired with bad 1600 * watermarks. So in order for us to be on the safe side, completely disable FBC 1601 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe 1602 * already suggests that watermarks may be bad, so try to be as safe as 1603 * possible. 1604 * 1605 * This function is called from the IRQ handler. 1606 */ 1607 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915) 1608 { 1609 struct intel_fbc *fbc; 1610 enum intel_fbc_id fbc_id; 1611 1612 for_each_intel_fbc(i915, fbc, fbc_id) 1613 __intel_fbc_handle_fifo_underrun_irq(fbc); 1614 } 1615 1616 /* 1617 * The DDX driver changes its behavior depending on the value it reads from 1618 * i915.enable_fbc, so sanitize it by translating the default value into either 1619 * 0 or 1 in order to allow it to know what's going on. 1620 * 1621 * Notice that this is done at driver initialization and we still allow user 1622 * space to change the value during runtime without sanitizing it again. IGT 1623 * relies on being able to change i915.enable_fbc at runtime. 1624 */ 1625 static int intel_sanitize_fbc_option(struct drm_i915_private *i915) 1626 { 1627 if (i915->params.enable_fbc >= 0) 1628 return !!i915->params.enable_fbc; 1629 1630 if (!HAS_FBC(i915)) 1631 return 0; 1632 1633 if (IS_BROADWELL(i915) || DISPLAY_VER(i915) >= 9) 1634 return 1; 1635 1636 return 0; 1637 } 1638 1639 static bool need_fbc_vtd_wa(struct drm_i915_private *i915) 1640 { 1641 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ 1642 if (intel_vtd_active(i915) && 1643 (IS_SKYLAKE(i915) || IS_BROXTON(i915))) { 1644 drm_info(&i915->drm, 1645 "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n"); 1646 return true; 1647 } 1648 1649 return false; 1650 } 1651 1652 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane) 1653 { 1654 if (!fbc) 1655 return; 1656 1657 plane->fbc = fbc; 1658 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; 1659 } 1660 1661 static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915, 1662 enum intel_fbc_id fbc_id) 1663 { 1664 struct intel_fbc *fbc; 1665 1666 fbc = kzalloc(sizeof(*fbc), GFP_KERNEL); 1667 if (!fbc) 1668 return NULL; 1669 1670 fbc->id = fbc_id; 1671 fbc->i915 = i915; 1672 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); 1673 mutex_init(&fbc->lock); 1674 1675 if (DISPLAY_VER(i915) >= 7) 1676 fbc->funcs = &ivb_fbc_funcs; 1677 else if (DISPLAY_VER(i915) == 6) 1678 fbc->funcs = &snb_fbc_funcs; 1679 else if (DISPLAY_VER(i915) == 5) 1680 fbc->funcs = &ilk_fbc_funcs; 1681 else if (IS_G4X(i915)) 1682 fbc->funcs = &g4x_fbc_funcs; 1683 else if (DISPLAY_VER(i915) == 4) 1684 fbc->funcs = &i965_fbc_funcs; 1685 else 1686 fbc->funcs = &i8xx_fbc_funcs; 1687 1688 return fbc; 1689 } 1690 1691 /** 1692 * intel_fbc_init - Initialize FBC 1693 * @i915: the i915 device 1694 * 1695 * This function might be called during PM init process. 1696 */ 1697 void intel_fbc_init(struct drm_i915_private *i915) 1698 { 1699 enum intel_fbc_id fbc_id; 1700 1701 if (!drm_mm_initialized(&i915->mm.stolen)) 1702 mkwrite_device_info(i915)->display.fbc_mask = 0; 1703 1704 if (need_fbc_vtd_wa(i915)) 1705 mkwrite_device_info(i915)->display.fbc_mask = 0; 1706 1707 i915->params.enable_fbc = intel_sanitize_fbc_option(i915); 1708 drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n", 1709 i915->params.enable_fbc); 1710 1711 for_each_fbc_id(i915, fbc_id) { 1712 struct intel_fbc *fbc; 1713 1714 fbc = intel_fbc_create(i915, fbc_id); 1715 if (!fbc) 1716 continue; 1717 1718 /* 1719 * We still don't have any sort of hardware state readout 1720 * for FBC, so deactivate it in case the BIOS activated it 1721 * to make sure software matches the hardware state. 1722 */ 1723 if (intel_fbc_hw_is_active(fbc)) 1724 intel_fbc_hw_deactivate(fbc); 1725 1726 i915->fbc[fbc->id] = fbc; 1727 } 1728 } 1729 1730 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused) 1731 { 1732 struct intel_fbc *fbc = m->private; 1733 struct drm_i915_private *i915 = fbc->i915; 1734 struct intel_plane *plane; 1735 intel_wakeref_t wakeref; 1736 1737 drm_modeset_lock_all(&i915->drm); 1738 1739 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1740 mutex_lock(&fbc->lock); 1741 1742 if (fbc->active) { 1743 seq_puts(m, "FBC enabled\n"); 1744 seq_printf(m, "Compressing: %s\n", 1745 yesno(intel_fbc_is_compressing(fbc))); 1746 } else { 1747 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); 1748 } 1749 1750 for_each_intel_plane(&i915->drm, plane) { 1751 const struct intel_plane_state *plane_state = 1752 to_intel_plane_state(plane->base.state); 1753 1754 if (plane->fbc != fbc) 1755 continue; 1756 1757 seq_printf(m, "%c [PLANE:%d:%s]: %s\n", 1758 fbc->state.plane == plane ? '*' : ' ', 1759 plane->base.base.id, plane->base.name, 1760 plane_state->no_fbc_reason ?: "FBC possible"); 1761 } 1762 1763 mutex_unlock(&fbc->lock); 1764 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1765 1766 drm_modeset_unlock_all(&i915->drm); 1767 1768 return 0; 1769 } 1770 1771 DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status); 1772 1773 static int intel_fbc_debugfs_false_color_get(void *data, u64 *val) 1774 { 1775 struct intel_fbc *fbc = data; 1776 1777 *val = fbc->false_color; 1778 1779 return 0; 1780 } 1781 1782 static int intel_fbc_debugfs_false_color_set(void *data, u64 val) 1783 { 1784 struct intel_fbc *fbc = data; 1785 1786 mutex_lock(&fbc->lock); 1787 1788 fbc->false_color = val; 1789 1790 if (fbc->active) 1791 fbc->funcs->set_false_color(fbc, fbc->false_color); 1792 1793 mutex_unlock(&fbc->lock); 1794 1795 return 0; 1796 } 1797 1798 DEFINE_SIMPLE_ATTRIBUTE(intel_fbc_debugfs_false_color_fops, 1799 intel_fbc_debugfs_false_color_get, 1800 intel_fbc_debugfs_false_color_set, 1801 "%llu\n"); 1802 1803 static void intel_fbc_debugfs_add(struct intel_fbc *fbc, 1804 struct dentry *parent) 1805 { 1806 debugfs_create_file("i915_fbc_status", 0444, parent, 1807 fbc, &intel_fbc_debugfs_status_fops); 1808 1809 if (fbc->funcs->set_false_color) 1810 debugfs_create_file("i915_fbc_false_color", 0644, parent, 1811 fbc, &intel_fbc_debugfs_false_color_fops); 1812 } 1813 1814 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc) 1815 { 1816 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1817 1818 if (plane->fbc) 1819 intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry); 1820 } 1821 1822 /* FIXME: remove this once igt is on board with per-crtc stuff */ 1823 void intel_fbc_debugfs_register(struct drm_i915_private *i915) 1824 { 1825 struct drm_minor *minor = i915->drm.primary; 1826 struct intel_fbc *fbc; 1827 1828 fbc = i915->fbc[INTEL_FBC_A]; 1829 if (fbc) 1830 intel_fbc_debugfs_add(fbc, minor->debugfs_root); 1831 } 1832