1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 /** 7 * DOC: display pinning helpers 8 */ 9 10 #include "intel_display_types.h" 11 #include "intel_fb_pin.h" 12 #include "intel_fb.h" 13 14 #include "intel_dpt.h" 15 16 #include "gem/i915_gem_object.h" 17 18 static struct i915_vma * 19 intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, 20 const struct i915_ggtt_view *view, 21 bool uses_fence, 22 unsigned long *out_flags, 23 struct i915_address_space *vm) 24 { 25 struct drm_device *dev = fb->dev; 26 struct drm_i915_private *dev_priv = to_i915(dev); 27 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 28 struct i915_vma *vma; 29 u32 alignment; 30 int ret; 31 32 if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) 33 return ERR_PTR(-EINVAL); 34 35 alignment = 4096 * 512; 36 37 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 38 39 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); 40 if (ret) { 41 vma = ERR_PTR(ret); 42 goto err; 43 } 44 45 vma = i915_vma_instance(obj, vm, view); 46 if (IS_ERR(vma)) 47 goto err; 48 49 if (i915_vma_misplaced(vma, 0, alignment, 0)) { 50 ret = i915_vma_unbind(vma); 51 if (ret) { 52 vma = ERR_PTR(ret); 53 goto err; 54 } 55 } 56 57 ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL); 58 if (ret) { 59 vma = ERR_PTR(ret); 60 goto err; 61 } 62 63 vma->display_alignment = max_t(u64, vma->display_alignment, alignment); 64 65 i915_gem_object_flush_if_display(obj); 66 67 i915_vma_get(vma); 68 err: 69 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 70 71 return vma; 72 } 73 74 struct i915_vma * 75 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 76 bool phys_cursor, 77 const struct i915_ggtt_view *view, 78 bool uses_fence, 79 unsigned long *out_flags) 80 { 81 struct drm_device *dev = fb->dev; 82 struct drm_i915_private *dev_priv = to_i915(dev); 83 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 84 intel_wakeref_t wakeref; 85 struct i915_gem_ww_ctx ww; 86 struct i915_vma *vma; 87 unsigned int pinctl; 88 u32 alignment; 89 int ret; 90 91 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) 92 return ERR_PTR(-EINVAL); 93 94 if (phys_cursor) 95 alignment = intel_cursor_alignment(dev_priv); 96 else 97 alignment = intel_surf_alignment(fb, 0); 98 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) 99 return ERR_PTR(-EINVAL); 100 101 /* Note that the w/a also requires 64 PTE of padding following the 102 * bo. We currently fill all unused PTE with the shadow page and so 103 * we should always have valid PTE following the scanout preventing 104 * the VT-d warning. 105 */ 106 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) 107 alignment = 256 * 1024; 108 109 /* 110 * Global gtt pte registers are special registers which actually forward 111 * writes to a chunk of system memory. Which means that there is no risk 112 * that the register values disappear as soon as we call 113 * intel_runtime_pm_put(), so it is correct to wrap only the 114 * pin/unpin/fence and not more. 115 */ 116 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 117 118 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 119 120 /* 121 * Valleyview is definitely limited to scanning out the first 122 * 512MiB. Lets presume this behaviour was inherited from the 123 * g4x display engine and that all earlier gen are similarly 124 * limited. Testing suggests that it is a little more 125 * complicated than this. For example, Cherryview appears quite 126 * happy to scanout from anywhere within its global aperture. 127 */ 128 pinctl = 0; 129 if (HAS_GMCH(dev_priv)) 130 pinctl |= PIN_MAPPABLE; 131 132 i915_gem_ww_ctx_init(&ww, true); 133 retry: 134 ret = i915_gem_object_lock(obj, &ww); 135 if (!ret && phys_cursor) 136 ret = i915_gem_object_attach_phys(obj, alignment); 137 else if (!ret && HAS_LMEM(dev_priv)) 138 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM); 139 /* TODO: Do we need to sync when migration becomes async? */ 140 if (!ret) 141 ret = i915_gem_object_pin_pages(obj); 142 if (ret) 143 goto err; 144 145 if (!ret) { 146 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment, 147 view, pinctl); 148 if (IS_ERR(vma)) { 149 ret = PTR_ERR(vma); 150 goto err_unpin; 151 } 152 } 153 154 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) { 155 /* 156 * Install a fence for tiled scan-out. Pre-i965 always needs a 157 * fence, whereas 965+ only requires a fence if using 158 * framebuffer compression. For simplicity, we always, when 159 * possible, install a fence as the cost is not that onerous. 160 * 161 * If we fail to fence the tiled scanout, then either the 162 * modeset will reject the change (which is highly unlikely as 163 * the affected systems, all but one, do not have unmappable 164 * space) or we will not be able to enable full powersaving 165 * techniques (also likely not to apply due to various limits 166 * FBC and the like impose on the size of the buffer, which 167 * presumably we violated anyway with this unmappable buffer). 168 * Anyway, it is presumably better to stumble onwards with 169 * something and try to run the system in a "less than optimal" 170 * mode that matches the user configuration. 171 */ 172 ret = i915_vma_pin_fence(vma); 173 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) { 174 i915_vma_unpin(vma); 175 goto err_unpin; 176 } 177 ret = 0; 178 179 if (vma->fence) 180 *out_flags |= PLANE_HAS_FENCE; 181 } 182 183 i915_vma_get(vma); 184 185 err_unpin: 186 i915_gem_object_unpin_pages(obj); 187 err: 188 if (ret == -EDEADLK) { 189 ret = i915_gem_ww_ctx_backoff(&ww); 190 if (!ret) 191 goto retry; 192 } 193 i915_gem_ww_ctx_fini(&ww); 194 if (ret) 195 vma = ERR_PTR(ret); 196 197 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 198 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 199 return vma; 200 } 201 202 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) 203 { 204 if (flags & PLANE_HAS_FENCE) 205 i915_vma_unpin_fence(vma); 206 i915_vma_unpin(vma); 207 i915_vma_put(vma); 208 } 209 210 int intel_plane_pin_fb(struct intel_plane_state *plane_state) 211 { 212 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 213 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 214 struct drm_framebuffer *fb = plane_state->hw.fb; 215 struct i915_vma *vma; 216 bool phys_cursor = 217 plane->id == PLANE_CURSOR && 218 INTEL_INFO(dev_priv)->display.cursor_needs_physical; 219 220 if (!intel_fb_uses_dpt(fb)) { 221 vma = intel_pin_and_fence_fb_obj(fb, phys_cursor, 222 &plane_state->view.gtt, 223 intel_plane_uses_fence(plane_state), 224 &plane_state->flags); 225 if (IS_ERR(vma)) 226 return PTR_ERR(vma); 227 228 plane_state->ggtt_vma = vma; 229 } else { 230 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 231 232 vma = intel_dpt_pin(intel_fb->dpt_vm); 233 if (IS_ERR(vma)) 234 return PTR_ERR(vma); 235 236 plane_state->ggtt_vma = vma; 237 238 vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false, 239 &plane_state->flags, intel_fb->dpt_vm); 240 if (IS_ERR(vma)) { 241 intel_dpt_unpin(intel_fb->dpt_vm); 242 plane_state->ggtt_vma = NULL; 243 return PTR_ERR(vma); 244 } 245 246 plane_state->dpt_vma = vma; 247 248 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); 249 } 250 251 return 0; 252 } 253 254 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) 255 { 256 struct drm_framebuffer *fb = old_plane_state->hw.fb; 257 struct i915_vma *vma; 258 259 if (!intel_fb_uses_dpt(fb)) { 260 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 261 if (vma) 262 intel_unpin_fb_vma(vma, old_plane_state->flags); 263 } else { 264 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 265 266 vma = fetch_and_zero(&old_plane_state->dpt_vma); 267 if (vma) 268 intel_unpin_fb_vma(vma, old_plane_state->flags); 269 270 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 271 if (vma) 272 intel_dpt_unpin(intel_fb->dpt_vm); 273 } 274 } 275