1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2021 Intel Corporation
4  */
5 
6 /**
7  * DOC: display pinning helpers
8  */
9 
10 #include "gem/i915_gem_domain.h"
11 #include "gem/i915_gem_object.h"
12 
13 #include "i915_drv.h"
14 #include "intel_display_types.h"
15 #include "intel_dpt.h"
16 #include "intel_fb.h"
17 #include "intel_fb_pin.h"
18 
19 static struct i915_vma *
20 intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
21 		     const struct i915_gtt_view *view,
22 		     bool uses_fence,
23 		     unsigned long *out_flags,
24 		     struct i915_address_space *vm)
25 {
26 	struct drm_device *dev = fb->dev;
27 	struct drm_i915_private *dev_priv = to_i915(dev);
28 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
29 	struct i915_gem_ww_ctx ww;
30 	struct i915_vma *vma;
31 	u32 alignment;
32 	int ret;
33 
34 	/*
35 	 * We are not syncing against the binding (and potential migrations)
36 	 * below, so this vm must never be async.
37 	 */
38 	GEM_WARN_ON(vm->bind_async_flags);
39 
40 	if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
41 		return ERR_PTR(-EINVAL);
42 
43 	alignment = 4096 * 512;
44 
45 	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
46 
47 	for_i915_gem_ww(&ww, ret, true) {
48 		ret = i915_gem_object_lock(obj, &ww);
49 		if (ret)
50 			continue;
51 
52 		if (HAS_LMEM(dev_priv)) {
53 			unsigned int flags = obj->flags;
54 
55 			/*
56 			 * For this type of buffer we need to able to read from the CPU
57 			 * the clear color value found in the buffer, hence we need to
58 			 * ensure it is always in the mappable part of lmem, if this is
59 			 * a small-bar device.
60 			 */
61 			if (intel_fb_rc_ccs_cc_plane(fb) >= 0)
62 				flags &= ~I915_BO_ALLOC_GPU_ONLY;
63 			ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0,
64 							flags);
65 			if (ret)
66 				continue;
67 		}
68 
69 		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
70 		if (ret)
71 			continue;
72 
73 		vma = i915_vma_instance(obj, vm, view);
74 		if (IS_ERR(vma)) {
75 			ret = PTR_ERR(vma);
76 			continue;
77 		}
78 
79 		if (i915_vma_misplaced(vma, 0, alignment, 0)) {
80 			ret = i915_vma_unbind(vma);
81 			if (ret)
82 				continue;
83 		}
84 
85 		ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL);
86 		if (ret)
87 			continue;
88 	}
89 	if (ret) {
90 		vma = ERR_PTR(ret);
91 		goto err;
92 	}
93 
94 	vma->display_alignment = max(vma->display_alignment, alignment);
95 
96 	i915_gem_object_flush_if_display(obj);
97 
98 	i915_vma_get(vma);
99 err:
100 	atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
101 
102 	return vma;
103 }
104 
105 struct i915_vma *
106 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
107 			   bool phys_cursor,
108 			   const struct i915_gtt_view *view,
109 			   bool uses_fence,
110 			   unsigned long *out_flags)
111 {
112 	struct drm_device *dev = fb->dev;
113 	struct drm_i915_private *dev_priv = to_i915(dev);
114 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
115 	intel_wakeref_t wakeref;
116 	struct i915_gem_ww_ctx ww;
117 	struct i915_vma *vma;
118 	unsigned int pinctl;
119 	u32 alignment;
120 	int ret;
121 
122 	if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
123 		return ERR_PTR(-EINVAL);
124 
125 	if (phys_cursor)
126 		alignment = intel_cursor_alignment(dev_priv);
127 	else
128 		alignment = intel_surf_alignment(fb, 0);
129 	if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
130 		return ERR_PTR(-EINVAL);
131 
132 	/* Note that the w/a also requires 64 PTE of padding following the
133 	 * bo. We currently fill all unused PTE with the shadow page and so
134 	 * we should always have valid PTE following the scanout preventing
135 	 * the VT-d warning.
136 	 */
137 	if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
138 		alignment = 256 * 1024;
139 
140 	/*
141 	 * Global gtt pte registers are special registers which actually forward
142 	 * writes to a chunk of system memory. Which means that there is no risk
143 	 * that the register values disappear as soon as we call
144 	 * intel_runtime_pm_put(), so it is correct to wrap only the
145 	 * pin/unpin/fence and not more.
146 	 */
147 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
148 
149 	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
150 
151 	/*
152 	 * Valleyview is definitely limited to scanning out the first
153 	 * 512MiB. Lets presume this behaviour was inherited from the
154 	 * g4x display engine and that all earlier gen are similarly
155 	 * limited. Testing suggests that it is a little more
156 	 * complicated than this. For example, Cherryview appears quite
157 	 * happy to scanout from anywhere within its global aperture.
158 	 */
159 	pinctl = 0;
160 	if (HAS_GMCH(dev_priv))
161 		pinctl |= PIN_MAPPABLE;
162 
163 	i915_gem_ww_ctx_init(&ww, true);
164 retry:
165 	ret = i915_gem_object_lock(obj, &ww);
166 	if (!ret && phys_cursor)
167 		ret = i915_gem_object_attach_phys(obj, alignment);
168 	else if (!ret && HAS_LMEM(dev_priv))
169 		ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0);
170 	if (!ret)
171 		ret = i915_gem_object_pin_pages(obj);
172 	if (ret)
173 		goto err;
174 
175 	vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
176 						   view, pinctl);
177 	if (IS_ERR(vma)) {
178 		ret = PTR_ERR(vma);
179 		goto err_unpin;
180 	}
181 
182 	if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
183 		/*
184 		 * Install a fence for tiled scan-out. Pre-i965 always needs a
185 		 * fence, whereas 965+ only requires a fence if using
186 		 * framebuffer compression.  For simplicity, we always, when
187 		 * possible, install a fence as the cost is not that onerous.
188 		 *
189 		 * If we fail to fence the tiled scanout, then either the
190 		 * modeset will reject the change (which is highly unlikely as
191 		 * the affected systems, all but one, do not have unmappable
192 		 * space) or we will not be able to enable full powersaving
193 		 * techniques (also likely not to apply due to various limits
194 		 * FBC and the like impose on the size of the buffer, which
195 		 * presumably we violated anyway with this unmappable buffer).
196 		 * Anyway, it is presumably better to stumble onwards with
197 		 * something and try to run the system in a "less than optimal"
198 		 * mode that matches the user configuration.
199 		 */
200 		ret = i915_vma_pin_fence(vma);
201 		if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
202 			i915_vma_unpin(vma);
203 			goto err_unpin;
204 		}
205 		ret = 0;
206 
207 		if (vma->fence)
208 			*out_flags |= PLANE_HAS_FENCE;
209 	}
210 
211 	i915_vma_get(vma);
212 
213 err_unpin:
214 	i915_gem_object_unpin_pages(obj);
215 err:
216 	if (ret == -EDEADLK) {
217 		ret = i915_gem_ww_ctx_backoff(&ww);
218 		if (!ret)
219 			goto retry;
220 	}
221 	i915_gem_ww_ctx_fini(&ww);
222 	if (ret)
223 		vma = ERR_PTR(ret);
224 
225 	atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
226 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
227 	return vma;
228 }
229 
230 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
231 {
232 	if (flags & PLANE_HAS_FENCE)
233 		i915_vma_unpin_fence(vma);
234 	i915_vma_unpin(vma);
235 	i915_vma_put(vma);
236 }
237 
238 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
239 {
240 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
241 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
242 	struct drm_framebuffer *fb = plane_state->hw.fb;
243 	struct i915_vma *vma;
244 	bool phys_cursor =
245 		plane->id == PLANE_CURSOR &&
246 		INTEL_INFO(dev_priv)->display.cursor_needs_physical;
247 
248 	if (!intel_fb_uses_dpt(fb)) {
249 		vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
250 						 &plane_state->view.gtt,
251 						 intel_plane_uses_fence(plane_state),
252 						 &plane_state->flags);
253 		if (IS_ERR(vma))
254 			return PTR_ERR(vma);
255 
256 		plane_state->ggtt_vma = vma;
257 	} else {
258 		struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
259 
260 		vma = intel_dpt_pin(intel_fb->dpt_vm);
261 		if (IS_ERR(vma))
262 			return PTR_ERR(vma);
263 
264 		plane_state->ggtt_vma = vma;
265 
266 		vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
267 					   &plane_state->flags, intel_fb->dpt_vm);
268 		if (IS_ERR(vma)) {
269 			intel_dpt_unpin(intel_fb->dpt_vm);
270 			plane_state->ggtt_vma = NULL;
271 			return PTR_ERR(vma);
272 		}
273 
274 		plane_state->dpt_vma = vma;
275 
276 		WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
277 	}
278 
279 	return 0;
280 }
281 
282 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
283 {
284 	struct drm_framebuffer *fb = old_plane_state->hw.fb;
285 	struct i915_vma *vma;
286 
287 	if (!intel_fb_uses_dpt(fb)) {
288 		vma = fetch_and_zero(&old_plane_state->ggtt_vma);
289 		if (vma)
290 			intel_unpin_fb_vma(vma, old_plane_state->flags);
291 	} else {
292 		struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
293 
294 		vma = fetch_and_zero(&old_plane_state->dpt_vma);
295 		if (vma)
296 			intel_unpin_fb_vma(vma, old_plane_state->flags);
297 
298 		vma = fetch_and_zero(&old_plane_state->ggtt_vma);
299 		if (vma)
300 			intel_dpt_unpin(intel_fb->dpt_vm);
301 	}
302 }
303