1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2021 Intel Corporation
4  */
5 
6 #include <drm/drm_blend.h>
7 #include <drm/drm_framebuffer.h>
8 #include <drm/drm_modeset_helper.h>
9 
10 #include "i915_drv.h"
11 #include "intel_display.h"
12 #include "intel_display_types.h"
13 #include "intel_dpt.h"
14 #include "intel_fb.h"
15 
16 #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
17 
18 /*
19  * From the Sky Lake PRM:
20  * "The Color Control Surface (CCS) contains the compression status of
21  *  the cache-line pairs. The compression state of the cache-line pair
22  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
23  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
24  *  cache-line-pairs. CCS is always Y tiled."
25  *
26  * Since cache line pairs refers to horizontally adjacent cache lines,
27  * each cache line in the CCS corresponds to an area of 32x16 cache
28  * lines on the main surface. Since each pixel is 4 bytes, this gives
29  * us a ratio of one byte in the CCS for each 8x16 pixels in the
30  * main surface.
31  */
32 static const struct drm_format_info skl_ccs_formats[] = {
33 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
34 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
35 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
36 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
37 	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
38 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
39 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
40 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
41 };
42 
43 /*
44  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
45  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
46  * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
47  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
48  * the main surface.
49  */
50 static const struct drm_format_info gen12_ccs_formats[] = {
51 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
52 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
53 	  .hsub = 1, .vsub = 1, },
54 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
55 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
56 	  .hsub = 1, .vsub = 1, },
57 	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
58 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
59 	  .hsub = 1, .vsub = 1, .has_alpha = true },
60 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
61 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
62 	  .hsub = 1, .vsub = 1, .has_alpha = true },
63 	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
64 	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
65 	  .hsub = 2, .vsub = 1, .is_yuv = true },
66 	{ .format = DRM_FORMAT_YVYU, .num_planes = 2,
67 	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
68 	  .hsub = 2, .vsub = 1, .is_yuv = true },
69 	{ .format = DRM_FORMAT_UYVY, .num_planes = 2,
70 	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
71 	  .hsub = 2, .vsub = 1, .is_yuv = true },
72 	{ .format = DRM_FORMAT_VYUY, .num_planes = 2,
73 	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
74 	  .hsub = 2, .vsub = 1, .is_yuv = true },
75 	{ .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
76 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
77 	  .hsub = 1, .vsub = 1, .is_yuv = true },
78 	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
79 	  .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
80 	  .hsub = 2, .vsub = 2, .is_yuv = true },
81 	{ .format = DRM_FORMAT_P010, .num_planes = 4,
82 	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
83 	  .hsub = 2, .vsub = 2, .is_yuv = true },
84 	{ .format = DRM_FORMAT_P012, .num_planes = 4,
85 	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
86 	  .hsub = 2, .vsub = 2, .is_yuv = true },
87 	{ .format = DRM_FORMAT_P016, .num_planes = 4,
88 	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
89 	  .hsub = 2, .vsub = 2, .is_yuv = true },
90 };
91 
92 /*
93  * Same as gen12_ccs_formats[] above, but with additional surface used
94  * to pass Clear Color information in plane 2 with 64 bits of data.
95  */
96 static const struct drm_format_info gen12_ccs_cc_formats[] = {
97 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
98 	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
99 	  .hsub = 1, .vsub = 1, },
100 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
101 	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
102 	  .hsub = 1, .vsub = 1, },
103 	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
104 	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
105 	  .hsub = 1, .vsub = 1, .has_alpha = true },
106 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
107 	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
108 	  .hsub = 1, .vsub = 1, .has_alpha = true },
109 };
110 
111 static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
112 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
113 	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
114 	  .hsub = 1, .vsub = 1, },
115 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
116 	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
117 	  .hsub = 1, .vsub = 1, },
118 	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
119 	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
120 	  .hsub = 1, .vsub = 1, .has_alpha = true },
121 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
122 	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
123 	  .hsub = 1, .vsub = 1, .has_alpha = true },
124 };
125 
126 struct intel_modifier_desc {
127 	u64 modifier;
128 	struct {
129 		u8 from;
130 		u8 until;
131 	} display_ver;
132 #define DISPLAY_VER_ALL		{ 0, -1 }
133 
134 	const struct drm_format_info *formats;
135 	int format_count;
136 #define FORMAT_OVERRIDE(format_list) \
137 	.formats = format_list, \
138 	.format_count = ARRAY_SIZE(format_list)
139 
140 	u8 plane_caps;
141 
142 	struct {
143 		u8 cc_planes:3;
144 		u8 packed_aux_planes:4;
145 		u8 planar_aux_planes:4;
146 	} ccs;
147 };
148 
149 #define INTEL_PLANE_CAP_CCS_MASK	(INTEL_PLANE_CAP_CCS_RC | \
150 					 INTEL_PLANE_CAP_CCS_RC_CC | \
151 					 INTEL_PLANE_CAP_CCS_MC)
152 #define INTEL_PLANE_CAP_TILING_MASK	(INTEL_PLANE_CAP_TILING_X | \
153 					 INTEL_PLANE_CAP_TILING_Y | \
154 					 INTEL_PLANE_CAP_TILING_Yf | \
155 					 INTEL_PLANE_CAP_TILING_4)
156 #define INTEL_PLANE_CAP_TILING_NONE	0
157 
158 static const struct intel_modifier_desc intel_modifiers[] = {
159 	{
160 		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
161 		.display_ver = { 13, 13 },
162 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
163 	}, {
164 		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
165 		.display_ver = { 13, 13 },
166 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
167 
168 		.ccs.cc_planes = BIT(1),
169 
170 		FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
171 	}, {
172 		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
173 		.display_ver = { 13, 13 },
174 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
175 	}, {
176 		.modifier = I915_FORMAT_MOD_4_TILED,
177 		.display_ver = { 13, -1 },
178 		.plane_caps = INTEL_PLANE_CAP_TILING_4,
179 	}, {
180 		.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
181 		.display_ver = { 12, 13 },
182 		.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
183 
184 		.ccs.packed_aux_planes = BIT(1),
185 		.ccs.planar_aux_planes = BIT(2) | BIT(3),
186 
187 		FORMAT_OVERRIDE(gen12_ccs_formats),
188 	}, {
189 		.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
190 		.display_ver = { 12, 13 },
191 		.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,
192 
193 		.ccs.packed_aux_planes = BIT(1),
194 
195 		FORMAT_OVERRIDE(gen12_ccs_formats),
196 	}, {
197 		.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
198 		.display_ver = { 12, 13 },
199 		.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC_CC,
200 
201 		.ccs.cc_planes = BIT(2),
202 		.ccs.packed_aux_planes = BIT(1),
203 
204 		FORMAT_OVERRIDE(gen12_ccs_cc_formats),
205 	}, {
206 		.modifier = I915_FORMAT_MOD_Yf_TILED_CCS,
207 		.display_ver = { 9, 11 },
208 		.plane_caps = INTEL_PLANE_CAP_TILING_Yf | INTEL_PLANE_CAP_CCS_RC,
209 
210 		.ccs.packed_aux_planes = BIT(1),
211 
212 		FORMAT_OVERRIDE(skl_ccs_formats),
213 	}, {
214 		.modifier = I915_FORMAT_MOD_Y_TILED_CCS,
215 		.display_ver = { 9, 11 },
216 		.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,
217 
218 		.ccs.packed_aux_planes = BIT(1),
219 
220 		FORMAT_OVERRIDE(skl_ccs_formats),
221 	}, {
222 		.modifier = I915_FORMAT_MOD_Yf_TILED,
223 		.display_ver = { 9, 11 },
224 		.plane_caps = INTEL_PLANE_CAP_TILING_Yf,
225 	}, {
226 		.modifier = I915_FORMAT_MOD_Y_TILED,
227 		.display_ver = { 9, 13 },
228 		.plane_caps = INTEL_PLANE_CAP_TILING_Y,
229 	}, {
230 		.modifier = I915_FORMAT_MOD_X_TILED,
231 		.display_ver = DISPLAY_VER_ALL,
232 		.plane_caps = INTEL_PLANE_CAP_TILING_X,
233 	}, {
234 		.modifier = DRM_FORMAT_MOD_LINEAR,
235 		.display_ver = DISPLAY_VER_ALL,
236 	},
237 };
238 
239 static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier)
240 {
241 	int i;
242 
243 	for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++)
244 		if (intel_modifiers[i].modifier == modifier)
245 			return &intel_modifiers[i];
246 
247 	return NULL;
248 }
249 
250 static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
251 {
252 	const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
253 
254 	if (WARN_ON(!md))
255 		return &intel_modifiers[0];
256 
257 	return md;
258 }
259 
260 static const struct drm_format_info *
261 lookup_format_info(const struct drm_format_info formats[],
262 		   int num_formats, u32 format)
263 {
264 	int i;
265 
266 	for (i = 0; i < num_formats; i++) {
267 		if (formats[i].format == format)
268 			return &formats[i];
269 	}
270 
271 	return NULL;
272 }
273 
274 /**
275  * intel_fb_get_format_info: Get a modifier specific format information
276  * @cmd: FB add command structure
277  *
278  * Returns:
279  * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0],
280  * or %NULL if the modifier doesn't override the format.
281  */
282 const struct drm_format_info *
283 intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
284 {
285 	const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]);
286 
287 	if (!md || !md->formats)
288 		return NULL;
289 
290 	return lookup_format_info(md->formats, md->format_count, cmd->pixel_format);
291 }
292 
293 static bool plane_caps_contain_any(u8 caps, u8 mask)
294 {
295 	return caps & mask;
296 }
297 
298 static bool plane_caps_contain_all(u8 caps, u8 mask)
299 {
300 	return (caps & mask) == mask;
301 }
302 
303 /**
304  * intel_fb_is_tiled_modifier: Check if a modifier is a tiled modifier type
305  * @modifier: Modifier to check
306  *
307  * Returns:
308  * Returns %true if @modifier is a tiled modifier.
309  */
310 bool intel_fb_is_tiled_modifier(u64 modifier)
311 {
312 	return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
313 				      INTEL_PLANE_CAP_TILING_MASK);
314 }
315 
316 /**
317  * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
318  * @modifier: Modifier to check
319  *
320  * Returns:
321  * Returns %true if @modifier is a render, render with color clear or
322  * media compression modifier.
323  */
324 bool intel_fb_is_ccs_modifier(u64 modifier)
325 {
326 	return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
327 				      INTEL_PLANE_CAP_CCS_MASK);
328 }
329 
330 /**
331  * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type
332  * @modifier: Modifier to check
333  *
334  * Returns:
335  * Returns %true if @modifier is a render with color clear modifier.
336  */
337 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
338 {
339 	return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
340 				      INTEL_PLANE_CAP_CCS_RC_CC);
341 }
342 
343 /**
344  * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
345  * @modifier: Modifier to check
346  *
347  * Returns:
348  * Returns %true if @modifier is a media compression modifier.
349  */
350 bool intel_fb_is_mc_ccs_modifier(u64 modifier)
351 {
352 	return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
353 				      INTEL_PLANE_CAP_CCS_MC);
354 }
355 
356 static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
357 					     u8 display_ver_from, u8 display_ver_until)
358 {
359 	return md->display_ver.from <= display_ver_until &&
360 		display_ver_from <= md->display_ver.until;
361 }
362 
363 static bool plane_has_modifier(struct drm_i915_private *i915,
364 			       u8 plane_caps,
365 			       const struct intel_modifier_desc *md)
366 {
367 	if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until))
368 		return false;
369 
370 	if (!plane_caps_contain_all(plane_caps, md->plane_caps))
371 		return false;
372 
373 	return true;
374 }
375 
376 /**
377  * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities
378  * @i915: i915 device instance
379  * @plane_caps: capabilities for the plane the modifiers are queried for
380  *
381  * Returns:
382  * Returns the list of modifiers allowed by the @i915 platform and @plane_caps.
383  * The caller must free the returned buffer.
384  */
385 u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
386 				  u8 plane_caps)
387 {
388 	u64 *list, *p;
389 	int count = 1;		/* +1 for invalid modifier terminator */
390 	int i;
391 
392 	for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
393 		if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
394 			count++;
395 	}
396 
397 	list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);
398 	if (drm_WARN_ON(&i915->drm, !list))
399 		return NULL;
400 
401 	p = list;
402 	for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
403 		if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
404 			*p++ = intel_modifiers[i].modifier;
405 	}
406 	*p++ = DRM_FORMAT_MOD_INVALID;
407 
408 	return list;
409 }
410 
411 /**
412  * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane
413  * @plane: Plane to check the modifier support for
414  * @modifier: The modifier to check the support for
415  *
416  * Returns:
417  * %true if the @modifier is supported on @plane.
418  */
419 bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
420 {
421 	int i;
422 
423 	for (i = 0; i < plane->base.modifier_count; i++)
424 		if (plane->base.modifiers[i] == modifier)
425 			return true;
426 
427 	return false;
428 }
429 
430 static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
431 				     const struct drm_format_info *info)
432 {
433 	if (!info->is_yuv)
434 		return false;
435 
436 	if (hweight8(md->ccs.planar_aux_planes) == 2)
437 		return info->num_planes == 4;
438 	else
439 		return info->num_planes == 2;
440 }
441 
442 /**
443  * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar
444  * @info: format to check
445  * @modifier: modifier used with the format
446  *
447  * Returns:
448  * %true if @info / @modifier is YUV semiplanar.
449  */
450 bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
451 					 u64 modifier)
452 {
453 	return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
454 }
455 
456 static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md,
457 			     const struct drm_format_info *format)
458 {
459 	if (format_is_yuv_semiplanar(md, format))
460 		return md->ccs.planar_aux_planes;
461 	else
462 		return md->ccs.packed_aux_planes;
463 }
464 
465 /**
466  * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane
467  * @fb: Framebuffer
468  * @color_plane: color plane index to check
469  *
470  * Returns:
471  * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane.
472  */
473 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
474 {
475 	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
476 
477 	return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
478 }
479 
480 /**
481  * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane
482  * @fb: Framebuffer
483  * @color_plane: color plane index to check
484  *
485  * Returns:
486  * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane.
487  */
488 static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
489 {
490 	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
491 
492 	return check_modifier_display_ver_range(md, 12, 13) &&
493 	       ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
494 }
495 
496 /**
497  * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
498  * @fb: Framebuffer
499  *
500  * Returns:
501  * Returns the index of the color clear plane for @fb, or -1 if @fb is not a
502  * framebuffer using a render compression/color clear modifier.
503  */
504 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
505 {
506 	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
507 
508 	if (!md->ccs.cc_planes)
509 		return -1;
510 
511 	drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
512 
513 	return ilog2((int)md->ccs.cc_planes);
514 }
515 
516 static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane)
517 {
518 	return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
519 }
520 
521 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
522 {
523 	return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
524 		color_plane == 1;
525 }
526 
527 bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
528 {
529 	return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
530 	       intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) ||
531 	       is_gen12_ccs_cc_plane(fb, color_plane);
532 }
533 
534 int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
535 {
536 	drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
537 		    (main_plane && main_plane >= fb->format->num_planes / 2));
538 
539 	return fb->format->num_planes / 2 + main_plane;
540 }
541 
542 int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
543 {
544 	drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
545 		    ccs_plane < fb->format->num_planes / 2);
546 
547 	if (is_gen12_ccs_cc_plane(fb, ccs_plane))
548 		return 0;
549 
550 	return ccs_plane - fb->format->num_planes / 2;
551 }
552 
553 static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane)
554 {
555 	int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane);
556 	unsigned int main_stride = fb->base.pitches[main_plane];
557 	unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane);
558 
559 	return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64;
560 }
561 
562 int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
563 {
564 	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
565 	struct drm_i915_private *i915 = to_i915(fb->dev);
566 
567 	if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)
568 		return main_to_ccs_plane(fb, main_plane);
569 	else if (DISPLAY_VER(i915) < 11 &&
570 		 format_is_yuv_semiplanar(md, fb->format))
571 		return 1;
572 	else
573 		return 0;
574 }
575 
576 unsigned int intel_tile_size(const struct drm_i915_private *i915)
577 {
578 	return DISPLAY_VER(i915) == 2 ? 2048 : 4096;
579 }
580 
581 unsigned int
582 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
583 {
584 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
585 	unsigned int cpp = fb->format->cpp[color_plane];
586 
587 	switch (fb->modifier) {
588 	case DRM_FORMAT_MOD_LINEAR:
589 		return intel_tile_size(dev_priv);
590 	case I915_FORMAT_MOD_X_TILED:
591 		if (DISPLAY_VER(dev_priv) == 2)
592 			return 128;
593 		else
594 			return 512;
595 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
596 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
597 	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
598 	case I915_FORMAT_MOD_4_TILED:
599 		/*
600 		 * Each 4K tile consists of 64B(8*8) subtiles, with
601 		 * same shape as Y Tile(i.e 4*16B OWords)
602 		 */
603 		return 128;
604 	case I915_FORMAT_MOD_Y_TILED_CCS:
605 		if (intel_fb_is_ccs_aux_plane(fb, color_plane))
606 			return 128;
607 		fallthrough;
608 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
609 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
610 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
611 		if (intel_fb_is_ccs_aux_plane(fb, color_plane) ||
612 		    is_gen12_ccs_cc_plane(fb, color_plane))
613 			return 64;
614 		fallthrough;
615 	case I915_FORMAT_MOD_Y_TILED:
616 		if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
617 			return 128;
618 		else
619 			return 512;
620 	case I915_FORMAT_MOD_Yf_TILED_CCS:
621 		if (intel_fb_is_ccs_aux_plane(fb, color_plane))
622 			return 128;
623 		fallthrough;
624 	case I915_FORMAT_MOD_Yf_TILED:
625 		switch (cpp) {
626 		case 1:
627 			return 64;
628 		case 2:
629 		case 4:
630 			return 128;
631 		case 8:
632 		case 16:
633 			return 256;
634 		default:
635 			MISSING_CASE(cpp);
636 			return cpp;
637 		}
638 		break;
639 	default:
640 		MISSING_CASE(fb->modifier);
641 		return cpp;
642 	}
643 }
644 
645 unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
646 {
647 	return intel_tile_size(to_i915(fb->dev)) /
648 		intel_tile_width_bytes(fb, color_plane);
649 }
650 
651 /*
652  * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT
653  * page tile size.
654  */
655 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
656 			    unsigned int *tile_width,
657 			    unsigned int *tile_height)
658 {
659 	unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
660 	unsigned int cpp = fb->format->cpp[color_plane];
661 
662 	*tile_width = tile_width_bytes / cpp;
663 	*tile_height = intel_tile_height(fb, color_plane);
664 }
665 
666 /*
667  * Return the tile dimensions in pixel units, based on the tile block size.
668  * The block covers the full GTT page sized tile on all tiled surfaces and
669  * it's a 64 byte portion of the tile on TGL+ CCS surfaces.
670  */
671 static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane,
672 				  unsigned int *tile_width,
673 				  unsigned int *tile_height)
674 {
675 	intel_tile_dims(fb, color_plane, tile_width, tile_height);
676 
677 	if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane))
678 		*tile_height = 1;
679 }
680 
681 unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane)
682 {
683 	unsigned int tile_width, tile_height;
684 
685 	intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
686 
687 	return fb->pitches[color_plane] * tile_height;
688 }
689 
690 unsigned int
691 intel_fb_align_height(const struct drm_framebuffer *fb,
692 		      int color_plane, unsigned int height)
693 {
694 	unsigned int tile_height = intel_tile_height(fb, color_plane);
695 
696 	return ALIGN(height, tile_height);
697 }
698 
699 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
700 {
701 	u8 tiling_caps = lookup_modifier(fb_modifier)->plane_caps &
702 			 INTEL_PLANE_CAP_TILING_MASK;
703 
704 	switch (tiling_caps) {
705 	case INTEL_PLANE_CAP_TILING_Y:
706 		return I915_TILING_Y;
707 	case INTEL_PLANE_CAP_TILING_X:
708 		return I915_TILING_X;
709 	case INTEL_PLANE_CAP_TILING_4:
710 	case INTEL_PLANE_CAP_TILING_Yf:
711 	case INTEL_PLANE_CAP_TILING_NONE:
712 		return I915_TILING_NONE;
713 	default:
714 		MISSING_CASE(tiling_caps);
715 		return I915_TILING_NONE;
716 	}
717 }
718 
719 static bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
720 {
721 	return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
722 }
723 
724 bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
725 {
726 	return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
727 }
728 
729 unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
730 {
731 	if (IS_I830(i915))
732 		return 16 * 1024;
733 	else if (IS_I85X(i915))
734 		return 256;
735 	else if (IS_I845G(i915) || IS_I865G(i915))
736 		return 32;
737 	else
738 		return 4 * 1024;
739 }
740 
741 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
742 {
743 	if (DISPLAY_VER(dev_priv) >= 9)
744 		return 256 * 1024;
745 	else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
746 		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
747 		return 128 * 1024;
748 	else if (DISPLAY_VER(dev_priv) >= 4)
749 		return 4 * 1024;
750 	else
751 		return 0;
752 }
753 
754 unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
755 				  int color_plane)
756 {
757 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
758 
759 	if (intel_fb_uses_dpt(fb))
760 		return 512 * 4096;
761 
762 	/* AUX_DIST needs only 4K alignment */
763 	if (intel_fb_is_ccs_aux_plane(fb, color_plane))
764 		return 4096;
765 
766 	if (is_semiplanar_uv_plane(fb, color_plane)) {
767 		/*
768 		 * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
769 		 * alignment for linear UV planes on all platforms.
770 		 */
771 		if (DISPLAY_VER(dev_priv) >= 12) {
772 			if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
773 				return intel_linear_alignment(dev_priv);
774 
775 			return intel_tile_row_size(fb, color_plane);
776 		}
777 
778 		return 4096;
779 	}
780 
781 	drm_WARN_ON(&dev_priv->drm, color_plane != 0);
782 
783 	switch (fb->modifier) {
784 	case DRM_FORMAT_MOD_LINEAR:
785 		return intel_linear_alignment(dev_priv);
786 	case I915_FORMAT_MOD_X_TILED:
787 		if (HAS_ASYNC_FLIPS(dev_priv))
788 			return 256 * 1024;
789 		return 0;
790 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
791 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
792 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
793 		return 16 * 1024;
794 	case I915_FORMAT_MOD_Y_TILED_CCS:
795 	case I915_FORMAT_MOD_Yf_TILED_CCS:
796 	case I915_FORMAT_MOD_Y_TILED:
797 	case I915_FORMAT_MOD_4_TILED:
798 	case I915_FORMAT_MOD_Yf_TILED:
799 		return 1 * 1024 * 1024;
800 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
801 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
802 	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
803 		return 16 * 1024;
804 	default:
805 		MISSING_CASE(fb->modifier);
806 		return 0;
807 	}
808 }
809 
810 void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
811 				    const struct drm_framebuffer *fb,
812 				    int color_plane)
813 {
814 	int main_plane;
815 
816 	if (color_plane == 0) {
817 		*hsub = 1;
818 		*vsub = 1;
819 
820 		return;
821 	}
822 
823 	/*
824 	 * TODO: Deduct the subsampling from the char block for all CCS
825 	 * formats and planes.
826 	 */
827 	if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) {
828 		*hsub = fb->format->hsub;
829 		*vsub = fb->format->vsub;
830 
831 		return;
832 	}
833 
834 	main_plane = skl_ccs_to_main_plane(fb, color_plane);
835 	*hsub = drm_format_info_block_width(fb->format, color_plane) /
836 		drm_format_info_block_width(fb->format, main_plane);
837 
838 	/*
839 	 * The min stride check in the core framebuffer_check() function
840 	 * assumes that format->hsub applies to every plane except for the
841 	 * first plane. That's incorrect for the CCS AUX plane of the first
842 	 * plane, but for the above check to pass we must define the block
843 	 * width with that subsampling applied to it. Adjust the width here
844 	 * accordingly, so we can calculate the actual subsampling factor.
845 	 */
846 	if (main_plane == 0)
847 		*hsub *= fb->format->hsub;
848 
849 	*vsub = 32;
850 }
851 
852 static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h)
853 {
854 	int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ?
855 			 skl_ccs_to_main_plane(&fb->base, color_plane) : 0;
856 	unsigned int main_width = fb->base.width;
857 	unsigned int main_height = fb->base.height;
858 	int main_hsub, main_vsub;
859 	int hsub, vsub;
860 
861 	intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane);
862 	intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane);
863 
864 	*w = DIV_ROUND_UP(main_width, main_hsub * hsub);
865 	*h = DIV_ROUND_UP(main_height, main_vsub * vsub);
866 }
867 
868 static u32 intel_adjust_tile_offset(int *x, int *y,
869 				    unsigned int tile_width,
870 				    unsigned int tile_height,
871 				    unsigned int tile_size,
872 				    unsigned int pitch_tiles,
873 				    u32 old_offset,
874 				    u32 new_offset)
875 {
876 	unsigned int pitch_pixels = pitch_tiles * tile_width;
877 	unsigned int tiles;
878 
879 	WARN_ON(old_offset & (tile_size - 1));
880 	WARN_ON(new_offset & (tile_size - 1));
881 	WARN_ON(new_offset > old_offset);
882 
883 	tiles = (old_offset - new_offset) / tile_size;
884 
885 	*y += tiles / pitch_tiles * tile_height;
886 	*x += tiles % pitch_tiles * tile_width;
887 
888 	/* minimize x in case it got needlessly big */
889 	*y += *x / pitch_pixels * tile_height;
890 	*x %= pitch_pixels;
891 
892 	return new_offset;
893 }
894 
895 static u32 intel_adjust_linear_offset(int *x, int *y,
896 				      unsigned int cpp,
897 				      unsigned int pitch,
898 				      u32 old_offset,
899 				      u32 new_offset)
900 {
901 	old_offset += *y * pitch + *x * cpp;
902 
903 	*y = (old_offset - new_offset) / pitch;
904 	*x = ((old_offset - new_offset) - *y * pitch) / cpp;
905 
906 	return new_offset;
907 }
908 
909 static u32 intel_adjust_aligned_offset(int *x, int *y,
910 				       const struct drm_framebuffer *fb,
911 				       int color_plane,
912 				       unsigned int rotation,
913 				       unsigned int pitch,
914 				       u32 old_offset, u32 new_offset)
915 {
916 	struct drm_i915_private *i915 = to_i915(fb->dev);
917 	unsigned int cpp = fb->format->cpp[color_plane];
918 
919 	drm_WARN_ON(&i915->drm, new_offset > old_offset);
920 
921 	if (!is_surface_linear(fb, color_plane)) {
922 		unsigned int tile_size, tile_width, tile_height;
923 		unsigned int pitch_tiles;
924 
925 		tile_size = intel_tile_size(i915);
926 		intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
927 
928 		if (drm_rotation_90_or_270(rotation)) {
929 			pitch_tiles = pitch / tile_height;
930 			swap(tile_width, tile_height);
931 		} else {
932 			pitch_tiles = pitch / (tile_width * cpp);
933 		}
934 
935 		intel_adjust_tile_offset(x, y, tile_width, tile_height,
936 					 tile_size, pitch_tiles,
937 					 old_offset, new_offset);
938 	} else {
939 		intel_adjust_linear_offset(x, y, cpp, pitch,
940 					   old_offset, new_offset);
941 	}
942 
943 	return new_offset;
944 }
945 
946 /*
947  * Adjust the tile offset by moving the difference into
948  * the x/y offsets.
949  */
950 u32 intel_plane_adjust_aligned_offset(int *x, int *y,
951 				      const struct intel_plane_state *state,
952 				      int color_plane,
953 				      u32 old_offset, u32 new_offset)
954 {
955 	return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
956 					   state->hw.rotation,
957 					   state->view.color_plane[color_plane].mapping_stride,
958 					   old_offset, new_offset);
959 }
960 
961 /*
962  * Computes the aligned offset to the base tile and adjusts
963  * x, y. bytes per pixel is assumed to be a power-of-two.
964  *
965  * In the 90/270 rotated case, x and y are assumed
966  * to be already rotated to match the rotated GTT view, and
967  * pitch is the tile_height aligned framebuffer height.
968  *
969  * This function is used when computing the derived information
970  * under intel_framebuffer, so using any of that information
971  * here is not allowed. Anything under drm_framebuffer can be
972  * used. This is why the user has to pass in the pitch since it
973  * is specified in the rotated orientation.
974  */
975 static u32 intel_compute_aligned_offset(struct drm_i915_private *i915,
976 					int *x, int *y,
977 					const struct drm_framebuffer *fb,
978 					int color_plane,
979 					unsigned int pitch,
980 					unsigned int rotation,
981 					u32 alignment)
982 {
983 	unsigned int cpp = fb->format->cpp[color_plane];
984 	u32 offset, offset_aligned;
985 
986 	if (!is_surface_linear(fb, color_plane)) {
987 		unsigned int tile_size, tile_width, tile_height;
988 		unsigned int tile_rows, tiles, pitch_tiles;
989 
990 		tile_size = intel_tile_size(i915);
991 		intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
992 
993 		if (drm_rotation_90_or_270(rotation)) {
994 			pitch_tiles = pitch / tile_height;
995 			swap(tile_width, tile_height);
996 		} else {
997 			pitch_tiles = pitch / (tile_width * cpp);
998 		}
999 
1000 		tile_rows = *y / tile_height;
1001 		*y %= tile_height;
1002 
1003 		tiles = *x / tile_width;
1004 		*x %= tile_width;
1005 
1006 		offset = (tile_rows * pitch_tiles + tiles) * tile_size;
1007 
1008 		offset_aligned = offset;
1009 		if (alignment)
1010 			offset_aligned = rounddown(offset_aligned, alignment);
1011 
1012 		intel_adjust_tile_offset(x, y, tile_width, tile_height,
1013 					 tile_size, pitch_tiles,
1014 					 offset, offset_aligned);
1015 	} else {
1016 		offset = *y * pitch + *x * cpp;
1017 		offset_aligned = offset;
1018 		if (alignment) {
1019 			offset_aligned = rounddown(offset_aligned, alignment);
1020 			*y = (offset % alignment) / pitch;
1021 			*x = ((offset % alignment) - *y * pitch) / cpp;
1022 		} else {
1023 			*y = *x = 0;
1024 		}
1025 	}
1026 
1027 	return offset_aligned;
1028 }
1029 
1030 u32 intel_plane_compute_aligned_offset(int *x, int *y,
1031 				       const struct intel_plane_state *state,
1032 				       int color_plane)
1033 {
1034 	struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
1035 	struct drm_i915_private *i915 = to_i915(intel_plane->base.dev);
1036 	const struct drm_framebuffer *fb = state->hw.fb;
1037 	unsigned int rotation = state->hw.rotation;
1038 	int pitch = state->view.color_plane[color_plane].mapping_stride;
1039 	u32 alignment;
1040 
1041 	if (intel_plane->id == PLANE_CURSOR)
1042 		alignment = intel_cursor_alignment(i915);
1043 	else
1044 		alignment = intel_surf_alignment(fb, color_plane);
1045 
1046 	return intel_compute_aligned_offset(i915, x, y, fb, color_plane,
1047 					    pitch, rotation, alignment);
1048 }
1049 
1050 /* Convert the fb->offset[] into x/y offsets */
1051 static int intel_fb_offset_to_xy(int *x, int *y,
1052 				 const struct drm_framebuffer *fb,
1053 				 int color_plane)
1054 {
1055 	struct drm_i915_private *i915 = to_i915(fb->dev);
1056 	unsigned int height;
1057 	u32 alignment;
1058 
1059 	if (DISPLAY_VER(i915) >= 12 &&
1060 	    !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) &&
1061 	    is_semiplanar_uv_plane(fb, color_plane))
1062 		alignment = intel_tile_row_size(fb, color_plane);
1063 	else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
1064 		alignment = intel_tile_size(i915);
1065 	else
1066 		alignment = 0;
1067 
1068 	if (alignment != 0 && fb->offsets[color_plane] % alignment) {
1069 		drm_dbg_kms(&i915->drm,
1070 			    "Misaligned offset 0x%08x for color plane %d\n",
1071 			    fb->offsets[color_plane], color_plane);
1072 		return -EINVAL;
1073 	}
1074 
1075 	height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
1076 	height = ALIGN(height, intel_tile_height(fb, color_plane));
1077 
1078 	/* Catch potential overflows early */
1079 	if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
1080 			    fb->offsets[color_plane])) {
1081 		drm_dbg_kms(&i915->drm,
1082 			    "Bad offset 0x%08x or pitch %d for color plane %d\n",
1083 			    fb->offsets[color_plane], fb->pitches[color_plane],
1084 			    color_plane);
1085 		return -ERANGE;
1086 	}
1087 
1088 	*x = 0;
1089 	*y = 0;
1090 
1091 	intel_adjust_aligned_offset(x, y,
1092 				    fb, color_plane, DRM_MODE_ROTATE_0,
1093 				    fb->pitches[color_plane],
1094 				    fb->offsets[color_plane], 0);
1095 
1096 	return 0;
1097 }
1098 
1099 static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y)
1100 {
1101 	struct drm_i915_private *i915 = to_i915(fb->dev);
1102 	const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1103 	int main_plane;
1104 	int hsub, vsub;
1105 	int tile_width, tile_height;
1106 	int ccs_x, ccs_y;
1107 	int main_x, main_y;
1108 
1109 	if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane))
1110 		return 0;
1111 
1112 	/*
1113 	 * While all the tile dimensions are based on a 2k or 4k GTT page size
1114 	 * here the main and CCS coordinates must match only within a (64 byte
1115 	 * on TGL+) block inside the tile.
1116 	 */
1117 	intel_tile_block_dims(fb, ccs_plane, &tile_width, &tile_height);
1118 	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1119 
1120 	tile_width *= hsub;
1121 	tile_height *= vsub;
1122 
1123 	ccs_x = (x * hsub) % tile_width;
1124 	ccs_y = (y * vsub) % tile_height;
1125 
1126 	main_plane = skl_ccs_to_main_plane(fb, ccs_plane);
1127 	main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width;
1128 	main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height;
1129 
1130 	/*
1131 	 * CCS doesn't have its own x/y offset register, so the intra CCS tile
1132 	 * x/y offsets must match between CCS and the main surface.
1133 	 */
1134 	if (main_x != ccs_x || main_y != ccs_y) {
1135 		drm_dbg_kms(&i915->drm,
1136 			      "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
1137 			      main_x, main_y,
1138 			      ccs_x, ccs_y,
1139 			      intel_fb->normal_view.color_plane[main_plane].x,
1140 			      intel_fb->normal_view.color_plane[main_plane].y,
1141 			      x, y);
1142 		return -EINVAL;
1143 	}
1144 
1145 	return 0;
1146 }
1147 
1148 static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
1149 {
1150 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1151 	struct drm_i915_private *i915 = to_i915(plane->base.dev);
1152 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1153 	int i;
1154 
1155 	/* We don't want to deal with remapping with cursors */
1156 	if (plane->id == PLANE_CURSOR)
1157 		return false;
1158 
1159 	/*
1160 	 * The display engine limits already match/exceed the
1161 	 * render engine limits, so not much point in remapping.
1162 	 * Would also need to deal with the fence POT alignment
1163 	 * and gen2 2KiB GTT tile size.
1164 	 */
1165 	if (DISPLAY_VER(i915) < 4)
1166 		return false;
1167 
1168 	/*
1169 	 * The new CCS hash mode isn't compatible with remapping as
1170 	 * the virtual address of the pages affects the compressed data.
1171 	 */
1172 	if (intel_fb_is_ccs_modifier(fb->modifier))
1173 		return false;
1174 
1175 	/* Linear needs a page aligned stride for remapping */
1176 	if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1177 		unsigned int alignment = intel_tile_size(i915) - 1;
1178 
1179 		for (i = 0; i < fb->format->num_planes; i++) {
1180 			if (fb->pitches[i] & alignment)
1181 				return false;
1182 		}
1183 	}
1184 
1185 	return true;
1186 }
1187 
1188 bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
1189 {
1190 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
1191 
1192 	return IS_ALDERLAKE_P(i915) && fb->base.modifier != DRM_FORMAT_MOD_LINEAR;
1193 }
1194 
1195 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
1196 {
1197 	if (drm_rotation_90_or_270(rotation))
1198 		return fb->rotated_view.color_plane[color_plane].mapping_stride;
1199 	else if (intel_fb_needs_pot_stride_remap(fb))
1200 		return fb->remapped_view.color_plane[color_plane].mapping_stride;
1201 	else
1202 		return fb->normal_view.color_plane[color_plane].mapping_stride;
1203 }
1204 
1205 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
1206 {
1207 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1208 	const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);
1209 	unsigned int rotation = plane_state->hw.rotation;
1210 	u32 stride, max_stride;
1211 
1212 	/*
1213 	 * No remapping for invisible planes since we don't have
1214 	 * an actual source viewport to remap.
1215 	 */
1216 	if (!plane_state->uapi.visible)
1217 		return false;
1218 
1219 	if (!intel_plane_can_remap(plane_state))
1220 		return false;
1221 
1222 	/*
1223 	 * FIXME: aux plane limits on gen9+ are
1224 	 * unclear in Bspec, for now no checking.
1225 	 */
1226 	stride = intel_fb_pitch(fb, 0, rotation);
1227 	max_stride = plane->max_stride(plane, fb->base.format->format,
1228 				       fb->base.modifier, rotation);
1229 
1230 	return stride > max_stride;
1231 }
1232 
1233 static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane,
1234 				      int plane_width, int *x, int *y)
1235 {
1236 	struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
1237 	int ret;
1238 
1239 	ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane);
1240 	if (ret) {
1241 		drm_dbg_kms(fb->base.dev,
1242 			    "bad fb plane %d offset: 0x%x\n",
1243 			    color_plane, fb->base.offsets[color_plane]);
1244 		return ret;
1245 	}
1246 
1247 	ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y);
1248 	if (ret)
1249 		return ret;
1250 
1251 	/*
1252 	 * The fence (if used) is aligned to the start of the object
1253 	 * so having the framebuffer wrap around across the edge of the
1254 	 * fenced region doesn't really work. We have no API to configure
1255 	 * the fence start offset within the object (nor could we probably
1256 	 * on gen2/3). So it's just easier if we just require that the
1257 	 * fb layout agrees with the fence layout. We already check that the
1258 	 * fb stride matches the fence stride elsewhere.
1259 	 */
1260 	if (color_plane == 0 && i915_gem_object_is_tiled(obj) &&
1261 	    (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) {
1262 		drm_dbg_kms(fb->base.dev,
1263 			    "bad fb plane %d offset: 0x%x\n",
1264 			    color_plane, fb->base.offsets[color_plane]);
1265 		return -EINVAL;
1266 	}
1267 
1268 	return 0;
1269 }
1270 
1271 static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y)
1272 {
1273 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
1274 	unsigned int tile_size = intel_tile_size(i915);
1275 	u32 offset;
1276 
1277 	offset = intel_compute_aligned_offset(i915, x, y, &fb->base, color_plane,
1278 					      fb->base.pitches[color_plane],
1279 					      DRM_MODE_ROTATE_0,
1280 					      tile_size);
1281 
1282 	return offset / tile_size;
1283 }
1284 
1285 struct fb_plane_view_dims {
1286 	unsigned int width, height;
1287 	unsigned int tile_width, tile_height;
1288 };
1289 
1290 static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane,
1291 				 unsigned int width, unsigned int height,
1292 				 struct fb_plane_view_dims *dims)
1293 {
1294 	dims->width = width;
1295 	dims->height = height;
1296 
1297 	intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height);
1298 }
1299 
1300 static unsigned int
1301 plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
1302 			    const struct fb_plane_view_dims *dims)
1303 {
1304 	return DIV_ROUND_UP(fb->base.pitches[color_plane],
1305 			    dims->tile_width * fb->base.format->cpp[color_plane]);
1306 }
1307 
1308 static unsigned int
1309 plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
1310 			    unsigned int pitch_tiles)
1311 {
1312 	if (intel_fb_needs_pot_stride_remap(fb)) {
1313 		/*
1314 		 * ADL_P, the only platform needing a POT stride has a minimum
1315 		 * of 8 main surface tiles.
1316 		 */
1317 		return roundup_pow_of_two(max(pitch_tiles, 8u));
1318 	} else {
1319 		return pitch_tiles;
1320 	}
1321 }
1322 
1323 static unsigned int
1324 plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane,
1325 			  unsigned int tile_width,
1326 			  unsigned int src_stride_tiles, unsigned int dst_stride_tiles)
1327 {
1328 	unsigned int stride_tiles;
1329 
1330 	if (IS_ALDERLAKE_P(to_i915(fb->base.dev)))
1331 		stride_tiles = src_stride_tiles;
1332 	else
1333 		stride_tiles = dst_stride_tiles;
1334 
1335 	return stride_tiles * tile_width * fb->base.format->cpp[color_plane];
1336 }
1337 
1338 static unsigned int
1339 plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane,
1340 		       const struct fb_plane_view_dims *dims,
1341 		       int x)
1342 {
1343 	return DIV_ROUND_UP(x + dims->width, dims->tile_width);
1344 }
1345 
1346 static unsigned int
1347 plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane,
1348 			const struct fb_plane_view_dims *dims,
1349 			int y)
1350 {
1351 	return DIV_ROUND_UP(y + dims->height, dims->tile_height);
1352 }
1353 
1354 static unsigned int
1355 plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane,
1356 			const struct fb_plane_view_dims *dims,
1357 			int x, int y)
1358 {
1359 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
1360 	unsigned int size;
1361 
1362 	size = (y + dims->height) * fb->base.pitches[color_plane] +
1363 		x * fb->base.format->cpp[color_plane];
1364 
1365 	return DIV_ROUND_UP(size, intel_tile_size(i915));
1366 }
1367 
1368 #define assign_chk_ovf(i915, var, val) ({ \
1369 	drm_WARN_ON(&(i915)->drm, overflows_type(val, var)); \
1370 	(var) = (val); \
1371 })
1372 
1373 #define assign_bfld_chk_ovf(i915, var, val) ({ \
1374 	(var) = (val); \
1375 	drm_WARN_ON(&(i915)->drm, (var) != (val)); \
1376 	(var); \
1377 })
1378 
1379 static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane,
1380 				 const struct fb_plane_view_dims *dims,
1381 				 u32 obj_offset, u32 gtt_offset, int x, int y,
1382 				 struct intel_fb_view *view)
1383 {
1384 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
1385 	struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane];
1386 	struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane];
1387 	unsigned int tile_width = dims->tile_width;
1388 	unsigned int tile_height = dims->tile_height;
1389 	unsigned int tile_size = intel_tile_size(i915);
1390 	struct drm_rect r;
1391 	u32 size = 0;
1392 
1393 	assign_bfld_chk_ovf(i915, remap_info->offset, obj_offset);
1394 
1395 	if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) {
1396 		remap_info->linear = 1;
1397 
1398 		assign_chk_ovf(i915, remap_info->size,
1399 			       plane_view_linear_tiles(fb, color_plane, dims, x, y));
1400 	} else {
1401 		remap_info->linear = 0;
1402 
1403 		assign_chk_ovf(i915, remap_info->src_stride,
1404 			       plane_view_src_stride_tiles(fb, color_plane, dims));
1405 		assign_chk_ovf(i915, remap_info->width,
1406 			       plane_view_width_tiles(fb, color_plane, dims, x));
1407 		assign_chk_ovf(i915, remap_info->height,
1408 			       plane_view_height_tiles(fb, color_plane, dims, y));
1409 	}
1410 
1411 	if (view->gtt.type == I915_GTT_VIEW_ROTATED) {
1412 		drm_WARN_ON(&i915->drm, remap_info->linear);
1413 		check_array_bounds(i915, view->gtt.rotated.plane, color_plane);
1414 
1415 		assign_chk_ovf(i915, remap_info->dst_stride,
1416 			       plane_view_dst_stride_tiles(fb, color_plane, remap_info->height));
1417 
1418 		/* rotate the x/y offsets to match the GTT view */
1419 		drm_rect_init(&r, x, y, dims->width, dims->height);
1420 		drm_rect_rotate(&r,
1421 				remap_info->width * tile_width,
1422 				remap_info->height * tile_height,
1423 				DRM_MODE_ROTATE_270);
1424 
1425 		color_plane_info->x = r.x1;
1426 		color_plane_info->y = r.y1;
1427 
1428 		color_plane_info->mapping_stride = remap_info->dst_stride * tile_height;
1429 		color_plane_info->scanout_stride = color_plane_info->mapping_stride;
1430 
1431 		size += remap_info->dst_stride * remap_info->width;
1432 
1433 		/* rotate the tile dimensions to match the GTT view */
1434 		swap(tile_width, tile_height);
1435 	} else {
1436 		drm_WARN_ON(&i915->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED);
1437 
1438 		check_array_bounds(i915, view->gtt.remapped.plane, color_plane);
1439 
1440 		if (view->gtt.remapped.plane_alignment) {
1441 			unsigned int aligned_offset = ALIGN(gtt_offset,
1442 							    view->gtt.remapped.plane_alignment);
1443 
1444 			size += aligned_offset - gtt_offset;
1445 			gtt_offset = aligned_offset;
1446 		}
1447 
1448 		color_plane_info->x = x;
1449 		color_plane_info->y = y;
1450 
1451 		if (remap_info->linear) {
1452 			color_plane_info->mapping_stride = fb->base.pitches[color_plane];
1453 			color_plane_info->scanout_stride = color_plane_info->mapping_stride;
1454 
1455 			size += remap_info->size;
1456 		} else {
1457 			unsigned int dst_stride = plane_view_dst_stride_tiles(fb, color_plane,
1458 									      remap_info->width);
1459 
1460 			assign_chk_ovf(i915, remap_info->dst_stride, dst_stride);
1461 			color_plane_info->mapping_stride = dst_stride *
1462 							   tile_width *
1463 							   fb->base.format->cpp[color_plane];
1464 			color_plane_info->scanout_stride =
1465 				plane_view_scanout_stride(fb, color_plane, tile_width,
1466 							  remap_info->src_stride,
1467 							  dst_stride);
1468 
1469 			size += dst_stride * remap_info->height;
1470 		}
1471 	}
1472 
1473 	/*
1474 	 * We only keep the x/y offsets, so push all of the gtt offset into
1475 	 * the x/y offsets.  x,y will hold the first pixel of the framebuffer
1476 	 * plane from the start of the remapped/rotated gtt mapping.
1477 	 */
1478 	if (remap_info->linear)
1479 		intel_adjust_linear_offset(&color_plane_info->x, &color_plane_info->y,
1480 					   fb->base.format->cpp[color_plane],
1481 					   color_plane_info->mapping_stride,
1482 					   gtt_offset * tile_size, 0);
1483 	else
1484 		intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y,
1485 					 tile_width, tile_height,
1486 					 tile_size, remap_info->dst_stride,
1487 					 gtt_offset * tile_size, 0);
1488 
1489 	return size;
1490 }
1491 
1492 #undef assign_chk_ovf
1493 
1494 /* Return number of tiles @color_plane needs. */
1495 static unsigned int
1496 calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane,
1497 		       const struct fb_plane_view_dims *dims,
1498 		       int x, int y)
1499 {
1500 	unsigned int tiles;
1501 
1502 	if (is_surface_linear(&fb->base, color_plane)) {
1503 		tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y);
1504 	} else {
1505 		tiles = plane_view_src_stride_tiles(fb, color_plane, dims) *
1506 			plane_view_height_tiles(fb, color_plane, dims, y);
1507 		/*
1508 		 * If the plane isn't horizontally tile aligned,
1509 		 * we need one more tile.
1510 		 */
1511 		if (x != 0)
1512 			tiles++;
1513 	}
1514 
1515 	return tiles;
1516 }
1517 
1518 static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_view *view,
1519 			       enum i915_gtt_view_type view_type)
1520 {
1521 	memset(view, 0, sizeof(*view));
1522 	view->gtt.type = view_type;
1523 
1524 	if (view_type == I915_GTT_VIEW_REMAPPED && IS_ALDERLAKE_P(i915))
1525 		view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE;
1526 }
1527 
1528 bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb)
1529 {
1530 	if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13)
1531 		return false;
1532 
1533 	return fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||
1534 	       fb->base.modifier == I915_FORMAT_MOD_Yf_TILED;
1535 }
1536 
1537 int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb)
1538 {
1539 	struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
1540 	u32 gtt_offset_rotated = 0;
1541 	u32 gtt_offset_remapped = 0;
1542 	unsigned int max_size = 0;
1543 	int i, num_planes = fb->base.format->num_planes;
1544 	unsigned int tile_size = intel_tile_size(i915);
1545 
1546 	intel_fb_view_init(i915, &fb->normal_view, I915_GTT_VIEW_NORMAL);
1547 
1548 	drm_WARN_ON(&i915->drm,
1549 		    intel_fb_supports_90_270_rotation(fb) &&
1550 		    intel_fb_needs_pot_stride_remap(fb));
1551 
1552 	if (intel_fb_supports_90_270_rotation(fb))
1553 		intel_fb_view_init(i915, &fb->rotated_view, I915_GTT_VIEW_ROTATED);
1554 	if (intel_fb_needs_pot_stride_remap(fb))
1555 		intel_fb_view_init(i915, &fb->remapped_view, I915_GTT_VIEW_REMAPPED);
1556 
1557 	for (i = 0; i < num_planes; i++) {
1558 		struct fb_plane_view_dims view_dims;
1559 		unsigned int width, height;
1560 		unsigned int cpp, size;
1561 		u32 offset;
1562 		int x, y;
1563 		int ret;
1564 
1565 		/*
1566 		 * Plane 2 of Render Compression with Clear Color fb modifier
1567 		 * is consumed by the driver and not passed to DE. Skip the
1568 		 * arithmetic related to alignment and offset calculation.
1569 		 */
1570 		if (is_gen12_ccs_cc_plane(&fb->base, i)) {
1571 			if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE))
1572 				continue;
1573 			else
1574 				return -EINVAL;
1575 		}
1576 
1577 		cpp = fb->base.format->cpp[i];
1578 		intel_fb_plane_dims(fb, i, &width, &height);
1579 
1580 		ret = convert_plane_offset_to_xy(fb, i, width, &x, &y);
1581 		if (ret)
1582 			return ret;
1583 
1584 		init_plane_view_dims(fb, i, width, height, &view_dims);
1585 
1586 		/*
1587 		 * First pixel of the framebuffer from
1588 		 * the start of the normal gtt mapping.
1589 		 */
1590 		fb->normal_view.color_plane[i].x = x;
1591 		fb->normal_view.color_plane[i].y = y;
1592 		fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i];
1593 		fb->normal_view.color_plane[i].scanout_stride =
1594 			fb->normal_view.color_plane[i].mapping_stride;
1595 
1596 		offset = calc_plane_aligned_offset(fb, i, &x, &y);
1597 
1598 		if (intel_fb_supports_90_270_rotation(fb))
1599 			gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims,
1600 								    offset, gtt_offset_rotated, x, y,
1601 								    &fb->rotated_view);
1602 
1603 		if (intel_fb_needs_pot_stride_remap(fb))
1604 			gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims,
1605 								     offset, gtt_offset_remapped, x, y,
1606 								     &fb->remapped_view);
1607 
1608 		size = calc_plane_normal_size(fb, i, &view_dims, x, y);
1609 		/* how many tiles in total needed in the bo */
1610 		max_size = max(max_size, offset + size);
1611 	}
1612 
1613 	if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
1614 		drm_dbg_kms(&i915->drm,
1615 			    "fb too big for bo (need %llu bytes, have %zu bytes)\n",
1616 			    mul_u32_u32(max_size, tile_size), obj->base.size);
1617 		return -EINVAL;
1618 	}
1619 
1620 	return 0;
1621 }
1622 
1623 static void intel_plane_remap_gtt(struct intel_plane_state *plane_state)
1624 {
1625 	struct drm_i915_private *i915 =
1626 		to_i915(plane_state->uapi.plane->dev);
1627 	struct drm_framebuffer *fb = plane_state->hw.fb;
1628 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1629 	unsigned int rotation = plane_state->hw.rotation;
1630 	int i, num_planes = fb->format->num_planes;
1631 	unsigned int src_x, src_y;
1632 	unsigned int src_w, src_h;
1633 	u32 gtt_offset = 0;
1634 
1635 	intel_fb_view_init(i915, &plane_state->view,
1636 			   drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED :
1637 							      I915_GTT_VIEW_REMAPPED);
1638 
1639 	src_x = plane_state->uapi.src.x1 >> 16;
1640 	src_y = plane_state->uapi.src.y1 >> 16;
1641 	src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1642 	src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1643 
1644 	drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier));
1645 
1646 	/* Make src coordinates relative to the viewport */
1647 	drm_rect_translate(&plane_state->uapi.src,
1648 			   -(src_x << 16), -(src_y << 16));
1649 
1650 	/* Rotate src coordinates to match rotated GTT view */
1651 	if (drm_rotation_90_or_270(rotation))
1652 		drm_rect_rotate(&plane_state->uapi.src,
1653 				src_w << 16, src_h << 16,
1654 				DRM_MODE_ROTATE_270);
1655 
1656 	for (i = 0; i < num_planes; i++) {
1657 		unsigned int hsub = i ? fb->format->hsub : 1;
1658 		unsigned int vsub = i ? fb->format->vsub : 1;
1659 		struct fb_plane_view_dims view_dims;
1660 		unsigned int width, height;
1661 		unsigned int x, y;
1662 		u32 offset;
1663 
1664 		x = src_x / hsub;
1665 		y = src_y / vsub;
1666 		width = src_w / hsub;
1667 		height = src_h / vsub;
1668 
1669 		init_plane_view_dims(intel_fb, i, width, height, &view_dims);
1670 
1671 		/*
1672 		 * First pixel of the src viewport from the
1673 		 * start of the normal gtt mapping.
1674 		 */
1675 		x += intel_fb->normal_view.color_plane[i].x;
1676 		y += intel_fb->normal_view.color_plane[i].y;
1677 
1678 		offset = calc_plane_aligned_offset(intel_fb, i, &x, &y);
1679 
1680 		gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims,
1681 						    offset, gtt_offset, x, y,
1682 						    &plane_state->view);
1683 	}
1684 }
1685 
1686 void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation,
1687 			struct intel_fb_view *view)
1688 {
1689 	if (drm_rotation_90_or_270(rotation))
1690 		*view = fb->rotated_view;
1691 	else if (intel_fb_needs_pot_stride_remap(fb))
1692 		*view = fb->remapped_view;
1693 	else
1694 		*view = fb->normal_view;
1695 }
1696 
1697 static
1698 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
1699 			u32 pixel_format, u64 modifier)
1700 {
1701 	/*
1702 	 * Arbitrary limit for gen4+ chosen to match the
1703 	 * render engine max stride.
1704 	 *
1705 	 * The new CCS hash mode makes remapping impossible
1706 	 */
1707 	if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) ||
1708 	    intel_modifier_uses_dpt(dev_priv, modifier))
1709 		return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
1710 	else if (DISPLAY_VER(dev_priv) >= 7)
1711 		return 256 * 1024;
1712 	else
1713 		return 128 * 1024;
1714 }
1715 
1716 static u32
1717 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1718 {
1719 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
1720 	u32 tile_width;
1721 
1722 	if (is_surface_linear(fb, color_plane)) {
1723 		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
1724 							   fb->format->format,
1725 							   fb->modifier);
1726 
1727 		/*
1728 		 * To make remapping with linear generally feasible
1729 		 * we need the stride to be page aligned.
1730 		 */
1731 		if (fb->pitches[color_plane] > max_stride &&
1732 		    !intel_fb_is_ccs_modifier(fb->modifier))
1733 			return intel_tile_size(dev_priv);
1734 		else
1735 			return 64;
1736 	}
1737 
1738 	tile_width = intel_tile_width_bytes(fb, color_plane);
1739 	if (intel_fb_is_ccs_modifier(fb->modifier)) {
1740 		/*
1741 		 * On TGL the surface stride must be 4 tile aligned, mapped by
1742 		 * one 64 byte cacheline on the CCS AUX surface.
1743 		 */
1744 		if (DISPLAY_VER(dev_priv) >= 12)
1745 			tile_width *= 4;
1746 		/*
1747 		 * Display WA #0531: skl,bxt,kbl,glk
1748 		 *
1749 		 * Render decompression and plane width > 3840
1750 		 * combined with horizontal panning requires the
1751 		 * plane stride to be a multiple of 4. We'll just
1752 		 * require the entire fb to accommodate that to avoid
1753 		 * potential runtime errors at plane configuration time.
1754 		 */
1755 		else if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
1756 			 color_plane == 0 && fb->width > 3840)
1757 			tile_width *= 4;
1758 	}
1759 	return tile_width;
1760 }
1761 
1762 static int intel_plane_check_stride(const struct intel_plane_state *plane_state)
1763 {
1764 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1765 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1766 	unsigned int rotation = plane_state->hw.rotation;
1767 	u32 stride, max_stride;
1768 
1769 	/*
1770 	 * We ignore stride for all invisible planes that
1771 	 * can be remapped. Otherwise we could end up
1772 	 * with a false positive when the remapping didn't
1773 	 * kick in due the plane being invisible.
1774 	 */
1775 	if (intel_plane_can_remap(plane_state) &&
1776 	    !plane_state->uapi.visible)
1777 		return 0;
1778 
1779 	/* FIXME other color planes? */
1780 	stride = plane_state->view.color_plane[0].mapping_stride;
1781 	max_stride = plane->max_stride(plane, fb->format->format,
1782 				       fb->modifier, rotation);
1783 
1784 	if (stride > max_stride) {
1785 		DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
1786 			      fb->base.id, stride,
1787 			      plane->base.base.id, plane->base.name, max_stride);
1788 		return -EINVAL;
1789 	}
1790 
1791 	return 0;
1792 }
1793 
1794 int intel_plane_compute_gtt(struct intel_plane_state *plane_state)
1795 {
1796 	const struct intel_framebuffer *fb =
1797 		to_intel_framebuffer(plane_state->hw.fb);
1798 	unsigned int rotation = plane_state->hw.rotation;
1799 
1800 	if (!fb)
1801 		return 0;
1802 
1803 	if (intel_plane_needs_remap(plane_state)) {
1804 		intel_plane_remap_gtt(plane_state);
1805 
1806 		/*
1807 		 * Sometimes even remapping can't overcome
1808 		 * the stride limitations :( Can happen with
1809 		 * big plane sizes and suitably misaligned
1810 		 * offsets.
1811 		 */
1812 		return intel_plane_check_stride(plane_state);
1813 	}
1814 
1815 	intel_fb_fill_view(fb, rotation, &plane_state->view);
1816 
1817 	/* Rotate src coordinates to match rotated GTT view */
1818 	if (drm_rotation_90_or_270(rotation))
1819 		drm_rect_rotate(&plane_state->uapi.src,
1820 				fb->base.width << 16, fb->base.height << 16,
1821 				DRM_MODE_ROTATE_270);
1822 
1823 	return intel_plane_check_stride(plane_state);
1824 }
1825 
1826 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1827 {
1828 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1829 
1830 	drm_framebuffer_cleanup(fb);
1831 
1832 	if (intel_fb_uses_dpt(fb))
1833 		intel_dpt_destroy(intel_fb->dpt_vm);
1834 
1835 	intel_frontbuffer_put(intel_fb->frontbuffer);
1836 
1837 	kfree(intel_fb);
1838 }
1839 
1840 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1841 						struct drm_file *file,
1842 						unsigned int *handle)
1843 {
1844 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1845 	struct drm_i915_private *i915 = to_i915(obj->base.dev);
1846 
1847 	if (i915_gem_object_is_userptr(obj)) {
1848 		drm_dbg(&i915->drm,
1849 			"attempting to use a userptr for a framebuffer, denied\n");
1850 		return -EINVAL;
1851 	}
1852 
1853 	return drm_gem_handle_create(file, &obj->base, handle);
1854 }
1855 
1856 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
1857 					struct drm_file *file,
1858 					unsigned int flags, unsigned int color,
1859 					struct drm_clip_rect *clips,
1860 					unsigned int num_clips)
1861 {
1862 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1863 
1864 	i915_gem_object_flush_if_display(obj);
1865 	intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
1866 
1867 	return 0;
1868 }
1869 
1870 static const struct drm_framebuffer_funcs intel_fb_funcs = {
1871 	.destroy = intel_user_framebuffer_destroy,
1872 	.create_handle = intel_user_framebuffer_create_handle,
1873 	.dirty = intel_user_framebuffer_dirty,
1874 };
1875 
1876 int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
1877 			   struct drm_i915_gem_object *obj,
1878 			   struct drm_mode_fb_cmd2 *mode_cmd)
1879 {
1880 	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
1881 	struct drm_framebuffer *fb = &intel_fb->base;
1882 	u32 max_stride;
1883 	unsigned int tiling, stride;
1884 	int ret = -EINVAL;
1885 	int i;
1886 
1887 	intel_fb->frontbuffer = intel_frontbuffer_get(obj);
1888 	if (!intel_fb->frontbuffer)
1889 		return -ENOMEM;
1890 
1891 	i915_gem_object_lock(obj, NULL);
1892 	tiling = i915_gem_object_get_tiling(obj);
1893 	stride = i915_gem_object_get_stride(obj);
1894 	i915_gem_object_unlock(obj);
1895 
1896 	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
1897 		/*
1898 		 * If there's a fence, enforce that
1899 		 * the fb modifier and tiling mode match.
1900 		 */
1901 		if (tiling != I915_TILING_NONE &&
1902 		    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
1903 			drm_dbg_kms(&dev_priv->drm,
1904 				    "tiling_mode doesn't match fb modifier\n");
1905 			goto err;
1906 		}
1907 	} else {
1908 		if (tiling == I915_TILING_X) {
1909 			mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
1910 		} else if (tiling == I915_TILING_Y) {
1911 			drm_dbg_kms(&dev_priv->drm,
1912 				    "No Y tiling for legacy addfb\n");
1913 			goto err;
1914 		}
1915 	}
1916 
1917 	if (!drm_any_plane_has_format(&dev_priv->drm,
1918 				      mode_cmd->pixel_format,
1919 				      mode_cmd->modifier[0])) {
1920 		drm_dbg_kms(&dev_priv->drm,
1921 			    "unsupported pixel format %p4cc / modifier 0x%llx\n",
1922 			    &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1923 		goto err;
1924 	}
1925 
1926 	/*
1927 	 * gen2/3 display engine uses the fence if present,
1928 	 * so the tiling mode must match the fb modifier exactly.
1929 	 */
1930 	if (DISPLAY_VER(dev_priv) < 4 &&
1931 	    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
1932 		drm_dbg_kms(&dev_priv->drm,
1933 			    "tiling_mode must match fb modifier exactly on gen2/3\n");
1934 		goto err;
1935 	}
1936 
1937 	max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
1938 					 mode_cmd->modifier[0]);
1939 	if (mode_cmd->pitches[0] > max_stride) {
1940 		drm_dbg_kms(&dev_priv->drm,
1941 			    "%s pitch (%u) must be at most %d\n",
1942 			    mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
1943 			    "tiled" : "linear",
1944 			    mode_cmd->pitches[0], max_stride);
1945 		goto err;
1946 	}
1947 
1948 	/*
1949 	 * If there's a fence, enforce that
1950 	 * the fb pitch and fence stride match.
1951 	 */
1952 	if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
1953 		drm_dbg_kms(&dev_priv->drm,
1954 			    "pitch (%d) must match tiling stride (%d)\n",
1955 			    mode_cmd->pitches[0], stride);
1956 		goto err;
1957 	}
1958 
1959 	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
1960 	if (mode_cmd->offsets[0] != 0) {
1961 		drm_dbg_kms(&dev_priv->drm,
1962 			    "plane 0 offset (0x%08x) must be 0\n",
1963 			    mode_cmd->offsets[0]);
1964 		goto err;
1965 	}
1966 
1967 	drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
1968 
1969 	for (i = 0; i < fb->format->num_planes; i++) {
1970 		u32 stride_alignment;
1971 
1972 		if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1973 			drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
1974 				    i);
1975 			goto err;
1976 		}
1977 
1978 		stride_alignment = intel_fb_stride_alignment(fb, i);
1979 		if (fb->pitches[i] & (stride_alignment - 1)) {
1980 			drm_dbg_kms(&dev_priv->drm,
1981 				    "plane %d pitch (%d) must be at least %u byte aligned\n",
1982 				    i, fb->pitches[i], stride_alignment);
1983 			goto err;
1984 		}
1985 
1986 		if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) {
1987 			int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i);
1988 
1989 			if (fb->pitches[i] != ccs_aux_stride) {
1990 				drm_dbg_kms(&dev_priv->drm,
1991 					    "ccs aux plane %d pitch (%d) must be %d\n",
1992 					    i,
1993 					    fb->pitches[i], ccs_aux_stride);
1994 				goto err;
1995 			}
1996 		}
1997 
1998 		fb->obj[i] = &obj->base;
1999 	}
2000 
2001 	ret = intel_fill_fb_info(dev_priv, intel_fb);
2002 	if (ret)
2003 		goto err;
2004 
2005 	if (intel_fb_uses_dpt(fb)) {
2006 		struct i915_address_space *vm;
2007 
2008 		vm = intel_dpt_create(intel_fb);
2009 		if (IS_ERR(vm)) {
2010 			drm_dbg_kms(&dev_priv->drm, "failed to create DPT\n");
2011 			ret = PTR_ERR(vm);
2012 			goto err;
2013 		}
2014 
2015 		intel_fb->dpt_vm = vm;
2016 	}
2017 
2018 	ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
2019 	if (ret) {
2020 		drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
2021 		goto err_free_dpt;
2022 	}
2023 
2024 	return 0;
2025 
2026 err_free_dpt:
2027 	if (intel_fb_uses_dpt(fb))
2028 		intel_dpt_destroy(intel_fb->dpt_vm);
2029 err:
2030 	intel_frontbuffer_put(intel_fb->frontbuffer);
2031 	return ret;
2032 }
2033 
2034 struct drm_framebuffer *
2035 intel_user_framebuffer_create(struct drm_device *dev,
2036 			      struct drm_file *filp,
2037 			      const struct drm_mode_fb_cmd2 *user_mode_cmd)
2038 {
2039 	struct drm_framebuffer *fb;
2040 	struct drm_i915_gem_object *obj;
2041 	struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
2042 	struct drm_i915_private *i915;
2043 
2044 	obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
2045 	if (!obj)
2046 		return ERR_PTR(-ENOENT);
2047 
2048 	/* object is backed with LMEM for discrete */
2049 	i915 = to_i915(obj->base.dev);
2050 	if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) {
2051 		/* object is "remote", not in local memory */
2052 		i915_gem_object_put(obj);
2053 		drm_dbg_kms(&i915->drm, "framebuffer must reside in local memory\n");
2054 		return ERR_PTR(-EREMOTE);
2055 	}
2056 
2057 	fb = intel_framebuffer_create(obj, &mode_cmd);
2058 	i915_gem_object_put(obj);
2059 
2060 	return fb;
2061 }
2062 
2063 struct drm_framebuffer *
2064 intel_framebuffer_create(struct drm_i915_gem_object *obj,
2065 			 struct drm_mode_fb_cmd2 *mode_cmd)
2066 {
2067 	struct intel_framebuffer *intel_fb;
2068 	int ret;
2069 
2070 	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2071 	if (!intel_fb)
2072 		return ERR_PTR(-ENOMEM);
2073 
2074 	ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
2075 	if (ret)
2076 		goto err;
2077 
2078 	return &intel_fb->base;
2079 
2080 err:
2081 	kfree(intel_fb);
2082 	return ERR_PTR(ret);
2083 }
2084