1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include <drm/drm_framebuffer.h> 7 8 #include "intel_display.h" 9 #include "intel_display_types.h" 10 #include "intel_fb.h" 11 12 #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a)) 13 14 bool is_ccs_plane(const struct drm_framebuffer *fb, int plane) 15 { 16 if (!is_ccs_modifier(fb->modifier)) 17 return false; 18 19 return plane >= fb->format->num_planes / 2; 20 } 21 22 bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane) 23 { 24 return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); 25 } 26 27 bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane) 28 { 29 return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC && 30 plane == 2; 31 } 32 33 bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) 34 { 35 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 36 color_plane == 1; 37 } 38 39 bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) 40 { 41 return fb->modifier == DRM_FORMAT_MOD_LINEAR || 42 is_gen12_ccs_plane(fb, color_plane); 43 } 44 45 int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) 46 { 47 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) || 48 (main_plane && main_plane >= fb->format->num_planes / 2)); 49 50 return fb->format->num_planes / 2 + main_plane; 51 } 52 53 int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) 54 { 55 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) || 56 ccs_plane < fb->format->num_planes / 2); 57 58 if (is_gen12_ccs_cc_plane(fb, ccs_plane)) 59 return 0; 60 61 return ccs_plane - fb->format->num_planes / 2; 62 } 63 64 int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) 65 { 66 struct drm_i915_private *i915 = to_i915(fb->dev); 67 68 if (is_ccs_modifier(fb->modifier)) 69 return main_to_ccs_plane(fb, main_plane); 70 else if (DISPLAY_VER(i915) < 11 && 71 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 72 return 1; 73 else 74 return 0; 75 } 76 77 unsigned int intel_tile_size(const struct drm_i915_private *i915) 78 { 79 return DISPLAY_VER(i915) == 2 ? 2048 : 4096; 80 } 81 82 unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane) 83 { 84 if (is_gen12_ccs_plane(fb, color_plane)) 85 return 1; 86 87 return intel_tile_size(to_i915(fb->dev)) / 88 intel_tile_width_bytes(fb, color_plane); 89 } 90 91 /* Return the tile dimensions in pixel units */ 92 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane, 93 unsigned int *tile_width, 94 unsigned int *tile_height) 95 { 96 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane); 97 unsigned int cpp = fb->format->cpp[color_plane]; 98 99 *tile_width = tile_width_bytes / cpp; 100 *tile_height = intel_tile_height(fb, color_plane); 101 } 102 103 unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane) 104 { 105 unsigned int tile_width, tile_height; 106 107 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 108 109 return fb->pitches[color_plane] * tile_height; 110 } 111 112 unsigned int intel_cursor_alignment(const struct drm_i915_private *i915) 113 { 114 if (IS_I830(i915)) 115 return 16 * 1024; 116 else if (IS_I85X(i915)) 117 return 256; 118 else if (IS_I845G(i915) || IS_I865G(i915)) 119 return 32; 120 else 121 return 4 * 1024; 122 } 123 124 void intel_fb_plane_get_subsampling(int *hsub, int *vsub, 125 const struct drm_framebuffer *fb, 126 int color_plane) 127 { 128 int main_plane; 129 130 if (color_plane == 0) { 131 *hsub = 1; 132 *vsub = 1; 133 134 return; 135 } 136 137 /* 138 * TODO: Deduct the subsampling from the char block for all CCS 139 * formats and planes. 140 */ 141 if (!is_gen12_ccs_plane(fb, color_plane)) { 142 *hsub = fb->format->hsub; 143 *vsub = fb->format->vsub; 144 145 return; 146 } 147 148 main_plane = skl_ccs_to_main_plane(fb, color_plane); 149 *hsub = drm_format_info_block_width(fb->format, color_plane) / 150 drm_format_info_block_width(fb->format, main_plane); 151 152 /* 153 * The min stride check in the core framebuffer_check() function 154 * assumes that format->hsub applies to every plane except for the 155 * first plane. That's incorrect for the CCS AUX plane of the first 156 * plane, but for the above check to pass we must define the block 157 * width with that subsampling applied to it. Adjust the width here 158 * accordingly, so we can calculate the actual subsampling factor. 159 */ 160 if (main_plane == 0) 161 *hsub *= fb->format->hsub; 162 163 *vsub = 32; 164 } 165 166 static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h) 167 { 168 int main_plane = is_ccs_plane(&fb->base, color_plane) ? 169 skl_ccs_to_main_plane(&fb->base, color_plane) : 0; 170 int main_hsub, main_vsub; 171 int hsub, vsub; 172 173 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane); 174 intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane); 175 *w = fb->base.width / main_hsub / hsub; 176 *h = fb->base.height / main_vsub / vsub; 177 } 178 179 static u32 intel_adjust_tile_offset(int *x, int *y, 180 unsigned int tile_width, 181 unsigned int tile_height, 182 unsigned int tile_size, 183 unsigned int pitch_tiles, 184 u32 old_offset, 185 u32 new_offset) 186 { 187 unsigned int pitch_pixels = pitch_tiles * tile_width; 188 unsigned int tiles; 189 190 WARN_ON(old_offset & (tile_size - 1)); 191 WARN_ON(new_offset & (tile_size - 1)); 192 WARN_ON(new_offset > old_offset); 193 194 tiles = (old_offset - new_offset) / tile_size; 195 196 *y += tiles / pitch_tiles * tile_height; 197 *x += tiles % pitch_tiles * tile_width; 198 199 /* minimize x in case it got needlessly big */ 200 *y += *x / pitch_pixels * tile_height; 201 *x %= pitch_pixels; 202 203 return new_offset; 204 } 205 206 static u32 intel_adjust_aligned_offset(int *x, int *y, 207 const struct drm_framebuffer *fb, 208 int color_plane, 209 unsigned int rotation, 210 unsigned int pitch, 211 u32 old_offset, u32 new_offset) 212 { 213 struct drm_i915_private *i915 = to_i915(fb->dev); 214 unsigned int cpp = fb->format->cpp[color_plane]; 215 216 drm_WARN_ON(&i915->drm, new_offset > old_offset); 217 218 if (!is_surface_linear(fb, color_plane)) { 219 unsigned int tile_size, tile_width, tile_height; 220 unsigned int pitch_tiles; 221 222 tile_size = intel_tile_size(i915); 223 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 224 225 if (drm_rotation_90_or_270(rotation)) { 226 pitch_tiles = pitch / tile_height; 227 swap(tile_width, tile_height); 228 } else { 229 pitch_tiles = pitch / (tile_width * cpp); 230 } 231 232 intel_adjust_tile_offset(x, y, tile_width, tile_height, 233 tile_size, pitch_tiles, 234 old_offset, new_offset); 235 } else { 236 old_offset += *y * pitch + *x * cpp; 237 238 *y = (old_offset - new_offset) / pitch; 239 *x = ((old_offset - new_offset) - *y * pitch) / cpp; 240 } 241 242 return new_offset; 243 } 244 245 /* 246 * Adjust the tile offset by moving the difference into 247 * the x/y offsets. 248 */ 249 u32 intel_plane_adjust_aligned_offset(int *x, int *y, 250 const struct intel_plane_state *state, 251 int color_plane, 252 u32 old_offset, u32 new_offset) 253 { 254 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane, 255 state->hw.rotation, 256 state->view.color_plane[color_plane].stride, 257 old_offset, new_offset); 258 } 259 260 /* 261 * Computes the aligned offset to the base tile and adjusts 262 * x, y. bytes per pixel is assumed to be a power-of-two. 263 * 264 * In the 90/270 rotated case, x and y are assumed 265 * to be already rotated to match the rotated GTT view, and 266 * pitch is the tile_height aligned framebuffer height. 267 * 268 * This function is used when computing the derived information 269 * under intel_framebuffer, so using any of that information 270 * here is not allowed. Anything under drm_framebuffer can be 271 * used. This is why the user has to pass in the pitch since it 272 * is specified in the rotated orientation. 273 */ 274 static u32 intel_compute_aligned_offset(struct drm_i915_private *i915, 275 int *x, int *y, 276 const struct drm_framebuffer *fb, 277 int color_plane, 278 unsigned int pitch, 279 unsigned int rotation, 280 u32 alignment) 281 { 282 unsigned int cpp = fb->format->cpp[color_plane]; 283 u32 offset, offset_aligned; 284 285 if (!is_surface_linear(fb, color_plane)) { 286 unsigned int tile_size, tile_width, tile_height; 287 unsigned int tile_rows, tiles, pitch_tiles; 288 289 tile_size = intel_tile_size(i915); 290 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 291 292 if (drm_rotation_90_or_270(rotation)) { 293 pitch_tiles = pitch / tile_height; 294 swap(tile_width, tile_height); 295 } else { 296 pitch_tiles = pitch / (tile_width * cpp); 297 } 298 299 tile_rows = *y / tile_height; 300 *y %= tile_height; 301 302 tiles = *x / tile_width; 303 *x %= tile_width; 304 305 offset = (tile_rows * pitch_tiles + tiles) * tile_size; 306 307 offset_aligned = offset; 308 if (alignment) 309 offset_aligned = rounddown(offset_aligned, alignment); 310 311 intel_adjust_tile_offset(x, y, tile_width, tile_height, 312 tile_size, pitch_tiles, 313 offset, offset_aligned); 314 } else { 315 offset = *y * pitch + *x * cpp; 316 offset_aligned = offset; 317 if (alignment) { 318 offset_aligned = rounddown(offset_aligned, alignment); 319 *y = (offset % alignment) / pitch; 320 *x = ((offset % alignment) - *y * pitch) / cpp; 321 } else { 322 *y = *x = 0; 323 } 324 } 325 326 return offset_aligned; 327 } 328 329 u32 intel_plane_compute_aligned_offset(int *x, int *y, 330 const struct intel_plane_state *state, 331 int color_plane) 332 { 333 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane); 334 struct drm_i915_private *i915 = to_i915(intel_plane->base.dev); 335 const struct drm_framebuffer *fb = state->hw.fb; 336 unsigned int rotation = state->hw.rotation; 337 int pitch = state->view.color_plane[color_plane].stride; 338 u32 alignment; 339 340 if (intel_plane->id == PLANE_CURSOR) 341 alignment = intel_cursor_alignment(i915); 342 else 343 alignment = intel_surf_alignment(fb, color_plane); 344 345 return intel_compute_aligned_offset(i915, x, y, fb, color_plane, 346 pitch, rotation, alignment); 347 } 348 349 /* Convert the fb->offset[] into x/y offsets */ 350 static int intel_fb_offset_to_xy(int *x, int *y, 351 const struct drm_framebuffer *fb, 352 int color_plane) 353 { 354 struct drm_i915_private *i915 = to_i915(fb->dev); 355 unsigned int height; 356 u32 alignment; 357 358 if (DISPLAY_VER(i915) >= 12 && 359 is_semiplanar_uv_plane(fb, color_plane)) 360 alignment = intel_tile_row_size(fb, color_plane); 361 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) 362 alignment = intel_tile_size(i915); 363 else 364 alignment = 0; 365 366 if (alignment != 0 && fb->offsets[color_plane] % alignment) { 367 drm_dbg_kms(&i915->drm, 368 "Misaligned offset 0x%08x for color plane %d\n", 369 fb->offsets[color_plane], color_plane); 370 return -EINVAL; 371 } 372 373 height = drm_framebuffer_plane_height(fb->height, fb, color_plane); 374 height = ALIGN(height, intel_tile_height(fb, color_plane)); 375 376 /* Catch potential overflows early */ 377 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]), 378 fb->offsets[color_plane])) { 379 drm_dbg_kms(&i915->drm, 380 "Bad offset 0x%08x or pitch %d for color plane %d\n", 381 fb->offsets[color_plane], fb->pitches[color_plane], 382 color_plane); 383 return -ERANGE; 384 } 385 386 *x = 0; 387 *y = 0; 388 389 intel_adjust_aligned_offset(x, y, 390 fb, color_plane, DRM_MODE_ROTATE_0, 391 fb->pitches[color_plane], 392 fb->offsets[color_plane], 0); 393 394 return 0; 395 } 396 397 static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y) 398 { 399 struct drm_i915_private *i915 = to_i915(fb->dev); 400 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 401 int main_plane; 402 int hsub, vsub; 403 int tile_width, tile_height; 404 int ccs_x, ccs_y; 405 int main_x, main_y; 406 407 if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane)) 408 return 0; 409 410 intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height); 411 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 412 413 tile_width *= hsub; 414 tile_height *= vsub; 415 416 ccs_x = (x * hsub) % tile_width; 417 ccs_y = (y * vsub) % tile_height; 418 419 main_plane = skl_ccs_to_main_plane(fb, ccs_plane); 420 main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width; 421 main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height; 422 423 /* 424 * CCS doesn't have its own x/y offset register, so the intra CCS tile 425 * x/y offsets must match between CCS and the main surface. 426 */ 427 if (main_x != ccs_x || main_y != ccs_y) { 428 drm_dbg_kms(&i915->drm, 429 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", 430 main_x, main_y, 431 ccs_x, ccs_y, 432 intel_fb->normal_view.color_plane[main_plane].x, 433 intel_fb->normal_view.color_plane[main_plane].y, 434 x, y); 435 return -EINVAL; 436 } 437 438 return 0; 439 } 440 441 static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) 442 { 443 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 444 struct drm_i915_private *i915 = to_i915(plane->base.dev); 445 const struct drm_framebuffer *fb = plane_state->hw.fb; 446 int i; 447 448 /* We don't want to deal with remapping with cursors */ 449 if (plane->id == PLANE_CURSOR) 450 return false; 451 452 /* 453 * The display engine limits already match/exceed the 454 * render engine limits, so not much point in remapping. 455 * Would also need to deal with the fence POT alignment 456 * and gen2 2KiB GTT tile size. 457 */ 458 if (DISPLAY_VER(i915) < 4) 459 return false; 460 461 /* 462 * The new CCS hash mode isn't compatible with remapping as 463 * the virtual address of the pages affects the compressed data. 464 */ 465 if (is_ccs_modifier(fb->modifier)) 466 return false; 467 468 /* Linear needs a page aligned stride for remapping */ 469 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { 470 unsigned int alignment = intel_tile_size(i915) - 1; 471 472 for (i = 0; i < fb->format->num_planes; i++) { 473 if (fb->pitches[i] & alignment) 474 return false; 475 } 476 } 477 478 return true; 479 } 480 481 bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) 482 { 483 struct drm_i915_private *i915 = to_i915(fb->base.dev); 484 485 return IS_ALDERLAKE_P(i915) && fb->base.modifier != DRM_FORMAT_MOD_LINEAR && 486 !is_ccs_modifier(fb->base.modifier); 487 } 488 489 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation) 490 { 491 if (drm_rotation_90_or_270(rotation)) 492 return fb->rotated_view.color_plane[color_plane].stride; 493 else if (intel_fb_needs_pot_stride_remap(fb)) 494 return fb->remapped_view.color_plane[color_plane].stride; 495 else 496 return fb->normal_view.color_plane[color_plane].stride; 497 } 498 499 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) 500 { 501 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 502 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); 503 unsigned int rotation = plane_state->hw.rotation; 504 u32 stride, max_stride; 505 506 /* 507 * No remapping for invisible planes since we don't have 508 * an actual source viewport to remap. 509 */ 510 if (!plane_state->uapi.visible) 511 return false; 512 513 if (!intel_plane_can_remap(plane_state)) 514 return false; 515 516 /* 517 * FIXME: aux plane limits on gen9+ are 518 * unclear in Bspec, for now no checking. 519 */ 520 stride = intel_fb_pitch(fb, 0, rotation); 521 max_stride = plane->max_stride(plane, fb->base.format->format, 522 fb->base.modifier, rotation); 523 524 return stride > max_stride; 525 } 526 527 static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane, 528 int plane_width, int *x, int *y) 529 { 530 struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base); 531 int ret; 532 533 ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane); 534 if (ret) { 535 drm_dbg_kms(fb->base.dev, 536 "bad fb plane %d offset: 0x%x\n", 537 color_plane, fb->base.offsets[color_plane]); 538 return ret; 539 } 540 541 ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y); 542 if (ret) 543 return ret; 544 545 /* 546 * The fence (if used) is aligned to the start of the object 547 * so having the framebuffer wrap around across the edge of the 548 * fenced region doesn't really work. We have no API to configure 549 * the fence start offset within the object (nor could we probably 550 * on gen2/3). So it's just easier if we just require that the 551 * fb layout agrees with the fence layout. We already check that the 552 * fb stride matches the fence stride elsewhere. 553 */ 554 if (color_plane == 0 && i915_gem_object_is_tiled(obj) && 555 (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) { 556 drm_dbg_kms(fb->base.dev, 557 "bad fb plane %d offset: 0x%x\n", 558 color_plane, fb->base.offsets[color_plane]); 559 return -EINVAL; 560 } 561 562 return 0; 563 } 564 565 static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y) 566 { 567 struct drm_i915_private *i915 = to_i915(fb->base.dev); 568 unsigned int tile_size = intel_tile_size(i915); 569 u32 offset; 570 571 offset = intel_compute_aligned_offset(i915, x, y, &fb->base, color_plane, 572 fb->base.pitches[color_plane], 573 DRM_MODE_ROTATE_0, 574 tile_size); 575 576 return offset / tile_size; 577 } 578 579 struct fb_plane_view_dims { 580 unsigned int width, height; 581 unsigned int tile_width, tile_height; 582 }; 583 584 static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane, 585 unsigned int width, unsigned int height, 586 struct fb_plane_view_dims *dims) 587 { 588 dims->width = width; 589 dims->height = height; 590 591 intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height); 592 } 593 594 static unsigned int 595 plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 596 const struct fb_plane_view_dims *dims) 597 { 598 return DIV_ROUND_UP(fb->base.pitches[color_plane], 599 dims->tile_width * fb->base.format->cpp[color_plane]); 600 } 601 602 static unsigned int 603 plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 604 unsigned int pitch_tiles) 605 { 606 if (intel_fb_needs_pot_stride_remap(fb)) 607 /* 608 * ADL_P, the only platform needing a POT stride has a minimum 609 * of 8 stride tiles. 610 */ 611 return roundup_pow_of_two(max(pitch_tiles, 8u)); 612 else 613 return pitch_tiles; 614 } 615 616 static unsigned int 617 plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane, 618 const struct fb_plane_view_dims *dims, 619 int x) 620 { 621 return DIV_ROUND_UP(x + dims->width, dims->tile_width); 622 } 623 624 static unsigned int 625 plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane, 626 const struct fb_plane_view_dims *dims, 627 int y) 628 { 629 return DIV_ROUND_UP(y + dims->height, dims->tile_height); 630 } 631 632 #define assign_chk_ovf(i915, var, val) ({ \ 633 drm_WARN_ON(&(i915)->drm, overflows_type(val, var)); \ 634 (var) = (val); \ 635 }) 636 637 static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane, 638 const struct fb_plane_view_dims *dims, 639 u32 obj_offset, u32 gtt_offset, int x, int y, 640 struct intel_fb_view *view) 641 { 642 struct drm_i915_private *i915 = to_i915(fb->base.dev); 643 struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane]; 644 struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane]; 645 unsigned int tile_width = dims->tile_width; 646 unsigned int tile_height = dims->tile_height; 647 unsigned int tile_size = intel_tile_size(i915); 648 struct drm_rect r; 649 u32 size; 650 651 assign_chk_ovf(i915, remap_info->offset, obj_offset); 652 assign_chk_ovf(i915, remap_info->src_stride, plane_view_src_stride_tiles(fb, color_plane, dims)); 653 assign_chk_ovf(i915, remap_info->width, plane_view_width_tiles(fb, color_plane, dims, x)); 654 assign_chk_ovf(i915, remap_info->height, plane_view_height_tiles(fb, color_plane, dims, y)); 655 656 if (view->gtt.type == I915_GGTT_VIEW_ROTATED) { 657 check_array_bounds(i915, view->gtt.rotated.plane, color_plane); 658 659 assign_chk_ovf(i915, remap_info->dst_stride, 660 plane_view_dst_stride_tiles(fb, color_plane, remap_info->height)); 661 662 /* rotate the x/y offsets to match the GTT view */ 663 drm_rect_init(&r, x, y, dims->width, dims->height); 664 drm_rect_rotate(&r, 665 remap_info->width * tile_width, 666 remap_info->height * tile_height, 667 DRM_MODE_ROTATE_270); 668 669 color_plane_info->x = r.x1; 670 color_plane_info->y = r.y1; 671 672 color_plane_info->stride = remap_info->dst_stride * tile_height; 673 674 size = remap_info->dst_stride * remap_info->width; 675 676 /* rotate the tile dimensions to match the GTT view */ 677 swap(tile_width, tile_height); 678 } else { 679 drm_WARN_ON(&i915->drm, view->gtt.type != I915_GGTT_VIEW_REMAPPED); 680 681 check_array_bounds(i915, view->gtt.remapped.plane, color_plane); 682 683 assign_chk_ovf(i915, remap_info->dst_stride, 684 plane_view_dst_stride_tiles(fb, color_plane, remap_info->width)); 685 686 color_plane_info->x = x; 687 color_plane_info->y = y; 688 689 color_plane_info->stride = remap_info->dst_stride * tile_width * 690 fb->base.format->cpp[color_plane]; 691 692 size = remap_info->dst_stride * remap_info->height; 693 } 694 695 /* 696 * We only keep the x/y offsets, so push all of the gtt offset into 697 * the x/y offsets. x,y will hold the first pixel of the framebuffer 698 * plane from the start of the remapped/rotated gtt mapping. 699 */ 700 intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y, 701 tile_width, tile_height, 702 tile_size, remap_info->dst_stride, 703 gtt_offset * tile_size, 0); 704 705 return size; 706 } 707 708 #undef assign_chk_ovf 709 710 /* Return number of tiles @color_plane needs. */ 711 static unsigned int 712 calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane, 713 const struct fb_plane_view_dims *dims, 714 int x, int y) 715 { 716 struct drm_i915_private *i915 = to_i915(fb->base.dev); 717 unsigned int tiles; 718 719 if (is_surface_linear(&fb->base, color_plane)) { 720 unsigned int size; 721 722 size = (y + dims->height) * fb->base.pitches[color_plane] + 723 x * fb->base.format->cpp[color_plane]; 724 tiles = DIV_ROUND_UP(size, intel_tile_size(i915)); 725 } else { 726 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) * 727 plane_view_height_tiles(fb, color_plane, dims, y); 728 /* 729 * If the plane isn't horizontally tile aligned, 730 * we need one more tile. 731 */ 732 if (x != 0) 733 tiles++; 734 } 735 736 return tiles; 737 } 738 739 static void intel_fb_view_init(struct intel_fb_view *view, enum i915_ggtt_view_type view_type) 740 { 741 memset(view, 0, sizeof(*view)); 742 view->gtt.type = view_type; 743 } 744 745 bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) 746 { 747 if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13) 748 return false; 749 750 return fb->base.modifier == I915_FORMAT_MOD_Y_TILED || 751 fb->base.modifier == I915_FORMAT_MOD_Yf_TILED; 752 } 753 754 int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb) 755 { 756 struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base); 757 u32 gtt_offset_rotated = 0; 758 u32 gtt_offset_remapped = 0; 759 unsigned int max_size = 0; 760 int i, num_planes = fb->base.format->num_planes; 761 unsigned int tile_size = intel_tile_size(i915); 762 763 intel_fb_view_init(&fb->normal_view, I915_GGTT_VIEW_NORMAL); 764 765 drm_WARN_ON(&i915->drm, 766 intel_fb_supports_90_270_rotation(fb) && 767 intel_fb_needs_pot_stride_remap(fb)); 768 769 if (intel_fb_supports_90_270_rotation(fb)) 770 intel_fb_view_init(&fb->rotated_view, I915_GGTT_VIEW_ROTATED); 771 if (intel_fb_needs_pot_stride_remap(fb)) 772 intel_fb_view_init(&fb->remapped_view, I915_GGTT_VIEW_REMAPPED); 773 774 for (i = 0; i < num_planes; i++) { 775 struct fb_plane_view_dims view_dims; 776 unsigned int width, height; 777 unsigned int cpp, size; 778 u32 offset; 779 int x, y; 780 int ret; 781 782 /* 783 * Plane 2 of Render Compression with Clear Color fb modifier 784 * is consumed by the driver and not passed to DE. Skip the 785 * arithmetic related to alignment and offset calculation. 786 */ 787 if (is_gen12_ccs_cc_plane(&fb->base, i)) { 788 if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE)) 789 continue; 790 else 791 return -EINVAL; 792 } 793 794 cpp = fb->base.format->cpp[i]; 795 intel_fb_plane_dims(fb, i, &width, &height); 796 797 ret = convert_plane_offset_to_xy(fb, i, width, &x, &y); 798 if (ret) 799 return ret; 800 801 init_plane_view_dims(fb, i, width, height, &view_dims); 802 803 /* 804 * First pixel of the framebuffer from 805 * the start of the normal gtt mapping. 806 */ 807 fb->normal_view.color_plane[i].x = x; 808 fb->normal_view.color_plane[i].y = y; 809 fb->normal_view.color_plane[i].stride = fb->base.pitches[i]; 810 811 offset = calc_plane_aligned_offset(fb, i, &x, &y); 812 813 if (intel_fb_supports_90_270_rotation(fb)) 814 gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims, 815 offset, gtt_offset_rotated, x, y, 816 &fb->rotated_view); 817 818 if (intel_fb_needs_pot_stride_remap(fb)) 819 gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims, 820 offset, gtt_offset_remapped, x, y, 821 &fb->remapped_view); 822 823 size = calc_plane_normal_size(fb, i, &view_dims, x, y); 824 /* how many tiles in total needed in the bo */ 825 max_size = max(max_size, offset + size); 826 } 827 828 if (mul_u32_u32(max_size, tile_size) > obj->base.size) { 829 drm_dbg_kms(&i915->drm, 830 "fb too big for bo (need %llu bytes, have %zu bytes)\n", 831 mul_u32_u32(max_size, tile_size), obj->base.size); 832 return -EINVAL; 833 } 834 835 return 0; 836 } 837 838 static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) 839 { 840 struct drm_i915_private *i915 = 841 to_i915(plane_state->uapi.plane->dev); 842 struct drm_framebuffer *fb = plane_state->hw.fb; 843 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 844 unsigned int rotation = plane_state->hw.rotation; 845 int i, num_planes = fb->format->num_planes; 846 unsigned int src_x, src_y; 847 unsigned int src_w, src_h; 848 u32 gtt_offset = 0; 849 850 intel_fb_view_init(&plane_state->view, 851 drm_rotation_90_or_270(rotation) ? I915_GGTT_VIEW_ROTATED : 852 I915_GGTT_VIEW_REMAPPED); 853 854 src_x = plane_state->uapi.src.x1 >> 16; 855 src_y = plane_state->uapi.src.y1 >> 16; 856 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 857 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 858 859 drm_WARN_ON(&i915->drm, is_ccs_modifier(fb->modifier)); 860 861 /* Make src coordinates relative to the viewport */ 862 drm_rect_translate(&plane_state->uapi.src, 863 -(src_x << 16), -(src_y << 16)); 864 865 /* Rotate src coordinates to match rotated GTT view */ 866 if (drm_rotation_90_or_270(rotation)) 867 drm_rect_rotate(&plane_state->uapi.src, 868 src_w << 16, src_h << 16, 869 DRM_MODE_ROTATE_270); 870 871 for (i = 0; i < num_planes; i++) { 872 unsigned int hsub = i ? fb->format->hsub : 1; 873 unsigned int vsub = i ? fb->format->vsub : 1; 874 struct fb_plane_view_dims view_dims; 875 unsigned int width, height; 876 unsigned int x, y; 877 u32 offset; 878 879 x = src_x / hsub; 880 y = src_y / vsub; 881 width = src_w / hsub; 882 height = src_h / vsub; 883 884 init_plane_view_dims(intel_fb, i, width, height, &view_dims); 885 886 /* 887 * First pixel of the src viewport from the 888 * start of the normal gtt mapping. 889 */ 890 x += intel_fb->normal_view.color_plane[i].x; 891 y += intel_fb->normal_view.color_plane[i].y; 892 893 offset = calc_plane_aligned_offset(intel_fb, i, &x, &y); 894 895 gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims, 896 offset, gtt_offset, x, y, 897 &plane_state->view); 898 } 899 } 900 901 void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation, 902 struct intel_fb_view *view) 903 { 904 if (drm_rotation_90_or_270(rotation)) 905 *view = fb->rotated_view; 906 else if (intel_fb_needs_pot_stride_remap(fb)) 907 *view = fb->remapped_view; 908 else 909 *view = fb->normal_view; 910 } 911 912 static int intel_plane_check_stride(const struct intel_plane_state *plane_state) 913 { 914 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 915 const struct drm_framebuffer *fb = plane_state->hw.fb; 916 unsigned int rotation = plane_state->hw.rotation; 917 u32 stride, max_stride; 918 919 /* 920 * We ignore stride for all invisible planes that 921 * can be remapped. Otherwise we could end up 922 * with a false positive when the remapping didn't 923 * kick in due the plane being invisible. 924 */ 925 if (intel_plane_can_remap(plane_state) && 926 !plane_state->uapi.visible) 927 return 0; 928 929 /* FIXME other color planes? */ 930 stride = plane_state->view.color_plane[0].stride; 931 max_stride = plane->max_stride(plane, fb->format->format, 932 fb->modifier, rotation); 933 934 if (stride > max_stride) { 935 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n", 936 fb->base.id, stride, 937 plane->base.base.id, plane->base.name, max_stride); 938 return -EINVAL; 939 } 940 941 return 0; 942 } 943 944 int intel_plane_compute_gtt(struct intel_plane_state *plane_state) 945 { 946 const struct intel_framebuffer *fb = 947 to_intel_framebuffer(plane_state->hw.fb); 948 unsigned int rotation = plane_state->hw.rotation; 949 950 if (!fb) 951 return 0; 952 953 if (intel_plane_needs_remap(plane_state)) { 954 intel_plane_remap_gtt(plane_state); 955 956 /* 957 * Sometimes even remapping can't overcome 958 * the stride limitations :( Can happen with 959 * big plane sizes and suitably misaligned 960 * offsets. 961 */ 962 return intel_plane_check_stride(plane_state); 963 } 964 965 intel_fb_fill_view(fb, rotation, &plane_state->view); 966 967 /* Rotate src coordinates to match rotated GTT view */ 968 if (drm_rotation_90_or_270(rotation)) 969 drm_rect_rotate(&plane_state->uapi.src, 970 fb->base.width << 16, fb->base.height << 16, 971 DRM_MODE_ROTATE_270); 972 973 return intel_plane_check_stride(plane_state); 974 } 975