1 /*
2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2007 Intel Corporation
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *	Eric Anholt <eric@anholt.net>
26  */
27 
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/i915_drm.h>
34 
35 #include "i915_drv.h"
36 #include "intel_connector.h"
37 #include "intel_display_types.h"
38 #include "intel_dvo.h"
39 #include "intel_dvo_dev.h"
40 #include "intel_gmbus.h"
41 #include "intel_panel.h"
42 
43 #define INTEL_DVO_CHIP_NONE	0
44 #define INTEL_DVO_CHIP_LVDS	1
45 #define INTEL_DVO_CHIP_TMDS	2
46 #define INTEL_DVO_CHIP_TVOUT	4
47 
48 #define SIL164_ADDR	0x38
49 #define CH7xxx_ADDR	0x76
50 #define TFP410_ADDR	0x38
51 #define NS2501_ADDR     0x38
52 
53 static const struct intel_dvo_device intel_dvo_devices[] = {
54 	{
55 		.type = INTEL_DVO_CHIP_TMDS,
56 		.name = "sil164",
57 		.dvo_reg = DVOC,
58 		.dvo_srcdim_reg = DVOC_SRCDIM,
59 		.slave_addr = SIL164_ADDR,
60 		.dev_ops = &sil164_ops,
61 	},
62 	{
63 		.type = INTEL_DVO_CHIP_TMDS,
64 		.name = "ch7xxx",
65 		.dvo_reg = DVOC,
66 		.dvo_srcdim_reg = DVOC_SRCDIM,
67 		.slave_addr = CH7xxx_ADDR,
68 		.dev_ops = &ch7xxx_ops,
69 	},
70 	{
71 		.type = INTEL_DVO_CHIP_TMDS,
72 		.name = "ch7xxx",
73 		.dvo_reg = DVOC,
74 		.dvo_srcdim_reg = DVOC_SRCDIM,
75 		.slave_addr = 0x75, /* For some ch7010 */
76 		.dev_ops = &ch7xxx_ops,
77 	},
78 	{
79 		.type = INTEL_DVO_CHIP_LVDS,
80 		.name = "ivch",
81 		.dvo_reg = DVOA,
82 		.dvo_srcdim_reg = DVOA_SRCDIM,
83 		.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
84 		.dev_ops = &ivch_ops,
85 	},
86 	{
87 		.type = INTEL_DVO_CHIP_TMDS,
88 		.name = "tfp410",
89 		.dvo_reg = DVOC,
90 		.dvo_srcdim_reg = DVOC_SRCDIM,
91 		.slave_addr = TFP410_ADDR,
92 		.dev_ops = &tfp410_ops,
93 	},
94 	{
95 		.type = INTEL_DVO_CHIP_LVDS,
96 		.name = "ch7017",
97 		.dvo_reg = DVOC,
98 		.dvo_srcdim_reg = DVOC_SRCDIM,
99 		.slave_addr = 0x75,
100 		.gpio = GMBUS_PIN_DPB,
101 		.dev_ops = &ch7017_ops,
102 	},
103 	{
104 	        .type = INTEL_DVO_CHIP_TMDS,
105 		.name = "ns2501",
106 		.dvo_reg = DVOB,
107 		.dvo_srcdim_reg = DVOB_SRCDIM,
108 		.slave_addr = NS2501_ADDR,
109 		.dev_ops = &ns2501_ops,
110        }
111 };
112 
113 struct intel_dvo {
114 	struct intel_encoder base;
115 
116 	struct intel_dvo_device dev;
117 
118 	struct intel_connector *attached_connector;
119 
120 	bool panel_wants_dither;
121 };
122 
123 static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder)
124 {
125 	return container_of(encoder, struct intel_dvo, base);
126 }
127 
128 static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector)
129 {
130 	return enc_to_dvo(intel_attached_encoder(connector));
131 }
132 
133 static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
134 {
135 	struct drm_device *dev = connector->base.dev;
136 	struct drm_i915_private *dev_priv = to_i915(dev);
137 	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
138 	u32 tmp;
139 
140 	tmp = I915_READ(intel_dvo->dev.dvo_reg);
141 
142 	if (!(tmp & DVO_ENABLE))
143 		return false;
144 
145 	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
146 }
147 
148 static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
149 				   enum pipe *pipe)
150 {
151 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
152 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
153 	u32 tmp;
154 
155 	tmp = I915_READ(intel_dvo->dev.dvo_reg);
156 
157 	*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
158 
159 	return tmp & DVO_ENABLE;
160 }
161 
162 static void intel_dvo_get_config(struct intel_encoder *encoder,
163 				 struct intel_crtc_state *pipe_config)
164 {
165 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
166 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
167 	u32 tmp, flags = 0;
168 
169 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);
170 
171 	tmp = I915_READ(intel_dvo->dev.dvo_reg);
172 	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
173 		flags |= DRM_MODE_FLAG_PHSYNC;
174 	else
175 		flags |= DRM_MODE_FLAG_NHSYNC;
176 	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
177 		flags |= DRM_MODE_FLAG_PVSYNC;
178 	else
179 		flags |= DRM_MODE_FLAG_NVSYNC;
180 
181 	pipe_config->base.adjusted_mode.flags |= flags;
182 
183 	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
184 }
185 
186 static void intel_disable_dvo(struct intel_encoder *encoder,
187 			      const struct intel_crtc_state *old_crtc_state,
188 			      const struct drm_connector_state *old_conn_state)
189 {
190 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
191 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
192 	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
193 	u32 temp = I915_READ(dvo_reg);
194 
195 	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
196 	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
197 	I915_READ(dvo_reg);
198 }
199 
200 static void intel_enable_dvo(struct intel_encoder *encoder,
201 			     const struct intel_crtc_state *pipe_config,
202 			     const struct drm_connector_state *conn_state)
203 {
204 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
205 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
206 	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
207 	u32 temp = I915_READ(dvo_reg);
208 
209 	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
210 					 &pipe_config->base.mode,
211 					 &pipe_config->base.adjusted_mode);
212 
213 	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
214 	I915_READ(dvo_reg);
215 
216 	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
217 }
218 
219 static enum drm_mode_status
220 intel_dvo_mode_valid(struct drm_connector *connector,
221 		     struct drm_display_mode *mode)
222 {
223 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
224 	const struct drm_display_mode *fixed_mode =
225 		to_intel_connector(connector)->panel.fixed_mode;
226 	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
227 	int target_clock = mode->clock;
228 
229 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
230 		return MODE_NO_DBLESCAN;
231 
232 	/* XXX: Validate clock range */
233 
234 	if (fixed_mode) {
235 		if (mode->hdisplay > fixed_mode->hdisplay)
236 			return MODE_PANEL;
237 		if (mode->vdisplay > fixed_mode->vdisplay)
238 			return MODE_PANEL;
239 
240 		target_clock = fixed_mode->clock;
241 	}
242 
243 	if (target_clock > max_dotclk)
244 		return MODE_CLOCK_HIGH;
245 
246 	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
247 }
248 
249 static int intel_dvo_compute_config(struct intel_encoder *encoder,
250 				    struct intel_crtc_state *pipe_config,
251 				    struct drm_connector_state *conn_state)
252 {
253 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
254 	const struct drm_display_mode *fixed_mode =
255 		intel_dvo->attached_connector->panel.fixed_mode;
256 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
257 
258 	/*
259 	 * If we have timings from the BIOS for the panel, put them in
260 	 * to the adjusted mode.  The CRTC will be set up for this mode,
261 	 * with the panel scaling set up to source from the H/VDisplay
262 	 * of the original mode.
263 	 */
264 	if (fixed_mode)
265 		intel_fixed_panel_mode(fixed_mode, adjusted_mode);
266 
267 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
268 		return -EINVAL;
269 
270 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
271 
272 	return 0;
273 }
274 
275 static void intel_dvo_pre_enable(struct intel_encoder *encoder,
276 				 const struct intel_crtc_state *pipe_config,
277 				 const struct drm_connector_state *conn_state)
278 {
279 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
280 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
281 	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
282 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
283 	int pipe = crtc->pipe;
284 	u32 dvo_val;
285 	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
286 	i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;
287 
288 	/* Save the data order, since I don't know what it should be set to. */
289 	dvo_val = I915_READ(dvo_reg) &
290 		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
291 	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
292 		   DVO_BLANK_ACTIVE_HIGH;
293 
294 	dvo_val |= DVO_PIPE_SEL(pipe);
295 	dvo_val |= DVO_PIPE_STALL;
296 	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
297 		dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
298 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
299 		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
300 
301 	/*I915_WRITE(DVOB_SRCDIM,
302 	  (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
303 	  (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
304 	I915_WRITE(dvo_srcdim_reg,
305 		   (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
306 		   (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
307 	/*I915_WRITE(DVOB, dvo_val);*/
308 	I915_WRITE(dvo_reg, dvo_val);
309 }
310 
311 static enum drm_connector_status
312 intel_dvo_detect(struct drm_connector *connector, bool force)
313 {
314 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
315 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
316 		      connector->base.id, connector->name);
317 	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
318 }
319 
320 static int intel_dvo_get_modes(struct drm_connector *connector)
321 {
322 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
323 	const struct drm_display_mode *fixed_mode =
324 		to_intel_connector(connector)->panel.fixed_mode;
325 
326 	/*
327 	 * We should probably have an i2c driver get_modes function for those
328 	 * devices which will have a fixed set of modes determined by the chip
329 	 * (TV-out, for example), but for now with just TMDS and LVDS,
330 	 * that's not the case.
331 	 */
332 	intel_ddc_get_modes(connector,
333 			    intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC));
334 	if (!list_empty(&connector->probed_modes))
335 		return 1;
336 
337 	if (fixed_mode) {
338 		struct drm_display_mode *mode;
339 		mode = drm_mode_duplicate(connector->dev, fixed_mode);
340 		if (mode) {
341 			drm_mode_probed_add(connector, mode);
342 			return 1;
343 		}
344 	}
345 
346 	return 0;
347 }
348 
349 static const struct drm_connector_funcs intel_dvo_connector_funcs = {
350 	.detect = intel_dvo_detect,
351 	.late_register = intel_connector_register,
352 	.early_unregister = intel_connector_unregister,
353 	.destroy = intel_connector_destroy,
354 	.fill_modes = drm_helper_probe_single_connector_modes,
355 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
356 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
357 };
358 
359 static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
360 	.mode_valid = intel_dvo_mode_valid,
361 	.get_modes = intel_dvo_get_modes,
362 };
363 
364 static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
365 {
366 	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));
367 
368 	if (intel_dvo->dev.dev_ops->destroy)
369 		intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
370 
371 	intel_encoder_destroy(encoder);
372 }
373 
374 static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
375 	.destroy = intel_dvo_enc_destroy,
376 };
377 
378 /*
379  * Attempts to get a fixed panel timing for LVDS (currently only the i830).
380  *
381  * Other chips with DVO LVDS will need to extend this to deal with the LVDS
382  * chip being on DVOB/C and having multiple pipes.
383  */
384 static struct drm_display_mode *
385 intel_dvo_get_current_mode(struct intel_encoder *encoder)
386 {
387 	struct drm_display_mode *mode;
388 
389 	mode = intel_encoder_current_mode(encoder);
390 	if (mode) {
391 		DRM_DEBUG_KMS("using current (BIOS) mode: ");
392 		drm_mode_debug_printmodeline(mode);
393 		mode->type |= DRM_MODE_TYPE_PREFERRED;
394 	}
395 
396 	return mode;
397 }
398 
399 static enum port intel_dvo_port(i915_reg_t dvo_reg)
400 {
401 	if (i915_mmio_reg_equal(dvo_reg, DVOA))
402 		return PORT_A;
403 	else if (i915_mmio_reg_equal(dvo_reg, DVOB))
404 		return PORT_B;
405 	else
406 		return PORT_C;
407 }
408 
409 void intel_dvo_init(struct drm_i915_private *dev_priv)
410 {
411 	struct intel_encoder *intel_encoder;
412 	struct intel_dvo *intel_dvo;
413 	struct intel_connector *intel_connector;
414 	int i;
415 	int encoder_type = DRM_MODE_ENCODER_NONE;
416 
417 	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
418 	if (!intel_dvo)
419 		return;
420 
421 	intel_connector = intel_connector_alloc();
422 	if (!intel_connector) {
423 		kfree(intel_dvo);
424 		return;
425 	}
426 
427 	intel_dvo->attached_connector = intel_connector;
428 
429 	intel_encoder = &intel_dvo->base;
430 
431 	intel_encoder->disable = intel_disable_dvo;
432 	intel_encoder->enable = intel_enable_dvo;
433 	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
434 	intel_encoder->get_config = intel_dvo_get_config;
435 	intel_encoder->compute_config = intel_dvo_compute_config;
436 	intel_encoder->pre_enable = intel_dvo_pre_enable;
437 	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
438 
439 	/* Now, try to find a controller */
440 	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
441 		struct drm_connector *connector = &intel_connector->base;
442 		const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
443 		struct i2c_adapter *i2c;
444 		int gpio;
445 		bool dvoinit;
446 		enum pipe pipe;
447 		u32 dpll[I915_MAX_PIPES];
448 		enum port port;
449 
450 		/*
451 		 * Allow the I2C driver info to specify the GPIO to be used in
452 		 * special cases, but otherwise default to what's defined
453 		 * in the spec.
454 		 */
455 		if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
456 			gpio = dvo->gpio;
457 		else if (dvo->type == INTEL_DVO_CHIP_LVDS)
458 			gpio = GMBUS_PIN_SSC;
459 		else
460 			gpio = GMBUS_PIN_DPB;
461 
462 		/*
463 		 * Set up the I2C bus necessary for the chip we're probing.
464 		 * It appears that everything is on GPIOE except for panels
465 		 * on i830 laptops, which are on GPIOB (DVOA).
466 		 */
467 		i2c = intel_gmbus_get_adapter(dev_priv, gpio);
468 
469 		intel_dvo->dev = *dvo;
470 
471 		/*
472 		 * GMBUS NAK handling seems to be unstable, hence let the
473 		 * transmitter detection run in bit banging mode for now.
474 		 */
475 		intel_gmbus_force_bit(i2c, true);
476 
477 		/*
478 		 * ns2501 requires the DVO 2x clock before it will
479 		 * respond to i2c accesses, so make sure we have
480 		 * have the clock enabled before we attempt to
481 		 * initialize the device.
482 		 */
483 		for_each_pipe(dev_priv, pipe) {
484 			dpll[pipe] = I915_READ(DPLL(pipe));
485 			I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
486 		}
487 
488 		dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
489 
490 		/* restore the DVO 2x clock state to original */
491 		for_each_pipe(dev_priv, pipe) {
492 			I915_WRITE(DPLL(pipe), dpll[pipe]);
493 		}
494 
495 		intel_gmbus_force_bit(i2c, false);
496 
497 		if (!dvoinit)
498 			continue;
499 
500 		port = intel_dvo_port(dvo->dvo_reg);
501 		drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
502 				 &intel_dvo_enc_funcs, encoder_type,
503 				 "DVO %c", port_name(port));
504 
505 		intel_encoder->type = INTEL_OUTPUT_DVO;
506 		intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
507 		intel_encoder->port = port;
508 		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
509 
510 		switch (dvo->type) {
511 		case INTEL_DVO_CHIP_TMDS:
512 			intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) |
513 				(1 << INTEL_OUTPUT_DVO);
514 			drm_connector_init(&dev_priv->drm, connector,
515 					   &intel_dvo_connector_funcs,
516 					   DRM_MODE_CONNECTOR_DVII);
517 			encoder_type = DRM_MODE_ENCODER_TMDS;
518 			break;
519 		case INTEL_DVO_CHIP_LVDS:
520 			intel_encoder->cloneable = 0;
521 			drm_connector_init(&dev_priv->drm, connector,
522 					   &intel_dvo_connector_funcs,
523 					   DRM_MODE_CONNECTOR_LVDS);
524 			encoder_type = DRM_MODE_ENCODER_LVDS;
525 			break;
526 		}
527 
528 		drm_connector_helper_add(connector,
529 					 &intel_dvo_connector_helper_funcs);
530 		connector->display_info.subpixel_order = SubPixelHorizontalRGB;
531 		connector->interlace_allowed = false;
532 		connector->doublescan_allowed = false;
533 
534 		intel_connector_attach_encoder(intel_connector, intel_encoder);
535 		if (dvo->type == INTEL_DVO_CHIP_LVDS) {
536 			/*
537 			 * For our LVDS chipsets, we should hopefully be able
538 			 * to dig the fixed panel mode out of the BIOS data.
539 			 * However, it's in a different format from the BIOS
540 			 * data on chipsets with integrated LVDS (stored in AIM
541 			 * headers, likely), so for now, just get the current
542 			 * mode being output through DVO.
543 			 */
544 			intel_panel_init(&intel_connector->panel,
545 					 intel_dvo_get_current_mode(intel_encoder),
546 					 NULL);
547 			intel_dvo->panel_wants_dither = true;
548 		}
549 
550 		return;
551 	}
552 
553 	kfree(intel_dvo);
554 	kfree(intel_connector);
555 }
556