1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 */ 27 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 34 #include "i915_drv.h" 35 #include "intel_connector.h" 36 #include "intel_display_types.h" 37 #include "intel_dvo.h" 38 #include "intel_dvo_dev.h" 39 #include "intel_gmbus.h" 40 #include "intel_panel.h" 41 42 #define INTEL_DVO_CHIP_NONE 0 43 #define INTEL_DVO_CHIP_LVDS 1 44 #define INTEL_DVO_CHIP_TMDS 2 45 #define INTEL_DVO_CHIP_TVOUT 4 46 #define INTEL_DVO_CHIP_LVDS_NO_FIXED 5 47 48 #define SIL164_ADDR 0x38 49 #define CH7xxx_ADDR 0x76 50 #define TFP410_ADDR 0x38 51 #define NS2501_ADDR 0x38 52 53 static const struct intel_dvo_device intel_dvo_devices[] = { 54 { 55 .type = INTEL_DVO_CHIP_TMDS, 56 .name = "sil164", 57 .dvo_reg = DVOC, 58 .dvo_srcdim_reg = DVOC_SRCDIM, 59 .slave_addr = SIL164_ADDR, 60 .dev_ops = &sil164_ops, 61 }, 62 { 63 .type = INTEL_DVO_CHIP_TMDS, 64 .name = "ch7xxx", 65 .dvo_reg = DVOC, 66 .dvo_srcdim_reg = DVOC_SRCDIM, 67 .slave_addr = CH7xxx_ADDR, 68 .dev_ops = &ch7xxx_ops, 69 }, 70 { 71 .type = INTEL_DVO_CHIP_TMDS, 72 .name = "ch7xxx", 73 .dvo_reg = DVOC, 74 .dvo_srcdim_reg = DVOC_SRCDIM, 75 .slave_addr = 0x75, /* For some ch7010 */ 76 .dev_ops = &ch7xxx_ops, 77 }, 78 { 79 .type = INTEL_DVO_CHIP_LVDS, 80 .name = "ivch", 81 .dvo_reg = DVOA, 82 .dvo_srcdim_reg = DVOA_SRCDIM, 83 .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ 84 .dev_ops = &ivch_ops, 85 }, 86 { 87 .type = INTEL_DVO_CHIP_TMDS, 88 .name = "tfp410", 89 .dvo_reg = DVOC, 90 .dvo_srcdim_reg = DVOC_SRCDIM, 91 .slave_addr = TFP410_ADDR, 92 .dev_ops = &tfp410_ops, 93 }, 94 { 95 .type = INTEL_DVO_CHIP_LVDS, 96 .name = "ch7017", 97 .dvo_reg = DVOC, 98 .dvo_srcdim_reg = DVOC_SRCDIM, 99 .slave_addr = 0x75, 100 .gpio = GMBUS_PIN_DPB, 101 .dev_ops = &ch7017_ops, 102 }, 103 { 104 .type = INTEL_DVO_CHIP_LVDS_NO_FIXED, 105 .name = "ns2501", 106 .dvo_reg = DVOB, 107 .dvo_srcdim_reg = DVOB_SRCDIM, 108 .slave_addr = NS2501_ADDR, 109 .dev_ops = &ns2501_ops, 110 }, 111 }; 112 113 struct intel_dvo { 114 struct intel_encoder base; 115 116 struct intel_dvo_device dev; 117 118 struct intel_connector *attached_connector; 119 120 bool panel_wants_dither; 121 }; 122 123 static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) 124 { 125 return container_of(encoder, struct intel_dvo, base); 126 } 127 128 static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector) 129 { 130 return enc_to_dvo(intel_attached_encoder(connector)); 131 } 132 133 static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) 134 { 135 struct drm_device *dev = connector->base.dev; 136 struct drm_i915_private *dev_priv = to_i915(dev); 137 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 138 u32 tmp; 139 140 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); 141 142 if (!(tmp & DVO_ENABLE)) 143 return false; 144 145 return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); 146 } 147 148 static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, 149 enum pipe *pipe) 150 { 151 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 152 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 153 u32 tmp; 154 155 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); 156 157 *pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT; 158 159 return tmp & DVO_ENABLE; 160 } 161 162 static void intel_dvo_get_config(struct intel_encoder *encoder, 163 struct intel_crtc_state *pipe_config) 164 { 165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 166 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 167 u32 tmp, flags = 0; 168 169 pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); 170 171 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); 172 if (tmp & DVO_HSYNC_ACTIVE_HIGH) 173 flags |= DRM_MODE_FLAG_PHSYNC; 174 else 175 flags |= DRM_MODE_FLAG_NHSYNC; 176 if (tmp & DVO_VSYNC_ACTIVE_HIGH) 177 flags |= DRM_MODE_FLAG_PVSYNC; 178 else 179 flags |= DRM_MODE_FLAG_NVSYNC; 180 181 pipe_config->hw.adjusted_mode.flags |= flags; 182 183 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 184 } 185 186 static void intel_disable_dvo(struct intel_atomic_state *state, 187 struct intel_encoder *encoder, 188 const struct intel_crtc_state *old_crtc_state, 189 const struct drm_connector_state *old_conn_state) 190 { 191 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 192 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 193 i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; 194 u32 temp = intel_de_read(dev_priv, dvo_reg); 195 196 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); 197 intel_de_write(dev_priv, dvo_reg, temp & ~DVO_ENABLE); 198 intel_de_read(dev_priv, dvo_reg); 199 } 200 201 static void intel_enable_dvo(struct intel_atomic_state *state, 202 struct intel_encoder *encoder, 203 const struct intel_crtc_state *pipe_config, 204 const struct drm_connector_state *conn_state) 205 { 206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 207 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 208 i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; 209 u32 temp = intel_de_read(dev_priv, dvo_reg); 210 211 intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, 212 &pipe_config->hw.mode, 213 &pipe_config->hw.adjusted_mode); 214 215 intel_de_write(dev_priv, dvo_reg, temp | DVO_ENABLE); 216 intel_de_read(dev_priv, dvo_reg); 217 218 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); 219 } 220 221 static enum drm_mode_status 222 intel_dvo_mode_valid(struct drm_connector *connector, 223 struct drm_display_mode *mode) 224 { 225 struct intel_dvo *intel_dvo = intel_attached_dvo(to_intel_connector(connector)); 226 const struct drm_display_mode *fixed_mode = 227 to_intel_connector(connector)->panel.fixed_mode; 228 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 229 int target_clock = mode->clock; 230 231 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 232 return MODE_NO_DBLESCAN; 233 234 /* XXX: Validate clock range */ 235 236 if (fixed_mode) { 237 if (mode->hdisplay > fixed_mode->hdisplay) 238 return MODE_PANEL; 239 if (mode->vdisplay > fixed_mode->vdisplay) 240 return MODE_PANEL; 241 242 target_clock = fixed_mode->clock; 243 } 244 245 if (target_clock > max_dotclk) 246 return MODE_CLOCK_HIGH; 247 248 return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); 249 } 250 251 static int intel_dvo_compute_config(struct intel_encoder *encoder, 252 struct intel_crtc_state *pipe_config, 253 struct drm_connector_state *conn_state) 254 { 255 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 256 const struct drm_display_mode *fixed_mode = 257 intel_dvo->attached_connector->panel.fixed_mode; 258 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 259 260 /* 261 * If we have timings from the BIOS for the panel, put them in 262 * to the adjusted mode. The CRTC will be set up for this mode, 263 * with the panel scaling set up to source from the H/VDisplay 264 * of the original mode. 265 */ 266 if (fixed_mode) 267 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 268 269 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 270 return -EINVAL; 271 272 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 273 274 return 0; 275 } 276 277 static void intel_dvo_pre_enable(struct intel_atomic_state *state, 278 struct intel_encoder *encoder, 279 const struct intel_crtc_state *pipe_config, 280 const struct drm_connector_state *conn_state) 281 { 282 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 283 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 284 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 285 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 286 enum pipe pipe = crtc->pipe; 287 u32 dvo_val; 288 i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; 289 i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg; 290 291 /* Save the data order, since I don't know what it should be set to. */ 292 dvo_val = intel_de_read(dev_priv, dvo_reg) & 293 (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); 294 dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | 295 DVO_BLANK_ACTIVE_HIGH; 296 297 dvo_val |= DVO_PIPE_SEL(pipe); 298 dvo_val |= DVO_PIPE_STALL; 299 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 300 dvo_val |= DVO_HSYNC_ACTIVE_HIGH; 301 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 302 dvo_val |= DVO_VSYNC_ACTIVE_HIGH; 303 304 /*I915_WRITE(DVOB_SRCDIM, 305 (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | 306 (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ 307 intel_de_write(dev_priv, dvo_srcdim_reg, 308 (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); 309 /*I915_WRITE(DVOB, dvo_val);*/ 310 intel_de_write(dev_priv, dvo_reg, dvo_val); 311 } 312 313 static enum drm_connector_status 314 intel_dvo_detect(struct drm_connector *connector, bool force) 315 { 316 struct intel_dvo *intel_dvo = intel_attached_dvo(to_intel_connector(connector)); 317 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 318 connector->base.id, connector->name); 319 return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); 320 } 321 322 static int intel_dvo_get_modes(struct drm_connector *connector) 323 { 324 struct drm_i915_private *dev_priv = to_i915(connector->dev); 325 const struct drm_display_mode *fixed_mode = 326 to_intel_connector(connector)->panel.fixed_mode; 327 328 /* 329 * We should probably have an i2c driver get_modes function for those 330 * devices which will have a fixed set of modes determined by the chip 331 * (TV-out, for example), but for now with just TMDS and LVDS, 332 * that's not the case. 333 */ 334 intel_ddc_get_modes(connector, 335 intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC)); 336 if (!list_empty(&connector->probed_modes)) 337 return 1; 338 339 if (fixed_mode) { 340 struct drm_display_mode *mode; 341 mode = drm_mode_duplicate(connector->dev, fixed_mode); 342 if (mode) { 343 drm_mode_probed_add(connector, mode); 344 return 1; 345 } 346 } 347 348 return 0; 349 } 350 351 static const struct drm_connector_funcs intel_dvo_connector_funcs = { 352 .detect = intel_dvo_detect, 353 .late_register = intel_connector_register, 354 .early_unregister = intel_connector_unregister, 355 .destroy = intel_connector_destroy, 356 .fill_modes = drm_helper_probe_single_connector_modes, 357 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 358 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 359 }; 360 361 static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { 362 .mode_valid = intel_dvo_mode_valid, 363 .get_modes = intel_dvo_get_modes, 364 }; 365 366 static void intel_dvo_enc_destroy(struct drm_encoder *encoder) 367 { 368 struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); 369 370 if (intel_dvo->dev.dev_ops->destroy) 371 intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); 372 373 intel_encoder_destroy(encoder); 374 } 375 376 static const struct drm_encoder_funcs intel_dvo_enc_funcs = { 377 .destroy = intel_dvo_enc_destroy, 378 }; 379 380 /* 381 * Attempts to get a fixed panel timing for LVDS (currently only the i830). 382 * 383 * Other chips with DVO LVDS will need to extend this to deal with the LVDS 384 * chip being on DVOB/C and having multiple pipes. 385 */ 386 static struct drm_display_mode * 387 intel_dvo_get_current_mode(struct intel_encoder *encoder) 388 { 389 struct drm_display_mode *mode; 390 391 mode = intel_encoder_current_mode(encoder); 392 if (mode) { 393 DRM_DEBUG_KMS("using current (BIOS) mode: "); 394 drm_mode_debug_printmodeline(mode); 395 mode->type |= DRM_MODE_TYPE_PREFERRED; 396 } 397 398 return mode; 399 } 400 401 static enum port intel_dvo_port(i915_reg_t dvo_reg) 402 { 403 if (i915_mmio_reg_equal(dvo_reg, DVOA)) 404 return PORT_A; 405 else if (i915_mmio_reg_equal(dvo_reg, DVOB)) 406 return PORT_B; 407 else 408 return PORT_C; 409 } 410 411 void intel_dvo_init(struct drm_i915_private *dev_priv) 412 { 413 struct intel_encoder *intel_encoder; 414 struct intel_dvo *intel_dvo; 415 struct intel_connector *intel_connector; 416 int i; 417 int encoder_type = DRM_MODE_ENCODER_NONE; 418 419 intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL); 420 if (!intel_dvo) 421 return; 422 423 intel_connector = intel_connector_alloc(); 424 if (!intel_connector) { 425 kfree(intel_dvo); 426 return; 427 } 428 429 intel_dvo->attached_connector = intel_connector; 430 431 intel_encoder = &intel_dvo->base; 432 433 intel_encoder->disable = intel_disable_dvo; 434 intel_encoder->enable = intel_enable_dvo; 435 intel_encoder->get_hw_state = intel_dvo_get_hw_state; 436 intel_encoder->get_config = intel_dvo_get_config; 437 intel_encoder->compute_config = intel_dvo_compute_config; 438 intel_encoder->pre_enable = intel_dvo_pre_enable; 439 intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; 440 441 /* Now, try to find a controller */ 442 for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { 443 struct drm_connector *connector = &intel_connector->base; 444 const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; 445 struct i2c_adapter *i2c; 446 int gpio; 447 bool dvoinit; 448 enum pipe pipe; 449 u32 dpll[I915_MAX_PIPES]; 450 enum port port; 451 452 /* 453 * Allow the I2C driver info to specify the GPIO to be used in 454 * special cases, but otherwise default to what's defined 455 * in the spec. 456 */ 457 if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio)) 458 gpio = dvo->gpio; 459 else if (dvo->type == INTEL_DVO_CHIP_LVDS) 460 gpio = GMBUS_PIN_SSC; 461 else 462 gpio = GMBUS_PIN_DPB; 463 464 /* 465 * Set up the I2C bus necessary for the chip we're probing. 466 * It appears that everything is on GPIOE except for panels 467 * on i830 laptops, which are on GPIOB (DVOA). 468 */ 469 i2c = intel_gmbus_get_adapter(dev_priv, gpio); 470 471 intel_dvo->dev = *dvo; 472 473 /* 474 * GMBUS NAK handling seems to be unstable, hence let the 475 * transmitter detection run in bit banging mode for now. 476 */ 477 intel_gmbus_force_bit(i2c, true); 478 479 /* 480 * ns2501 requires the DVO 2x clock before it will 481 * respond to i2c accesses, so make sure we have 482 * have the clock enabled before we attempt to 483 * initialize the device. 484 */ 485 for_each_pipe(dev_priv, pipe) { 486 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); 487 intel_de_write(dev_priv, DPLL(pipe), 488 dpll[pipe] | DPLL_DVO_2X_MODE); 489 } 490 491 dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); 492 493 /* restore the DVO 2x clock state to original */ 494 for_each_pipe(dev_priv, pipe) { 495 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); 496 } 497 498 intel_gmbus_force_bit(i2c, false); 499 500 if (!dvoinit) 501 continue; 502 503 port = intel_dvo_port(dvo->dvo_reg); 504 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 505 &intel_dvo_enc_funcs, encoder_type, 506 "DVO %c", port_name(port)); 507 508 intel_encoder->type = INTEL_OUTPUT_DVO; 509 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 510 intel_encoder->port = port; 511 intel_encoder->pipe_mask = ~0; 512 513 if (dvo->type != INTEL_DVO_CHIP_LVDS) 514 intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) | 515 (1 << INTEL_OUTPUT_DVO); 516 517 switch (dvo->type) { 518 case INTEL_DVO_CHIP_TMDS: 519 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | 520 DRM_CONNECTOR_POLL_DISCONNECT; 521 drm_connector_init(&dev_priv->drm, connector, 522 &intel_dvo_connector_funcs, 523 DRM_MODE_CONNECTOR_DVII); 524 encoder_type = DRM_MODE_ENCODER_TMDS; 525 break; 526 case INTEL_DVO_CHIP_LVDS_NO_FIXED: 527 case INTEL_DVO_CHIP_LVDS: 528 drm_connector_init(&dev_priv->drm, connector, 529 &intel_dvo_connector_funcs, 530 DRM_MODE_CONNECTOR_LVDS); 531 encoder_type = DRM_MODE_ENCODER_LVDS; 532 break; 533 } 534 535 drm_connector_helper_add(connector, 536 &intel_dvo_connector_helper_funcs); 537 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 538 connector->interlace_allowed = false; 539 connector->doublescan_allowed = false; 540 541 intel_connector_attach_encoder(intel_connector, intel_encoder); 542 if (dvo->type == INTEL_DVO_CHIP_LVDS) { 543 /* 544 * For our LVDS chipsets, we should hopefully be able 545 * to dig the fixed panel mode out of the BIOS data. 546 * However, it's in a different format from the BIOS 547 * data on chipsets with integrated LVDS (stored in AIM 548 * headers, likely), so for now, just get the current 549 * mode being output through DVO. 550 */ 551 intel_panel_init(&intel_connector->panel, 552 intel_dvo_get_current_mode(intel_encoder), 553 NULL); 554 intel_dvo->panel_wants_dither = true; 555 } 556 557 return; 558 } 559 560 kfree(intel_dvo); 561 kfree(intel_connector); 562 } 563