1379bc100SJani Nikula /* 2379bc100SJani Nikula * Copyright 2006 Dave Airlie <airlied@linux.ie> 3379bc100SJani Nikula * Copyright © 2006-2007 Intel Corporation 4379bc100SJani Nikula * 5379bc100SJani Nikula * Permission is hereby granted, free of charge, to any person obtaining a 6379bc100SJani Nikula * copy of this software and associated documentation files (the "Software"), 7379bc100SJani Nikula * to deal in the Software without restriction, including without limitation 8379bc100SJani Nikula * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9379bc100SJani Nikula * and/or sell copies of the Software, and to permit persons to whom the 10379bc100SJani Nikula * Software is furnished to do so, subject to the following conditions: 11379bc100SJani Nikula * 12379bc100SJani Nikula * The above copyright notice and this permission notice (including the next 13379bc100SJani Nikula * paragraph) shall be included in all copies or substantial portions of the 14379bc100SJani Nikula * Software. 15379bc100SJani Nikula * 16379bc100SJani Nikula * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17379bc100SJani Nikula * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18379bc100SJani Nikula * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19379bc100SJani Nikula * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20379bc100SJani Nikula * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21379bc100SJani Nikula * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22379bc100SJani Nikula * DEALINGS IN THE SOFTWARE. 23379bc100SJani Nikula * 24379bc100SJani Nikula * Authors: 25379bc100SJani Nikula * Eric Anholt <eric@anholt.net> 26379bc100SJani Nikula */ 27379bc100SJani Nikula 28379bc100SJani Nikula #include <linux/i2c.h> 29379bc100SJani Nikula #include <linux/slab.h> 30379bc100SJani Nikula 31379bc100SJani Nikula #include <drm/drm_atomic_helper.h> 32379bc100SJani Nikula #include <drm/drm_crtc.h> 33379bc100SJani Nikula 34379bc100SJani Nikula #include "i915_drv.h" 35379bc100SJani Nikula #include "intel_connector.h" 367785ae0bSVille Syrjälä #include "intel_de.h" 371d455f8dSJani Nikula #include "intel_display_types.h" 38379bc100SJani Nikula #include "intel_dvo.h" 39379bc100SJani Nikula #include "intel_dvo_dev.h" 40379bc100SJani Nikula #include "intel_gmbus.h" 41379bc100SJani Nikula #include "intel_panel.h" 42379bc100SJani Nikula 43379bc100SJani Nikula #define INTEL_DVO_CHIP_NONE 0 44379bc100SJani Nikula #define INTEL_DVO_CHIP_LVDS 1 45379bc100SJani Nikula #define INTEL_DVO_CHIP_TMDS 2 46379bc100SJani Nikula #define INTEL_DVO_CHIP_TVOUT 4 4745608c50SVille Syrjälä #define INTEL_DVO_CHIP_LVDS_NO_FIXED 5 48379bc100SJani Nikula 49379bc100SJani Nikula #define SIL164_ADDR 0x38 50379bc100SJani Nikula #define CH7xxx_ADDR 0x76 51379bc100SJani Nikula #define TFP410_ADDR 0x38 52379bc100SJani Nikula #define NS2501_ADDR 0x38 53379bc100SJani Nikula 54379bc100SJani Nikula static const struct intel_dvo_device intel_dvo_devices[] = { 55379bc100SJani Nikula { 56379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 57379bc100SJani Nikula .name = "sil164", 58379bc100SJani Nikula .dvo_reg = DVOC, 59379bc100SJani Nikula .dvo_srcdim_reg = DVOC_SRCDIM, 60379bc100SJani Nikula .slave_addr = SIL164_ADDR, 61379bc100SJani Nikula .dev_ops = &sil164_ops, 62379bc100SJani Nikula }, 63379bc100SJani Nikula { 64379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 65379bc100SJani Nikula .name = "ch7xxx", 66379bc100SJani Nikula .dvo_reg = DVOC, 67379bc100SJani Nikula .dvo_srcdim_reg = DVOC_SRCDIM, 68379bc100SJani Nikula .slave_addr = CH7xxx_ADDR, 69379bc100SJani Nikula .dev_ops = &ch7xxx_ops, 70379bc100SJani Nikula }, 71379bc100SJani Nikula { 72379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 73379bc100SJani Nikula .name = "ch7xxx", 74379bc100SJani Nikula .dvo_reg = DVOC, 75379bc100SJani Nikula .dvo_srcdim_reg = DVOC_SRCDIM, 76379bc100SJani Nikula .slave_addr = 0x75, /* For some ch7010 */ 77379bc100SJani Nikula .dev_ops = &ch7xxx_ops, 78379bc100SJani Nikula }, 79379bc100SJani Nikula { 80379bc100SJani Nikula .type = INTEL_DVO_CHIP_LVDS, 81379bc100SJani Nikula .name = "ivch", 82379bc100SJani Nikula .dvo_reg = DVOA, 83379bc100SJani Nikula .dvo_srcdim_reg = DVOA_SRCDIM, 84379bc100SJani Nikula .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ 85379bc100SJani Nikula .dev_ops = &ivch_ops, 86379bc100SJani Nikula }, 87379bc100SJani Nikula { 88379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 89379bc100SJani Nikula .name = "tfp410", 90379bc100SJani Nikula .dvo_reg = DVOC, 91379bc100SJani Nikula .dvo_srcdim_reg = DVOC_SRCDIM, 92379bc100SJani Nikula .slave_addr = TFP410_ADDR, 93379bc100SJani Nikula .dev_ops = &tfp410_ops, 94379bc100SJani Nikula }, 95379bc100SJani Nikula { 96379bc100SJani Nikula .type = INTEL_DVO_CHIP_LVDS, 97379bc100SJani Nikula .name = "ch7017", 98379bc100SJani Nikula .dvo_reg = DVOC, 99379bc100SJani Nikula .dvo_srcdim_reg = DVOC_SRCDIM, 100379bc100SJani Nikula .slave_addr = 0x75, 101379bc100SJani Nikula .gpio = GMBUS_PIN_DPB, 102379bc100SJani Nikula .dev_ops = &ch7017_ops, 103379bc100SJani Nikula }, 104379bc100SJani Nikula { 10545608c50SVille Syrjälä .type = INTEL_DVO_CHIP_LVDS_NO_FIXED, 106379bc100SJani Nikula .name = "ns2501", 107379bc100SJani Nikula .dvo_reg = DVOB, 108379bc100SJani Nikula .dvo_srcdim_reg = DVOB_SRCDIM, 109379bc100SJani Nikula .slave_addr = NS2501_ADDR, 110379bc100SJani Nikula .dev_ops = &ns2501_ops, 11145608c50SVille Syrjälä }, 112379bc100SJani Nikula }; 113379bc100SJani Nikula 114379bc100SJani Nikula struct intel_dvo { 115379bc100SJani Nikula struct intel_encoder base; 116379bc100SJani Nikula 117379bc100SJani Nikula struct intel_dvo_device dev; 118379bc100SJani Nikula 119379bc100SJani Nikula struct intel_connector *attached_connector; 120379bc100SJani Nikula 121379bc100SJani Nikula bool panel_wants_dither; 122379bc100SJani Nikula }; 123379bc100SJani Nikula 124379bc100SJani Nikula static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) 125379bc100SJani Nikula { 126379bc100SJani Nikula return container_of(encoder, struct intel_dvo, base); 127379bc100SJani Nikula } 128379bc100SJani Nikula 12943a6d19cSVille Syrjälä static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector) 130379bc100SJani Nikula { 131379bc100SJani Nikula return enc_to_dvo(intel_attached_encoder(connector)); 132379bc100SJani Nikula } 133379bc100SJani Nikula 134379bc100SJani Nikula static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) 135379bc100SJani Nikula { 136379bc100SJani Nikula struct drm_device *dev = connector->base.dev; 137379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(dev); 13843a6d19cSVille Syrjälä struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 139379bc100SJani Nikula u32 tmp; 140379bc100SJani Nikula 1413f7c376dSJani Nikula tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); 142379bc100SJani Nikula 143379bc100SJani Nikula if (!(tmp & DVO_ENABLE)) 144379bc100SJani Nikula return false; 145379bc100SJani Nikula 146379bc100SJani Nikula return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); 147379bc100SJani Nikula } 148379bc100SJani Nikula 149379bc100SJani Nikula static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, 150379bc100SJani Nikula enum pipe *pipe) 151379bc100SJani Nikula { 152379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 153379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 154379bc100SJani Nikula u32 tmp; 155379bc100SJani Nikula 1563f7c376dSJani Nikula tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); 157379bc100SJani Nikula 158379bc100SJani Nikula *pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT; 159379bc100SJani Nikula 160379bc100SJani Nikula return tmp & DVO_ENABLE; 161379bc100SJani Nikula } 162379bc100SJani Nikula 163379bc100SJani Nikula static void intel_dvo_get_config(struct intel_encoder *encoder, 164379bc100SJani Nikula struct intel_crtc_state *pipe_config) 165379bc100SJani Nikula { 166379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 167379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 168379bc100SJani Nikula u32 tmp, flags = 0; 169379bc100SJani Nikula 170379bc100SJani Nikula pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); 171379bc100SJani Nikula 1723f7c376dSJani Nikula tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); 173379bc100SJani Nikula if (tmp & DVO_HSYNC_ACTIVE_HIGH) 174379bc100SJani Nikula flags |= DRM_MODE_FLAG_PHSYNC; 175379bc100SJani Nikula else 176379bc100SJani Nikula flags |= DRM_MODE_FLAG_NHSYNC; 177379bc100SJani Nikula if (tmp & DVO_VSYNC_ACTIVE_HIGH) 178379bc100SJani Nikula flags |= DRM_MODE_FLAG_PVSYNC; 179379bc100SJani Nikula else 180379bc100SJani Nikula flags |= DRM_MODE_FLAG_NVSYNC; 181379bc100SJani Nikula 1821326a92cSMaarten Lankhorst pipe_config->hw.adjusted_mode.flags |= flags; 183379bc100SJani Nikula 1841326a92cSMaarten Lankhorst pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 185379bc100SJani Nikula } 186379bc100SJani Nikula 187ede9771dSVille Syrjälä static void intel_disable_dvo(struct intel_atomic_state *state, 188ede9771dSVille Syrjälä struct intel_encoder *encoder, 189379bc100SJani Nikula const struct intel_crtc_state *old_crtc_state, 190379bc100SJani Nikula const struct drm_connector_state *old_conn_state) 191379bc100SJani Nikula { 192379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 193379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 194379bc100SJani Nikula i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; 1953f7c376dSJani Nikula u32 temp = intel_de_read(dev_priv, dvo_reg); 196379bc100SJani Nikula 197379bc100SJani Nikula intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); 1983f7c376dSJani Nikula intel_de_write(dev_priv, dvo_reg, temp & ~DVO_ENABLE); 1993f7c376dSJani Nikula intel_de_read(dev_priv, dvo_reg); 200379bc100SJani Nikula } 201379bc100SJani Nikula 202ede9771dSVille Syrjälä static void intel_enable_dvo(struct intel_atomic_state *state, 203ede9771dSVille Syrjälä struct intel_encoder *encoder, 204379bc100SJani Nikula const struct intel_crtc_state *pipe_config, 205379bc100SJani Nikula const struct drm_connector_state *conn_state) 206379bc100SJani Nikula { 207379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 208379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 209379bc100SJani Nikula i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; 2103f7c376dSJani Nikula u32 temp = intel_de_read(dev_priv, dvo_reg); 211379bc100SJani Nikula 212379bc100SJani Nikula intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, 2131326a92cSMaarten Lankhorst &pipe_config->hw.mode, 2141326a92cSMaarten Lankhorst &pipe_config->hw.adjusted_mode); 215379bc100SJani Nikula 2163f7c376dSJani Nikula intel_de_write(dev_priv, dvo_reg, temp | DVO_ENABLE); 2173f7c376dSJani Nikula intel_de_read(dev_priv, dvo_reg); 218379bc100SJani Nikula 219379bc100SJani Nikula intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); 220379bc100SJani Nikula } 221379bc100SJani Nikula 222379bc100SJani Nikula static enum drm_mode_status 223379bc100SJani Nikula intel_dvo_mode_valid(struct drm_connector *connector, 224379bc100SJani Nikula struct drm_display_mode *mode) 225379bc100SJani Nikula { 226*8a567b11SVille Syrjälä struct intel_connector *intel_connector = to_intel_connector(connector); 227*8a567b11SVille Syrjälä struct intel_dvo *intel_dvo = intel_attached_dvo(intel_connector); 228379bc100SJani Nikula const struct drm_display_mode *fixed_mode = 229*8a567b11SVille Syrjälä intel_connector->panel.fixed_mode; 230379bc100SJani Nikula int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 231379bc100SJani Nikula int target_clock = mode->clock; 232379bc100SJani Nikula 233379bc100SJani Nikula if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 234379bc100SJani Nikula return MODE_NO_DBLESCAN; 235379bc100SJani Nikula 236379bc100SJani Nikula /* XXX: Validate clock range */ 237379bc100SJani Nikula 238379bc100SJani Nikula if (fixed_mode) { 239*8a567b11SVille Syrjälä enum drm_mode_status status; 240*8a567b11SVille Syrjälä 241*8a567b11SVille Syrjälä status = intel_panel_mode_valid(intel_connector, mode); 242*8a567b11SVille Syrjälä if (status != MODE_OK) 243*8a567b11SVille Syrjälä return status; 244379bc100SJani Nikula 245379bc100SJani Nikula target_clock = fixed_mode->clock; 246379bc100SJani Nikula } 247379bc100SJani Nikula 248379bc100SJani Nikula if (target_clock > max_dotclk) 249379bc100SJani Nikula return MODE_CLOCK_HIGH; 250379bc100SJani Nikula 251379bc100SJani Nikula return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); 252379bc100SJani Nikula } 253379bc100SJani Nikula 254379bc100SJani Nikula static int intel_dvo_compute_config(struct intel_encoder *encoder, 255379bc100SJani Nikula struct intel_crtc_state *pipe_config, 256379bc100SJani Nikula struct drm_connector_state *conn_state) 257379bc100SJani Nikula { 258379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 259379bc100SJani Nikula const struct drm_display_mode *fixed_mode = 260379bc100SJani Nikula intel_dvo->attached_connector->panel.fixed_mode; 2611326a92cSMaarten Lankhorst struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 262379bc100SJani Nikula 263379bc100SJani Nikula /* 264379bc100SJani Nikula * If we have timings from the BIOS for the panel, put them in 265379bc100SJani Nikula * to the adjusted mode. The CRTC will be set up for this mode, 266379bc100SJani Nikula * with the panel scaling set up to source from the H/VDisplay 267379bc100SJani Nikula * of the original mode. 268379bc100SJani Nikula */ 269379bc100SJani Nikula if (fixed_mode) 2704b93f49dSJani Nikula intel_panel_fixed_mode(fixed_mode, adjusted_mode); 271379bc100SJani Nikula 272379bc100SJani Nikula if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 273379bc100SJani Nikula return -EINVAL; 274379bc100SJani Nikula 275379bc100SJani Nikula pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 276379bc100SJani Nikula 277379bc100SJani Nikula return 0; 278379bc100SJani Nikula } 279379bc100SJani Nikula 280ede9771dSVille Syrjälä static void intel_dvo_pre_enable(struct intel_atomic_state *state, 281ede9771dSVille Syrjälä struct intel_encoder *encoder, 282379bc100SJani Nikula const struct intel_crtc_state *pipe_config, 283379bc100SJani Nikula const struct drm_connector_state *conn_state) 284379bc100SJani Nikula { 285379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2862225f3c6SMaarten Lankhorst struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2871326a92cSMaarten Lankhorst const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 288379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 289d048a268SVille Syrjälä enum pipe pipe = crtc->pipe; 290379bc100SJani Nikula u32 dvo_val; 291379bc100SJani Nikula i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; 292379bc100SJani Nikula i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg; 293379bc100SJani Nikula 294379bc100SJani Nikula /* Save the data order, since I don't know what it should be set to. */ 2953f7c376dSJani Nikula dvo_val = intel_de_read(dev_priv, dvo_reg) & 296379bc100SJani Nikula (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); 297379bc100SJani Nikula dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | 298379bc100SJani Nikula DVO_BLANK_ACTIVE_HIGH; 299379bc100SJani Nikula 300379bc100SJani Nikula dvo_val |= DVO_PIPE_SEL(pipe); 301379bc100SJani Nikula dvo_val |= DVO_PIPE_STALL; 302379bc100SJani Nikula if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 303379bc100SJani Nikula dvo_val |= DVO_HSYNC_ACTIVE_HIGH; 304379bc100SJani Nikula if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 305379bc100SJani Nikula dvo_val |= DVO_VSYNC_ACTIVE_HIGH; 306379bc100SJani Nikula 3073f7c376dSJani Nikula intel_de_write(dev_priv, dvo_srcdim_reg, 3083f7c376dSJani Nikula (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); 3093f7c376dSJani Nikula intel_de_write(dev_priv, dvo_reg, dvo_val); 310379bc100SJani Nikula } 311379bc100SJani Nikula 312379bc100SJani Nikula static enum drm_connector_status 313379bc100SJani Nikula intel_dvo_detect(struct drm_connector *connector, bool force) 314379bc100SJani Nikula { 315b81dddb9SVille Syrjälä struct drm_i915_private *i915 = to_i915(connector->dev); 31643a6d19cSVille Syrjälä struct intel_dvo *intel_dvo = intel_attached_dvo(to_intel_connector(connector)); 317b81dddb9SVille Syrjälä 318379bc100SJani Nikula DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 319379bc100SJani Nikula connector->base.id, connector->name); 320b81dddb9SVille Syrjälä 321b81dddb9SVille Syrjälä if (!INTEL_DISPLAY_ENABLED(i915)) 322b81dddb9SVille Syrjälä return connector_status_disconnected; 323b81dddb9SVille Syrjälä 324379bc100SJani Nikula return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); 325379bc100SJani Nikula } 326379bc100SJani Nikula 327379bc100SJani Nikula static int intel_dvo_get_modes(struct drm_connector *connector) 328379bc100SJani Nikula { 329379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(connector->dev); 330379bc100SJani Nikula const struct drm_display_mode *fixed_mode = 331379bc100SJani Nikula to_intel_connector(connector)->panel.fixed_mode; 3324a2236f9SVille Syrjälä int num_modes; 333379bc100SJani Nikula 334379bc100SJani Nikula /* 335379bc100SJani Nikula * We should probably have an i2c driver get_modes function for those 336379bc100SJani Nikula * devices which will have a fixed set of modes determined by the chip 337379bc100SJani Nikula * (TV-out, for example), but for now with just TMDS and LVDS, 338379bc100SJani Nikula * that's not the case. 339379bc100SJani Nikula */ 3404a2236f9SVille Syrjälä num_modes = intel_ddc_get_modes(connector, 341379bc100SJani Nikula intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC)); 3424a2236f9SVille Syrjälä if (num_modes) 3434a2236f9SVille Syrjälä return num_modes; 344379bc100SJani Nikula 345379bc100SJani Nikula if (fixed_mode) { 346379bc100SJani Nikula struct drm_display_mode *mode; 3474a2236f9SVille Syrjälä 348379bc100SJani Nikula mode = drm_mode_duplicate(connector->dev, fixed_mode); 349379bc100SJani Nikula if (mode) { 350379bc100SJani Nikula drm_mode_probed_add(connector, mode); 3514a2236f9SVille Syrjälä num_modes++; 352379bc100SJani Nikula } 353379bc100SJani Nikula } 354379bc100SJani Nikula 3554a2236f9SVille Syrjälä return num_modes; 356379bc100SJani Nikula } 357379bc100SJani Nikula 358379bc100SJani Nikula static const struct drm_connector_funcs intel_dvo_connector_funcs = { 359379bc100SJani Nikula .detect = intel_dvo_detect, 360379bc100SJani Nikula .late_register = intel_connector_register, 361379bc100SJani Nikula .early_unregister = intel_connector_unregister, 362379bc100SJani Nikula .destroy = intel_connector_destroy, 363379bc100SJani Nikula .fill_modes = drm_helper_probe_single_connector_modes, 364379bc100SJani Nikula .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 365379bc100SJani Nikula .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 366379bc100SJani Nikula }; 367379bc100SJani Nikula 368379bc100SJani Nikula static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { 369379bc100SJani Nikula .mode_valid = intel_dvo_mode_valid, 370379bc100SJani Nikula .get_modes = intel_dvo_get_modes, 371379bc100SJani Nikula }; 372379bc100SJani Nikula 373379bc100SJani Nikula static void intel_dvo_enc_destroy(struct drm_encoder *encoder) 374379bc100SJani Nikula { 375379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); 376379bc100SJani Nikula 377379bc100SJani Nikula if (intel_dvo->dev.dev_ops->destroy) 378379bc100SJani Nikula intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); 379379bc100SJani Nikula 380379bc100SJani Nikula intel_encoder_destroy(encoder); 381379bc100SJani Nikula } 382379bc100SJani Nikula 383379bc100SJani Nikula static const struct drm_encoder_funcs intel_dvo_enc_funcs = { 384379bc100SJani Nikula .destroy = intel_dvo_enc_destroy, 385379bc100SJani Nikula }; 386379bc100SJani Nikula 387379bc100SJani Nikula /* 388379bc100SJani Nikula * Attempts to get a fixed panel timing for LVDS (currently only the i830). 389379bc100SJani Nikula * 390379bc100SJani Nikula * Other chips with DVO LVDS will need to extend this to deal with the LVDS 391379bc100SJani Nikula * chip being on DVOB/C and having multiple pipes. 392379bc100SJani Nikula */ 393379bc100SJani Nikula static struct drm_display_mode * 394379bc100SJani Nikula intel_dvo_get_current_mode(struct intel_encoder *encoder) 395379bc100SJani Nikula { 396379bc100SJani Nikula struct drm_display_mode *mode; 397379bc100SJani Nikula 398379bc100SJani Nikula mode = intel_encoder_current_mode(encoder); 399379bc100SJani Nikula if (mode) { 400379bc100SJani Nikula DRM_DEBUG_KMS("using current (BIOS) mode: "); 401379bc100SJani Nikula drm_mode_debug_printmodeline(mode); 402379bc100SJani Nikula mode->type |= DRM_MODE_TYPE_PREFERRED; 403379bc100SJani Nikula } 404379bc100SJani Nikula 405379bc100SJani Nikula return mode; 406379bc100SJani Nikula } 407379bc100SJani Nikula 408379bc100SJani Nikula static enum port intel_dvo_port(i915_reg_t dvo_reg) 409379bc100SJani Nikula { 410379bc100SJani Nikula if (i915_mmio_reg_equal(dvo_reg, DVOA)) 411379bc100SJani Nikula return PORT_A; 412379bc100SJani Nikula else if (i915_mmio_reg_equal(dvo_reg, DVOB)) 413379bc100SJani Nikula return PORT_B; 414379bc100SJani Nikula else 415379bc100SJani Nikula return PORT_C; 416379bc100SJani Nikula } 417379bc100SJani Nikula 418379bc100SJani Nikula void intel_dvo_init(struct drm_i915_private *dev_priv) 419379bc100SJani Nikula { 420379bc100SJani Nikula struct intel_encoder *intel_encoder; 421379bc100SJani Nikula struct intel_dvo *intel_dvo; 422379bc100SJani Nikula struct intel_connector *intel_connector; 423379bc100SJani Nikula int i; 424379bc100SJani Nikula int encoder_type = DRM_MODE_ENCODER_NONE; 425379bc100SJani Nikula 426379bc100SJani Nikula intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL); 427379bc100SJani Nikula if (!intel_dvo) 428379bc100SJani Nikula return; 429379bc100SJani Nikula 430379bc100SJani Nikula intel_connector = intel_connector_alloc(); 431379bc100SJani Nikula if (!intel_connector) { 432379bc100SJani Nikula kfree(intel_dvo); 433379bc100SJani Nikula return; 434379bc100SJani Nikula } 435379bc100SJani Nikula 436379bc100SJani Nikula intel_dvo->attached_connector = intel_connector; 437379bc100SJani Nikula 438379bc100SJani Nikula intel_encoder = &intel_dvo->base; 439379bc100SJani Nikula 440379bc100SJani Nikula intel_encoder->disable = intel_disable_dvo; 441379bc100SJani Nikula intel_encoder->enable = intel_enable_dvo; 442379bc100SJani Nikula intel_encoder->get_hw_state = intel_dvo_get_hw_state; 443379bc100SJani Nikula intel_encoder->get_config = intel_dvo_get_config; 444379bc100SJani Nikula intel_encoder->compute_config = intel_dvo_compute_config; 445379bc100SJani Nikula intel_encoder->pre_enable = intel_dvo_pre_enable; 446379bc100SJani Nikula intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; 447379bc100SJani Nikula 448379bc100SJani Nikula /* Now, try to find a controller */ 449379bc100SJani Nikula for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { 450379bc100SJani Nikula struct drm_connector *connector = &intel_connector->base; 451379bc100SJani Nikula const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; 452379bc100SJani Nikula struct i2c_adapter *i2c; 453379bc100SJani Nikula int gpio; 454379bc100SJani Nikula bool dvoinit; 455379bc100SJani Nikula enum pipe pipe; 456379bc100SJani Nikula u32 dpll[I915_MAX_PIPES]; 457379bc100SJani Nikula enum port port; 458379bc100SJani Nikula 459379bc100SJani Nikula /* 460379bc100SJani Nikula * Allow the I2C driver info to specify the GPIO to be used in 461379bc100SJani Nikula * special cases, but otherwise default to what's defined 462379bc100SJani Nikula * in the spec. 463379bc100SJani Nikula */ 464379bc100SJani Nikula if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio)) 465379bc100SJani Nikula gpio = dvo->gpio; 466379bc100SJani Nikula else if (dvo->type == INTEL_DVO_CHIP_LVDS) 467379bc100SJani Nikula gpio = GMBUS_PIN_SSC; 468379bc100SJani Nikula else 469379bc100SJani Nikula gpio = GMBUS_PIN_DPB; 470379bc100SJani Nikula 471379bc100SJani Nikula /* 472379bc100SJani Nikula * Set up the I2C bus necessary for the chip we're probing. 473379bc100SJani Nikula * It appears that everything is on GPIOE except for panels 474379bc100SJani Nikula * on i830 laptops, which are on GPIOB (DVOA). 475379bc100SJani Nikula */ 476379bc100SJani Nikula i2c = intel_gmbus_get_adapter(dev_priv, gpio); 477379bc100SJani Nikula 478379bc100SJani Nikula intel_dvo->dev = *dvo; 479379bc100SJani Nikula 480379bc100SJani Nikula /* 481379bc100SJani Nikula * GMBUS NAK handling seems to be unstable, hence let the 482379bc100SJani Nikula * transmitter detection run in bit banging mode for now. 483379bc100SJani Nikula */ 484379bc100SJani Nikula intel_gmbus_force_bit(i2c, true); 485379bc100SJani Nikula 486379bc100SJani Nikula /* 487379bc100SJani Nikula * ns2501 requires the DVO 2x clock before it will 488379bc100SJani Nikula * respond to i2c accesses, so make sure we have 489379bc100SJani Nikula * have the clock enabled before we attempt to 490379bc100SJani Nikula * initialize the device. 491379bc100SJani Nikula */ 492379bc100SJani Nikula for_each_pipe(dev_priv, pipe) { 4933f7c376dSJani Nikula dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); 4943f7c376dSJani Nikula intel_de_write(dev_priv, DPLL(pipe), 4953f7c376dSJani Nikula dpll[pipe] | DPLL_DVO_2X_MODE); 496379bc100SJani Nikula } 497379bc100SJani Nikula 498379bc100SJani Nikula dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); 499379bc100SJani Nikula 500379bc100SJani Nikula /* restore the DVO 2x clock state to original */ 501379bc100SJani Nikula for_each_pipe(dev_priv, pipe) { 5023f7c376dSJani Nikula intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); 503379bc100SJani Nikula } 504379bc100SJani Nikula 505379bc100SJani Nikula intel_gmbus_force_bit(i2c, false); 506379bc100SJani Nikula 507379bc100SJani Nikula if (!dvoinit) 508379bc100SJani Nikula continue; 509379bc100SJani Nikula 510379bc100SJani Nikula port = intel_dvo_port(dvo->dvo_reg); 511379bc100SJani Nikula drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 512379bc100SJani Nikula &intel_dvo_enc_funcs, encoder_type, 513379bc100SJani Nikula "DVO %c", port_name(port)); 514379bc100SJani Nikula 515379bc100SJani Nikula intel_encoder->type = INTEL_OUTPUT_DVO; 516379bc100SJani Nikula intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 517379bc100SJani Nikula intel_encoder->port = port; 51834053ee1SVille Syrjälä intel_encoder->pipe_mask = ~0; 519379bc100SJani Nikula 52045608c50SVille Syrjälä if (dvo->type != INTEL_DVO_CHIP_LVDS) 521379bc100SJani Nikula intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) | 522379bc100SJani Nikula (1 << INTEL_OUTPUT_DVO); 52345608c50SVille Syrjälä 52445608c50SVille Syrjälä switch (dvo->type) { 52545608c50SVille Syrjälä case INTEL_DVO_CHIP_TMDS: 52637ec52abSVille Syrjälä intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | 52737ec52abSVille Syrjälä DRM_CONNECTOR_POLL_DISCONNECT; 528379bc100SJani Nikula drm_connector_init(&dev_priv->drm, connector, 529379bc100SJani Nikula &intel_dvo_connector_funcs, 530379bc100SJani Nikula DRM_MODE_CONNECTOR_DVII); 531379bc100SJani Nikula encoder_type = DRM_MODE_ENCODER_TMDS; 532379bc100SJani Nikula break; 53345608c50SVille Syrjälä case INTEL_DVO_CHIP_LVDS_NO_FIXED: 534379bc100SJani Nikula case INTEL_DVO_CHIP_LVDS: 535379bc100SJani Nikula drm_connector_init(&dev_priv->drm, connector, 536379bc100SJani Nikula &intel_dvo_connector_funcs, 537379bc100SJani Nikula DRM_MODE_CONNECTOR_LVDS); 538379bc100SJani Nikula encoder_type = DRM_MODE_ENCODER_LVDS; 539379bc100SJani Nikula break; 540379bc100SJani Nikula } 541379bc100SJani Nikula 542379bc100SJani Nikula drm_connector_helper_add(connector, 543379bc100SJani Nikula &intel_dvo_connector_helper_funcs); 544379bc100SJani Nikula connector->display_info.subpixel_order = SubPixelHorizontalRGB; 545379bc100SJani Nikula connector->interlace_allowed = false; 546379bc100SJani Nikula connector->doublescan_allowed = false; 547379bc100SJani Nikula 548379bc100SJani Nikula intel_connector_attach_encoder(intel_connector, intel_encoder); 549379bc100SJani Nikula if (dvo->type == INTEL_DVO_CHIP_LVDS) { 550379bc100SJani Nikula /* 551379bc100SJani Nikula * For our LVDS chipsets, we should hopefully be able 552379bc100SJani Nikula * to dig the fixed panel mode out of the BIOS data. 553379bc100SJani Nikula * However, it's in a different format from the BIOS 554379bc100SJani Nikula * data on chipsets with integrated LVDS (stored in AIM 555379bc100SJani Nikula * headers, likely), so for now, just get the current 556379bc100SJani Nikula * mode being output through DVO. 557379bc100SJani Nikula */ 558379bc100SJani Nikula intel_panel_init(&intel_connector->panel, 559379bc100SJani Nikula intel_dvo_get_current_mode(intel_encoder), 560379bc100SJani Nikula NULL); 561379bc100SJani Nikula intel_dvo->panel_wants_dither = true; 562379bc100SJani Nikula } 563379bc100SJani Nikula 564379bc100SJani Nikula return; 565379bc100SJani Nikula } 566379bc100SJani Nikula 567379bc100SJani Nikula kfree(intel_dvo); 568379bc100SJani Nikula kfree(intel_connector); 569379bc100SJani Nikula } 570