1379bc100SJani Nikula /* 2379bc100SJani Nikula * Copyright 2006 Dave Airlie <airlied@linux.ie> 3379bc100SJani Nikula * Copyright © 2006-2007 Intel Corporation 4379bc100SJani Nikula * 5379bc100SJani Nikula * Permission is hereby granted, free of charge, to any person obtaining a 6379bc100SJani Nikula * copy of this software and associated documentation files (the "Software"), 7379bc100SJani Nikula * to deal in the Software without restriction, including without limitation 8379bc100SJani Nikula * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9379bc100SJani Nikula * and/or sell copies of the Software, and to permit persons to whom the 10379bc100SJani Nikula * Software is furnished to do so, subject to the following conditions: 11379bc100SJani Nikula * 12379bc100SJani Nikula * The above copyright notice and this permission notice (including the next 13379bc100SJani Nikula * paragraph) shall be included in all copies or substantial portions of the 14379bc100SJani Nikula * Software. 15379bc100SJani Nikula * 16379bc100SJani Nikula * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17379bc100SJani Nikula * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18379bc100SJani Nikula * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19379bc100SJani Nikula * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20379bc100SJani Nikula * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21379bc100SJani Nikula * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22379bc100SJani Nikula * DEALINGS IN THE SOFTWARE. 23379bc100SJani Nikula * 24379bc100SJani Nikula * Authors: 25379bc100SJani Nikula * Eric Anholt <eric@anholt.net> 26379bc100SJani Nikula */ 27379bc100SJani Nikula 28379bc100SJani Nikula #include <linux/i2c.h> 29379bc100SJani Nikula #include <linux/slab.h> 30379bc100SJani Nikula 31379bc100SJani Nikula #include <drm/drm_atomic_helper.h> 32379bc100SJani Nikula #include <drm/drm_crtc.h> 33379bc100SJani Nikula #include <drm/i915_drm.h> 34379bc100SJani Nikula 35379bc100SJani Nikula #include "i915_drv.h" 36379bc100SJani Nikula #include "intel_connector.h" 37379bc100SJani Nikula #include "intel_drv.h" 38379bc100SJani Nikula #include "intel_dvo.h" 39379bc100SJani Nikula #include "intel_dvo_dev.h" 40379bc100SJani Nikula #include "intel_gmbus.h" 41379bc100SJani Nikula #include "intel_panel.h" 42379bc100SJani Nikula 43379bc100SJani Nikula #define INTEL_DVO_CHIP_NONE 0 44379bc100SJani Nikula #define INTEL_DVO_CHIP_LVDS 1 45379bc100SJani Nikula #define INTEL_DVO_CHIP_TMDS 2 46379bc100SJani Nikula #define INTEL_DVO_CHIP_TVOUT 4 47379bc100SJani Nikula 48379bc100SJani Nikula #define SIL164_ADDR 0x38 49379bc100SJani Nikula #define CH7xxx_ADDR 0x76 50379bc100SJani Nikula #define TFP410_ADDR 0x38 51379bc100SJani Nikula #define NS2501_ADDR 0x38 52379bc100SJani Nikula 53379bc100SJani Nikula static const struct intel_dvo_device intel_dvo_devices[] = { 54379bc100SJani Nikula { 55379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 56379bc100SJani Nikula .name = "sil164", 57379bc100SJani Nikula .dvo_reg = DVOC, 58379bc100SJani Nikula .dvo_srcdim_reg = DVOC_SRCDIM, 59379bc100SJani Nikula .slave_addr = SIL164_ADDR, 60379bc100SJani Nikula .dev_ops = &sil164_ops, 61379bc100SJani Nikula }, 62379bc100SJani Nikula { 63379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 64379bc100SJani Nikula .name = "ch7xxx", 65379bc100SJani Nikula .dvo_reg = DVOC, 66379bc100SJani Nikula .dvo_srcdim_reg = DVOC_SRCDIM, 67379bc100SJani Nikula .slave_addr = CH7xxx_ADDR, 68379bc100SJani Nikula .dev_ops = &ch7xxx_ops, 69379bc100SJani Nikula }, 70379bc100SJani Nikula { 71379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 72379bc100SJani Nikula .name = "ch7xxx", 73379bc100SJani Nikula .dvo_reg = DVOC, 74379bc100SJani Nikula .dvo_srcdim_reg = DVOC_SRCDIM, 75379bc100SJani Nikula .slave_addr = 0x75, /* For some ch7010 */ 76379bc100SJani Nikula .dev_ops = &ch7xxx_ops, 77379bc100SJani Nikula }, 78379bc100SJani Nikula { 79379bc100SJani Nikula .type = INTEL_DVO_CHIP_LVDS, 80379bc100SJani Nikula .name = "ivch", 81379bc100SJani Nikula .dvo_reg = DVOA, 82379bc100SJani Nikula .dvo_srcdim_reg = DVOA_SRCDIM, 83379bc100SJani Nikula .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ 84379bc100SJani Nikula .dev_ops = &ivch_ops, 85379bc100SJani Nikula }, 86379bc100SJani Nikula { 87379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 88379bc100SJani Nikula .name = "tfp410", 89379bc100SJani Nikula .dvo_reg = DVOC, 90379bc100SJani Nikula .dvo_srcdim_reg = DVOC_SRCDIM, 91379bc100SJani Nikula .slave_addr = TFP410_ADDR, 92379bc100SJani Nikula .dev_ops = &tfp410_ops, 93379bc100SJani Nikula }, 94379bc100SJani Nikula { 95379bc100SJani Nikula .type = INTEL_DVO_CHIP_LVDS, 96379bc100SJani Nikula .name = "ch7017", 97379bc100SJani Nikula .dvo_reg = DVOC, 98379bc100SJani Nikula .dvo_srcdim_reg = DVOC_SRCDIM, 99379bc100SJani Nikula .slave_addr = 0x75, 100379bc100SJani Nikula .gpio = GMBUS_PIN_DPB, 101379bc100SJani Nikula .dev_ops = &ch7017_ops, 102379bc100SJani Nikula }, 103379bc100SJani Nikula { 104379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 105379bc100SJani Nikula .name = "ns2501", 106379bc100SJani Nikula .dvo_reg = DVOB, 107379bc100SJani Nikula .dvo_srcdim_reg = DVOB_SRCDIM, 108379bc100SJani Nikula .slave_addr = NS2501_ADDR, 109379bc100SJani Nikula .dev_ops = &ns2501_ops, 110379bc100SJani Nikula } 111379bc100SJani Nikula }; 112379bc100SJani Nikula 113379bc100SJani Nikula struct intel_dvo { 114379bc100SJani Nikula struct intel_encoder base; 115379bc100SJani Nikula 116379bc100SJani Nikula struct intel_dvo_device dev; 117379bc100SJani Nikula 118379bc100SJani Nikula struct intel_connector *attached_connector; 119379bc100SJani Nikula 120379bc100SJani Nikula bool panel_wants_dither; 121379bc100SJani Nikula }; 122379bc100SJani Nikula 123379bc100SJani Nikula static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) 124379bc100SJani Nikula { 125379bc100SJani Nikula return container_of(encoder, struct intel_dvo, base); 126379bc100SJani Nikula } 127379bc100SJani Nikula 128379bc100SJani Nikula static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector) 129379bc100SJani Nikula { 130379bc100SJani Nikula return enc_to_dvo(intel_attached_encoder(connector)); 131379bc100SJani Nikula } 132379bc100SJani Nikula 133379bc100SJani Nikula static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) 134379bc100SJani Nikula { 135379bc100SJani Nikula struct drm_device *dev = connector->base.dev; 136379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(dev); 137379bc100SJani Nikula struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base); 138379bc100SJani Nikula u32 tmp; 139379bc100SJani Nikula 140379bc100SJani Nikula tmp = I915_READ(intel_dvo->dev.dvo_reg); 141379bc100SJani Nikula 142379bc100SJani Nikula if (!(tmp & DVO_ENABLE)) 143379bc100SJani Nikula return false; 144379bc100SJani Nikula 145379bc100SJani Nikula return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); 146379bc100SJani Nikula } 147379bc100SJani Nikula 148379bc100SJani Nikula static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, 149379bc100SJani Nikula enum pipe *pipe) 150379bc100SJani Nikula { 151379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 152379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 153379bc100SJani Nikula u32 tmp; 154379bc100SJani Nikula 155379bc100SJani Nikula tmp = I915_READ(intel_dvo->dev.dvo_reg); 156379bc100SJani Nikula 157379bc100SJani Nikula *pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT; 158379bc100SJani Nikula 159379bc100SJani Nikula return tmp & DVO_ENABLE; 160379bc100SJani Nikula } 161379bc100SJani Nikula 162379bc100SJani Nikula static void intel_dvo_get_config(struct intel_encoder *encoder, 163379bc100SJani Nikula struct intel_crtc_state *pipe_config) 164379bc100SJani Nikula { 165379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 166379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 167379bc100SJani Nikula u32 tmp, flags = 0; 168379bc100SJani Nikula 169379bc100SJani Nikula pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); 170379bc100SJani Nikula 171379bc100SJani Nikula tmp = I915_READ(intel_dvo->dev.dvo_reg); 172379bc100SJani Nikula if (tmp & DVO_HSYNC_ACTIVE_HIGH) 173379bc100SJani Nikula flags |= DRM_MODE_FLAG_PHSYNC; 174379bc100SJani Nikula else 175379bc100SJani Nikula flags |= DRM_MODE_FLAG_NHSYNC; 176379bc100SJani Nikula if (tmp & DVO_VSYNC_ACTIVE_HIGH) 177379bc100SJani Nikula flags |= DRM_MODE_FLAG_PVSYNC; 178379bc100SJani Nikula else 179379bc100SJani Nikula flags |= DRM_MODE_FLAG_NVSYNC; 180379bc100SJani Nikula 181379bc100SJani Nikula pipe_config->base.adjusted_mode.flags |= flags; 182379bc100SJani Nikula 183379bc100SJani Nikula pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 184379bc100SJani Nikula } 185379bc100SJani Nikula 186379bc100SJani Nikula static void intel_disable_dvo(struct intel_encoder *encoder, 187379bc100SJani Nikula const struct intel_crtc_state *old_crtc_state, 188379bc100SJani Nikula const struct drm_connector_state *old_conn_state) 189379bc100SJani Nikula { 190379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 191379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 192379bc100SJani Nikula i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; 193379bc100SJani Nikula u32 temp = I915_READ(dvo_reg); 194379bc100SJani Nikula 195379bc100SJani Nikula intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); 196379bc100SJani Nikula I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); 197379bc100SJani Nikula I915_READ(dvo_reg); 198379bc100SJani Nikula } 199379bc100SJani Nikula 200379bc100SJani Nikula static void intel_enable_dvo(struct intel_encoder *encoder, 201379bc100SJani Nikula const struct intel_crtc_state *pipe_config, 202379bc100SJani Nikula const struct drm_connector_state *conn_state) 203379bc100SJani Nikula { 204379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 205379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 206379bc100SJani Nikula i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; 207379bc100SJani Nikula u32 temp = I915_READ(dvo_reg); 208379bc100SJani Nikula 209379bc100SJani Nikula intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, 210379bc100SJani Nikula &pipe_config->base.mode, 211379bc100SJani Nikula &pipe_config->base.adjusted_mode); 212379bc100SJani Nikula 213379bc100SJani Nikula I915_WRITE(dvo_reg, temp | DVO_ENABLE); 214379bc100SJani Nikula I915_READ(dvo_reg); 215379bc100SJani Nikula 216379bc100SJani Nikula intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); 217379bc100SJani Nikula } 218379bc100SJani Nikula 219379bc100SJani Nikula static enum drm_mode_status 220379bc100SJani Nikula intel_dvo_mode_valid(struct drm_connector *connector, 221379bc100SJani Nikula struct drm_display_mode *mode) 222379bc100SJani Nikula { 223379bc100SJani Nikula struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 224379bc100SJani Nikula const struct drm_display_mode *fixed_mode = 225379bc100SJani Nikula to_intel_connector(connector)->panel.fixed_mode; 226379bc100SJani Nikula int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 227379bc100SJani Nikula int target_clock = mode->clock; 228379bc100SJani Nikula 229379bc100SJani Nikula if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 230379bc100SJani Nikula return MODE_NO_DBLESCAN; 231379bc100SJani Nikula 232379bc100SJani Nikula /* XXX: Validate clock range */ 233379bc100SJani Nikula 234379bc100SJani Nikula if (fixed_mode) { 235379bc100SJani Nikula if (mode->hdisplay > fixed_mode->hdisplay) 236379bc100SJani Nikula return MODE_PANEL; 237379bc100SJani Nikula if (mode->vdisplay > fixed_mode->vdisplay) 238379bc100SJani Nikula return MODE_PANEL; 239379bc100SJani Nikula 240379bc100SJani Nikula target_clock = fixed_mode->clock; 241379bc100SJani Nikula } 242379bc100SJani Nikula 243379bc100SJani Nikula if (target_clock > max_dotclk) 244379bc100SJani Nikula return MODE_CLOCK_HIGH; 245379bc100SJani Nikula 246379bc100SJani Nikula return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); 247379bc100SJani Nikula } 248379bc100SJani Nikula 249379bc100SJani Nikula static int intel_dvo_compute_config(struct intel_encoder *encoder, 250379bc100SJani Nikula struct intel_crtc_state *pipe_config, 251379bc100SJani Nikula struct drm_connector_state *conn_state) 252379bc100SJani Nikula { 253379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 254379bc100SJani Nikula const struct drm_display_mode *fixed_mode = 255379bc100SJani Nikula intel_dvo->attached_connector->panel.fixed_mode; 256379bc100SJani Nikula struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 257379bc100SJani Nikula 258379bc100SJani Nikula /* 259379bc100SJani Nikula * If we have timings from the BIOS for the panel, put them in 260379bc100SJani Nikula * to the adjusted mode. The CRTC will be set up for this mode, 261379bc100SJani Nikula * with the panel scaling set up to source from the H/VDisplay 262379bc100SJani Nikula * of the original mode. 263379bc100SJani Nikula */ 264379bc100SJani Nikula if (fixed_mode) 265379bc100SJani Nikula intel_fixed_panel_mode(fixed_mode, adjusted_mode); 266379bc100SJani Nikula 267379bc100SJani Nikula if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 268379bc100SJani Nikula return -EINVAL; 269379bc100SJani Nikula 270379bc100SJani Nikula pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 271379bc100SJani Nikula 272379bc100SJani Nikula return 0; 273379bc100SJani Nikula } 274379bc100SJani Nikula 275379bc100SJani Nikula static void intel_dvo_pre_enable(struct intel_encoder *encoder, 276379bc100SJani Nikula const struct intel_crtc_state *pipe_config, 277379bc100SJani Nikula const struct drm_connector_state *conn_state) 278379bc100SJani Nikula { 279379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 280379bc100SJani Nikula struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 281379bc100SJani Nikula const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 282379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 283379bc100SJani Nikula int pipe = crtc->pipe; 284379bc100SJani Nikula u32 dvo_val; 285379bc100SJani Nikula i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; 286379bc100SJani Nikula i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg; 287379bc100SJani Nikula 288379bc100SJani Nikula /* Save the data order, since I don't know what it should be set to. */ 289379bc100SJani Nikula dvo_val = I915_READ(dvo_reg) & 290379bc100SJani Nikula (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); 291379bc100SJani Nikula dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | 292379bc100SJani Nikula DVO_BLANK_ACTIVE_HIGH; 293379bc100SJani Nikula 294379bc100SJani Nikula dvo_val |= DVO_PIPE_SEL(pipe); 295379bc100SJani Nikula dvo_val |= DVO_PIPE_STALL; 296379bc100SJani Nikula if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 297379bc100SJani Nikula dvo_val |= DVO_HSYNC_ACTIVE_HIGH; 298379bc100SJani Nikula if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 299379bc100SJani Nikula dvo_val |= DVO_VSYNC_ACTIVE_HIGH; 300379bc100SJani Nikula 301379bc100SJani Nikula /*I915_WRITE(DVOB_SRCDIM, 302379bc100SJani Nikula (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | 303379bc100SJani Nikula (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ 304379bc100SJani Nikula I915_WRITE(dvo_srcdim_reg, 305379bc100SJani Nikula (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | 306379bc100SJani Nikula (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); 307379bc100SJani Nikula /*I915_WRITE(DVOB, dvo_val);*/ 308379bc100SJani Nikula I915_WRITE(dvo_reg, dvo_val); 309379bc100SJani Nikula } 310379bc100SJani Nikula 311379bc100SJani Nikula static enum drm_connector_status 312379bc100SJani Nikula intel_dvo_detect(struct drm_connector *connector, bool force) 313379bc100SJani Nikula { 314379bc100SJani Nikula struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 315379bc100SJani Nikula DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 316379bc100SJani Nikula connector->base.id, connector->name); 317379bc100SJani Nikula return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); 318379bc100SJani Nikula } 319379bc100SJani Nikula 320379bc100SJani Nikula static int intel_dvo_get_modes(struct drm_connector *connector) 321379bc100SJani Nikula { 322379bc100SJani Nikula struct drm_i915_private *dev_priv = to_i915(connector->dev); 323379bc100SJani Nikula const struct drm_display_mode *fixed_mode = 324379bc100SJani Nikula to_intel_connector(connector)->panel.fixed_mode; 325379bc100SJani Nikula 326379bc100SJani Nikula /* 327379bc100SJani Nikula * We should probably have an i2c driver get_modes function for those 328379bc100SJani Nikula * devices which will have a fixed set of modes determined by the chip 329379bc100SJani Nikula * (TV-out, for example), but for now with just TMDS and LVDS, 330379bc100SJani Nikula * that's not the case. 331379bc100SJani Nikula */ 332379bc100SJani Nikula intel_ddc_get_modes(connector, 333379bc100SJani Nikula intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC)); 334379bc100SJani Nikula if (!list_empty(&connector->probed_modes)) 335379bc100SJani Nikula return 1; 336379bc100SJani Nikula 337379bc100SJani Nikula if (fixed_mode) { 338379bc100SJani Nikula struct drm_display_mode *mode; 339379bc100SJani Nikula mode = drm_mode_duplicate(connector->dev, fixed_mode); 340379bc100SJani Nikula if (mode) { 341379bc100SJani Nikula drm_mode_probed_add(connector, mode); 342379bc100SJani Nikula return 1; 343379bc100SJani Nikula } 344379bc100SJani Nikula } 345379bc100SJani Nikula 346379bc100SJani Nikula return 0; 347379bc100SJani Nikula } 348379bc100SJani Nikula 349379bc100SJani Nikula static const struct drm_connector_funcs intel_dvo_connector_funcs = { 350379bc100SJani Nikula .detect = intel_dvo_detect, 351379bc100SJani Nikula .late_register = intel_connector_register, 352379bc100SJani Nikula .early_unregister = intel_connector_unregister, 353379bc100SJani Nikula .destroy = intel_connector_destroy, 354379bc100SJani Nikula .fill_modes = drm_helper_probe_single_connector_modes, 355379bc100SJani Nikula .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 356379bc100SJani Nikula .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 357379bc100SJani Nikula }; 358379bc100SJani Nikula 359379bc100SJani Nikula static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { 360379bc100SJani Nikula .mode_valid = intel_dvo_mode_valid, 361379bc100SJani Nikula .get_modes = intel_dvo_get_modes, 362379bc100SJani Nikula }; 363379bc100SJani Nikula 364379bc100SJani Nikula static void intel_dvo_enc_destroy(struct drm_encoder *encoder) 365379bc100SJani Nikula { 366379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); 367379bc100SJani Nikula 368379bc100SJani Nikula if (intel_dvo->dev.dev_ops->destroy) 369379bc100SJani Nikula intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); 370379bc100SJani Nikula 371379bc100SJani Nikula intel_encoder_destroy(encoder); 372379bc100SJani Nikula } 373379bc100SJani Nikula 374379bc100SJani Nikula static const struct drm_encoder_funcs intel_dvo_enc_funcs = { 375379bc100SJani Nikula .destroy = intel_dvo_enc_destroy, 376379bc100SJani Nikula }; 377379bc100SJani Nikula 378379bc100SJani Nikula /* 379379bc100SJani Nikula * Attempts to get a fixed panel timing for LVDS (currently only the i830). 380379bc100SJani Nikula * 381379bc100SJani Nikula * Other chips with DVO LVDS will need to extend this to deal with the LVDS 382379bc100SJani Nikula * chip being on DVOB/C and having multiple pipes. 383379bc100SJani Nikula */ 384379bc100SJani Nikula static struct drm_display_mode * 385379bc100SJani Nikula intel_dvo_get_current_mode(struct intel_encoder *encoder) 386379bc100SJani Nikula { 387379bc100SJani Nikula struct drm_display_mode *mode; 388379bc100SJani Nikula 389379bc100SJani Nikula mode = intel_encoder_current_mode(encoder); 390379bc100SJani Nikula if (mode) { 391379bc100SJani Nikula DRM_DEBUG_KMS("using current (BIOS) mode: "); 392379bc100SJani Nikula drm_mode_debug_printmodeline(mode); 393379bc100SJani Nikula mode->type |= DRM_MODE_TYPE_PREFERRED; 394379bc100SJani Nikula } 395379bc100SJani Nikula 396379bc100SJani Nikula return mode; 397379bc100SJani Nikula } 398379bc100SJani Nikula 399379bc100SJani Nikula static enum port intel_dvo_port(i915_reg_t dvo_reg) 400379bc100SJani Nikula { 401379bc100SJani Nikula if (i915_mmio_reg_equal(dvo_reg, DVOA)) 402379bc100SJani Nikula return PORT_A; 403379bc100SJani Nikula else if (i915_mmio_reg_equal(dvo_reg, DVOB)) 404379bc100SJani Nikula return PORT_B; 405379bc100SJani Nikula else 406379bc100SJani Nikula return PORT_C; 407379bc100SJani Nikula } 408379bc100SJani Nikula 409379bc100SJani Nikula void intel_dvo_init(struct drm_i915_private *dev_priv) 410379bc100SJani Nikula { 411379bc100SJani Nikula struct intel_encoder *intel_encoder; 412379bc100SJani Nikula struct intel_dvo *intel_dvo; 413379bc100SJani Nikula struct intel_connector *intel_connector; 414379bc100SJani Nikula int i; 415379bc100SJani Nikula int encoder_type = DRM_MODE_ENCODER_NONE; 416379bc100SJani Nikula 417379bc100SJani Nikula intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL); 418379bc100SJani Nikula if (!intel_dvo) 419379bc100SJani Nikula return; 420379bc100SJani Nikula 421379bc100SJani Nikula intel_connector = intel_connector_alloc(); 422379bc100SJani Nikula if (!intel_connector) { 423379bc100SJani Nikula kfree(intel_dvo); 424379bc100SJani Nikula return; 425379bc100SJani Nikula } 426379bc100SJani Nikula 427379bc100SJani Nikula intel_dvo->attached_connector = intel_connector; 428379bc100SJani Nikula 429379bc100SJani Nikula intel_encoder = &intel_dvo->base; 430379bc100SJani Nikula 431379bc100SJani Nikula intel_encoder->disable = intel_disable_dvo; 432379bc100SJani Nikula intel_encoder->enable = intel_enable_dvo; 433379bc100SJani Nikula intel_encoder->get_hw_state = intel_dvo_get_hw_state; 434379bc100SJani Nikula intel_encoder->get_config = intel_dvo_get_config; 435379bc100SJani Nikula intel_encoder->compute_config = intel_dvo_compute_config; 436379bc100SJani Nikula intel_encoder->pre_enable = intel_dvo_pre_enable; 437379bc100SJani Nikula intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; 438379bc100SJani Nikula 439379bc100SJani Nikula /* Now, try to find a controller */ 440379bc100SJani Nikula for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { 441379bc100SJani Nikula struct drm_connector *connector = &intel_connector->base; 442379bc100SJani Nikula const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; 443379bc100SJani Nikula struct i2c_adapter *i2c; 444379bc100SJani Nikula int gpio; 445379bc100SJani Nikula bool dvoinit; 446379bc100SJani Nikula enum pipe pipe; 447379bc100SJani Nikula u32 dpll[I915_MAX_PIPES]; 448379bc100SJani Nikula enum port port; 449379bc100SJani Nikula 450379bc100SJani Nikula /* 451379bc100SJani Nikula * Allow the I2C driver info to specify the GPIO to be used in 452379bc100SJani Nikula * special cases, but otherwise default to what's defined 453379bc100SJani Nikula * in the spec. 454379bc100SJani Nikula */ 455379bc100SJani Nikula if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio)) 456379bc100SJani Nikula gpio = dvo->gpio; 457379bc100SJani Nikula else if (dvo->type == INTEL_DVO_CHIP_LVDS) 458379bc100SJani Nikula gpio = GMBUS_PIN_SSC; 459379bc100SJani Nikula else 460379bc100SJani Nikula gpio = GMBUS_PIN_DPB; 461379bc100SJani Nikula 462379bc100SJani Nikula /* 463379bc100SJani Nikula * Set up the I2C bus necessary for the chip we're probing. 464379bc100SJani Nikula * It appears that everything is on GPIOE except for panels 465379bc100SJani Nikula * on i830 laptops, which are on GPIOB (DVOA). 466379bc100SJani Nikula */ 467379bc100SJani Nikula i2c = intel_gmbus_get_adapter(dev_priv, gpio); 468379bc100SJani Nikula 469379bc100SJani Nikula intel_dvo->dev = *dvo; 470379bc100SJani Nikula 471379bc100SJani Nikula /* 472379bc100SJani Nikula * GMBUS NAK handling seems to be unstable, hence let the 473379bc100SJani Nikula * transmitter detection run in bit banging mode for now. 474379bc100SJani Nikula */ 475379bc100SJani Nikula intel_gmbus_force_bit(i2c, true); 476379bc100SJani Nikula 477379bc100SJani Nikula /* 478379bc100SJani Nikula * ns2501 requires the DVO 2x clock before it will 479379bc100SJani Nikula * respond to i2c accesses, so make sure we have 480379bc100SJani Nikula * have the clock enabled before we attempt to 481379bc100SJani Nikula * initialize the device. 482379bc100SJani Nikula */ 483379bc100SJani Nikula for_each_pipe(dev_priv, pipe) { 484379bc100SJani Nikula dpll[pipe] = I915_READ(DPLL(pipe)); 485379bc100SJani Nikula I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); 486379bc100SJani Nikula } 487379bc100SJani Nikula 488379bc100SJani Nikula dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); 489379bc100SJani Nikula 490379bc100SJani Nikula /* restore the DVO 2x clock state to original */ 491379bc100SJani Nikula for_each_pipe(dev_priv, pipe) { 492379bc100SJani Nikula I915_WRITE(DPLL(pipe), dpll[pipe]); 493379bc100SJani Nikula } 494379bc100SJani Nikula 495379bc100SJani Nikula intel_gmbus_force_bit(i2c, false); 496379bc100SJani Nikula 497379bc100SJani Nikula if (!dvoinit) 498379bc100SJani Nikula continue; 499379bc100SJani Nikula 500379bc100SJani Nikula port = intel_dvo_port(dvo->dvo_reg); 501379bc100SJani Nikula drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 502379bc100SJani Nikula &intel_dvo_enc_funcs, encoder_type, 503379bc100SJani Nikula "DVO %c", port_name(port)); 504379bc100SJani Nikula 505379bc100SJani Nikula intel_encoder->type = INTEL_OUTPUT_DVO; 506379bc100SJani Nikula intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 507379bc100SJani Nikula intel_encoder->port = port; 508379bc100SJani Nikula intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 509379bc100SJani Nikula 510379bc100SJani Nikula switch (dvo->type) { 511379bc100SJani Nikula case INTEL_DVO_CHIP_TMDS: 512379bc100SJani Nikula intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) | 513379bc100SJani Nikula (1 << INTEL_OUTPUT_DVO); 514379bc100SJani Nikula drm_connector_init(&dev_priv->drm, connector, 515379bc100SJani Nikula &intel_dvo_connector_funcs, 516379bc100SJani Nikula DRM_MODE_CONNECTOR_DVII); 517379bc100SJani Nikula encoder_type = DRM_MODE_ENCODER_TMDS; 518379bc100SJani Nikula break; 519379bc100SJani Nikula case INTEL_DVO_CHIP_LVDS: 520379bc100SJani Nikula intel_encoder->cloneable = 0; 521379bc100SJani Nikula drm_connector_init(&dev_priv->drm, connector, 522379bc100SJani Nikula &intel_dvo_connector_funcs, 523379bc100SJani Nikula DRM_MODE_CONNECTOR_LVDS); 524379bc100SJani Nikula encoder_type = DRM_MODE_ENCODER_LVDS; 525379bc100SJani Nikula break; 526379bc100SJani Nikula } 527379bc100SJani Nikula 528379bc100SJani Nikula drm_connector_helper_add(connector, 529379bc100SJani Nikula &intel_dvo_connector_helper_funcs); 530379bc100SJani Nikula connector->display_info.subpixel_order = SubPixelHorizontalRGB; 531379bc100SJani Nikula connector->interlace_allowed = false; 532379bc100SJani Nikula connector->doublescan_allowed = false; 533379bc100SJani Nikula 534379bc100SJani Nikula intel_connector_attach_encoder(intel_connector, intel_encoder); 535379bc100SJani Nikula if (dvo->type == INTEL_DVO_CHIP_LVDS) { 536379bc100SJani Nikula /* 537379bc100SJani Nikula * For our LVDS chipsets, we should hopefully be able 538379bc100SJani Nikula * to dig the fixed panel mode out of the BIOS data. 539379bc100SJani Nikula * However, it's in a different format from the BIOS 540379bc100SJani Nikula * data on chipsets with integrated LVDS (stored in AIM 541379bc100SJani Nikula * headers, likely), so for now, just get the current 542379bc100SJani Nikula * mode being output through DVO. 543379bc100SJani Nikula */ 544379bc100SJani Nikula intel_panel_init(&intel_connector->panel, 545379bc100SJani Nikula intel_dvo_get_current_mode(intel_encoder), 546379bc100SJani Nikula NULL); 547379bc100SJani Nikula intel_dvo->panel_wants_dither = true; 548379bc100SJani Nikula } 549379bc100SJani Nikula 550379bc100SJani Nikula return; 551379bc100SJani Nikula } 552379bc100SJani Nikula 553379bc100SJani Nikula kfree(intel_dvo); 554379bc100SJani Nikula kfree(intel_connector); 555379bc100SJani Nikula } 556