1379bc100SJani Nikula /* 2379bc100SJani Nikula * Copyright 2006 Dave Airlie <airlied@linux.ie> 3379bc100SJani Nikula * Copyright © 2006-2007 Intel Corporation 4379bc100SJani Nikula * 5379bc100SJani Nikula * Permission is hereby granted, free of charge, to any person obtaining a 6379bc100SJani Nikula * copy of this software and associated documentation files (the "Software"), 7379bc100SJani Nikula * to deal in the Software without restriction, including without limitation 8379bc100SJani Nikula * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9379bc100SJani Nikula * and/or sell copies of the Software, and to permit persons to whom the 10379bc100SJani Nikula * Software is furnished to do so, subject to the following conditions: 11379bc100SJani Nikula * 12379bc100SJani Nikula * The above copyright notice and this permission notice (including the next 13379bc100SJani Nikula * paragraph) shall be included in all copies or substantial portions of the 14379bc100SJani Nikula * Software. 15379bc100SJani Nikula * 16379bc100SJani Nikula * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17379bc100SJani Nikula * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18379bc100SJani Nikula * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19379bc100SJani Nikula * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20379bc100SJani Nikula * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21379bc100SJani Nikula * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22379bc100SJani Nikula * DEALINGS IN THE SOFTWARE. 23379bc100SJani Nikula * 24379bc100SJani Nikula * Authors: 25379bc100SJani Nikula * Eric Anholt <eric@anholt.net> 26379bc100SJani Nikula */ 27379bc100SJani Nikula 28379bc100SJani Nikula #include <linux/i2c.h> 29379bc100SJani Nikula #include <linux/slab.h> 30379bc100SJani Nikula 31379bc100SJani Nikula #include <drm/drm_atomic_helper.h> 32379bc100SJani Nikula #include <drm/drm_crtc.h> 33379bc100SJani Nikula 34379bc100SJani Nikula #include "i915_drv.h" 35801543b2SJani Nikula #include "i915_reg.h" 36379bc100SJani Nikula #include "intel_connector.h" 377785ae0bSVille Syrjälä #include "intel_de.h" 381d455f8dSJani Nikula #include "intel_display_types.h" 39379bc100SJani Nikula #include "intel_dvo.h" 40379bc100SJani Nikula #include "intel_dvo_dev.h" 41379bc100SJani Nikula #include "intel_gmbus.h" 42379bc100SJani Nikula #include "intel_panel.h" 43379bc100SJani Nikula 44379bc100SJani Nikula #define INTEL_DVO_CHIP_NONE 0 45379bc100SJani Nikula #define INTEL_DVO_CHIP_LVDS 1 46379bc100SJani Nikula #define INTEL_DVO_CHIP_TMDS 2 47379bc100SJani Nikula #define INTEL_DVO_CHIP_TVOUT 4 4845608c50SVille Syrjälä #define INTEL_DVO_CHIP_LVDS_NO_FIXED 5 49379bc100SJani Nikula 50379bc100SJani Nikula #define SIL164_ADDR 0x38 51379bc100SJani Nikula #define CH7xxx_ADDR 0x76 52379bc100SJani Nikula #define TFP410_ADDR 0x38 53379bc100SJani Nikula #define NS2501_ADDR 0x38 54379bc100SJani Nikula 55379bc100SJani Nikula static const struct intel_dvo_device intel_dvo_devices[] = { 56379bc100SJani Nikula { 57379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 58379bc100SJani Nikula .name = "sil164", 59a8d9a13dSVille Syrjälä .port = PORT_C, 60379bc100SJani Nikula .slave_addr = SIL164_ADDR, 61379bc100SJani Nikula .dev_ops = &sil164_ops, 62379bc100SJani Nikula }, 63379bc100SJani Nikula { 64379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 65379bc100SJani Nikula .name = "ch7xxx", 66a8d9a13dSVille Syrjälä .port = PORT_C, 67379bc100SJani Nikula .slave_addr = CH7xxx_ADDR, 68379bc100SJani Nikula .dev_ops = &ch7xxx_ops, 69379bc100SJani Nikula }, 70379bc100SJani Nikula { 71379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 72379bc100SJani Nikula .name = "ch7xxx", 73a8d9a13dSVille Syrjälä .port = PORT_C, 74379bc100SJani Nikula .slave_addr = 0x75, /* For some ch7010 */ 75379bc100SJani Nikula .dev_ops = &ch7xxx_ops, 76379bc100SJani Nikula }, 77379bc100SJani Nikula { 78379bc100SJani Nikula .type = INTEL_DVO_CHIP_LVDS, 79379bc100SJani Nikula .name = "ivch", 80a8d9a13dSVille Syrjälä .port = PORT_A, 81379bc100SJani Nikula .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ 82379bc100SJani Nikula .dev_ops = &ivch_ops, 83379bc100SJani Nikula }, 84379bc100SJani Nikula { 85379bc100SJani Nikula .type = INTEL_DVO_CHIP_TMDS, 86379bc100SJani Nikula .name = "tfp410", 87a8d9a13dSVille Syrjälä .port = PORT_C, 88379bc100SJani Nikula .slave_addr = TFP410_ADDR, 89379bc100SJani Nikula .dev_ops = &tfp410_ops, 90379bc100SJani Nikula }, 91379bc100SJani Nikula { 92379bc100SJani Nikula .type = INTEL_DVO_CHIP_LVDS, 93379bc100SJani Nikula .name = "ch7017", 94a8d9a13dSVille Syrjälä .port = PORT_C, 95379bc100SJani Nikula .slave_addr = 0x75, 96379bc100SJani Nikula .gpio = GMBUS_PIN_DPB, 97379bc100SJani Nikula .dev_ops = &ch7017_ops, 98379bc100SJani Nikula }, 99379bc100SJani Nikula { 10045608c50SVille Syrjälä .type = INTEL_DVO_CHIP_LVDS_NO_FIXED, 101379bc100SJani Nikula .name = "ns2501", 102a8d9a13dSVille Syrjälä .port = PORT_B, 103379bc100SJani Nikula .slave_addr = NS2501_ADDR, 104379bc100SJani Nikula .dev_ops = &ns2501_ops, 10545608c50SVille Syrjälä }, 106379bc100SJani Nikula }; 107379bc100SJani Nikula 108379bc100SJani Nikula struct intel_dvo { 109379bc100SJani Nikula struct intel_encoder base; 110379bc100SJani Nikula 111379bc100SJani Nikula struct intel_dvo_device dev; 112379bc100SJani Nikula 113379bc100SJani Nikula struct intel_connector *attached_connector; 114379bc100SJani Nikula }; 115379bc100SJani Nikula 116379bc100SJani Nikula static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) 117379bc100SJani Nikula { 118379bc100SJani Nikula return container_of(encoder, struct intel_dvo, base); 119379bc100SJani Nikula } 120379bc100SJani Nikula 12143a6d19cSVille Syrjälä static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector) 122379bc100SJani Nikula { 123379bc100SJani Nikula return enc_to_dvo(intel_attached_encoder(connector)); 124379bc100SJani Nikula } 125379bc100SJani Nikula 126379bc100SJani Nikula static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) 127379bc100SJani Nikula { 128ef228dbfSVille Syrjälä struct drm_i915_private *i915 = to_i915(connector->base.dev); 129a8d9a13dSVille Syrjälä struct intel_encoder *encoder = intel_attached_encoder(connector); 130a8d9a13dSVille Syrjälä struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 131a8d9a13dSVille Syrjälä enum port port = encoder->port; 132379bc100SJani Nikula u32 tmp; 133379bc100SJani Nikula 134a8d9a13dSVille Syrjälä tmp = intel_de_read(i915, DVO(port)); 135379bc100SJani Nikula 136379bc100SJani Nikula if (!(tmp & DVO_ENABLE)) 137379bc100SJani Nikula return false; 138379bc100SJani Nikula 139379bc100SJani Nikula return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); 140379bc100SJani Nikula } 141379bc100SJani Nikula 142379bc100SJani Nikula static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, 143379bc100SJani Nikula enum pipe *pipe) 144379bc100SJani Nikula { 145ef228dbfSVille Syrjälä struct drm_i915_private *i915 = to_i915(encoder->base.dev); 146a8d9a13dSVille Syrjälä enum port port = encoder->port; 147379bc100SJani Nikula u32 tmp; 148379bc100SJani Nikula 149a8d9a13dSVille Syrjälä tmp = intel_de_read(i915, DVO(port)); 150379bc100SJani Nikula 1517ce5b3a7SVille Syrjälä *pipe = REG_FIELD_GET(DVO_PIPE_SEL_MASK, tmp); 152379bc100SJani Nikula 153379bc100SJani Nikula return tmp & DVO_ENABLE; 154379bc100SJani Nikula } 155379bc100SJani Nikula 156379bc100SJani Nikula static void intel_dvo_get_config(struct intel_encoder *encoder, 157379bc100SJani Nikula struct intel_crtc_state *pipe_config) 158379bc100SJani Nikula { 159ef228dbfSVille Syrjälä struct drm_i915_private *i915 = to_i915(encoder->base.dev); 160a8d9a13dSVille Syrjälä enum port port = encoder->port; 161379bc100SJani Nikula u32 tmp, flags = 0; 162379bc100SJani Nikula 163379bc100SJani Nikula pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); 164379bc100SJani Nikula 165a8d9a13dSVille Syrjälä tmp = intel_de_read(i915, DVO(port)); 166379bc100SJani Nikula if (tmp & DVO_HSYNC_ACTIVE_HIGH) 167379bc100SJani Nikula flags |= DRM_MODE_FLAG_PHSYNC; 168379bc100SJani Nikula else 169379bc100SJani Nikula flags |= DRM_MODE_FLAG_NHSYNC; 170379bc100SJani Nikula if (tmp & DVO_VSYNC_ACTIVE_HIGH) 171379bc100SJani Nikula flags |= DRM_MODE_FLAG_PVSYNC; 172379bc100SJani Nikula else 173379bc100SJani Nikula flags |= DRM_MODE_FLAG_NVSYNC; 174379bc100SJani Nikula 1751326a92cSMaarten Lankhorst pipe_config->hw.adjusted_mode.flags |= flags; 176379bc100SJani Nikula 1771326a92cSMaarten Lankhorst pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 178379bc100SJani Nikula } 179379bc100SJani Nikula 180ede9771dSVille Syrjälä static void intel_disable_dvo(struct intel_atomic_state *state, 181ede9771dSVille Syrjälä struct intel_encoder *encoder, 182379bc100SJani Nikula const struct intel_crtc_state *old_crtc_state, 183379bc100SJani Nikula const struct drm_connector_state *old_conn_state) 184379bc100SJani Nikula { 185ef228dbfSVille Syrjälä struct drm_i915_private *i915 = to_i915(encoder->base.dev); 186379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 187a8d9a13dSVille Syrjälä enum port port = encoder->port; 188379bc100SJani Nikula 189379bc100SJani Nikula intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); 190*079c4c0cSVille Syrjälä 191*079c4c0cSVille Syrjälä intel_de_rmw(i915, DVO(port), DVO_ENABLE, 0); 192*079c4c0cSVille Syrjälä intel_de_posting_read(i915, DVO(port)); 193379bc100SJani Nikula } 194379bc100SJani Nikula 195ede9771dSVille Syrjälä static void intel_enable_dvo(struct intel_atomic_state *state, 196ede9771dSVille Syrjälä struct intel_encoder *encoder, 197379bc100SJani Nikula const struct intel_crtc_state *pipe_config, 198379bc100SJani Nikula const struct drm_connector_state *conn_state) 199379bc100SJani Nikula { 200ef228dbfSVille Syrjälä struct drm_i915_private *i915 = to_i915(encoder->base.dev); 201379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 202a8d9a13dSVille Syrjälä enum port port = encoder->port; 203379bc100SJani Nikula 204379bc100SJani Nikula intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, 2051326a92cSMaarten Lankhorst &pipe_config->hw.mode, 2061326a92cSMaarten Lankhorst &pipe_config->hw.adjusted_mode); 207379bc100SJani Nikula 208*079c4c0cSVille Syrjälä intel_de_rmw(i915, DVO(port), 0, DVO_ENABLE); 209*079c4c0cSVille Syrjälä intel_de_posting_read(i915, DVO(port)); 210379bc100SJani Nikula 211379bc100SJani Nikula intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); 212379bc100SJani Nikula } 213379bc100SJani Nikula 214379bc100SJani Nikula static enum drm_mode_status 21509b350d7SVille Syrjälä intel_dvo_mode_valid(struct drm_connector *_connector, 216379bc100SJani Nikula struct drm_display_mode *mode) 217379bc100SJani Nikula { 21809b350d7SVille Syrjälä struct intel_connector *connector = to_intel_connector(_connector); 21909b350d7SVille Syrjälä struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 220379bc100SJani Nikula const struct drm_display_mode *fixed_mode = 22109b350d7SVille Syrjälä intel_panel_fixed_mode(connector, mode); 22209b350d7SVille Syrjälä int max_dotclk = to_i915(connector->base.dev)->max_dotclk_freq; 223379bc100SJani Nikula int target_clock = mode->clock; 224379bc100SJani Nikula 225379bc100SJani Nikula if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 226379bc100SJani Nikula return MODE_NO_DBLESCAN; 227379bc100SJani Nikula 228379bc100SJani Nikula /* XXX: Validate clock range */ 229379bc100SJani Nikula 230379bc100SJani Nikula if (fixed_mode) { 2318a567b11SVille Syrjälä enum drm_mode_status status; 2328a567b11SVille Syrjälä 23309b350d7SVille Syrjälä status = intel_panel_mode_valid(connector, mode); 2348a567b11SVille Syrjälä if (status != MODE_OK) 2358a567b11SVille Syrjälä return status; 236379bc100SJani Nikula 237379bc100SJani Nikula target_clock = fixed_mode->clock; 238379bc100SJani Nikula } 239379bc100SJani Nikula 240379bc100SJani Nikula if (target_clock > max_dotclk) 241379bc100SJani Nikula return MODE_CLOCK_HIGH; 242379bc100SJani Nikula 243379bc100SJani Nikula return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); 244379bc100SJani Nikula } 245379bc100SJani Nikula 246379bc100SJani Nikula static int intel_dvo_compute_config(struct intel_encoder *encoder, 247379bc100SJani Nikula struct intel_crtc_state *pipe_config, 248379bc100SJani Nikula struct drm_connector_state *conn_state) 249379bc100SJani Nikula { 250379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 251cff4c2c6SVille Syrjälä struct intel_connector *connector = to_intel_connector(conn_state->connector); 2521326a92cSMaarten Lankhorst struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 25309270678SVille Syrjälä const struct drm_display_mode *fixed_mode = 25409270678SVille Syrjälä intel_panel_fixed_mode(intel_dvo->attached_connector, adjusted_mode); 255379bc100SJani Nikula 256379bc100SJani Nikula /* 257379bc100SJani Nikula * If we have timings from the BIOS for the panel, put them in 258379bc100SJani Nikula * to the adjusted mode. The CRTC will be set up for this mode, 259379bc100SJani Nikula * with the panel scaling set up to source from the H/VDisplay 260379bc100SJani Nikula * of the original mode. 261379bc100SJani Nikula */ 262cff4c2c6SVille Syrjälä if (fixed_mode) { 263cff4c2c6SVille Syrjälä int ret; 264cff4c2c6SVille Syrjälä 265cff4c2c6SVille Syrjälä ret = intel_panel_compute_config(connector, adjusted_mode); 266cff4c2c6SVille Syrjälä if (ret) 267cff4c2c6SVille Syrjälä return ret; 268cff4c2c6SVille Syrjälä } 269379bc100SJani Nikula 270379bc100SJani Nikula if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 271379bc100SJani Nikula return -EINVAL; 272379bc100SJani Nikula 273379bc100SJani Nikula pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 274379bc100SJani Nikula 275379bc100SJani Nikula return 0; 276379bc100SJani Nikula } 277379bc100SJani Nikula 278ede9771dSVille Syrjälä static void intel_dvo_pre_enable(struct intel_atomic_state *state, 279ede9771dSVille Syrjälä struct intel_encoder *encoder, 280379bc100SJani Nikula const struct intel_crtc_state *pipe_config, 281379bc100SJani Nikula const struct drm_connector_state *conn_state) 282379bc100SJani Nikula { 283ef228dbfSVille Syrjälä struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2842225f3c6SMaarten Lankhorst struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2851326a92cSMaarten Lankhorst const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 286a8d9a13dSVille Syrjälä enum port port = encoder->port; 287d048a268SVille Syrjälä enum pipe pipe = crtc->pipe; 288379bc100SJani Nikula u32 dvo_val; 289379bc100SJani Nikula 2909710a5c1SVille Syrjälä /* Save the active data order, since I don't know what it should be set to. */ 291a8d9a13dSVille Syrjälä dvo_val = intel_de_read(i915, DVO(port)) & 2925abd7d8dSVille Syrjälä (DVO_DEDICATED_INT_ENABLE | 2937ce5b3a7SVille Syrjälä DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_MASK); 294379bc100SJani Nikula dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | 295379bc100SJani Nikula DVO_BLANK_ACTIVE_HIGH; 296379bc100SJani Nikula 297379bc100SJani Nikula dvo_val |= DVO_PIPE_SEL(pipe); 298379bc100SJani Nikula dvo_val |= DVO_PIPE_STALL; 299379bc100SJani Nikula if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 300379bc100SJani Nikula dvo_val |= DVO_HSYNC_ACTIVE_HIGH; 301379bc100SJani Nikula if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 302379bc100SJani Nikula dvo_val |= DVO_VSYNC_ACTIVE_HIGH; 303379bc100SJani Nikula 304a8d9a13dSVille Syrjälä intel_de_write(i915, DVO_SRCDIM(port), 3057ce5b3a7SVille Syrjälä DVO_SRCDIM_HORIZONTAL(adjusted_mode->crtc_hdisplay) | 3067ce5b3a7SVille Syrjälä DVO_SRCDIM_VERTICAL(adjusted_mode->crtc_vdisplay)); 307a8d9a13dSVille Syrjälä intel_de_write(i915, DVO(port), dvo_val); 308379bc100SJani Nikula } 309379bc100SJani Nikula 310379bc100SJani Nikula static enum drm_connector_status 31109b350d7SVille Syrjälä intel_dvo_detect(struct drm_connector *_connector, bool force) 312379bc100SJani Nikula { 31309b350d7SVille Syrjälä struct intel_connector *connector = to_intel_connector(_connector); 31409b350d7SVille Syrjälä struct drm_i915_private *i915 = to_i915(connector->base.dev); 31509b350d7SVille Syrjälä struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 316b81dddb9SVille Syrjälä 317f322ed0dSVille Syrjälä drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 31809b350d7SVille Syrjälä connector->base.base.id, connector->base.name); 319b81dddb9SVille Syrjälä 320b81dddb9SVille Syrjälä if (!INTEL_DISPLAY_ENABLED(i915)) 321b81dddb9SVille Syrjälä return connector_status_disconnected; 322b81dddb9SVille Syrjälä 323379bc100SJani Nikula return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); 324379bc100SJani Nikula } 325379bc100SJani Nikula 32609b350d7SVille Syrjälä static int intel_dvo_get_modes(struct drm_connector *_connector) 327379bc100SJani Nikula { 32809b350d7SVille Syrjälä struct intel_connector *connector = to_intel_connector(_connector); 329ef228dbfSVille Syrjälä struct drm_i915_private *i915 = to_i915(connector->base.dev); 3304a2236f9SVille Syrjälä int num_modes; 331379bc100SJani Nikula 332379bc100SJani Nikula /* 333379bc100SJani Nikula * We should probably have an i2c driver get_modes function for those 334379bc100SJani Nikula * devices which will have a fixed set of modes determined by the chip 335379bc100SJani Nikula * (TV-out, for example), but for now with just TMDS and LVDS, 336379bc100SJani Nikula * that's not the case. 337379bc100SJani Nikula */ 33809b350d7SVille Syrjälä num_modes = intel_ddc_get_modes(&connector->base, 339ef228dbfSVille Syrjälä intel_gmbus_get_adapter(i915, GMBUS_PIN_DPC)); 3404a2236f9SVille Syrjälä if (num_modes) 3414a2236f9SVille Syrjälä return num_modes; 342379bc100SJani Nikula 34309b350d7SVille Syrjälä return intel_panel_get_modes(connector); 344379bc100SJani Nikula } 345379bc100SJani Nikula 346379bc100SJani Nikula static const struct drm_connector_funcs intel_dvo_connector_funcs = { 347379bc100SJani Nikula .detect = intel_dvo_detect, 348379bc100SJani Nikula .late_register = intel_connector_register, 349379bc100SJani Nikula .early_unregister = intel_connector_unregister, 350379bc100SJani Nikula .destroy = intel_connector_destroy, 351379bc100SJani Nikula .fill_modes = drm_helper_probe_single_connector_modes, 352379bc100SJani Nikula .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 353379bc100SJani Nikula .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 354379bc100SJani Nikula }; 355379bc100SJani Nikula 356379bc100SJani Nikula static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { 357379bc100SJani Nikula .mode_valid = intel_dvo_mode_valid, 358379bc100SJani Nikula .get_modes = intel_dvo_get_modes, 359379bc100SJani Nikula }; 360379bc100SJani Nikula 361379bc100SJani Nikula static void intel_dvo_enc_destroy(struct drm_encoder *encoder) 362379bc100SJani Nikula { 363379bc100SJani Nikula struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); 364379bc100SJani Nikula 365379bc100SJani Nikula if (intel_dvo->dev.dev_ops->destroy) 366379bc100SJani Nikula intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); 367379bc100SJani Nikula 368379bc100SJani Nikula intel_encoder_destroy(encoder); 369379bc100SJani Nikula } 370379bc100SJani Nikula 371379bc100SJani Nikula static const struct drm_encoder_funcs intel_dvo_enc_funcs = { 372379bc100SJani Nikula .destroy = intel_dvo_enc_destroy, 373379bc100SJani Nikula }; 374379bc100SJani Nikula 3756ebf5cafSVille Syrjälä static int intel_dvo_encoder_type(const struct intel_dvo_device *dvo) 3766ebf5cafSVille Syrjälä { 3776ebf5cafSVille Syrjälä switch (dvo->type) { 3786ebf5cafSVille Syrjälä case INTEL_DVO_CHIP_TMDS: 3796ebf5cafSVille Syrjälä return DRM_MODE_ENCODER_TMDS; 3806ebf5cafSVille Syrjälä case INTEL_DVO_CHIP_LVDS_NO_FIXED: 3816ebf5cafSVille Syrjälä case INTEL_DVO_CHIP_LVDS: 3826ebf5cafSVille Syrjälä return DRM_MODE_ENCODER_LVDS; 3836ebf5cafSVille Syrjälä default: 3846ebf5cafSVille Syrjälä MISSING_CASE(dvo->type); 3856ebf5cafSVille Syrjälä return DRM_MODE_ENCODER_NONE; 3866ebf5cafSVille Syrjälä } 3876ebf5cafSVille Syrjälä } 3886ebf5cafSVille Syrjälä 389201ec1bbSVille Syrjälä static int intel_dvo_connector_type(const struct intel_dvo_device *dvo) 390201ec1bbSVille Syrjälä { 391201ec1bbSVille Syrjälä switch (dvo->type) { 392201ec1bbSVille Syrjälä case INTEL_DVO_CHIP_TMDS: 393201ec1bbSVille Syrjälä return DRM_MODE_CONNECTOR_DVII; 394201ec1bbSVille Syrjälä case INTEL_DVO_CHIP_LVDS_NO_FIXED: 395201ec1bbSVille Syrjälä case INTEL_DVO_CHIP_LVDS: 396201ec1bbSVille Syrjälä return DRM_MODE_CONNECTOR_LVDS; 397201ec1bbSVille Syrjälä default: 398201ec1bbSVille Syrjälä MISSING_CASE(dvo->type); 399201ec1bbSVille Syrjälä return DRM_MODE_CONNECTOR_Unknown; 400201ec1bbSVille Syrjälä } 401201ec1bbSVille Syrjälä } 402201ec1bbSVille Syrjälä 403d82b9a89SVille Syrjälä static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv, 404d82b9a89SVille Syrjälä struct intel_dvo *intel_dvo, 405d82b9a89SVille Syrjälä const struct intel_dvo_device *dvo) 406379bc100SJani Nikula { 407379bc100SJani Nikula struct i2c_adapter *i2c; 408379bc100SJani Nikula u32 dpll[I915_MAX_PIPES]; 409d82b9a89SVille Syrjälä enum pipe pipe; 410d82b9a89SVille Syrjälä int gpio; 411d82b9a89SVille Syrjälä bool ret; 412379bc100SJani Nikula 413379bc100SJani Nikula /* 414379bc100SJani Nikula * Allow the I2C driver info to specify the GPIO to be used in 415379bc100SJani Nikula * special cases, but otherwise default to what's defined 416379bc100SJani Nikula * in the spec. 417379bc100SJani Nikula */ 418379bc100SJani Nikula if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio)) 419379bc100SJani Nikula gpio = dvo->gpio; 420379bc100SJani Nikula else if (dvo->type == INTEL_DVO_CHIP_LVDS) 421379bc100SJani Nikula gpio = GMBUS_PIN_SSC; 422379bc100SJani Nikula else 423379bc100SJani Nikula gpio = GMBUS_PIN_DPB; 424379bc100SJani Nikula 425379bc100SJani Nikula /* 426379bc100SJani Nikula * Set up the I2C bus necessary for the chip we're probing. 427379bc100SJani Nikula * It appears that everything is on GPIOE except for panels 428379bc100SJani Nikula * on i830 laptops, which are on GPIOB (DVOA). 429379bc100SJani Nikula */ 430379bc100SJani Nikula i2c = intel_gmbus_get_adapter(dev_priv, gpio); 431379bc100SJani Nikula 432379bc100SJani Nikula intel_dvo->dev = *dvo; 433379bc100SJani Nikula 434379bc100SJani Nikula /* 435379bc100SJani Nikula * GMBUS NAK handling seems to be unstable, hence let the 436379bc100SJani Nikula * transmitter detection run in bit banging mode for now. 437379bc100SJani Nikula */ 438379bc100SJani Nikula intel_gmbus_force_bit(i2c, true); 439379bc100SJani Nikula 440379bc100SJani Nikula /* 441379bc100SJani Nikula * ns2501 requires the DVO 2x clock before it will 442379bc100SJani Nikula * respond to i2c accesses, so make sure we have 443d82b9a89SVille Syrjälä * the clock enabled before we attempt to initialize 444d82b9a89SVille Syrjälä * the device. 445379bc100SJani Nikula */ 446379bc100SJani Nikula for_each_pipe(dev_priv, pipe) { 4473f7c376dSJani Nikula dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); 4483f7c376dSJani Nikula intel_de_write(dev_priv, DPLL(pipe), 4493f7c376dSJani Nikula dpll[pipe] | DPLL_DVO_2X_MODE); 450379bc100SJani Nikula } 451379bc100SJani Nikula 452d82b9a89SVille Syrjälä ret = dvo->dev_ops->init(&intel_dvo->dev, i2c); 453379bc100SJani Nikula 454379bc100SJani Nikula /* restore the DVO 2x clock state to original */ 455379bc100SJani Nikula for_each_pipe(dev_priv, pipe) { 4563f7c376dSJani Nikula intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); 457379bc100SJani Nikula } 458379bc100SJani Nikula 459379bc100SJani Nikula intel_gmbus_force_bit(i2c, false); 460379bc100SJani Nikula 461d82b9a89SVille Syrjälä return ret; 462d82b9a89SVille Syrjälä } 463d82b9a89SVille Syrjälä 464ef228dbfSVille Syrjälä static bool intel_dvo_probe(struct drm_i915_private *i915, 465d82b9a89SVille Syrjälä struct intel_dvo *intel_dvo) 466d82b9a89SVille Syrjälä { 467d82b9a89SVille Syrjälä int i; 468d82b9a89SVille Syrjälä 469d82b9a89SVille Syrjälä /* Now, try to find a controller */ 470d82b9a89SVille Syrjälä for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { 471ef228dbfSVille Syrjälä if (intel_dvo_init_dev(i915, intel_dvo, 472d82b9a89SVille Syrjälä &intel_dvo_devices[i])) 473d82b9a89SVille Syrjälä return true; 474d82b9a89SVille Syrjälä } 475d82b9a89SVille Syrjälä 476d82b9a89SVille Syrjälä return false; 477d82b9a89SVille Syrjälä } 478d82b9a89SVille Syrjälä 479ef228dbfSVille Syrjälä void intel_dvo_init(struct drm_i915_private *i915) 480d82b9a89SVille Syrjälä { 48109b350d7SVille Syrjälä struct intel_connector *connector; 48209b350d7SVille Syrjälä struct intel_encoder *encoder; 483d82b9a89SVille Syrjälä struct intel_dvo *intel_dvo; 484d82b9a89SVille Syrjälä 485d82b9a89SVille Syrjälä intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL); 486d82b9a89SVille Syrjälä if (!intel_dvo) 487d82b9a89SVille Syrjälä return; 488d82b9a89SVille Syrjälä 48909b350d7SVille Syrjälä connector = intel_connector_alloc(); 49009b350d7SVille Syrjälä if (!connector) { 491d82b9a89SVille Syrjälä kfree(intel_dvo); 492d82b9a89SVille Syrjälä return; 493d82b9a89SVille Syrjälä } 494d82b9a89SVille Syrjälä 49509b350d7SVille Syrjälä intel_dvo->attached_connector = connector; 496d82b9a89SVille Syrjälä 49709b350d7SVille Syrjälä encoder = &intel_dvo->base; 498d82b9a89SVille Syrjälä 49909b350d7SVille Syrjälä encoder->disable = intel_disable_dvo; 50009b350d7SVille Syrjälä encoder->enable = intel_enable_dvo; 50109b350d7SVille Syrjälä encoder->get_hw_state = intel_dvo_get_hw_state; 50209b350d7SVille Syrjälä encoder->get_config = intel_dvo_get_config; 50309b350d7SVille Syrjälä encoder->compute_config = intel_dvo_compute_config; 50409b350d7SVille Syrjälä encoder->pre_enable = intel_dvo_pre_enable; 50509b350d7SVille Syrjälä connector->get_hw_state = intel_dvo_connector_get_hw_state; 506d82b9a89SVille Syrjälä 507ef228dbfSVille Syrjälä if (!intel_dvo_probe(i915, intel_dvo)) { 508d82b9a89SVille Syrjälä kfree(intel_dvo); 50909b350d7SVille Syrjälä intel_connector_free(connector); 510d82b9a89SVille Syrjälä return; 511d82b9a89SVille Syrjälä } 512379bc100SJani Nikula 51309b350d7SVille Syrjälä encoder->type = INTEL_OUTPUT_DVO; 51409b350d7SVille Syrjälä encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 515a8d9a13dSVille Syrjälä encoder->port = intel_dvo->dev.port; 51609b350d7SVille Syrjälä encoder->pipe_mask = ~0; 517379bc100SJani Nikula 518d82b9a89SVille Syrjälä if (intel_dvo->dev.type != INTEL_DVO_CHIP_LVDS) 51909b350d7SVille Syrjälä encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG) | 52049fd5403SVille Syrjälä BIT(INTEL_OUTPUT_DVO); 52145608c50SVille Syrjälä 522ef228dbfSVille Syrjälä drm_encoder_init(&i915->drm, &encoder->base, 523c584f86cSVille Syrjälä &intel_dvo_enc_funcs, 524d82b9a89SVille Syrjälä intel_dvo_encoder_type(&intel_dvo->dev), 52509b350d7SVille Syrjälä "DVO %c", port_name(encoder->port)); 526c584f86cSVille Syrjälä 527d82b9a89SVille Syrjälä if (intel_dvo->dev.type == INTEL_DVO_CHIP_TMDS) 52809b350d7SVille Syrjälä connector->polled = DRM_CONNECTOR_POLL_CONNECT | 52937ec52abSVille Syrjälä DRM_CONNECTOR_POLL_DISCONNECT; 530201ec1bbSVille Syrjälä 531ef228dbfSVille Syrjälä drm_connector_init(&i915->drm, &connector->base, 532379bc100SJani Nikula &intel_dvo_connector_funcs, 533d82b9a89SVille Syrjälä intel_dvo_connector_type(&intel_dvo->dev)); 534379bc100SJani Nikula 53509b350d7SVille Syrjälä drm_connector_helper_add(&connector->base, 536379bc100SJani Nikula &intel_dvo_connector_helper_funcs); 53709b350d7SVille Syrjälä connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; 538379bc100SJani Nikula 53909b350d7SVille Syrjälä intel_connector_attach_encoder(connector, encoder); 54009b350d7SVille Syrjälä 541d82b9a89SVille Syrjälä if (intel_dvo->dev.type == INTEL_DVO_CHIP_LVDS) { 542379bc100SJani Nikula /* 543379bc100SJani Nikula * For our LVDS chipsets, we should hopefully be able 544379bc100SJani Nikula * to dig the fixed panel mode out of the BIOS data. 545379bc100SJani Nikula * However, it's in a different format from the BIOS 546379bc100SJani Nikula * data on chipsets with integrated LVDS (stored in AIM 547379bc100SJani Nikula * headers, likely), so for now, just get the current 548379bc100SJani Nikula * mode being output through DVO. 549379bc100SJani Nikula */ 55009b350d7SVille Syrjälä intel_panel_add_encoder_fixed_mode(connector, encoder); 5515248cc78SVille Syrjälä 55209b350d7SVille Syrjälä intel_panel_init(connector); 553379bc100SJani Nikula } 554379bc100SJani Nikula } 555