1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/machine.h> 29 #include <linux/mfd/intel_soc_pmic.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/machine.h> 32 #include <linux/slab.h> 33 34 #include <asm/unaligned.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 39 #include <video/mipi_display.h> 40 41 #include "i915_drv.h" 42 #include "i915_reg.h" 43 #include "intel_display_types.h" 44 #include "intel_dsi.h" 45 #include "intel_dsi_vbt.h" 46 #include "vlv_dsi.h" 47 #include "vlv_dsi_regs.h" 48 #include "vlv_sideband.h" 49 50 #define MIPI_TRANSFER_MODE_SHIFT 0 51 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 52 #define MIPI_PORT_SHIFT 3 53 54 /* base offsets for gpio pads */ 55 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 56 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 57 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 58 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 59 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 60 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 61 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 62 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 63 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 64 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 65 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 66 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 67 68 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 69 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 70 71 struct gpio_map { 72 u16 base_offset; 73 bool init; 74 }; 75 76 static struct gpio_map vlv_gpio_table[] = { 77 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 78 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 79 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 80 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 81 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 82 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 83 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 84 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 85 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 86 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 87 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 88 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 89 }; 90 91 struct i2c_adapter_lookup { 92 u16 slave_addr; 93 struct intel_dsi *intel_dsi; 94 acpi_handle dev_handle; 95 }; 96 97 #define CHV_GPIO_IDX_START_N 0 98 #define CHV_GPIO_IDX_START_E 73 99 #define CHV_GPIO_IDX_START_SW 100 100 #define CHV_GPIO_IDX_START_SE 198 101 102 #define CHV_VBT_MAX_PINS_PER_FMLY 15 103 104 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 105 #define CHV_GPIO_GPIOEN (1 << 15) 106 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 107 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 108 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 109 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 110 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 111 112 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 113 #define CHV_GPIO_CFGLOCK (1 << 31) 114 115 /* ICL DSI Display GPIO Pins */ 116 #define ICL_GPIO_DDSP_HPD_A 0 117 #define ICL_GPIO_L_VDDEN_1 1 118 #define ICL_GPIO_L_BKLTEN_1 2 119 #define ICL_GPIO_DDPA_CTRLCLK_1 3 120 #define ICL_GPIO_DDPA_CTRLDATA_1 4 121 #define ICL_GPIO_DDSP_HPD_B 5 122 #define ICL_GPIO_L_VDDEN_2 6 123 #define ICL_GPIO_L_BKLTEN_2 7 124 #define ICL_GPIO_DDPA_CTRLCLK_2 8 125 #define ICL_GPIO_DDPA_CTRLDATA_2 9 126 127 static enum port intel_dsi_seq_port_to_port(u8 port) 128 { 129 return port ? PORT_C : PORT_A; 130 } 131 132 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 133 const u8 *data) 134 { 135 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 136 struct mipi_dsi_device *dsi_device; 137 u8 type, flags, seq_port; 138 u16 len; 139 enum port port; 140 141 drm_dbg_kms(&dev_priv->drm, "\n"); 142 143 flags = *data++; 144 type = *data++; 145 146 len = *((u16 *) data); 147 data += 2; 148 149 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 150 151 /* For DSI single link on Port A & C, the seq_port value which is 152 * parsed from Sequence Block#53 of VBT has been set to 0 153 * Now, read/write of packets for the DSI single link on Port A and 154 * Port C will based on the DVO port from VBT block 2. 155 */ 156 if (intel_dsi->ports == (1 << PORT_C)) 157 port = PORT_C; 158 else 159 port = intel_dsi_seq_port_to_port(seq_port); 160 161 dsi_device = intel_dsi->dsi_hosts[port]->device; 162 if (!dsi_device) { 163 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", 164 port_name(port)); 165 goto out; 166 } 167 168 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 169 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 170 else 171 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 172 173 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 174 175 switch (type) { 176 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 177 mipi_dsi_generic_write(dsi_device, NULL, 0); 178 break; 179 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 180 mipi_dsi_generic_write(dsi_device, data, 1); 181 break; 182 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 183 mipi_dsi_generic_write(dsi_device, data, 2); 184 break; 185 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 186 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 187 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 188 drm_dbg(&dev_priv->drm, 189 "Generic Read not yet implemented or used\n"); 190 break; 191 case MIPI_DSI_GENERIC_LONG_WRITE: 192 mipi_dsi_generic_write(dsi_device, data, len); 193 break; 194 case MIPI_DSI_DCS_SHORT_WRITE: 195 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 196 break; 197 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 198 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 199 break; 200 case MIPI_DSI_DCS_READ: 201 drm_dbg(&dev_priv->drm, 202 "DCS Read not yet implemented or used\n"); 203 break; 204 case MIPI_DSI_DCS_LONG_WRITE: 205 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 206 break; 207 } 208 209 if (DISPLAY_VER(dev_priv) < 11) 210 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 211 212 out: 213 data += len; 214 215 return data; 216 } 217 218 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 219 { 220 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 221 u32 delay = *((const u32 *) data); 222 223 drm_dbg_kms(&i915->drm, "\n"); 224 225 usleep_range(delay, delay + 10); 226 data += 4; 227 228 return data; 229 } 230 231 static void vlv_exec_gpio(struct drm_i915_private *dev_priv, 232 u8 gpio_source, u8 gpio_index, bool value) 233 { 234 struct gpio_map *map; 235 u16 pconf0, padval; 236 u32 tmp; 237 u8 port; 238 239 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 240 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", 241 gpio_index); 242 return; 243 } 244 245 map = &vlv_gpio_table[gpio_index]; 246 247 if (dev_priv->vbt.dsi.seq_version >= 3) { 248 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 249 port = IOSF_PORT_GPIO_NC; 250 } else { 251 if (gpio_source == 0) { 252 port = IOSF_PORT_GPIO_NC; 253 } else if (gpio_source == 1) { 254 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); 255 return; 256 } else { 257 drm_dbg_kms(&dev_priv->drm, 258 "unknown gpio source %u\n", gpio_source); 259 return; 260 } 261 } 262 263 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 264 padval = VLV_GPIO_PAD_VAL(map->base_offset); 265 266 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 267 if (!map->init) { 268 /* FIXME: remove constant below */ 269 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 270 map->init = true; 271 } 272 273 tmp = 0x4 | value; 274 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 275 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 276 } 277 278 static void chv_exec_gpio(struct drm_i915_private *dev_priv, 279 u8 gpio_source, u8 gpio_index, bool value) 280 { 281 u16 cfg0, cfg1; 282 u16 family_num; 283 u8 port; 284 285 if (dev_priv->vbt.dsi.seq_version >= 3) { 286 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 287 /* XXX: it's unclear whether 255->57 is part of SE. */ 288 gpio_index -= CHV_GPIO_IDX_START_SE; 289 port = CHV_IOSF_PORT_GPIO_SE; 290 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 291 gpio_index -= CHV_GPIO_IDX_START_SW; 292 port = CHV_IOSF_PORT_GPIO_SW; 293 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 294 gpio_index -= CHV_GPIO_IDX_START_E; 295 port = CHV_IOSF_PORT_GPIO_E; 296 } else { 297 port = CHV_IOSF_PORT_GPIO_N; 298 } 299 } else { 300 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 301 if (gpio_source != 0) { 302 drm_dbg_kms(&dev_priv->drm, 303 "unknown gpio source %u\n", gpio_source); 304 return; 305 } 306 307 if (gpio_index >= CHV_GPIO_IDX_START_E) { 308 drm_dbg_kms(&dev_priv->drm, 309 "invalid gpio index %u for GPIO N\n", 310 gpio_index); 311 return; 312 } 313 314 port = CHV_IOSF_PORT_GPIO_N; 315 } 316 317 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 318 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 319 320 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 321 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 322 323 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 324 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 325 vlv_iosf_sb_write(dev_priv, port, cfg0, 326 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 327 CHV_GPIO_GPIOTXSTATE(value)); 328 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 329 } 330 331 static void bxt_exec_gpio(struct drm_i915_private *dev_priv, 332 u8 gpio_source, u8 gpio_index, bool value) 333 { 334 /* XXX: this table is a quick ugly hack. */ 335 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 336 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 337 338 if (!gpio_desc) { 339 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 340 NULL, gpio_index, 341 value ? GPIOD_OUT_LOW : 342 GPIOD_OUT_HIGH); 343 344 if (IS_ERR_OR_NULL(gpio_desc)) { 345 drm_err(&dev_priv->drm, 346 "GPIO index %u request failed (%ld)\n", 347 gpio_index, PTR_ERR(gpio_desc)); 348 return; 349 } 350 351 bxt_gpio_table[gpio_index] = gpio_desc; 352 } 353 354 gpiod_set_value(gpio_desc, value); 355 } 356 357 static void icl_exec_gpio(struct drm_i915_private *dev_priv, 358 u8 gpio_source, u8 gpio_index, bool value) 359 { 360 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); 361 } 362 363 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 364 { 365 struct drm_device *dev = intel_dsi->base.base.dev; 366 struct drm_i915_private *dev_priv = to_i915(dev); 367 u8 gpio_source, gpio_index = 0, gpio_number; 368 bool value; 369 370 drm_dbg_kms(&dev_priv->drm, "\n"); 371 372 if (dev_priv->vbt.dsi.seq_version >= 3) 373 gpio_index = *data++; 374 375 gpio_number = *data++; 376 377 /* gpio source in sequence v2 only */ 378 if (dev_priv->vbt.dsi.seq_version == 2) 379 gpio_source = (*data >> 1) & 3; 380 else 381 gpio_source = 0; 382 383 /* pull up/down */ 384 value = *data++ & 1; 385 386 if (DISPLAY_VER(dev_priv) >= 11) 387 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); 388 else if (IS_VALLEYVIEW(dev_priv)) 389 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 390 else if (IS_CHERRYVIEW(dev_priv)) 391 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 392 else 393 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value); 394 395 return data; 396 } 397 398 #ifdef CONFIG_ACPI 399 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 400 { 401 struct i2c_adapter_lookup *lookup = data; 402 struct intel_dsi *intel_dsi = lookup->intel_dsi; 403 struct acpi_resource_i2c_serialbus *sb; 404 struct i2c_adapter *adapter; 405 acpi_handle adapter_handle; 406 acpi_status status; 407 408 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 409 return 1; 410 411 if (lookup->slave_addr != sb->slave_address) 412 return 1; 413 414 status = acpi_get_handle(lookup->dev_handle, 415 sb->resource_source.string_ptr, 416 &adapter_handle); 417 if (ACPI_FAILURE(status)) 418 return 1; 419 420 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 421 if (adapter) 422 intel_dsi->i2c_bus_num = adapter->nr; 423 424 return 1; 425 } 426 427 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 428 const u16 slave_addr) 429 { 430 struct drm_device *drm_dev = intel_dsi->base.base.dev; 431 struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev); 432 struct i2c_adapter_lookup lookup = { 433 .slave_addr = slave_addr, 434 .intel_dsi = intel_dsi, 435 .dev_handle = acpi_device_handle(adev), 436 }; 437 LIST_HEAD(resource_list); 438 439 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup); 440 acpi_dev_free_resource_list(&resource_list); 441 } 442 #else 443 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 444 const u16 slave_addr) 445 { 446 } 447 #endif 448 449 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 450 { 451 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 452 struct i2c_adapter *adapter; 453 struct i2c_msg msg; 454 int ret; 455 u8 vbt_i2c_bus_num = *(data + 2); 456 u16 slave_addr = *(u16 *)(data + 3); 457 u8 reg_offset = *(data + 5); 458 u8 payload_size = *(data + 6); 459 u8 *payload_data; 460 461 if (intel_dsi->i2c_bus_num < 0) { 462 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 463 i2c_acpi_find_adapter(intel_dsi, slave_addr); 464 } 465 466 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 467 if (!adapter) { 468 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n"); 469 goto err_bus; 470 } 471 472 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 473 if (!payload_data) 474 goto err_alloc; 475 476 payload_data[0] = reg_offset; 477 memcpy(&payload_data[1], (data + 7), payload_size); 478 479 msg.addr = slave_addr; 480 msg.flags = 0; 481 msg.len = payload_size + 1; 482 msg.buf = payload_data; 483 484 ret = i2c_transfer(adapter, &msg, 1); 485 if (ret < 0) 486 drm_err(&i915->drm, 487 "Failed to xfer payload of size (%u) to reg (%u)\n", 488 payload_size, reg_offset); 489 490 kfree(payload_data); 491 err_alloc: 492 i2c_put_adapter(adapter); 493 err_bus: 494 return data + payload_size + 7; 495 } 496 497 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 498 { 499 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 500 501 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n"); 502 503 return data + *(data + 5) + 6; 504 } 505 506 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 507 { 508 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 509 #ifdef CONFIG_PMIC_OPREGION 510 u32 value, mask, reg_address; 511 u16 i2c_address; 512 int ret; 513 514 /* byte 0 aka PMIC Flag is reserved */ 515 i2c_address = get_unaligned_le16(data + 1); 516 reg_address = get_unaligned_le32(data + 3); 517 value = get_unaligned_le32(data + 7); 518 mask = get_unaligned_le32(data + 11); 519 520 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 521 reg_address, 522 value, mask); 523 if (ret) 524 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); 525 #else 526 drm_err(&i915->drm, 527 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 528 #endif 529 530 return data + 15; 531 } 532 533 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 534 const u8 *data); 535 static const fn_mipi_elem_exec exec_elem[] = { 536 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 537 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 538 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 539 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 540 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 541 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 542 }; 543 544 /* 545 * MIPI Sequence from VBT #53 parsing logic 546 * We have already separated each seqence during bios parsing 547 * Following is generic execution function for any sequence 548 */ 549 550 static const char * const seq_name[] = { 551 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 552 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 553 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 554 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 555 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 556 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 557 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 558 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 559 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 560 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 561 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 562 }; 563 564 static const char *sequence_name(enum mipi_seq seq_id) 565 { 566 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 567 return seq_name[seq_id]; 568 else 569 return "(unknown)"; 570 } 571 572 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 573 enum mipi_seq seq_id) 574 { 575 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 576 const u8 *data; 577 fn_mipi_elem_exec mipi_elem_exec; 578 579 if (drm_WARN_ON(&dev_priv->drm, 580 seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) 581 return; 582 583 data = dev_priv->vbt.dsi.sequence[seq_id]; 584 if (!data) 585 return; 586 587 drm_WARN_ON(&dev_priv->drm, *data != seq_id); 588 589 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", 590 seq_id, sequence_name(seq_id)); 591 592 /* Skip Sequence Byte. */ 593 data++; 594 595 /* Skip Size of Sequence. */ 596 if (dev_priv->vbt.dsi.seq_version >= 3) 597 data += 4; 598 599 while (1) { 600 u8 operation_byte = *data++; 601 u8 operation_size = 0; 602 603 if (operation_byte == MIPI_SEQ_ELEM_END) 604 break; 605 606 if (operation_byte < ARRAY_SIZE(exec_elem)) 607 mipi_elem_exec = exec_elem[operation_byte]; 608 else 609 mipi_elem_exec = NULL; 610 611 /* Size of Operation. */ 612 if (dev_priv->vbt.dsi.seq_version >= 3) 613 operation_size = *data++; 614 615 if (mipi_elem_exec) { 616 const u8 *next = data + operation_size; 617 618 data = mipi_elem_exec(intel_dsi, data); 619 620 /* Consistency check if we have size. */ 621 if (operation_size && data != next) { 622 drm_err(&dev_priv->drm, 623 "Inconsistent operation size\n"); 624 return; 625 } 626 } else if (operation_size) { 627 /* We have size, skip. */ 628 drm_dbg_kms(&dev_priv->drm, 629 "Unsupported MIPI operation byte %u\n", 630 operation_byte); 631 data += operation_size; 632 } else { 633 /* No size, can't skip without parsing. */ 634 drm_err(&dev_priv->drm, 635 "Unsupported MIPI operation byte %u\n", 636 operation_byte); 637 return; 638 } 639 } 640 } 641 642 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 643 enum mipi_seq seq_id) 644 { 645 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 646 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 647 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 648 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 649 650 intel_dsi_vbt_exec(intel_dsi, seq_id); 651 652 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 653 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 654 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 655 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 656 } 657 658 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 659 { 660 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 661 662 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 663 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) 664 return; 665 666 msleep(msec); 667 } 668 669 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 670 { 671 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 672 673 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); 674 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", 675 intel_dsi->pixel_overlap); 676 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); 677 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 678 drm_dbg_kms(&i915->drm, "Video mode format %s\n", 679 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ? 680 "non-burst with sync pulse" : 681 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ? 682 "non-burst with sync events" : 683 intel_dsi->video_mode == BURST_MODE ? 684 "burst" : "<unknown>"); 685 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", 686 intel_dsi->burst_mode_ratio); 687 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); 688 drm_dbg_kms(&i915->drm, "Eot %s\n", 689 enableddisabled(intel_dsi->eotp_pkt)); 690 drm_dbg_kms(&i915->drm, "Clockstop %s\n", 691 enableddisabled(!intel_dsi->clock_stop)); 692 drm_dbg_kms(&i915->drm, "Mode %s\n", 693 intel_dsi->operation_mode ? "command" : "video"); 694 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 695 drm_dbg_kms(&i915->drm, 696 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 697 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 698 drm_dbg_kms(&i915->drm, 699 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 700 else 701 drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); 702 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); 703 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); 704 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", 705 intel_dsi->lp_rx_timeout); 706 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", 707 intel_dsi->turn_arnd_val); 708 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); 709 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", 710 intel_dsi->hs_to_lp_count); 711 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 712 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 713 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", 714 intel_dsi->clk_lp_to_hs_count); 715 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", 716 intel_dsi->clk_hs_to_lp_count); 717 drm_dbg_kms(&i915->drm, "BTA %s\n", 718 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 719 } 720 721 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 722 { 723 struct drm_device *dev = intel_dsi->base.base.dev; 724 struct drm_i915_private *dev_priv = to_i915(dev); 725 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 726 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; 727 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; 728 u16 burst_mode_ratio; 729 enum port port; 730 731 drm_dbg_kms(&dev_priv->drm, "\n"); 732 733 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 734 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 735 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 736 intel_dsi->pixel_format = 737 pixel_format_from_register_bits( 738 mipi_config->videomode_color_format << 7); 739 740 intel_dsi->dual_link = mipi_config->dual_link; 741 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 742 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 743 intel_dsi->video_mode = mipi_config->video_transfer_mode; 744 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 745 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 746 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 747 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 748 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 749 intel_dsi->init_count = mipi_config->master_init_timer; 750 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 751 intel_dsi->video_frmt_cfg_bits = 752 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 753 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 754 755 /* Starting point, adjusted depending on dual link and burst mode */ 756 intel_dsi->pclk = mode->clock; 757 758 /* In dual link mode each port needs half of pixel clock */ 759 if (intel_dsi->dual_link) { 760 intel_dsi->pclk /= 2; 761 762 /* we can enable pixel_overlap if needed by panel. In this 763 * case we need to increase the pixelclock for extra pixels 764 */ 765 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 766 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 767 } 768 } 769 770 /* Burst Mode Ratio 771 * Target ddr frequency from VBT / non burst ddr freq 772 * multiply by 100 to preserve remainder 773 */ 774 if (intel_dsi->video_mode == BURST_MODE) { 775 if (mipi_config->target_burst_mode_freq) { 776 u32 bitrate = intel_dsi_bitrate(intel_dsi); 777 778 /* 779 * Sometimes the VBT contains a slightly lower clock, 780 * then the bitrate we have calculated, in this case 781 * just replace it with the calculated bitrate. 782 */ 783 if (mipi_config->target_burst_mode_freq < bitrate && 784 intel_fuzzy_clock_check( 785 mipi_config->target_burst_mode_freq, 786 bitrate)) 787 mipi_config->target_burst_mode_freq = bitrate; 788 789 if (mipi_config->target_burst_mode_freq < bitrate) { 790 drm_err(&dev_priv->drm, 791 "Burst mode freq is less than computed\n"); 792 return false; 793 } 794 795 burst_mode_ratio = DIV_ROUND_UP( 796 mipi_config->target_burst_mode_freq * 100, 797 bitrate); 798 799 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 800 } else { 801 drm_err(&dev_priv->drm, 802 "Burst mode target is not set\n"); 803 return false; 804 } 805 } else 806 burst_mode_ratio = 100; 807 808 intel_dsi->burst_mode_ratio = burst_mode_ratio; 809 810 /* delays in VBT are in unit of 100us, so need to convert 811 * here in ms 812 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 813 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 814 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 815 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 816 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 817 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 818 819 intel_dsi->i2c_bus_num = -1; 820 821 /* a regular driver would get the device in probe */ 822 for_each_dsi_port(port, intel_dsi->ports) { 823 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 824 } 825 826 return true; 827 } 828 829 /* 830 * On some BYT/CHT devs some sequences are incomplete and we need to manually 831 * control some GPIOs. We need to add a GPIO lookup table before we get these. 832 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 833 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 834 */ 835 static struct gpiod_lookup_table pmic_panel_gpio_table = { 836 /* Intel GFX is consumer */ 837 .dev_id = "0000:00:02.0", 838 .table = { 839 /* Panel EN/DISABLE */ 840 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 841 { } 842 }, 843 }; 844 845 static struct gpiod_lookup_table soc_panel_gpio_table = { 846 .dev_id = "0000:00:02.0", 847 .table = { 848 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 849 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 850 { } 851 }, 852 }; 853 854 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 855 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 856 "pwm0_grp", "pwm"), 857 }; 858 859 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 860 { 861 struct drm_device *dev = intel_dsi->base.base.dev; 862 struct drm_i915_private *dev_priv = to_i915(dev); 863 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 864 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 865 bool want_backlight_gpio = false; 866 bool want_panel_gpio = false; 867 struct pinctrl *pinctrl; 868 int ret; 869 870 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 871 mipi_config->pwm_blc == PPS_BLC_PMIC) { 872 gpiod_add_lookup_table(&pmic_panel_gpio_table); 873 want_panel_gpio = true; 874 } 875 876 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 877 gpiod_add_lookup_table(&soc_panel_gpio_table); 878 want_panel_gpio = true; 879 want_backlight_gpio = true; 880 881 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 882 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 883 ARRAY_SIZE(soc_pwm_pinctrl_map)); 884 if (ret) 885 drm_err(&dev_priv->drm, 886 "Failed to register pwm0 pinmux mapping\n"); 887 888 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 889 if (IS_ERR(pinctrl)) 890 drm_err(&dev_priv->drm, 891 "Failed to set pinmux to PWM\n"); 892 } 893 894 if (want_panel_gpio) { 895 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 896 if (IS_ERR(intel_dsi->gpio_panel)) { 897 drm_err(&dev_priv->drm, 898 "Failed to own gpio for panel control\n"); 899 intel_dsi->gpio_panel = NULL; 900 } 901 } 902 903 if (want_backlight_gpio) { 904 intel_dsi->gpio_backlight = 905 gpiod_get(dev->dev, "backlight", flags); 906 if (IS_ERR(intel_dsi->gpio_backlight)) { 907 drm_err(&dev_priv->drm, 908 "Failed to own gpio for backlight control\n"); 909 intel_dsi->gpio_backlight = NULL; 910 } 911 } 912 } 913 914 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 915 { 916 struct drm_device *dev = intel_dsi->base.base.dev; 917 struct drm_i915_private *dev_priv = to_i915(dev); 918 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 919 920 if (intel_dsi->gpio_panel) { 921 gpiod_put(intel_dsi->gpio_panel); 922 intel_dsi->gpio_panel = NULL; 923 } 924 925 if (intel_dsi->gpio_backlight) { 926 gpiod_put(intel_dsi->gpio_backlight); 927 intel_dsi->gpio_backlight = NULL; 928 } 929 930 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 931 mipi_config->pwm_blc == PPS_BLC_PMIC) 932 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 933 934 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 935 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 936 gpiod_remove_lookup_table(&soc_panel_gpio_table); 937 } 938 } 939