1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/machine.h> 29 #include <linux/mfd/intel_soc_pmic.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/machine.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <asm/unaligned.h> 36 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_edid.h> 39 40 #include <video/mipi_display.h> 41 42 #include "i915_drv.h" 43 #include "i915_reg.h" 44 #include "intel_display_types.h" 45 #include "intel_dsi.h" 46 #include "intel_dsi_vbt.h" 47 #include "vlv_dsi.h" 48 #include "vlv_dsi_regs.h" 49 #include "vlv_sideband.h" 50 51 #define MIPI_TRANSFER_MODE_SHIFT 0 52 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 53 #define MIPI_PORT_SHIFT 3 54 55 /* base offsets for gpio pads */ 56 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 57 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 58 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 59 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 60 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 61 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 62 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 63 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 64 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 65 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 66 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 67 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 68 69 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 70 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 71 72 struct gpio_map { 73 u16 base_offset; 74 bool init; 75 }; 76 77 static struct gpio_map vlv_gpio_table[] = { 78 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 79 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 80 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 81 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 82 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 83 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 84 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 85 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 86 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 87 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 88 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 89 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 90 }; 91 92 struct i2c_adapter_lookup { 93 u16 slave_addr; 94 struct intel_dsi *intel_dsi; 95 acpi_handle dev_handle; 96 }; 97 98 #define CHV_GPIO_IDX_START_N 0 99 #define CHV_GPIO_IDX_START_E 73 100 #define CHV_GPIO_IDX_START_SW 100 101 #define CHV_GPIO_IDX_START_SE 198 102 103 #define CHV_VBT_MAX_PINS_PER_FMLY 15 104 105 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 106 #define CHV_GPIO_GPIOEN (1 << 15) 107 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 108 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 109 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 110 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 111 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 112 113 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 114 #define CHV_GPIO_CFGLOCK (1 << 31) 115 116 /* ICL DSI Display GPIO Pins */ 117 #define ICL_GPIO_DDSP_HPD_A 0 118 #define ICL_GPIO_L_VDDEN_1 1 119 #define ICL_GPIO_L_BKLTEN_1 2 120 #define ICL_GPIO_DDPA_CTRLCLK_1 3 121 #define ICL_GPIO_DDPA_CTRLDATA_1 4 122 #define ICL_GPIO_DDSP_HPD_B 5 123 #define ICL_GPIO_L_VDDEN_2 6 124 #define ICL_GPIO_L_BKLTEN_2 7 125 #define ICL_GPIO_DDPA_CTRLCLK_2 8 126 #define ICL_GPIO_DDPA_CTRLDATA_2 9 127 128 static enum port intel_dsi_seq_port_to_port(u8 port) 129 { 130 return port ? PORT_C : PORT_A; 131 } 132 133 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 134 const u8 *data) 135 { 136 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 137 struct mipi_dsi_device *dsi_device; 138 u8 type, flags, seq_port; 139 u16 len; 140 enum port port; 141 142 drm_dbg_kms(&dev_priv->drm, "\n"); 143 144 flags = *data++; 145 type = *data++; 146 147 len = *((u16 *) data); 148 data += 2; 149 150 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 151 152 /* For DSI single link on Port A & C, the seq_port value which is 153 * parsed from Sequence Block#53 of VBT has been set to 0 154 * Now, read/write of packets for the DSI single link on Port A and 155 * Port C will based on the DVO port from VBT block 2. 156 */ 157 if (intel_dsi->ports == (1 << PORT_C)) 158 port = PORT_C; 159 else 160 port = intel_dsi_seq_port_to_port(seq_port); 161 162 dsi_device = intel_dsi->dsi_hosts[port]->device; 163 if (!dsi_device) { 164 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", 165 port_name(port)); 166 goto out; 167 } 168 169 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 170 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 171 else 172 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 173 174 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 175 176 switch (type) { 177 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 178 mipi_dsi_generic_write(dsi_device, NULL, 0); 179 break; 180 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 181 mipi_dsi_generic_write(dsi_device, data, 1); 182 break; 183 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 184 mipi_dsi_generic_write(dsi_device, data, 2); 185 break; 186 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 187 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 188 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 189 drm_dbg(&dev_priv->drm, 190 "Generic Read not yet implemented or used\n"); 191 break; 192 case MIPI_DSI_GENERIC_LONG_WRITE: 193 mipi_dsi_generic_write(dsi_device, data, len); 194 break; 195 case MIPI_DSI_DCS_SHORT_WRITE: 196 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 197 break; 198 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 199 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 200 break; 201 case MIPI_DSI_DCS_READ: 202 drm_dbg(&dev_priv->drm, 203 "DCS Read not yet implemented or used\n"); 204 break; 205 case MIPI_DSI_DCS_LONG_WRITE: 206 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 207 break; 208 } 209 210 if (DISPLAY_VER(dev_priv) < 11) 211 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 212 213 out: 214 data += len; 215 216 return data; 217 } 218 219 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 220 { 221 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 222 u32 delay = *((const u32 *) data); 223 224 drm_dbg_kms(&i915->drm, "\n"); 225 226 usleep_range(delay, delay + 10); 227 data += 4; 228 229 return data; 230 } 231 232 static void vlv_exec_gpio(struct drm_i915_private *dev_priv, 233 u8 gpio_source, u8 gpio_index, bool value) 234 { 235 struct gpio_map *map; 236 u16 pconf0, padval; 237 u32 tmp; 238 u8 port; 239 240 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 241 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", 242 gpio_index); 243 return; 244 } 245 246 map = &vlv_gpio_table[gpio_index]; 247 248 if (dev_priv->vbt.dsi.seq_version >= 3) { 249 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 250 port = IOSF_PORT_GPIO_NC; 251 } else { 252 if (gpio_source == 0) { 253 port = IOSF_PORT_GPIO_NC; 254 } else if (gpio_source == 1) { 255 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); 256 return; 257 } else { 258 drm_dbg_kms(&dev_priv->drm, 259 "unknown gpio source %u\n", gpio_source); 260 return; 261 } 262 } 263 264 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 265 padval = VLV_GPIO_PAD_VAL(map->base_offset); 266 267 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 268 if (!map->init) { 269 /* FIXME: remove constant below */ 270 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 271 map->init = true; 272 } 273 274 tmp = 0x4 | value; 275 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 276 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 277 } 278 279 static void chv_exec_gpio(struct drm_i915_private *dev_priv, 280 u8 gpio_source, u8 gpio_index, bool value) 281 { 282 u16 cfg0, cfg1; 283 u16 family_num; 284 u8 port; 285 286 if (dev_priv->vbt.dsi.seq_version >= 3) { 287 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 288 /* XXX: it's unclear whether 255->57 is part of SE. */ 289 gpio_index -= CHV_GPIO_IDX_START_SE; 290 port = CHV_IOSF_PORT_GPIO_SE; 291 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 292 gpio_index -= CHV_GPIO_IDX_START_SW; 293 port = CHV_IOSF_PORT_GPIO_SW; 294 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 295 gpio_index -= CHV_GPIO_IDX_START_E; 296 port = CHV_IOSF_PORT_GPIO_E; 297 } else { 298 port = CHV_IOSF_PORT_GPIO_N; 299 } 300 } else { 301 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 302 if (gpio_source != 0) { 303 drm_dbg_kms(&dev_priv->drm, 304 "unknown gpio source %u\n", gpio_source); 305 return; 306 } 307 308 if (gpio_index >= CHV_GPIO_IDX_START_E) { 309 drm_dbg_kms(&dev_priv->drm, 310 "invalid gpio index %u for GPIO N\n", 311 gpio_index); 312 return; 313 } 314 315 port = CHV_IOSF_PORT_GPIO_N; 316 } 317 318 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 319 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 320 321 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 322 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 323 324 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 325 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 326 vlv_iosf_sb_write(dev_priv, port, cfg0, 327 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 328 CHV_GPIO_GPIOTXSTATE(value)); 329 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 330 } 331 332 static void bxt_exec_gpio(struct drm_i915_private *dev_priv, 333 u8 gpio_source, u8 gpio_index, bool value) 334 { 335 /* XXX: this table is a quick ugly hack. */ 336 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 337 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 338 339 if (!gpio_desc) { 340 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 341 NULL, gpio_index, 342 value ? GPIOD_OUT_LOW : 343 GPIOD_OUT_HIGH); 344 345 if (IS_ERR_OR_NULL(gpio_desc)) { 346 drm_err(&dev_priv->drm, 347 "GPIO index %u request failed (%ld)\n", 348 gpio_index, PTR_ERR(gpio_desc)); 349 return; 350 } 351 352 bxt_gpio_table[gpio_index] = gpio_desc; 353 } 354 355 gpiod_set_value(gpio_desc, value); 356 } 357 358 static void icl_exec_gpio(struct drm_i915_private *dev_priv, 359 u8 gpio_source, u8 gpio_index, bool value) 360 { 361 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); 362 } 363 364 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 365 { 366 struct drm_device *dev = intel_dsi->base.base.dev; 367 struct drm_i915_private *dev_priv = to_i915(dev); 368 u8 gpio_source, gpio_index = 0, gpio_number; 369 bool value; 370 371 drm_dbg_kms(&dev_priv->drm, "\n"); 372 373 if (dev_priv->vbt.dsi.seq_version >= 3) 374 gpio_index = *data++; 375 376 gpio_number = *data++; 377 378 /* gpio source in sequence v2 only */ 379 if (dev_priv->vbt.dsi.seq_version == 2) 380 gpio_source = (*data >> 1) & 3; 381 else 382 gpio_source = 0; 383 384 /* pull up/down */ 385 value = *data++ & 1; 386 387 if (DISPLAY_VER(dev_priv) >= 11) 388 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); 389 else if (IS_VALLEYVIEW(dev_priv)) 390 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 391 else if (IS_CHERRYVIEW(dev_priv)) 392 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 393 else 394 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value); 395 396 return data; 397 } 398 399 #ifdef CONFIG_ACPI 400 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 401 { 402 struct i2c_adapter_lookup *lookup = data; 403 struct intel_dsi *intel_dsi = lookup->intel_dsi; 404 struct acpi_resource_i2c_serialbus *sb; 405 struct i2c_adapter *adapter; 406 acpi_handle adapter_handle; 407 acpi_status status; 408 409 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 410 return 1; 411 412 if (lookup->slave_addr != sb->slave_address) 413 return 1; 414 415 status = acpi_get_handle(lookup->dev_handle, 416 sb->resource_source.string_ptr, 417 &adapter_handle); 418 if (ACPI_FAILURE(status)) 419 return 1; 420 421 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 422 if (adapter) 423 intel_dsi->i2c_bus_num = adapter->nr; 424 425 return 1; 426 } 427 428 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 429 const u16 slave_addr) 430 { 431 struct drm_device *drm_dev = intel_dsi->base.base.dev; 432 struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev); 433 struct i2c_adapter_lookup lookup = { 434 .slave_addr = slave_addr, 435 .intel_dsi = intel_dsi, 436 .dev_handle = acpi_device_handle(adev), 437 }; 438 LIST_HEAD(resource_list); 439 440 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup); 441 acpi_dev_free_resource_list(&resource_list); 442 } 443 #else 444 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 445 const u16 slave_addr) 446 { 447 } 448 #endif 449 450 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 451 { 452 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 453 struct i2c_adapter *adapter; 454 struct i2c_msg msg; 455 int ret; 456 u8 vbt_i2c_bus_num = *(data + 2); 457 u16 slave_addr = *(u16 *)(data + 3); 458 u8 reg_offset = *(data + 5); 459 u8 payload_size = *(data + 6); 460 u8 *payload_data; 461 462 if (intel_dsi->i2c_bus_num < 0) { 463 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 464 i2c_acpi_find_adapter(intel_dsi, slave_addr); 465 } 466 467 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 468 if (!adapter) { 469 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n"); 470 goto err_bus; 471 } 472 473 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 474 if (!payload_data) 475 goto err_alloc; 476 477 payload_data[0] = reg_offset; 478 memcpy(&payload_data[1], (data + 7), payload_size); 479 480 msg.addr = slave_addr; 481 msg.flags = 0; 482 msg.len = payload_size + 1; 483 msg.buf = payload_data; 484 485 ret = i2c_transfer(adapter, &msg, 1); 486 if (ret < 0) 487 drm_err(&i915->drm, 488 "Failed to xfer payload of size (%u) to reg (%u)\n", 489 payload_size, reg_offset); 490 491 kfree(payload_data); 492 err_alloc: 493 i2c_put_adapter(adapter); 494 err_bus: 495 return data + payload_size + 7; 496 } 497 498 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 499 { 500 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 501 502 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n"); 503 504 return data + *(data + 5) + 6; 505 } 506 507 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 508 { 509 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 510 #ifdef CONFIG_PMIC_OPREGION 511 u32 value, mask, reg_address; 512 u16 i2c_address; 513 int ret; 514 515 /* byte 0 aka PMIC Flag is reserved */ 516 i2c_address = get_unaligned_le16(data + 1); 517 reg_address = get_unaligned_le32(data + 3); 518 value = get_unaligned_le32(data + 7); 519 mask = get_unaligned_le32(data + 11); 520 521 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 522 reg_address, 523 value, mask); 524 if (ret) 525 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); 526 #else 527 drm_err(&i915->drm, 528 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 529 #endif 530 531 return data + 15; 532 } 533 534 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 535 const u8 *data); 536 static const fn_mipi_elem_exec exec_elem[] = { 537 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 538 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 539 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 540 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 541 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 542 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 543 }; 544 545 /* 546 * MIPI Sequence from VBT #53 parsing logic 547 * We have already separated each seqence during bios parsing 548 * Following is generic execution function for any sequence 549 */ 550 551 static const char * const seq_name[] = { 552 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 553 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 554 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 555 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 556 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 557 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 558 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 559 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 560 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 561 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 562 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 563 }; 564 565 static const char *sequence_name(enum mipi_seq seq_id) 566 { 567 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 568 return seq_name[seq_id]; 569 else 570 return "(unknown)"; 571 } 572 573 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 574 enum mipi_seq seq_id) 575 { 576 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 577 const u8 *data; 578 fn_mipi_elem_exec mipi_elem_exec; 579 580 if (drm_WARN_ON(&dev_priv->drm, 581 seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) 582 return; 583 584 data = dev_priv->vbt.dsi.sequence[seq_id]; 585 if (!data) 586 return; 587 588 drm_WARN_ON(&dev_priv->drm, *data != seq_id); 589 590 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", 591 seq_id, sequence_name(seq_id)); 592 593 /* Skip Sequence Byte. */ 594 data++; 595 596 /* Skip Size of Sequence. */ 597 if (dev_priv->vbt.dsi.seq_version >= 3) 598 data += 4; 599 600 while (1) { 601 u8 operation_byte = *data++; 602 u8 operation_size = 0; 603 604 if (operation_byte == MIPI_SEQ_ELEM_END) 605 break; 606 607 if (operation_byte < ARRAY_SIZE(exec_elem)) 608 mipi_elem_exec = exec_elem[operation_byte]; 609 else 610 mipi_elem_exec = NULL; 611 612 /* Size of Operation. */ 613 if (dev_priv->vbt.dsi.seq_version >= 3) 614 operation_size = *data++; 615 616 if (mipi_elem_exec) { 617 const u8 *next = data + operation_size; 618 619 data = mipi_elem_exec(intel_dsi, data); 620 621 /* Consistency check if we have size. */ 622 if (operation_size && data != next) { 623 drm_err(&dev_priv->drm, 624 "Inconsistent operation size\n"); 625 return; 626 } 627 } else if (operation_size) { 628 /* We have size, skip. */ 629 drm_dbg_kms(&dev_priv->drm, 630 "Unsupported MIPI operation byte %u\n", 631 operation_byte); 632 data += operation_size; 633 } else { 634 /* No size, can't skip without parsing. */ 635 drm_err(&dev_priv->drm, 636 "Unsupported MIPI operation byte %u\n", 637 operation_byte); 638 return; 639 } 640 } 641 } 642 643 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 644 enum mipi_seq seq_id) 645 { 646 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 647 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 648 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 649 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 650 651 intel_dsi_vbt_exec(intel_dsi, seq_id); 652 653 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 654 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 655 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 656 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 657 } 658 659 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 660 { 661 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 662 663 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 664 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) 665 return; 666 667 msleep(msec); 668 } 669 670 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 671 { 672 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 673 674 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); 675 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", 676 intel_dsi->pixel_overlap); 677 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); 678 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 679 drm_dbg_kms(&i915->drm, "Video mode format %s\n", 680 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ? 681 "non-burst with sync pulse" : 682 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ? 683 "non-burst with sync events" : 684 intel_dsi->video_mode == BURST_MODE ? 685 "burst" : "<unknown>"); 686 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", 687 intel_dsi->burst_mode_ratio); 688 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); 689 drm_dbg_kms(&i915->drm, "Eot %s\n", 690 str_enabled_disabled(intel_dsi->eotp_pkt)); 691 drm_dbg_kms(&i915->drm, "Clockstop %s\n", 692 str_enabled_disabled(!intel_dsi->clock_stop)); 693 drm_dbg_kms(&i915->drm, "Mode %s\n", 694 intel_dsi->operation_mode ? "command" : "video"); 695 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 696 drm_dbg_kms(&i915->drm, 697 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 698 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 699 drm_dbg_kms(&i915->drm, 700 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 701 else 702 drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); 703 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); 704 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); 705 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", 706 intel_dsi->lp_rx_timeout); 707 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", 708 intel_dsi->turn_arnd_val); 709 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); 710 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", 711 intel_dsi->hs_to_lp_count); 712 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 713 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 714 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", 715 intel_dsi->clk_lp_to_hs_count); 716 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", 717 intel_dsi->clk_hs_to_lp_count); 718 drm_dbg_kms(&i915->drm, "BTA %s\n", 719 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 720 } 721 722 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 723 { 724 struct drm_device *dev = intel_dsi->base.base.dev; 725 struct drm_i915_private *dev_priv = to_i915(dev); 726 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 727 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; 728 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; 729 u16 burst_mode_ratio; 730 enum port port; 731 732 drm_dbg_kms(&dev_priv->drm, "\n"); 733 734 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 735 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 736 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 737 intel_dsi->pixel_format = 738 pixel_format_from_register_bits( 739 mipi_config->videomode_color_format << 7); 740 741 intel_dsi->dual_link = mipi_config->dual_link; 742 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 743 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 744 intel_dsi->video_mode = mipi_config->video_transfer_mode; 745 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 746 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 747 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 748 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 749 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 750 intel_dsi->init_count = mipi_config->master_init_timer; 751 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 752 intel_dsi->video_frmt_cfg_bits = 753 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 754 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 755 756 /* Starting point, adjusted depending on dual link and burst mode */ 757 intel_dsi->pclk = mode->clock; 758 759 /* In dual link mode each port needs half of pixel clock */ 760 if (intel_dsi->dual_link) { 761 intel_dsi->pclk /= 2; 762 763 /* we can enable pixel_overlap if needed by panel. In this 764 * case we need to increase the pixelclock for extra pixels 765 */ 766 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 767 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 768 } 769 } 770 771 /* Burst Mode Ratio 772 * Target ddr frequency from VBT / non burst ddr freq 773 * multiply by 100 to preserve remainder 774 */ 775 if (intel_dsi->video_mode == BURST_MODE) { 776 if (mipi_config->target_burst_mode_freq) { 777 u32 bitrate = intel_dsi_bitrate(intel_dsi); 778 779 /* 780 * Sometimes the VBT contains a slightly lower clock, 781 * then the bitrate we have calculated, in this case 782 * just replace it with the calculated bitrate. 783 */ 784 if (mipi_config->target_burst_mode_freq < bitrate && 785 intel_fuzzy_clock_check( 786 mipi_config->target_burst_mode_freq, 787 bitrate)) 788 mipi_config->target_burst_mode_freq = bitrate; 789 790 if (mipi_config->target_burst_mode_freq < bitrate) { 791 drm_err(&dev_priv->drm, 792 "Burst mode freq is less than computed\n"); 793 return false; 794 } 795 796 burst_mode_ratio = DIV_ROUND_UP( 797 mipi_config->target_burst_mode_freq * 100, 798 bitrate); 799 800 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 801 } else { 802 drm_err(&dev_priv->drm, 803 "Burst mode target is not set\n"); 804 return false; 805 } 806 } else 807 burst_mode_ratio = 100; 808 809 intel_dsi->burst_mode_ratio = burst_mode_ratio; 810 811 /* delays in VBT are in unit of 100us, so need to convert 812 * here in ms 813 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 814 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 815 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 816 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 817 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 818 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 819 820 intel_dsi->i2c_bus_num = -1; 821 822 /* a regular driver would get the device in probe */ 823 for_each_dsi_port(port, intel_dsi->ports) { 824 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 825 } 826 827 return true; 828 } 829 830 /* 831 * On some BYT/CHT devs some sequences are incomplete and we need to manually 832 * control some GPIOs. We need to add a GPIO lookup table before we get these. 833 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 834 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 835 */ 836 static struct gpiod_lookup_table pmic_panel_gpio_table = { 837 /* Intel GFX is consumer */ 838 .dev_id = "0000:00:02.0", 839 .table = { 840 /* Panel EN/DISABLE */ 841 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 842 { } 843 }, 844 }; 845 846 static struct gpiod_lookup_table soc_panel_gpio_table = { 847 .dev_id = "0000:00:02.0", 848 .table = { 849 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 850 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 851 { } 852 }, 853 }; 854 855 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 856 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 857 "pwm0_grp", "pwm"), 858 }; 859 860 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 861 { 862 struct drm_device *dev = intel_dsi->base.base.dev; 863 struct drm_i915_private *dev_priv = to_i915(dev); 864 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 865 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 866 bool want_backlight_gpio = false; 867 bool want_panel_gpio = false; 868 struct pinctrl *pinctrl; 869 int ret; 870 871 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 872 mipi_config->pwm_blc == PPS_BLC_PMIC) { 873 gpiod_add_lookup_table(&pmic_panel_gpio_table); 874 want_panel_gpio = true; 875 } 876 877 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 878 gpiod_add_lookup_table(&soc_panel_gpio_table); 879 want_panel_gpio = true; 880 want_backlight_gpio = true; 881 882 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 883 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 884 ARRAY_SIZE(soc_pwm_pinctrl_map)); 885 if (ret) 886 drm_err(&dev_priv->drm, 887 "Failed to register pwm0 pinmux mapping\n"); 888 889 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 890 if (IS_ERR(pinctrl)) 891 drm_err(&dev_priv->drm, 892 "Failed to set pinmux to PWM\n"); 893 } 894 895 if (want_panel_gpio) { 896 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 897 if (IS_ERR(intel_dsi->gpio_panel)) { 898 drm_err(&dev_priv->drm, 899 "Failed to own gpio for panel control\n"); 900 intel_dsi->gpio_panel = NULL; 901 } 902 } 903 904 if (want_backlight_gpio) { 905 intel_dsi->gpio_backlight = 906 gpiod_get(dev->dev, "backlight", flags); 907 if (IS_ERR(intel_dsi->gpio_backlight)) { 908 drm_err(&dev_priv->drm, 909 "Failed to own gpio for backlight control\n"); 910 intel_dsi->gpio_backlight = NULL; 911 } 912 } 913 } 914 915 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 916 { 917 struct drm_device *dev = intel_dsi->base.base.dev; 918 struct drm_i915_private *dev_priv = to_i915(dev); 919 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 920 921 if (intel_dsi->gpio_panel) { 922 gpiod_put(intel_dsi->gpio_panel); 923 intel_dsi->gpio_panel = NULL; 924 } 925 926 if (intel_dsi->gpio_backlight) { 927 gpiod_put(intel_dsi->gpio_backlight); 928 intel_dsi->gpio_backlight = NULL; 929 } 930 931 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 932 mipi_config->pwm_blc == PPS_BLC_PMIC) 933 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 934 935 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 936 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 937 gpiod_remove_lookup_table(&soc_panel_gpio_table); 938 } 939 } 940