1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/machine.h> 29 #include <linux/mfd/intel_soc_pmic.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/machine.h> 32 #include <linux/slab.h> 33 34 #include <asm/unaligned.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 39 #include <video/mipi_display.h> 40 41 #include "i915_drv.h" 42 #include "intel_display_types.h" 43 #include "intel_dsi.h" 44 #include "vlv_sideband.h" 45 46 #define MIPI_TRANSFER_MODE_SHIFT 0 47 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 48 #define MIPI_PORT_SHIFT 3 49 50 /* base offsets for gpio pads */ 51 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 52 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 53 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 54 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 55 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 56 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 57 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 58 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 59 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 60 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 61 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 62 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 63 64 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 65 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 66 67 struct gpio_map { 68 u16 base_offset; 69 bool init; 70 }; 71 72 static struct gpio_map vlv_gpio_table[] = { 73 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 74 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 75 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 76 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 77 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 78 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 79 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 80 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 81 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 82 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 83 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 84 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 85 }; 86 87 struct i2c_adapter_lookup { 88 u16 slave_addr; 89 struct intel_dsi *intel_dsi; 90 acpi_handle dev_handle; 91 }; 92 93 #define CHV_GPIO_IDX_START_N 0 94 #define CHV_GPIO_IDX_START_E 73 95 #define CHV_GPIO_IDX_START_SW 100 96 #define CHV_GPIO_IDX_START_SE 198 97 98 #define CHV_VBT_MAX_PINS_PER_FMLY 15 99 100 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 101 #define CHV_GPIO_GPIOEN (1 << 15) 102 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 103 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 104 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 105 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 106 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 107 108 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 109 #define CHV_GPIO_CFGLOCK (1 << 31) 110 111 /* ICL DSI Display GPIO Pins */ 112 #define ICL_GPIO_DDSP_HPD_A 0 113 #define ICL_GPIO_L_VDDEN_1 1 114 #define ICL_GPIO_L_BKLTEN_1 2 115 #define ICL_GPIO_DDPA_CTRLCLK_1 3 116 #define ICL_GPIO_DDPA_CTRLDATA_1 4 117 #define ICL_GPIO_DDSP_HPD_B 5 118 #define ICL_GPIO_L_VDDEN_2 6 119 #define ICL_GPIO_L_BKLTEN_2 7 120 #define ICL_GPIO_DDPA_CTRLCLK_2 8 121 #define ICL_GPIO_DDPA_CTRLDATA_2 9 122 123 static enum port intel_dsi_seq_port_to_port(u8 port) 124 { 125 return port ? PORT_C : PORT_A; 126 } 127 128 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 129 const u8 *data) 130 { 131 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 132 struct mipi_dsi_device *dsi_device; 133 u8 type, flags, seq_port; 134 u16 len; 135 enum port port; 136 137 drm_dbg_kms(&dev_priv->drm, "\n"); 138 139 flags = *data++; 140 type = *data++; 141 142 len = *((u16 *) data); 143 data += 2; 144 145 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 146 147 /* For DSI single link on Port A & C, the seq_port value which is 148 * parsed from Sequence Block#53 of VBT has been set to 0 149 * Now, read/write of packets for the DSI single link on Port A and 150 * Port C will based on the DVO port from VBT block 2. 151 */ 152 if (intel_dsi->ports == (1 << PORT_C)) 153 port = PORT_C; 154 else 155 port = intel_dsi_seq_port_to_port(seq_port); 156 157 dsi_device = intel_dsi->dsi_hosts[port]->device; 158 if (!dsi_device) { 159 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", 160 port_name(port)); 161 goto out; 162 } 163 164 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 165 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 166 else 167 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 168 169 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 170 171 switch (type) { 172 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 173 mipi_dsi_generic_write(dsi_device, NULL, 0); 174 break; 175 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 176 mipi_dsi_generic_write(dsi_device, data, 1); 177 break; 178 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 179 mipi_dsi_generic_write(dsi_device, data, 2); 180 break; 181 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 182 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 183 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 184 drm_dbg(&dev_priv->drm, 185 "Generic Read not yet implemented or used\n"); 186 break; 187 case MIPI_DSI_GENERIC_LONG_WRITE: 188 mipi_dsi_generic_write(dsi_device, data, len); 189 break; 190 case MIPI_DSI_DCS_SHORT_WRITE: 191 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 192 break; 193 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 194 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 195 break; 196 case MIPI_DSI_DCS_READ: 197 drm_dbg(&dev_priv->drm, 198 "DCS Read not yet implemented or used\n"); 199 break; 200 case MIPI_DSI_DCS_LONG_WRITE: 201 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 202 break; 203 } 204 205 if (DISPLAY_VER(dev_priv) < 11) 206 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 207 208 out: 209 data += len; 210 211 return data; 212 } 213 214 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 215 { 216 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 217 u32 delay = *((const u32 *) data); 218 219 drm_dbg_kms(&i915->drm, "\n"); 220 221 usleep_range(delay, delay + 10); 222 data += 4; 223 224 return data; 225 } 226 227 static void vlv_exec_gpio(struct drm_i915_private *dev_priv, 228 u8 gpio_source, u8 gpio_index, bool value) 229 { 230 struct gpio_map *map; 231 u16 pconf0, padval; 232 u32 tmp; 233 u8 port; 234 235 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 236 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", 237 gpio_index); 238 return; 239 } 240 241 map = &vlv_gpio_table[gpio_index]; 242 243 if (dev_priv->vbt.dsi.seq_version >= 3) { 244 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 245 port = IOSF_PORT_GPIO_NC; 246 } else { 247 if (gpio_source == 0) { 248 port = IOSF_PORT_GPIO_NC; 249 } else if (gpio_source == 1) { 250 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); 251 return; 252 } else { 253 drm_dbg_kms(&dev_priv->drm, 254 "unknown gpio source %u\n", gpio_source); 255 return; 256 } 257 } 258 259 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 260 padval = VLV_GPIO_PAD_VAL(map->base_offset); 261 262 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 263 if (!map->init) { 264 /* FIXME: remove constant below */ 265 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 266 map->init = true; 267 } 268 269 tmp = 0x4 | value; 270 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 271 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 272 } 273 274 static void chv_exec_gpio(struct drm_i915_private *dev_priv, 275 u8 gpio_source, u8 gpio_index, bool value) 276 { 277 u16 cfg0, cfg1; 278 u16 family_num; 279 u8 port; 280 281 if (dev_priv->vbt.dsi.seq_version >= 3) { 282 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 283 /* XXX: it's unclear whether 255->57 is part of SE. */ 284 gpio_index -= CHV_GPIO_IDX_START_SE; 285 port = CHV_IOSF_PORT_GPIO_SE; 286 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 287 gpio_index -= CHV_GPIO_IDX_START_SW; 288 port = CHV_IOSF_PORT_GPIO_SW; 289 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 290 gpio_index -= CHV_GPIO_IDX_START_E; 291 port = CHV_IOSF_PORT_GPIO_E; 292 } else { 293 port = CHV_IOSF_PORT_GPIO_N; 294 } 295 } else { 296 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 297 if (gpio_source != 0) { 298 drm_dbg_kms(&dev_priv->drm, 299 "unknown gpio source %u\n", gpio_source); 300 return; 301 } 302 303 if (gpio_index >= CHV_GPIO_IDX_START_E) { 304 drm_dbg_kms(&dev_priv->drm, 305 "invalid gpio index %u for GPIO N\n", 306 gpio_index); 307 return; 308 } 309 310 port = CHV_IOSF_PORT_GPIO_N; 311 } 312 313 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 314 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 315 316 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 317 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 318 319 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 320 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 321 vlv_iosf_sb_write(dev_priv, port, cfg0, 322 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 323 CHV_GPIO_GPIOTXSTATE(value)); 324 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 325 } 326 327 static void bxt_exec_gpio(struct drm_i915_private *dev_priv, 328 u8 gpio_source, u8 gpio_index, bool value) 329 { 330 /* XXX: this table is a quick ugly hack. */ 331 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 332 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 333 334 if (!gpio_desc) { 335 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 336 NULL, gpio_index, 337 value ? GPIOD_OUT_LOW : 338 GPIOD_OUT_HIGH); 339 340 if (IS_ERR_OR_NULL(gpio_desc)) { 341 drm_err(&dev_priv->drm, 342 "GPIO index %u request failed (%ld)\n", 343 gpio_index, PTR_ERR(gpio_desc)); 344 return; 345 } 346 347 bxt_gpio_table[gpio_index] = gpio_desc; 348 } 349 350 gpiod_set_value(gpio_desc, value); 351 } 352 353 static void icl_exec_gpio(struct drm_i915_private *dev_priv, 354 u8 gpio_source, u8 gpio_index, bool value) 355 { 356 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); 357 } 358 359 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 360 { 361 struct drm_device *dev = intel_dsi->base.base.dev; 362 struct drm_i915_private *dev_priv = to_i915(dev); 363 u8 gpio_source, gpio_index = 0, gpio_number; 364 bool value; 365 366 drm_dbg_kms(&dev_priv->drm, "\n"); 367 368 if (dev_priv->vbt.dsi.seq_version >= 3) 369 gpio_index = *data++; 370 371 gpio_number = *data++; 372 373 /* gpio source in sequence v2 only */ 374 if (dev_priv->vbt.dsi.seq_version == 2) 375 gpio_source = (*data >> 1) & 3; 376 else 377 gpio_source = 0; 378 379 /* pull up/down */ 380 value = *data++ & 1; 381 382 if (DISPLAY_VER(dev_priv) >= 11) 383 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); 384 else if (IS_VALLEYVIEW(dev_priv)) 385 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 386 else if (IS_CHERRYVIEW(dev_priv)) 387 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 388 else 389 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value); 390 391 return data; 392 } 393 394 #ifdef CONFIG_ACPI 395 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 396 { 397 struct i2c_adapter_lookup *lookup = data; 398 struct intel_dsi *intel_dsi = lookup->intel_dsi; 399 struct acpi_resource_i2c_serialbus *sb; 400 struct i2c_adapter *adapter; 401 acpi_handle adapter_handle; 402 acpi_status status; 403 404 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 405 return 1; 406 407 if (lookup->slave_addr != sb->slave_address) 408 return 1; 409 410 status = acpi_get_handle(lookup->dev_handle, 411 sb->resource_source.string_ptr, 412 &adapter_handle); 413 if (ACPI_FAILURE(status)) 414 return 1; 415 416 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 417 if (adapter) 418 intel_dsi->i2c_bus_num = adapter->nr; 419 420 return 1; 421 } 422 423 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 424 const u16 slave_addr) 425 { 426 struct drm_device *drm_dev = intel_dsi->base.base.dev; 427 struct device *dev = drm_dev->dev; 428 struct acpi_device *acpi_dev; 429 struct list_head resource_list; 430 struct i2c_adapter_lookup lookup; 431 432 acpi_dev = ACPI_COMPANION(dev); 433 if (acpi_dev) { 434 memset(&lookup, 0, sizeof(lookup)); 435 lookup.slave_addr = slave_addr; 436 lookup.intel_dsi = intel_dsi; 437 lookup.dev_handle = acpi_device_handle(acpi_dev); 438 439 INIT_LIST_HEAD(&resource_list); 440 acpi_dev_get_resources(acpi_dev, &resource_list, 441 i2c_adapter_lookup, 442 &lookup); 443 acpi_dev_free_resource_list(&resource_list); 444 } 445 } 446 #else 447 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 448 const u16 slave_addr) 449 { 450 } 451 #endif 452 453 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 454 { 455 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 456 struct i2c_adapter *adapter; 457 struct i2c_msg msg; 458 int ret; 459 u8 vbt_i2c_bus_num = *(data + 2); 460 u16 slave_addr = *(u16 *)(data + 3); 461 u8 reg_offset = *(data + 5); 462 u8 payload_size = *(data + 6); 463 u8 *payload_data; 464 465 if (intel_dsi->i2c_bus_num < 0) { 466 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 467 i2c_acpi_find_adapter(intel_dsi, slave_addr); 468 } 469 470 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 471 if (!adapter) { 472 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n"); 473 goto err_bus; 474 } 475 476 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 477 if (!payload_data) 478 goto err_alloc; 479 480 payload_data[0] = reg_offset; 481 memcpy(&payload_data[1], (data + 7), payload_size); 482 483 msg.addr = slave_addr; 484 msg.flags = 0; 485 msg.len = payload_size + 1; 486 msg.buf = payload_data; 487 488 ret = i2c_transfer(adapter, &msg, 1); 489 if (ret < 0) 490 drm_err(&i915->drm, 491 "Failed to xfer payload of size (%u) to reg (%u)\n", 492 payload_size, reg_offset); 493 494 kfree(payload_data); 495 err_alloc: 496 i2c_put_adapter(adapter); 497 err_bus: 498 return data + payload_size + 7; 499 } 500 501 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 502 { 503 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 504 505 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n"); 506 507 return data + *(data + 5) + 6; 508 } 509 510 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 511 { 512 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 513 #ifdef CONFIG_PMIC_OPREGION 514 u32 value, mask, reg_address; 515 u16 i2c_address; 516 int ret; 517 518 /* byte 0 aka PMIC Flag is reserved */ 519 i2c_address = get_unaligned_le16(data + 1); 520 reg_address = get_unaligned_le32(data + 3); 521 value = get_unaligned_le32(data + 7); 522 mask = get_unaligned_le32(data + 11); 523 524 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 525 reg_address, 526 value, mask); 527 if (ret) 528 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); 529 #else 530 drm_err(&i915->drm, 531 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 532 #endif 533 534 return data + 15; 535 } 536 537 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 538 const u8 *data); 539 static const fn_mipi_elem_exec exec_elem[] = { 540 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 541 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 542 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 543 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 544 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 545 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 546 }; 547 548 /* 549 * MIPI Sequence from VBT #53 parsing logic 550 * We have already separated each seqence during bios parsing 551 * Following is generic execution function for any sequence 552 */ 553 554 static const char * const seq_name[] = { 555 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 556 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 557 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 558 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 559 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 560 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 561 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 562 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 563 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 564 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 565 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 566 }; 567 568 static const char *sequence_name(enum mipi_seq seq_id) 569 { 570 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 571 return seq_name[seq_id]; 572 else 573 return "(unknown)"; 574 } 575 576 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 577 enum mipi_seq seq_id) 578 { 579 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 580 const u8 *data; 581 fn_mipi_elem_exec mipi_elem_exec; 582 583 if (drm_WARN_ON(&dev_priv->drm, 584 seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) 585 return; 586 587 data = dev_priv->vbt.dsi.sequence[seq_id]; 588 if (!data) 589 return; 590 591 drm_WARN_ON(&dev_priv->drm, *data != seq_id); 592 593 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", 594 seq_id, sequence_name(seq_id)); 595 596 /* Skip Sequence Byte. */ 597 data++; 598 599 /* Skip Size of Sequence. */ 600 if (dev_priv->vbt.dsi.seq_version >= 3) 601 data += 4; 602 603 while (1) { 604 u8 operation_byte = *data++; 605 u8 operation_size = 0; 606 607 if (operation_byte == MIPI_SEQ_ELEM_END) 608 break; 609 610 if (operation_byte < ARRAY_SIZE(exec_elem)) 611 mipi_elem_exec = exec_elem[operation_byte]; 612 else 613 mipi_elem_exec = NULL; 614 615 /* Size of Operation. */ 616 if (dev_priv->vbt.dsi.seq_version >= 3) 617 operation_size = *data++; 618 619 if (mipi_elem_exec) { 620 const u8 *next = data + operation_size; 621 622 data = mipi_elem_exec(intel_dsi, data); 623 624 /* Consistency check if we have size. */ 625 if (operation_size && data != next) { 626 drm_err(&dev_priv->drm, 627 "Inconsistent operation size\n"); 628 return; 629 } 630 } else if (operation_size) { 631 /* We have size, skip. */ 632 drm_dbg_kms(&dev_priv->drm, 633 "Unsupported MIPI operation byte %u\n", 634 operation_byte); 635 data += operation_size; 636 } else { 637 /* No size, can't skip without parsing. */ 638 drm_err(&dev_priv->drm, 639 "Unsupported MIPI operation byte %u\n", 640 operation_byte); 641 return; 642 } 643 } 644 } 645 646 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 647 enum mipi_seq seq_id) 648 { 649 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 650 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 651 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 652 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 653 654 intel_dsi_vbt_exec(intel_dsi, seq_id); 655 656 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 657 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 658 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 659 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 660 } 661 662 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 663 { 664 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 665 666 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 667 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) 668 return; 669 670 msleep(msec); 671 } 672 673 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 674 { 675 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 676 677 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); 678 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", 679 intel_dsi->pixel_overlap); 680 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); 681 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 682 drm_dbg_kms(&i915->drm, "Video mode format %s\n", 683 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ? 684 "non-burst with sync pulse" : 685 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ? 686 "non-burst with sync events" : 687 intel_dsi->video_mode_format == VIDEO_MODE_BURST ? 688 "burst" : "<unknown>"); 689 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", 690 intel_dsi->burst_mode_ratio); 691 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); 692 drm_dbg_kms(&i915->drm, "Eot %s\n", 693 enableddisabled(intel_dsi->eotp_pkt)); 694 drm_dbg_kms(&i915->drm, "Clockstop %s\n", 695 enableddisabled(!intel_dsi->clock_stop)); 696 drm_dbg_kms(&i915->drm, "Mode %s\n", 697 intel_dsi->operation_mode ? "command" : "video"); 698 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 699 drm_dbg_kms(&i915->drm, 700 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 701 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 702 drm_dbg_kms(&i915->drm, 703 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 704 else 705 drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); 706 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); 707 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); 708 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", 709 intel_dsi->lp_rx_timeout); 710 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", 711 intel_dsi->turn_arnd_val); 712 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); 713 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", 714 intel_dsi->hs_to_lp_count); 715 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 716 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 717 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", 718 intel_dsi->clk_lp_to_hs_count); 719 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", 720 intel_dsi->clk_hs_to_lp_count); 721 drm_dbg_kms(&i915->drm, "BTA %s\n", 722 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 723 } 724 725 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 726 { 727 struct drm_device *dev = intel_dsi->base.base.dev; 728 struct drm_i915_private *dev_priv = to_i915(dev); 729 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 730 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; 731 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; 732 u16 burst_mode_ratio; 733 enum port port; 734 735 drm_dbg_kms(&dev_priv->drm, "\n"); 736 737 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 738 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 739 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 740 intel_dsi->pixel_format = 741 pixel_format_from_register_bits( 742 mipi_config->videomode_color_format << 7); 743 744 intel_dsi->dual_link = mipi_config->dual_link; 745 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 746 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 747 intel_dsi->video_mode_format = mipi_config->video_transfer_mode; 748 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 749 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 750 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 751 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 752 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 753 intel_dsi->init_count = mipi_config->master_init_timer; 754 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 755 intel_dsi->video_frmt_cfg_bits = 756 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 757 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 758 759 /* Starting point, adjusted depending on dual link and burst mode */ 760 intel_dsi->pclk = mode->clock; 761 762 /* In dual link mode each port needs half of pixel clock */ 763 if (intel_dsi->dual_link) { 764 intel_dsi->pclk /= 2; 765 766 /* we can enable pixel_overlap if needed by panel. In this 767 * case we need to increase the pixelclock for extra pixels 768 */ 769 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 770 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 771 } 772 } 773 774 /* Burst Mode Ratio 775 * Target ddr frequency from VBT / non burst ddr freq 776 * multiply by 100 to preserve remainder 777 */ 778 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 779 if (mipi_config->target_burst_mode_freq) { 780 u32 bitrate = intel_dsi_bitrate(intel_dsi); 781 782 /* 783 * Sometimes the VBT contains a slightly lower clock, 784 * then the bitrate we have calculated, in this case 785 * just replace it with the calculated bitrate. 786 */ 787 if (mipi_config->target_burst_mode_freq < bitrate && 788 intel_fuzzy_clock_check( 789 mipi_config->target_burst_mode_freq, 790 bitrate)) 791 mipi_config->target_burst_mode_freq = bitrate; 792 793 if (mipi_config->target_burst_mode_freq < bitrate) { 794 drm_err(&dev_priv->drm, 795 "Burst mode freq is less than computed\n"); 796 return false; 797 } 798 799 burst_mode_ratio = DIV_ROUND_UP( 800 mipi_config->target_burst_mode_freq * 100, 801 bitrate); 802 803 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 804 } else { 805 drm_err(&dev_priv->drm, 806 "Burst mode target is not set\n"); 807 return false; 808 } 809 } else 810 burst_mode_ratio = 100; 811 812 intel_dsi->burst_mode_ratio = burst_mode_ratio; 813 814 /* delays in VBT are in unit of 100us, so need to convert 815 * here in ms 816 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 817 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 818 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 819 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 820 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 821 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 822 823 intel_dsi->i2c_bus_num = -1; 824 825 /* a regular driver would get the device in probe */ 826 for_each_dsi_port(port, intel_dsi->ports) { 827 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 828 } 829 830 return true; 831 } 832 833 /* 834 * On some BYT/CHT devs some sequences are incomplete and we need to manually 835 * control some GPIOs. We need to add a GPIO lookup table before we get these. 836 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 837 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 838 */ 839 static struct gpiod_lookup_table pmic_panel_gpio_table = { 840 /* Intel GFX is consumer */ 841 .dev_id = "0000:00:02.0", 842 .table = { 843 /* Panel EN/DISABLE */ 844 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 845 { } 846 }, 847 }; 848 849 static struct gpiod_lookup_table soc_panel_gpio_table = { 850 .dev_id = "0000:00:02.0", 851 .table = { 852 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 853 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 854 { } 855 }, 856 }; 857 858 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 859 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 860 "pwm0_grp", "pwm"), 861 }; 862 863 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 864 { 865 struct drm_device *dev = intel_dsi->base.base.dev; 866 struct drm_i915_private *dev_priv = to_i915(dev); 867 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 868 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 869 bool want_backlight_gpio = false; 870 bool want_panel_gpio = false; 871 struct pinctrl *pinctrl; 872 int ret; 873 874 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 875 mipi_config->pwm_blc == PPS_BLC_PMIC) { 876 gpiod_add_lookup_table(&pmic_panel_gpio_table); 877 want_panel_gpio = true; 878 } 879 880 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 881 gpiod_add_lookup_table(&soc_panel_gpio_table); 882 want_panel_gpio = true; 883 want_backlight_gpio = true; 884 885 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 886 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 887 ARRAY_SIZE(soc_pwm_pinctrl_map)); 888 if (ret) 889 drm_err(&dev_priv->drm, 890 "Failed to register pwm0 pinmux mapping\n"); 891 892 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 893 if (IS_ERR(pinctrl)) 894 drm_err(&dev_priv->drm, 895 "Failed to set pinmux to PWM\n"); 896 } 897 898 if (want_panel_gpio) { 899 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 900 if (IS_ERR(intel_dsi->gpio_panel)) { 901 drm_err(&dev_priv->drm, 902 "Failed to own gpio for panel control\n"); 903 intel_dsi->gpio_panel = NULL; 904 } 905 } 906 907 if (want_backlight_gpio) { 908 intel_dsi->gpio_backlight = 909 gpiod_get(dev->dev, "backlight", flags); 910 if (IS_ERR(intel_dsi->gpio_backlight)) { 911 drm_err(&dev_priv->drm, 912 "Failed to own gpio for backlight control\n"); 913 intel_dsi->gpio_backlight = NULL; 914 } 915 } 916 } 917 918 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 919 { 920 struct drm_device *dev = intel_dsi->base.base.dev; 921 struct drm_i915_private *dev_priv = to_i915(dev); 922 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 923 924 if (intel_dsi->gpio_panel) { 925 gpiod_put(intel_dsi->gpio_panel); 926 intel_dsi->gpio_panel = NULL; 927 } 928 929 if (intel_dsi->gpio_backlight) { 930 gpiod_put(intel_dsi->gpio_backlight); 931 intel_dsi->gpio_backlight = NULL; 932 } 933 934 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 935 mipi_config->pwm_blc == PPS_BLC_PMIC) 936 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 937 938 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 939 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 940 gpiod_remove_lookup_table(&soc_panel_gpio_table); 941 } 942 } 943