1 /*
2  * Copyright © 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24  *
25  */
26 
27 #include <linux/gpio/consumer.h>
28 #include <linux/gpio/machine.h>
29 #include <linux/mfd/intel_soc_pmic.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pinctrl/machine.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
34 
35 #include <asm/unaligned.h>
36 
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_edid.h>
39 
40 #include <video/mipi_display.h>
41 
42 #include "i915_drv.h"
43 #include "i915_reg.h"
44 #include "intel_display_types.h"
45 #include "intel_dsi.h"
46 #include "intel_dsi_vbt.h"
47 #include "vlv_dsi.h"
48 #include "vlv_dsi_regs.h"
49 #include "vlv_sideband.h"
50 
51 #define MIPI_TRANSFER_MODE_SHIFT	0
52 #define MIPI_VIRTUAL_CHANNEL_SHIFT	1
53 #define MIPI_PORT_SHIFT			3
54 
55 /* base offsets for gpio pads */
56 #define VLV_GPIO_NC_0_HV_DDI0_HPD	0x4130
57 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA	0x4120
58 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL	0x4110
59 #define VLV_GPIO_NC_3_PANEL0_VDDEN	0x4140
60 #define VLV_GPIO_NC_4_PANEL0_BKLTEN	0x4150
61 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL	0x4160
62 #define VLV_GPIO_NC_6_HV_DDI1_HPD	0x4180
63 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA	0x4190
64 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL	0x4170
65 #define VLV_GPIO_NC_9_PANEL1_VDDEN	0x4100
66 #define VLV_GPIO_NC_10_PANEL1_BKLTEN	0x40E0
67 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL	0x40F0
68 
69 #define VLV_GPIO_PCONF0(base_offset)	(base_offset)
70 #define VLV_GPIO_PAD_VAL(base_offset)	((base_offset) + 8)
71 
72 struct gpio_map {
73 	u16 base_offset;
74 	bool init;
75 };
76 
77 static struct gpio_map vlv_gpio_table[] = {
78 	{ VLV_GPIO_NC_0_HV_DDI0_HPD },
79 	{ VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
80 	{ VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
81 	{ VLV_GPIO_NC_3_PANEL0_VDDEN },
82 	{ VLV_GPIO_NC_4_PANEL0_BKLTEN },
83 	{ VLV_GPIO_NC_5_PANEL0_BKLTCTL },
84 	{ VLV_GPIO_NC_6_HV_DDI1_HPD },
85 	{ VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
86 	{ VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
87 	{ VLV_GPIO_NC_9_PANEL1_VDDEN },
88 	{ VLV_GPIO_NC_10_PANEL1_BKLTEN },
89 	{ VLV_GPIO_NC_11_PANEL1_BKLTCTL },
90 };
91 
92 struct i2c_adapter_lookup {
93 	u16 slave_addr;
94 	struct intel_dsi *intel_dsi;
95 	acpi_handle dev_handle;
96 };
97 
98 #define CHV_GPIO_IDX_START_N		0
99 #define CHV_GPIO_IDX_START_E		73
100 #define CHV_GPIO_IDX_START_SW		100
101 #define CHV_GPIO_IDX_START_SE		198
102 
103 #define CHV_VBT_MAX_PINS_PER_FMLY	15
104 
105 #define CHV_GPIO_PAD_CFG0(f, i)		(0x4400 + (f) * 0x400 + (i) * 8)
106 #define  CHV_GPIO_GPIOEN		(1 << 15)
107 #define  CHV_GPIO_GPIOCFG_GPIO		(0 << 8)
108 #define  CHV_GPIO_GPIOCFG_GPO		(1 << 8)
109 #define  CHV_GPIO_GPIOCFG_GPI		(2 << 8)
110 #define  CHV_GPIO_GPIOCFG_HIZ		(3 << 8)
111 #define  CHV_GPIO_GPIOTXSTATE(state)	((!!(state)) << 1)
112 
113 #define CHV_GPIO_PAD_CFG1(f, i)		(0x4400 + (f) * 0x400 + (i) * 8 + 4)
114 #define  CHV_GPIO_CFGLOCK		(1 << 31)
115 
116 /* ICL DSI Display GPIO Pins */
117 #define  ICL_GPIO_DDSP_HPD_A		0
118 #define  ICL_GPIO_L_VDDEN_1		1
119 #define  ICL_GPIO_L_BKLTEN_1		2
120 #define  ICL_GPIO_DDPA_CTRLCLK_1	3
121 #define  ICL_GPIO_DDPA_CTRLDATA_1	4
122 #define  ICL_GPIO_DDSP_HPD_B		5
123 #define  ICL_GPIO_L_VDDEN_2		6
124 #define  ICL_GPIO_L_BKLTEN_2		7
125 #define  ICL_GPIO_DDPA_CTRLCLK_2	8
126 #define  ICL_GPIO_DDPA_CTRLDATA_2	9
127 
128 static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,
129 					    u8 seq_port)
130 {
131 	/*
132 	 * If single link DSI is being used on any port, the VBT sequence block
133 	 * send packet apparently always has 0 for the port. Just use the port
134 	 * we have configured, and ignore the sequence block port.
135 	 */
136 	if (hweight8(intel_dsi->ports) == 1)
137 		return ffs(intel_dsi->ports) - 1;
138 
139 	if (seq_port) {
140 		if (intel_dsi->ports & BIT(PORT_B))
141 			return PORT_B;
142 		else if (intel_dsi->ports & BIT(PORT_C))
143 			return PORT_C;
144 	}
145 
146 	return PORT_A;
147 }
148 
149 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
150 				       const u8 *data)
151 {
152 	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
153 	struct mipi_dsi_device *dsi_device;
154 	u8 type, flags, seq_port;
155 	u16 len;
156 	enum port port;
157 
158 	drm_dbg_kms(&dev_priv->drm, "\n");
159 
160 	flags = *data++;
161 	type = *data++;
162 
163 	len = *((u16 *) data);
164 	data += 2;
165 
166 	seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
167 
168 	port = intel_dsi_seq_port_to_port(intel_dsi, seq_port);
169 
170 	if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port]))
171 		goto out;
172 
173 	dsi_device = intel_dsi->dsi_hosts[port]->device;
174 	if (!dsi_device) {
175 		drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",
176 			    port_name(port));
177 		goto out;
178 	}
179 
180 	if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
181 		dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
182 	else
183 		dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
184 
185 	dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
186 
187 	switch (type) {
188 	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
189 		mipi_dsi_generic_write(dsi_device, NULL, 0);
190 		break;
191 	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
192 		mipi_dsi_generic_write(dsi_device, data, 1);
193 		break;
194 	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
195 		mipi_dsi_generic_write(dsi_device, data, 2);
196 		break;
197 	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
198 	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
199 	case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
200 		drm_dbg(&dev_priv->drm,
201 			"Generic Read not yet implemented or used\n");
202 		break;
203 	case MIPI_DSI_GENERIC_LONG_WRITE:
204 		mipi_dsi_generic_write(dsi_device, data, len);
205 		break;
206 	case MIPI_DSI_DCS_SHORT_WRITE:
207 		mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
208 		break;
209 	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
210 		mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
211 		break;
212 	case MIPI_DSI_DCS_READ:
213 		drm_dbg(&dev_priv->drm,
214 			"DCS Read not yet implemented or used\n");
215 		break;
216 	case MIPI_DSI_DCS_LONG_WRITE:
217 		mipi_dsi_dcs_write_buffer(dsi_device, data, len);
218 		break;
219 	}
220 
221 	if (DISPLAY_VER(dev_priv) < 11)
222 		vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
223 
224 out:
225 	data += len;
226 
227 	return data;
228 }
229 
230 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
231 {
232 	struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
233 	u32 delay = *((const u32 *) data);
234 
235 	drm_dbg_kms(&i915->drm, "\n");
236 
237 	usleep_range(delay, delay + 10);
238 	data += 4;
239 
240 	return data;
241 }
242 
243 static void vlv_exec_gpio(struct intel_connector *connector,
244 			  u8 gpio_source, u8 gpio_index, bool value)
245 {
246 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
247 	struct gpio_map *map;
248 	u16 pconf0, padval;
249 	u32 tmp;
250 	u8 port;
251 
252 	if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
253 		drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n",
254 			    gpio_index);
255 		return;
256 	}
257 
258 	map = &vlv_gpio_table[gpio_index];
259 
260 	if (connector->panel.vbt.dsi.seq_version >= 3) {
261 		/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
262 		port = IOSF_PORT_GPIO_NC;
263 	} else {
264 		if (gpio_source == 0) {
265 			port = IOSF_PORT_GPIO_NC;
266 		} else if (gpio_source == 1) {
267 			drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n");
268 			return;
269 		} else {
270 			drm_dbg_kms(&dev_priv->drm,
271 				    "unknown gpio source %u\n", gpio_source);
272 			return;
273 		}
274 	}
275 
276 	pconf0 = VLV_GPIO_PCONF0(map->base_offset);
277 	padval = VLV_GPIO_PAD_VAL(map->base_offset);
278 
279 	vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
280 	if (!map->init) {
281 		/* FIXME: remove constant below */
282 		vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
283 		map->init = true;
284 	}
285 
286 	tmp = 0x4 | value;
287 	vlv_iosf_sb_write(dev_priv, port, padval, tmp);
288 	vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
289 }
290 
291 static void chv_exec_gpio(struct intel_connector *connector,
292 			  u8 gpio_source, u8 gpio_index, bool value)
293 {
294 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
295 	u16 cfg0, cfg1;
296 	u16 family_num;
297 	u8 port;
298 
299 	if (connector->panel.vbt.dsi.seq_version >= 3) {
300 		if (gpio_index >= CHV_GPIO_IDX_START_SE) {
301 			/* XXX: it's unclear whether 255->57 is part of SE. */
302 			gpio_index -= CHV_GPIO_IDX_START_SE;
303 			port = CHV_IOSF_PORT_GPIO_SE;
304 		} else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
305 			gpio_index -= CHV_GPIO_IDX_START_SW;
306 			port = CHV_IOSF_PORT_GPIO_SW;
307 		} else if (gpio_index >= CHV_GPIO_IDX_START_E) {
308 			gpio_index -= CHV_GPIO_IDX_START_E;
309 			port = CHV_IOSF_PORT_GPIO_E;
310 		} else {
311 			port = CHV_IOSF_PORT_GPIO_N;
312 		}
313 	} else {
314 		/* XXX: The spec is unclear about CHV GPIO on seq v2 */
315 		if (gpio_source != 0) {
316 			drm_dbg_kms(&dev_priv->drm,
317 				    "unknown gpio source %u\n", gpio_source);
318 			return;
319 		}
320 
321 		if (gpio_index >= CHV_GPIO_IDX_START_E) {
322 			drm_dbg_kms(&dev_priv->drm,
323 				    "invalid gpio index %u for GPIO N\n",
324 				    gpio_index);
325 			return;
326 		}
327 
328 		port = CHV_IOSF_PORT_GPIO_N;
329 	}
330 
331 	family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
332 	gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
333 
334 	cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
335 	cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
336 
337 	vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
338 	vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
339 	vlv_iosf_sb_write(dev_priv, port, cfg0,
340 			  CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
341 			  CHV_GPIO_GPIOTXSTATE(value));
342 	vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
343 }
344 
345 static void bxt_exec_gpio(struct intel_connector *connector,
346 			  u8 gpio_source, u8 gpio_index, bool value)
347 {
348 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
349 	/* XXX: this table is a quick ugly hack. */
350 	static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
351 	struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
352 
353 	if (!gpio_desc) {
354 		gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
355 						 NULL, gpio_index,
356 						 value ? GPIOD_OUT_LOW :
357 						 GPIOD_OUT_HIGH);
358 
359 		if (IS_ERR_OR_NULL(gpio_desc)) {
360 			drm_err(&dev_priv->drm,
361 				"GPIO index %u request failed (%ld)\n",
362 				gpio_index, PTR_ERR(gpio_desc));
363 			return;
364 		}
365 
366 		bxt_gpio_table[gpio_index] = gpio_desc;
367 	}
368 
369 	gpiod_set_value(gpio_desc, value);
370 }
371 
372 static void icl_exec_gpio(struct intel_connector *connector,
373 			  u8 gpio_source, u8 gpio_index, bool value)
374 {
375 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
376 
377 	drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
378 }
379 
380 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
381 {
382 	struct drm_device *dev = intel_dsi->base.base.dev;
383 	struct drm_i915_private *dev_priv = to_i915(dev);
384 	struct intel_connector *connector = intel_dsi->attached_connector;
385 	u8 gpio_source, gpio_index = 0, gpio_number;
386 	bool value;
387 
388 	drm_dbg_kms(&dev_priv->drm, "\n");
389 
390 	if (connector->panel.vbt.dsi.seq_version >= 3)
391 		gpio_index = *data++;
392 
393 	gpio_number = *data++;
394 
395 	/* gpio source in sequence v2 only */
396 	if (connector->panel.vbt.dsi.seq_version == 2)
397 		gpio_source = (*data >> 1) & 3;
398 	else
399 		gpio_source = 0;
400 
401 	/* pull up/down */
402 	value = *data++ & 1;
403 
404 	if (DISPLAY_VER(dev_priv) >= 11)
405 		icl_exec_gpio(connector, gpio_source, gpio_index, value);
406 	else if (IS_VALLEYVIEW(dev_priv))
407 		vlv_exec_gpio(connector, gpio_source, gpio_number, value);
408 	else if (IS_CHERRYVIEW(dev_priv))
409 		chv_exec_gpio(connector, gpio_source, gpio_number, value);
410 	else
411 		bxt_exec_gpio(connector, gpio_source, gpio_index, value);
412 
413 	return data;
414 }
415 
416 #ifdef CONFIG_ACPI
417 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
418 {
419 	struct i2c_adapter_lookup *lookup = data;
420 	struct intel_dsi *intel_dsi = lookup->intel_dsi;
421 	struct acpi_resource_i2c_serialbus *sb;
422 	struct i2c_adapter *adapter;
423 	acpi_handle adapter_handle;
424 	acpi_status status;
425 
426 	if (!i2c_acpi_get_i2c_resource(ares, &sb))
427 		return 1;
428 
429 	if (lookup->slave_addr != sb->slave_address)
430 		return 1;
431 
432 	status = acpi_get_handle(lookup->dev_handle,
433 				 sb->resource_source.string_ptr,
434 				 &adapter_handle);
435 	if (ACPI_FAILURE(status))
436 		return 1;
437 
438 	adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
439 	if (adapter)
440 		intel_dsi->i2c_bus_num = adapter->nr;
441 
442 	return 1;
443 }
444 
445 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
446 				  const u16 slave_addr)
447 {
448 	struct drm_device *drm_dev = intel_dsi->base.base.dev;
449 	struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev);
450 	struct i2c_adapter_lookup lookup = {
451 		.slave_addr = slave_addr,
452 		.intel_dsi = intel_dsi,
453 		.dev_handle = acpi_device_handle(adev),
454 	};
455 	LIST_HEAD(resource_list);
456 
457 	acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup);
458 	acpi_dev_free_resource_list(&resource_list);
459 }
460 #else
461 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
462 					 const u16 slave_addr)
463 {
464 }
465 #endif
466 
467 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
468 {
469 	struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
470 	struct i2c_adapter *adapter;
471 	struct i2c_msg msg;
472 	int ret;
473 	u8 vbt_i2c_bus_num = *(data + 2);
474 	u16 slave_addr = *(u16 *)(data + 3);
475 	u8 reg_offset = *(data + 5);
476 	u8 payload_size = *(data + 6);
477 	u8 *payload_data;
478 
479 	if (intel_dsi->i2c_bus_num < 0) {
480 		intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
481 		i2c_acpi_find_adapter(intel_dsi, slave_addr);
482 	}
483 
484 	adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
485 	if (!adapter) {
486 		drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n");
487 		goto err_bus;
488 	}
489 
490 	payload_data = kzalloc(payload_size + 1, GFP_KERNEL);
491 	if (!payload_data)
492 		goto err_alloc;
493 
494 	payload_data[0] = reg_offset;
495 	memcpy(&payload_data[1], (data + 7), payload_size);
496 
497 	msg.addr = slave_addr;
498 	msg.flags = 0;
499 	msg.len = payload_size + 1;
500 	msg.buf = payload_data;
501 
502 	ret = i2c_transfer(adapter, &msg, 1);
503 	if (ret < 0)
504 		drm_err(&i915->drm,
505 			"Failed to xfer payload of size (%u) to reg (%u)\n",
506 			payload_size, reg_offset);
507 
508 	kfree(payload_data);
509 err_alloc:
510 	i2c_put_adapter(adapter);
511 err_bus:
512 	return data + payload_size + 7;
513 }
514 
515 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
516 {
517 	struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
518 
519 	drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n");
520 
521 	return data + *(data + 5) + 6;
522 }
523 
524 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
525 {
526 	struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
527 #ifdef CONFIG_PMIC_OPREGION
528 	u32 value, mask, reg_address;
529 	u16 i2c_address;
530 	int ret;
531 
532 	/* byte 0 aka PMIC Flag is reserved */
533 	i2c_address	= get_unaligned_le16(data + 1);
534 	reg_address	= get_unaligned_le32(data + 3);
535 	value		= get_unaligned_le32(data + 7);
536 	mask		= get_unaligned_le32(data + 11);
537 
538 	ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
539 							reg_address,
540 							value, mask);
541 	if (ret)
542 		drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret);
543 #else
544 	drm_err(&i915->drm,
545 		"Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
546 #endif
547 
548 	return data + 15;
549 }
550 
551 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
552 					const u8 *data);
553 static const fn_mipi_elem_exec exec_elem[] = {
554 	[MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
555 	[MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
556 	[MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
557 	[MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
558 	[MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
559 	[MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
560 };
561 
562 /*
563  * MIPI Sequence from VBT #53 parsing logic
564  * We have already separated each seqence during bios parsing
565  * Following is generic execution function for any sequence
566  */
567 
568 static const char * const seq_name[] = {
569 	[MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
570 	[MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
571 	[MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
572 	[MIPI_SEQ_DISPLAY_OFF]  = "MIPI_SEQ_DISPLAY_OFF",
573 	[MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
574 	[MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
575 	[MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
576 	[MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
577 	[MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
578 	[MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
579 	[MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
580 };
581 
582 static const char *sequence_name(enum mipi_seq seq_id)
583 {
584 	if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
585 		return seq_name[seq_id];
586 	else
587 		return "(unknown)";
588 }
589 
590 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
591 			       enum mipi_seq seq_id)
592 {
593 	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
594 	struct intel_connector *connector = intel_dsi->attached_connector;
595 	const u8 *data;
596 	fn_mipi_elem_exec mipi_elem_exec;
597 
598 	if (drm_WARN_ON(&dev_priv->drm,
599 			seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence)))
600 		return;
601 
602 	data = connector->panel.vbt.dsi.sequence[seq_id];
603 	if (!data)
604 		return;
605 
606 	drm_WARN_ON(&dev_priv->drm, *data != seq_id);
607 
608 	drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",
609 		    seq_id, sequence_name(seq_id));
610 
611 	/* Skip Sequence Byte. */
612 	data++;
613 
614 	/* Skip Size of Sequence. */
615 	if (connector->panel.vbt.dsi.seq_version >= 3)
616 		data += 4;
617 
618 	while (1) {
619 		u8 operation_byte = *data++;
620 		u8 operation_size = 0;
621 
622 		if (operation_byte == MIPI_SEQ_ELEM_END)
623 			break;
624 
625 		if (operation_byte < ARRAY_SIZE(exec_elem))
626 			mipi_elem_exec = exec_elem[operation_byte];
627 		else
628 			mipi_elem_exec = NULL;
629 
630 		/* Size of Operation. */
631 		if (connector->panel.vbt.dsi.seq_version >= 3)
632 			operation_size = *data++;
633 
634 		if (mipi_elem_exec) {
635 			const u8 *next = data + operation_size;
636 
637 			data = mipi_elem_exec(intel_dsi, data);
638 
639 			/* Consistency check if we have size. */
640 			if (operation_size && data != next) {
641 				drm_err(&dev_priv->drm,
642 					"Inconsistent operation size\n");
643 				return;
644 			}
645 		} else if (operation_size) {
646 			/* We have size, skip. */
647 			drm_dbg_kms(&dev_priv->drm,
648 				    "Unsupported MIPI operation byte %u\n",
649 				    operation_byte);
650 			data += operation_size;
651 		} else {
652 			/* No size, can't skip without parsing. */
653 			drm_err(&dev_priv->drm,
654 				"Unsupported MIPI operation byte %u\n",
655 				operation_byte);
656 			return;
657 		}
658 	}
659 }
660 
661 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
662 				 enum mipi_seq seq_id)
663 {
664 	if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
665 		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
666 	if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
667 		gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
668 
669 	intel_dsi_vbt_exec(intel_dsi, seq_id);
670 
671 	if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
672 		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
673 	if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
674 		gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
675 }
676 
677 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
678 {
679 	struct intel_connector *connector = intel_dsi->attached_connector;
680 
681 	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
682 	if (is_vid_mode(intel_dsi) && connector->panel.vbt.dsi.seq_version >= 3)
683 		return;
684 
685 	msleep(msec);
686 }
687 
688 void intel_dsi_log_params(struct intel_dsi *intel_dsi)
689 {
690 	struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
691 
692 	drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk);
693 	drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",
694 		    intel_dsi->pixel_overlap);
695 	drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count);
696 	drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
697 	drm_dbg_kms(&i915->drm, "Video mode format %s\n",
698 		    intel_dsi->video_mode == NON_BURST_SYNC_PULSE ?
699 		    "non-burst with sync pulse" :
700 		    intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ?
701 		    "non-burst with sync events" :
702 		    intel_dsi->video_mode == BURST_MODE ?
703 		    "burst" : "<unknown>");
704 	drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",
705 		    intel_dsi->burst_mode_ratio);
706 	drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val);
707 	drm_dbg_kms(&i915->drm, "Eot %s\n",
708 		    str_enabled_disabled(intel_dsi->eotp_pkt));
709 	drm_dbg_kms(&i915->drm, "Clockstop %s\n",
710 		    str_enabled_disabled(!intel_dsi->clock_stop));
711 	drm_dbg_kms(&i915->drm, "Mode %s\n",
712 		    intel_dsi->operation_mode ? "command" : "video");
713 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
714 		drm_dbg_kms(&i915->drm,
715 			    "Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
716 	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
717 		drm_dbg_kms(&i915->drm,
718 			    "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
719 	else
720 		drm_dbg_kms(&i915->drm, "Dual link: NONE\n");
721 	drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format);
722 	drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div);
723 	drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",
724 		    intel_dsi->lp_rx_timeout);
725 	drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",
726 		    intel_dsi->turn_arnd_val);
727 	drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count);
728 	drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",
729 		    intel_dsi->hs_to_lp_count);
730 	drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
731 	drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
732 	drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",
733 		    intel_dsi->clk_lp_to_hs_count);
734 	drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",
735 		    intel_dsi->clk_hs_to_lp_count);
736 	drm_dbg_kms(&i915->drm, "BTA %s\n",
737 		    str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
738 }
739 
740 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
741 {
742 	struct drm_device *dev = intel_dsi->base.base.dev;
743 	struct drm_i915_private *dev_priv = to_i915(dev);
744 	struct intel_connector *connector = intel_dsi->attached_connector;
745 	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
746 	struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps;
747 	struct drm_display_mode *mode = connector->panel.vbt.lfp_lvds_vbt_mode;
748 	u16 burst_mode_ratio;
749 	enum port port;
750 
751 	drm_dbg_kms(&dev_priv->drm, "\n");
752 
753 	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
754 	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
755 	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
756 	intel_dsi->pixel_format =
757 			pixel_format_from_register_bits(
758 				mipi_config->videomode_color_format << 7);
759 
760 	intel_dsi->dual_link = mipi_config->dual_link;
761 	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
762 	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
763 	intel_dsi->video_mode = mipi_config->video_transfer_mode;
764 	intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
765 	intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
766 	intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
767 	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
768 	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
769 	intel_dsi->init_count = mipi_config->master_init_timer;
770 	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
771 	intel_dsi->video_frmt_cfg_bits =
772 		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
773 	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
774 
775 	/* Starting point, adjusted depending on dual link and burst mode */
776 	intel_dsi->pclk = mode->clock;
777 
778 	/* In dual link mode each port needs half of pixel clock */
779 	if (intel_dsi->dual_link) {
780 		intel_dsi->pclk /= 2;
781 
782 		/* we can enable pixel_overlap if needed by panel. In this
783 		 * case we need to increase the pixelclock for extra pixels
784 		 */
785 		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
786 			intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
787 		}
788 	}
789 
790 	/* Burst Mode Ratio
791 	 * Target ddr frequency from VBT / non burst ddr freq
792 	 * multiply by 100 to preserve remainder
793 	 */
794 	if (intel_dsi->video_mode == BURST_MODE) {
795 		if (mipi_config->target_burst_mode_freq) {
796 			u32 bitrate = intel_dsi_bitrate(intel_dsi);
797 
798 			/*
799 			 * Sometimes the VBT contains a slightly lower clock,
800 			 * then the bitrate we have calculated, in this case
801 			 * just replace it with the calculated bitrate.
802 			 */
803 			if (mipi_config->target_burst_mode_freq < bitrate &&
804 			    intel_fuzzy_clock_check(
805 					mipi_config->target_burst_mode_freq,
806 					bitrate))
807 				mipi_config->target_burst_mode_freq = bitrate;
808 
809 			if (mipi_config->target_burst_mode_freq < bitrate) {
810 				drm_err(&dev_priv->drm,
811 					"Burst mode freq is less than computed\n");
812 				return false;
813 			}
814 
815 			burst_mode_ratio = DIV_ROUND_UP(
816 				mipi_config->target_burst_mode_freq * 100,
817 				bitrate);
818 
819 			intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
820 		} else {
821 			drm_err(&dev_priv->drm,
822 				"Burst mode target is not set\n");
823 			return false;
824 		}
825 	} else
826 		burst_mode_ratio = 100;
827 
828 	intel_dsi->burst_mode_ratio = burst_mode_ratio;
829 
830 	/* delays in VBT are in unit of 100us, so need to convert
831 	 * here in ms
832 	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
833 	intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
834 	intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
835 	intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
836 	intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
837 	intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
838 
839 	intel_dsi->i2c_bus_num = -1;
840 
841 	/* a regular driver would get the device in probe */
842 	for_each_dsi_port(port, intel_dsi->ports) {
843 		mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
844 	}
845 
846 	return true;
847 }
848 
849 /*
850  * On some BYT/CHT devs some sequences are incomplete and we need to manually
851  * control some GPIOs. We need to add a GPIO lookup table before we get these.
852  * If the GOP did not initialize the panel (HDMI inserted) we may need to also
853  * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
854  */
855 static struct gpiod_lookup_table pmic_panel_gpio_table = {
856 	/* Intel GFX is consumer */
857 	.dev_id = "0000:00:02.0",
858 	.table = {
859 		/* Panel EN/DISABLE */
860 		GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
861 		{ }
862 	},
863 };
864 
865 static struct gpiod_lookup_table soc_panel_gpio_table = {
866 	.dev_id = "0000:00:02.0",
867 	.table = {
868 		GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
869 		GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
870 		{ }
871 	},
872 };
873 
874 static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
875 	PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
876 			  "pwm0_grp", "pwm"),
877 };
878 
879 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
880 {
881 	struct drm_device *dev = intel_dsi->base.base.dev;
882 	struct drm_i915_private *dev_priv = to_i915(dev);
883 	struct intel_connector *connector = intel_dsi->attached_connector;
884 	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
885 	enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
886 	bool want_backlight_gpio = false;
887 	bool want_panel_gpio = false;
888 	struct pinctrl *pinctrl;
889 	int ret;
890 
891 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
892 	    mipi_config->pwm_blc == PPS_BLC_PMIC) {
893 		gpiod_add_lookup_table(&pmic_panel_gpio_table);
894 		want_panel_gpio = true;
895 	}
896 
897 	if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
898 		gpiod_add_lookup_table(&soc_panel_gpio_table);
899 		want_panel_gpio = true;
900 		want_backlight_gpio = true;
901 
902 		/* Ensure PWM0 pin is muxed as PWM instead of GPIO */
903 		ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
904 					     ARRAY_SIZE(soc_pwm_pinctrl_map));
905 		if (ret)
906 			drm_err(&dev_priv->drm,
907 				"Failed to register pwm0 pinmux mapping\n");
908 
909 		pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
910 		if (IS_ERR(pinctrl))
911 			drm_err(&dev_priv->drm,
912 				"Failed to set pinmux to PWM\n");
913 	}
914 
915 	if (want_panel_gpio) {
916 		intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
917 		if (IS_ERR(intel_dsi->gpio_panel)) {
918 			drm_err(&dev_priv->drm,
919 				"Failed to own gpio for panel control\n");
920 			intel_dsi->gpio_panel = NULL;
921 		}
922 	}
923 
924 	if (want_backlight_gpio) {
925 		intel_dsi->gpio_backlight =
926 			gpiod_get(dev->dev, "backlight", flags);
927 		if (IS_ERR(intel_dsi->gpio_backlight)) {
928 			drm_err(&dev_priv->drm,
929 				"Failed to own gpio for backlight control\n");
930 			intel_dsi->gpio_backlight = NULL;
931 		}
932 	}
933 }
934 
935 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
936 {
937 	struct drm_device *dev = intel_dsi->base.base.dev;
938 	struct drm_i915_private *dev_priv = to_i915(dev);
939 	struct intel_connector *connector = intel_dsi->attached_connector;
940 	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
941 
942 	if (intel_dsi->gpio_panel) {
943 		gpiod_put(intel_dsi->gpio_panel);
944 		intel_dsi->gpio_panel = NULL;
945 	}
946 
947 	if (intel_dsi->gpio_backlight) {
948 		gpiod_put(intel_dsi->gpio_backlight);
949 		intel_dsi->gpio_backlight = NULL;
950 	}
951 
952 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
953 	    mipi_config->pwm_blc == PPS_BLC_PMIC)
954 		gpiod_remove_lookup_table(&pmic_panel_gpio_table);
955 
956 	if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
957 		pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
958 		gpiod_remove_lookup_table(&soc_panel_gpio_table);
959 	}
960 }
961