1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/machine.h> 29 #include <linux/mfd/intel_soc_pmic.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/machine.h> 32 #include <linux/slab.h> 33 34 #include <asm/unaligned.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 39 #include <video/mipi_display.h> 40 41 #include "i915_drv.h" 42 #include "i915_reg.h" 43 #include "intel_display_types.h" 44 #include "intel_dsi.h" 45 #include "intel_dsi_vbt.h" 46 #include "vlv_dsi.h" 47 #include "vlv_sideband.h" 48 49 #define MIPI_TRANSFER_MODE_SHIFT 0 50 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 51 #define MIPI_PORT_SHIFT 3 52 53 /* base offsets for gpio pads */ 54 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 55 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 56 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 57 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 58 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 59 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 60 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 61 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 62 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 63 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 64 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 65 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 66 67 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 68 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 69 70 struct gpio_map { 71 u16 base_offset; 72 bool init; 73 }; 74 75 static struct gpio_map vlv_gpio_table[] = { 76 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 77 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 78 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 79 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 80 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 81 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 82 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 83 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 84 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 85 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 86 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 87 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 88 }; 89 90 struct i2c_adapter_lookup { 91 u16 slave_addr; 92 struct intel_dsi *intel_dsi; 93 acpi_handle dev_handle; 94 }; 95 96 #define CHV_GPIO_IDX_START_N 0 97 #define CHV_GPIO_IDX_START_E 73 98 #define CHV_GPIO_IDX_START_SW 100 99 #define CHV_GPIO_IDX_START_SE 198 100 101 #define CHV_VBT_MAX_PINS_PER_FMLY 15 102 103 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 104 #define CHV_GPIO_GPIOEN (1 << 15) 105 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 106 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 107 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 108 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 109 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 110 111 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 112 #define CHV_GPIO_CFGLOCK (1 << 31) 113 114 /* ICL DSI Display GPIO Pins */ 115 #define ICL_GPIO_DDSP_HPD_A 0 116 #define ICL_GPIO_L_VDDEN_1 1 117 #define ICL_GPIO_L_BKLTEN_1 2 118 #define ICL_GPIO_DDPA_CTRLCLK_1 3 119 #define ICL_GPIO_DDPA_CTRLDATA_1 4 120 #define ICL_GPIO_DDSP_HPD_B 5 121 #define ICL_GPIO_L_VDDEN_2 6 122 #define ICL_GPIO_L_BKLTEN_2 7 123 #define ICL_GPIO_DDPA_CTRLCLK_2 8 124 #define ICL_GPIO_DDPA_CTRLDATA_2 9 125 126 static enum port intel_dsi_seq_port_to_port(u8 port) 127 { 128 return port ? PORT_C : PORT_A; 129 } 130 131 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 132 const u8 *data) 133 { 134 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 135 struct mipi_dsi_device *dsi_device; 136 u8 type, flags, seq_port; 137 u16 len; 138 enum port port; 139 140 drm_dbg_kms(&dev_priv->drm, "\n"); 141 142 flags = *data++; 143 type = *data++; 144 145 len = *((u16 *) data); 146 data += 2; 147 148 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 149 150 /* For DSI single link on Port A & C, the seq_port value which is 151 * parsed from Sequence Block#53 of VBT has been set to 0 152 * Now, read/write of packets for the DSI single link on Port A and 153 * Port C will based on the DVO port from VBT block 2. 154 */ 155 if (intel_dsi->ports == (1 << PORT_C)) 156 port = PORT_C; 157 else 158 port = intel_dsi_seq_port_to_port(seq_port); 159 160 dsi_device = intel_dsi->dsi_hosts[port]->device; 161 if (!dsi_device) { 162 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", 163 port_name(port)); 164 goto out; 165 } 166 167 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 168 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 169 else 170 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 171 172 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 173 174 switch (type) { 175 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 176 mipi_dsi_generic_write(dsi_device, NULL, 0); 177 break; 178 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 179 mipi_dsi_generic_write(dsi_device, data, 1); 180 break; 181 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 182 mipi_dsi_generic_write(dsi_device, data, 2); 183 break; 184 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 185 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 186 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 187 drm_dbg(&dev_priv->drm, 188 "Generic Read not yet implemented or used\n"); 189 break; 190 case MIPI_DSI_GENERIC_LONG_WRITE: 191 mipi_dsi_generic_write(dsi_device, data, len); 192 break; 193 case MIPI_DSI_DCS_SHORT_WRITE: 194 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 195 break; 196 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 197 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 198 break; 199 case MIPI_DSI_DCS_READ: 200 drm_dbg(&dev_priv->drm, 201 "DCS Read not yet implemented or used\n"); 202 break; 203 case MIPI_DSI_DCS_LONG_WRITE: 204 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 205 break; 206 } 207 208 if (DISPLAY_VER(dev_priv) < 11) 209 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 210 211 out: 212 data += len; 213 214 return data; 215 } 216 217 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 218 { 219 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 220 u32 delay = *((const u32 *) data); 221 222 drm_dbg_kms(&i915->drm, "\n"); 223 224 usleep_range(delay, delay + 10); 225 data += 4; 226 227 return data; 228 } 229 230 static void vlv_exec_gpio(struct drm_i915_private *dev_priv, 231 u8 gpio_source, u8 gpio_index, bool value) 232 { 233 struct gpio_map *map; 234 u16 pconf0, padval; 235 u32 tmp; 236 u8 port; 237 238 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 239 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", 240 gpio_index); 241 return; 242 } 243 244 map = &vlv_gpio_table[gpio_index]; 245 246 if (dev_priv->vbt.dsi.seq_version >= 3) { 247 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 248 port = IOSF_PORT_GPIO_NC; 249 } else { 250 if (gpio_source == 0) { 251 port = IOSF_PORT_GPIO_NC; 252 } else if (gpio_source == 1) { 253 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); 254 return; 255 } else { 256 drm_dbg_kms(&dev_priv->drm, 257 "unknown gpio source %u\n", gpio_source); 258 return; 259 } 260 } 261 262 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 263 padval = VLV_GPIO_PAD_VAL(map->base_offset); 264 265 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 266 if (!map->init) { 267 /* FIXME: remove constant below */ 268 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 269 map->init = true; 270 } 271 272 tmp = 0x4 | value; 273 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 274 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 275 } 276 277 static void chv_exec_gpio(struct drm_i915_private *dev_priv, 278 u8 gpio_source, u8 gpio_index, bool value) 279 { 280 u16 cfg0, cfg1; 281 u16 family_num; 282 u8 port; 283 284 if (dev_priv->vbt.dsi.seq_version >= 3) { 285 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 286 /* XXX: it's unclear whether 255->57 is part of SE. */ 287 gpio_index -= CHV_GPIO_IDX_START_SE; 288 port = CHV_IOSF_PORT_GPIO_SE; 289 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 290 gpio_index -= CHV_GPIO_IDX_START_SW; 291 port = CHV_IOSF_PORT_GPIO_SW; 292 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 293 gpio_index -= CHV_GPIO_IDX_START_E; 294 port = CHV_IOSF_PORT_GPIO_E; 295 } else { 296 port = CHV_IOSF_PORT_GPIO_N; 297 } 298 } else { 299 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 300 if (gpio_source != 0) { 301 drm_dbg_kms(&dev_priv->drm, 302 "unknown gpio source %u\n", gpio_source); 303 return; 304 } 305 306 if (gpio_index >= CHV_GPIO_IDX_START_E) { 307 drm_dbg_kms(&dev_priv->drm, 308 "invalid gpio index %u for GPIO N\n", 309 gpio_index); 310 return; 311 } 312 313 port = CHV_IOSF_PORT_GPIO_N; 314 } 315 316 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 317 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 318 319 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 320 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 321 322 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 323 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 324 vlv_iosf_sb_write(dev_priv, port, cfg0, 325 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 326 CHV_GPIO_GPIOTXSTATE(value)); 327 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 328 } 329 330 static void bxt_exec_gpio(struct drm_i915_private *dev_priv, 331 u8 gpio_source, u8 gpio_index, bool value) 332 { 333 /* XXX: this table is a quick ugly hack. */ 334 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 335 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 336 337 if (!gpio_desc) { 338 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 339 NULL, gpio_index, 340 value ? GPIOD_OUT_LOW : 341 GPIOD_OUT_HIGH); 342 343 if (IS_ERR_OR_NULL(gpio_desc)) { 344 drm_err(&dev_priv->drm, 345 "GPIO index %u request failed (%ld)\n", 346 gpio_index, PTR_ERR(gpio_desc)); 347 return; 348 } 349 350 bxt_gpio_table[gpio_index] = gpio_desc; 351 } 352 353 gpiod_set_value(gpio_desc, value); 354 } 355 356 static void icl_exec_gpio(struct drm_i915_private *dev_priv, 357 u8 gpio_source, u8 gpio_index, bool value) 358 { 359 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); 360 } 361 362 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 363 { 364 struct drm_device *dev = intel_dsi->base.base.dev; 365 struct drm_i915_private *dev_priv = to_i915(dev); 366 u8 gpio_source, gpio_index = 0, gpio_number; 367 bool value; 368 369 drm_dbg_kms(&dev_priv->drm, "\n"); 370 371 if (dev_priv->vbt.dsi.seq_version >= 3) 372 gpio_index = *data++; 373 374 gpio_number = *data++; 375 376 /* gpio source in sequence v2 only */ 377 if (dev_priv->vbt.dsi.seq_version == 2) 378 gpio_source = (*data >> 1) & 3; 379 else 380 gpio_source = 0; 381 382 /* pull up/down */ 383 value = *data++ & 1; 384 385 if (DISPLAY_VER(dev_priv) >= 11) 386 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); 387 else if (IS_VALLEYVIEW(dev_priv)) 388 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 389 else if (IS_CHERRYVIEW(dev_priv)) 390 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 391 else 392 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value); 393 394 return data; 395 } 396 397 #ifdef CONFIG_ACPI 398 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 399 { 400 struct i2c_adapter_lookup *lookup = data; 401 struct intel_dsi *intel_dsi = lookup->intel_dsi; 402 struct acpi_resource_i2c_serialbus *sb; 403 struct i2c_adapter *adapter; 404 acpi_handle adapter_handle; 405 acpi_status status; 406 407 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 408 return 1; 409 410 if (lookup->slave_addr != sb->slave_address) 411 return 1; 412 413 status = acpi_get_handle(lookup->dev_handle, 414 sb->resource_source.string_ptr, 415 &adapter_handle); 416 if (ACPI_FAILURE(status)) 417 return 1; 418 419 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 420 if (adapter) 421 intel_dsi->i2c_bus_num = adapter->nr; 422 423 return 1; 424 } 425 426 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 427 const u16 slave_addr) 428 { 429 struct drm_device *drm_dev = intel_dsi->base.base.dev; 430 struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev); 431 struct i2c_adapter_lookup lookup = { 432 .slave_addr = slave_addr, 433 .intel_dsi = intel_dsi, 434 .dev_handle = acpi_device_handle(adev), 435 }; 436 LIST_HEAD(resource_list); 437 438 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup); 439 acpi_dev_free_resource_list(&resource_list); 440 } 441 #else 442 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 443 const u16 slave_addr) 444 { 445 } 446 #endif 447 448 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 449 { 450 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 451 struct i2c_adapter *adapter; 452 struct i2c_msg msg; 453 int ret; 454 u8 vbt_i2c_bus_num = *(data + 2); 455 u16 slave_addr = *(u16 *)(data + 3); 456 u8 reg_offset = *(data + 5); 457 u8 payload_size = *(data + 6); 458 u8 *payload_data; 459 460 if (intel_dsi->i2c_bus_num < 0) { 461 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 462 i2c_acpi_find_adapter(intel_dsi, slave_addr); 463 } 464 465 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 466 if (!adapter) { 467 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n"); 468 goto err_bus; 469 } 470 471 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 472 if (!payload_data) 473 goto err_alloc; 474 475 payload_data[0] = reg_offset; 476 memcpy(&payload_data[1], (data + 7), payload_size); 477 478 msg.addr = slave_addr; 479 msg.flags = 0; 480 msg.len = payload_size + 1; 481 msg.buf = payload_data; 482 483 ret = i2c_transfer(adapter, &msg, 1); 484 if (ret < 0) 485 drm_err(&i915->drm, 486 "Failed to xfer payload of size (%u) to reg (%u)\n", 487 payload_size, reg_offset); 488 489 kfree(payload_data); 490 err_alloc: 491 i2c_put_adapter(adapter); 492 err_bus: 493 return data + payload_size + 7; 494 } 495 496 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 497 { 498 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 499 500 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n"); 501 502 return data + *(data + 5) + 6; 503 } 504 505 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 506 { 507 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 508 #ifdef CONFIG_PMIC_OPREGION 509 u32 value, mask, reg_address; 510 u16 i2c_address; 511 int ret; 512 513 /* byte 0 aka PMIC Flag is reserved */ 514 i2c_address = get_unaligned_le16(data + 1); 515 reg_address = get_unaligned_le32(data + 3); 516 value = get_unaligned_le32(data + 7); 517 mask = get_unaligned_le32(data + 11); 518 519 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 520 reg_address, 521 value, mask); 522 if (ret) 523 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); 524 #else 525 drm_err(&i915->drm, 526 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 527 #endif 528 529 return data + 15; 530 } 531 532 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 533 const u8 *data); 534 static const fn_mipi_elem_exec exec_elem[] = { 535 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 536 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 537 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 538 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 539 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 540 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 541 }; 542 543 /* 544 * MIPI Sequence from VBT #53 parsing logic 545 * We have already separated each seqence during bios parsing 546 * Following is generic execution function for any sequence 547 */ 548 549 static const char * const seq_name[] = { 550 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 551 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 552 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 553 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 554 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 555 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 556 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 557 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 558 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 559 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 560 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 561 }; 562 563 static const char *sequence_name(enum mipi_seq seq_id) 564 { 565 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 566 return seq_name[seq_id]; 567 else 568 return "(unknown)"; 569 } 570 571 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 572 enum mipi_seq seq_id) 573 { 574 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 575 const u8 *data; 576 fn_mipi_elem_exec mipi_elem_exec; 577 578 if (drm_WARN_ON(&dev_priv->drm, 579 seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) 580 return; 581 582 data = dev_priv->vbt.dsi.sequence[seq_id]; 583 if (!data) 584 return; 585 586 drm_WARN_ON(&dev_priv->drm, *data != seq_id); 587 588 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", 589 seq_id, sequence_name(seq_id)); 590 591 /* Skip Sequence Byte. */ 592 data++; 593 594 /* Skip Size of Sequence. */ 595 if (dev_priv->vbt.dsi.seq_version >= 3) 596 data += 4; 597 598 while (1) { 599 u8 operation_byte = *data++; 600 u8 operation_size = 0; 601 602 if (operation_byte == MIPI_SEQ_ELEM_END) 603 break; 604 605 if (operation_byte < ARRAY_SIZE(exec_elem)) 606 mipi_elem_exec = exec_elem[operation_byte]; 607 else 608 mipi_elem_exec = NULL; 609 610 /* Size of Operation. */ 611 if (dev_priv->vbt.dsi.seq_version >= 3) 612 operation_size = *data++; 613 614 if (mipi_elem_exec) { 615 const u8 *next = data + operation_size; 616 617 data = mipi_elem_exec(intel_dsi, data); 618 619 /* Consistency check if we have size. */ 620 if (operation_size && data != next) { 621 drm_err(&dev_priv->drm, 622 "Inconsistent operation size\n"); 623 return; 624 } 625 } else if (operation_size) { 626 /* We have size, skip. */ 627 drm_dbg_kms(&dev_priv->drm, 628 "Unsupported MIPI operation byte %u\n", 629 operation_byte); 630 data += operation_size; 631 } else { 632 /* No size, can't skip without parsing. */ 633 drm_err(&dev_priv->drm, 634 "Unsupported MIPI operation byte %u\n", 635 operation_byte); 636 return; 637 } 638 } 639 } 640 641 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 642 enum mipi_seq seq_id) 643 { 644 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 645 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 646 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 647 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 648 649 intel_dsi_vbt_exec(intel_dsi, seq_id); 650 651 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 652 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 653 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 654 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 655 } 656 657 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 658 { 659 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 660 661 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 662 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) 663 return; 664 665 msleep(msec); 666 } 667 668 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 669 { 670 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 671 672 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); 673 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", 674 intel_dsi->pixel_overlap); 675 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); 676 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 677 drm_dbg_kms(&i915->drm, "Video mode format %s\n", 678 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ? 679 "non-burst with sync pulse" : 680 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ? 681 "non-burst with sync events" : 682 intel_dsi->video_mode_format == VIDEO_MODE_BURST ? 683 "burst" : "<unknown>"); 684 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", 685 intel_dsi->burst_mode_ratio); 686 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); 687 drm_dbg_kms(&i915->drm, "Eot %s\n", 688 enableddisabled(intel_dsi->eotp_pkt)); 689 drm_dbg_kms(&i915->drm, "Clockstop %s\n", 690 enableddisabled(!intel_dsi->clock_stop)); 691 drm_dbg_kms(&i915->drm, "Mode %s\n", 692 intel_dsi->operation_mode ? "command" : "video"); 693 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 694 drm_dbg_kms(&i915->drm, 695 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 696 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 697 drm_dbg_kms(&i915->drm, 698 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 699 else 700 drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); 701 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); 702 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); 703 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", 704 intel_dsi->lp_rx_timeout); 705 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", 706 intel_dsi->turn_arnd_val); 707 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); 708 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", 709 intel_dsi->hs_to_lp_count); 710 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 711 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 712 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", 713 intel_dsi->clk_lp_to_hs_count); 714 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", 715 intel_dsi->clk_hs_to_lp_count); 716 drm_dbg_kms(&i915->drm, "BTA %s\n", 717 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 718 } 719 720 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 721 { 722 struct drm_device *dev = intel_dsi->base.base.dev; 723 struct drm_i915_private *dev_priv = to_i915(dev); 724 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 725 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; 726 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; 727 u16 burst_mode_ratio; 728 enum port port; 729 730 drm_dbg_kms(&dev_priv->drm, "\n"); 731 732 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 733 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 734 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 735 intel_dsi->pixel_format = 736 pixel_format_from_register_bits( 737 mipi_config->videomode_color_format << 7); 738 739 intel_dsi->dual_link = mipi_config->dual_link; 740 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 741 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 742 intel_dsi->video_mode_format = mipi_config->video_transfer_mode; 743 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 744 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 745 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 746 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 747 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 748 intel_dsi->init_count = mipi_config->master_init_timer; 749 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 750 intel_dsi->video_frmt_cfg_bits = 751 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 752 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 753 754 /* Starting point, adjusted depending on dual link and burst mode */ 755 intel_dsi->pclk = mode->clock; 756 757 /* In dual link mode each port needs half of pixel clock */ 758 if (intel_dsi->dual_link) { 759 intel_dsi->pclk /= 2; 760 761 /* we can enable pixel_overlap if needed by panel. In this 762 * case we need to increase the pixelclock for extra pixels 763 */ 764 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 765 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 766 } 767 } 768 769 /* Burst Mode Ratio 770 * Target ddr frequency from VBT / non burst ddr freq 771 * multiply by 100 to preserve remainder 772 */ 773 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 774 if (mipi_config->target_burst_mode_freq) { 775 u32 bitrate = intel_dsi_bitrate(intel_dsi); 776 777 /* 778 * Sometimes the VBT contains a slightly lower clock, 779 * then the bitrate we have calculated, in this case 780 * just replace it with the calculated bitrate. 781 */ 782 if (mipi_config->target_burst_mode_freq < bitrate && 783 intel_fuzzy_clock_check( 784 mipi_config->target_burst_mode_freq, 785 bitrate)) 786 mipi_config->target_burst_mode_freq = bitrate; 787 788 if (mipi_config->target_burst_mode_freq < bitrate) { 789 drm_err(&dev_priv->drm, 790 "Burst mode freq is less than computed\n"); 791 return false; 792 } 793 794 burst_mode_ratio = DIV_ROUND_UP( 795 mipi_config->target_burst_mode_freq * 100, 796 bitrate); 797 798 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 799 } else { 800 drm_err(&dev_priv->drm, 801 "Burst mode target is not set\n"); 802 return false; 803 } 804 } else 805 burst_mode_ratio = 100; 806 807 intel_dsi->burst_mode_ratio = burst_mode_ratio; 808 809 /* delays in VBT are in unit of 100us, so need to convert 810 * here in ms 811 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 812 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 813 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 814 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 815 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 816 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 817 818 intel_dsi->i2c_bus_num = -1; 819 820 /* a regular driver would get the device in probe */ 821 for_each_dsi_port(port, intel_dsi->ports) { 822 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 823 } 824 825 return true; 826 } 827 828 /* 829 * On some BYT/CHT devs some sequences are incomplete and we need to manually 830 * control some GPIOs. We need to add a GPIO lookup table before we get these. 831 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 832 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 833 */ 834 static struct gpiod_lookup_table pmic_panel_gpio_table = { 835 /* Intel GFX is consumer */ 836 .dev_id = "0000:00:02.0", 837 .table = { 838 /* Panel EN/DISABLE */ 839 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 840 { } 841 }, 842 }; 843 844 static struct gpiod_lookup_table soc_panel_gpio_table = { 845 .dev_id = "0000:00:02.0", 846 .table = { 847 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 848 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 849 { } 850 }, 851 }; 852 853 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 854 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 855 "pwm0_grp", "pwm"), 856 }; 857 858 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 859 { 860 struct drm_device *dev = intel_dsi->base.base.dev; 861 struct drm_i915_private *dev_priv = to_i915(dev); 862 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 863 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 864 bool want_backlight_gpio = false; 865 bool want_panel_gpio = false; 866 struct pinctrl *pinctrl; 867 int ret; 868 869 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 870 mipi_config->pwm_blc == PPS_BLC_PMIC) { 871 gpiod_add_lookup_table(&pmic_panel_gpio_table); 872 want_panel_gpio = true; 873 } 874 875 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 876 gpiod_add_lookup_table(&soc_panel_gpio_table); 877 want_panel_gpio = true; 878 want_backlight_gpio = true; 879 880 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 881 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 882 ARRAY_SIZE(soc_pwm_pinctrl_map)); 883 if (ret) 884 drm_err(&dev_priv->drm, 885 "Failed to register pwm0 pinmux mapping\n"); 886 887 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 888 if (IS_ERR(pinctrl)) 889 drm_err(&dev_priv->drm, 890 "Failed to set pinmux to PWM\n"); 891 } 892 893 if (want_panel_gpio) { 894 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 895 if (IS_ERR(intel_dsi->gpio_panel)) { 896 drm_err(&dev_priv->drm, 897 "Failed to own gpio for panel control\n"); 898 intel_dsi->gpio_panel = NULL; 899 } 900 } 901 902 if (want_backlight_gpio) { 903 intel_dsi->gpio_backlight = 904 gpiod_get(dev->dev, "backlight", flags); 905 if (IS_ERR(intel_dsi->gpio_backlight)) { 906 drm_err(&dev_priv->drm, 907 "Failed to own gpio for backlight control\n"); 908 intel_dsi->gpio_backlight = NULL; 909 } 910 } 911 } 912 913 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 914 { 915 struct drm_device *dev = intel_dsi->base.base.dev; 916 struct drm_i915_private *dev_priv = to_i915(dev); 917 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 918 919 if (intel_dsi->gpio_panel) { 920 gpiod_put(intel_dsi->gpio_panel); 921 intel_dsi->gpio_panel = NULL; 922 } 923 924 if (intel_dsi->gpio_backlight) { 925 gpiod_put(intel_dsi->gpio_backlight); 926 intel_dsi->gpio_backlight = NULL; 927 } 928 929 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 930 mipi_config->pwm_blc == PPS_BLC_PMIC) 931 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 932 933 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 934 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 935 gpiod_remove_lookup_table(&soc_panel_gpio_table); 936 } 937 } 938