1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/machine.h> 29 #include <linux/mfd/intel_soc_pmic.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/machine.h> 32 #include <linux/slab.h> 33 34 #include <asm/intel-mid.h> 35 #include <asm/unaligned.h> 36 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_edid.h> 39 #include <drm/i915_drm.h> 40 41 #include <video/mipi_display.h> 42 43 #include "i915_drv.h" 44 #include "intel_display_types.h" 45 #include "intel_dsi.h" 46 #include "intel_sideband.h" 47 48 #define MIPI_TRANSFER_MODE_SHIFT 0 49 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 50 #define MIPI_PORT_SHIFT 3 51 52 /* base offsets for gpio pads */ 53 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 54 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 55 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 56 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 57 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 58 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 59 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 60 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 61 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 62 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 63 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 64 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 65 66 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 67 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 68 69 struct gpio_map { 70 u16 base_offset; 71 bool init; 72 }; 73 74 static struct gpio_map vlv_gpio_table[] = { 75 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 76 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 77 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 78 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 79 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 80 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 81 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 82 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 83 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 84 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 85 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 86 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 87 }; 88 89 struct i2c_adapter_lookup { 90 u16 slave_addr; 91 struct intel_dsi *intel_dsi; 92 acpi_handle dev_handle; 93 }; 94 95 #define CHV_GPIO_IDX_START_N 0 96 #define CHV_GPIO_IDX_START_E 73 97 #define CHV_GPIO_IDX_START_SW 100 98 #define CHV_GPIO_IDX_START_SE 198 99 100 #define CHV_VBT_MAX_PINS_PER_FMLY 15 101 102 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 103 #define CHV_GPIO_GPIOEN (1 << 15) 104 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 105 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 106 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 107 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 108 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 109 110 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 111 #define CHV_GPIO_CFGLOCK (1 << 31) 112 113 /* ICL DSI Display GPIO Pins */ 114 #define ICL_GPIO_DDSP_HPD_A 0 115 #define ICL_GPIO_L_VDDEN_1 1 116 #define ICL_GPIO_L_BKLTEN_1 2 117 #define ICL_GPIO_DDPA_CTRLCLK_1 3 118 #define ICL_GPIO_DDPA_CTRLDATA_1 4 119 #define ICL_GPIO_DDSP_HPD_B 5 120 #define ICL_GPIO_L_VDDEN_2 6 121 #define ICL_GPIO_L_BKLTEN_2 7 122 #define ICL_GPIO_DDPA_CTRLCLK_2 8 123 #define ICL_GPIO_DDPA_CTRLDATA_2 9 124 125 static inline enum port intel_dsi_seq_port_to_port(u8 port) 126 { 127 return port ? PORT_C : PORT_A; 128 } 129 130 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 131 const u8 *data) 132 { 133 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 134 struct mipi_dsi_device *dsi_device; 135 u8 type, flags, seq_port; 136 u16 len; 137 enum port port; 138 139 drm_dbg_kms(&dev_priv->drm, "\n"); 140 141 flags = *data++; 142 type = *data++; 143 144 len = *((u16 *) data); 145 data += 2; 146 147 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 148 149 /* For DSI single link on Port A & C, the seq_port value which is 150 * parsed from Sequence Block#53 of VBT has been set to 0 151 * Now, read/write of packets for the DSI single link on Port A and 152 * Port C will based on the DVO port from VBT block 2. 153 */ 154 if (intel_dsi->ports == (1 << PORT_C)) 155 port = PORT_C; 156 else 157 port = intel_dsi_seq_port_to_port(seq_port); 158 159 dsi_device = intel_dsi->dsi_hosts[port]->device; 160 if (!dsi_device) { 161 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", 162 port_name(port)); 163 goto out; 164 } 165 166 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 167 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 168 else 169 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 170 171 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 172 173 switch (type) { 174 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 175 mipi_dsi_generic_write(dsi_device, NULL, 0); 176 break; 177 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 178 mipi_dsi_generic_write(dsi_device, data, 1); 179 break; 180 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 181 mipi_dsi_generic_write(dsi_device, data, 2); 182 break; 183 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 184 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 185 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 186 drm_dbg(&dev_priv->drm, 187 "Generic Read not yet implemented or used\n"); 188 break; 189 case MIPI_DSI_GENERIC_LONG_WRITE: 190 mipi_dsi_generic_write(dsi_device, data, len); 191 break; 192 case MIPI_DSI_DCS_SHORT_WRITE: 193 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 194 break; 195 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 196 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 197 break; 198 case MIPI_DSI_DCS_READ: 199 drm_dbg(&dev_priv->drm, 200 "DCS Read not yet implemented or used\n"); 201 break; 202 case MIPI_DSI_DCS_LONG_WRITE: 203 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 204 break; 205 } 206 207 if (INTEL_GEN(dev_priv) < 11) 208 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 209 210 out: 211 data += len; 212 213 return data; 214 } 215 216 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 217 { 218 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 219 u32 delay = *((const u32 *) data); 220 221 drm_dbg_kms(&i915->drm, "\n"); 222 223 usleep_range(delay, delay + 10); 224 data += 4; 225 226 return data; 227 } 228 229 static void vlv_exec_gpio(struct drm_i915_private *dev_priv, 230 u8 gpio_source, u8 gpio_index, bool value) 231 { 232 struct gpio_map *map; 233 u16 pconf0, padval; 234 u32 tmp; 235 u8 port; 236 237 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 238 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", 239 gpio_index); 240 return; 241 } 242 243 map = &vlv_gpio_table[gpio_index]; 244 245 if (dev_priv->vbt.dsi.seq_version >= 3) { 246 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 247 port = IOSF_PORT_GPIO_NC; 248 } else { 249 if (gpio_source == 0) { 250 port = IOSF_PORT_GPIO_NC; 251 } else if (gpio_source == 1) { 252 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); 253 return; 254 } else { 255 drm_dbg_kms(&dev_priv->drm, 256 "unknown gpio source %u\n", gpio_source); 257 return; 258 } 259 } 260 261 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 262 padval = VLV_GPIO_PAD_VAL(map->base_offset); 263 264 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 265 if (!map->init) { 266 /* FIXME: remove constant below */ 267 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 268 map->init = true; 269 } 270 271 tmp = 0x4 | value; 272 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 273 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 274 } 275 276 static void chv_exec_gpio(struct drm_i915_private *dev_priv, 277 u8 gpio_source, u8 gpio_index, bool value) 278 { 279 u16 cfg0, cfg1; 280 u16 family_num; 281 u8 port; 282 283 if (dev_priv->vbt.dsi.seq_version >= 3) { 284 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 285 /* XXX: it's unclear whether 255->57 is part of SE. */ 286 gpio_index -= CHV_GPIO_IDX_START_SE; 287 port = CHV_IOSF_PORT_GPIO_SE; 288 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 289 gpio_index -= CHV_GPIO_IDX_START_SW; 290 port = CHV_IOSF_PORT_GPIO_SW; 291 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 292 gpio_index -= CHV_GPIO_IDX_START_E; 293 port = CHV_IOSF_PORT_GPIO_E; 294 } else { 295 port = CHV_IOSF_PORT_GPIO_N; 296 } 297 } else { 298 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 299 if (gpio_source != 0) { 300 drm_dbg_kms(&dev_priv->drm, 301 "unknown gpio source %u\n", gpio_source); 302 return; 303 } 304 305 if (gpio_index >= CHV_GPIO_IDX_START_E) { 306 drm_dbg_kms(&dev_priv->drm, 307 "invalid gpio index %u for GPIO N\n", 308 gpio_index); 309 return; 310 } 311 312 port = CHV_IOSF_PORT_GPIO_N; 313 } 314 315 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 316 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 317 318 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 319 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 320 321 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 322 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 323 vlv_iosf_sb_write(dev_priv, port, cfg0, 324 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 325 CHV_GPIO_GPIOTXSTATE(value)); 326 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 327 } 328 329 static void bxt_exec_gpio(struct drm_i915_private *dev_priv, 330 u8 gpio_source, u8 gpio_index, bool value) 331 { 332 /* XXX: this table is a quick ugly hack. */ 333 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 334 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 335 336 if (!gpio_desc) { 337 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 338 NULL, gpio_index, 339 value ? GPIOD_OUT_LOW : 340 GPIOD_OUT_HIGH); 341 342 if (IS_ERR_OR_NULL(gpio_desc)) { 343 drm_err(&dev_priv->drm, 344 "GPIO index %u request failed (%ld)\n", 345 gpio_index, PTR_ERR(gpio_desc)); 346 return; 347 } 348 349 bxt_gpio_table[gpio_index] = gpio_desc; 350 } 351 352 gpiod_set_value(gpio_desc, value); 353 } 354 355 static void icl_exec_gpio(struct drm_i915_private *dev_priv, 356 u8 gpio_source, u8 gpio_index, bool value) 357 { 358 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); 359 } 360 361 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 362 { 363 struct drm_device *dev = intel_dsi->base.base.dev; 364 struct drm_i915_private *dev_priv = to_i915(dev); 365 u8 gpio_source, gpio_index = 0, gpio_number; 366 bool value; 367 368 drm_dbg_kms(&dev_priv->drm, "\n"); 369 370 if (dev_priv->vbt.dsi.seq_version >= 3) 371 gpio_index = *data++; 372 373 gpio_number = *data++; 374 375 /* gpio source in sequence v2 only */ 376 if (dev_priv->vbt.dsi.seq_version == 2) 377 gpio_source = (*data >> 1) & 3; 378 else 379 gpio_source = 0; 380 381 /* pull up/down */ 382 value = *data++ & 1; 383 384 if (INTEL_GEN(dev_priv) >= 11) 385 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); 386 else if (IS_VALLEYVIEW(dev_priv)) 387 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 388 else if (IS_CHERRYVIEW(dev_priv)) 389 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 390 else 391 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value); 392 393 return data; 394 } 395 396 #ifdef CONFIG_ACPI 397 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 398 { 399 struct i2c_adapter_lookup *lookup = data; 400 struct intel_dsi *intel_dsi = lookup->intel_dsi; 401 struct acpi_resource_i2c_serialbus *sb; 402 struct i2c_adapter *adapter; 403 acpi_handle adapter_handle; 404 acpi_status status; 405 406 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 407 return 1; 408 409 if (lookup->slave_addr != sb->slave_address) 410 return 1; 411 412 status = acpi_get_handle(lookup->dev_handle, 413 sb->resource_source.string_ptr, 414 &adapter_handle); 415 if (ACPI_FAILURE(status)) 416 return 1; 417 418 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 419 if (adapter) 420 intel_dsi->i2c_bus_num = adapter->nr; 421 422 return 1; 423 } 424 425 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 426 const u16 slave_addr) 427 { 428 struct drm_device *drm_dev = intel_dsi->base.base.dev; 429 struct device *dev = &drm_dev->pdev->dev; 430 struct acpi_device *acpi_dev; 431 struct list_head resource_list; 432 struct i2c_adapter_lookup lookup; 433 434 acpi_dev = ACPI_COMPANION(dev); 435 if (acpi_dev) { 436 memset(&lookup, 0, sizeof(lookup)); 437 lookup.slave_addr = slave_addr; 438 lookup.intel_dsi = intel_dsi; 439 lookup.dev_handle = acpi_device_handle(acpi_dev); 440 441 INIT_LIST_HEAD(&resource_list); 442 acpi_dev_get_resources(acpi_dev, &resource_list, 443 i2c_adapter_lookup, 444 &lookup); 445 acpi_dev_free_resource_list(&resource_list); 446 } 447 } 448 #else 449 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 450 const u16 slave_addr) 451 { 452 } 453 #endif 454 455 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 456 { 457 struct drm_device *drm_dev = intel_dsi->base.base.dev; 458 struct device *dev = &drm_dev->pdev->dev; 459 struct i2c_adapter *adapter; 460 struct i2c_msg msg; 461 int ret; 462 u8 vbt_i2c_bus_num = *(data + 2); 463 u16 slave_addr = *(u16 *)(data + 3); 464 u8 reg_offset = *(data + 5); 465 u8 payload_size = *(data + 6); 466 u8 *payload_data; 467 468 if (intel_dsi->i2c_bus_num < 0) { 469 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 470 i2c_acpi_find_adapter(intel_dsi, slave_addr); 471 } 472 473 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 474 if (!adapter) { 475 DRM_DEV_ERROR(dev, "Cannot find a valid i2c bus for xfer\n"); 476 goto err_bus; 477 } 478 479 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 480 if (!payload_data) 481 goto err_alloc; 482 483 payload_data[0] = reg_offset; 484 memcpy(&payload_data[1], (data + 7), payload_size); 485 486 msg.addr = slave_addr; 487 msg.flags = 0; 488 msg.len = payload_size + 1; 489 msg.buf = payload_data; 490 491 ret = i2c_transfer(adapter, &msg, 1); 492 if (ret < 0) 493 DRM_DEV_ERROR(dev, 494 "Failed to xfer payload of size (%u) to reg (%u)\n", 495 payload_size, reg_offset); 496 497 kfree(payload_data); 498 err_alloc: 499 i2c_put_adapter(adapter); 500 err_bus: 501 return data + payload_size + 7; 502 } 503 504 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 505 { 506 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 507 508 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n"); 509 510 return data + *(data + 5) + 6; 511 } 512 513 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 514 { 515 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 516 #ifdef CONFIG_PMIC_OPREGION 517 u32 value, mask, reg_address; 518 u16 i2c_address; 519 int ret; 520 521 /* byte 0 aka PMIC Flag is reserved */ 522 i2c_address = get_unaligned_le16(data + 1); 523 reg_address = get_unaligned_le32(data + 3); 524 value = get_unaligned_le32(data + 7); 525 mask = get_unaligned_le32(data + 11); 526 527 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 528 reg_address, 529 value, mask); 530 if (ret) 531 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); 532 #else 533 drm_err(&i915->drm, 534 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 535 #endif 536 537 return data + 15; 538 } 539 540 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 541 const u8 *data); 542 static const fn_mipi_elem_exec exec_elem[] = { 543 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 544 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 545 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 546 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 547 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 548 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 549 }; 550 551 /* 552 * MIPI Sequence from VBT #53 parsing logic 553 * We have already separated each seqence during bios parsing 554 * Following is generic execution function for any sequence 555 */ 556 557 static const char * const seq_name[] = { 558 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 559 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 560 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 561 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 562 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 563 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 564 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 565 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 566 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 567 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 568 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 569 }; 570 571 static const char *sequence_name(enum mipi_seq seq_id) 572 { 573 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 574 return seq_name[seq_id]; 575 else 576 return "(unknown)"; 577 } 578 579 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 580 enum mipi_seq seq_id) 581 { 582 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 583 const u8 *data; 584 fn_mipi_elem_exec mipi_elem_exec; 585 586 if (drm_WARN_ON(&dev_priv->drm, 587 seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) 588 return; 589 590 data = dev_priv->vbt.dsi.sequence[seq_id]; 591 if (!data) 592 return; 593 594 drm_WARN_ON(&dev_priv->drm, *data != seq_id); 595 596 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", 597 seq_id, sequence_name(seq_id)); 598 599 /* Skip Sequence Byte. */ 600 data++; 601 602 /* Skip Size of Sequence. */ 603 if (dev_priv->vbt.dsi.seq_version >= 3) 604 data += 4; 605 606 while (1) { 607 u8 operation_byte = *data++; 608 u8 operation_size = 0; 609 610 if (operation_byte == MIPI_SEQ_ELEM_END) 611 break; 612 613 if (operation_byte < ARRAY_SIZE(exec_elem)) 614 mipi_elem_exec = exec_elem[operation_byte]; 615 else 616 mipi_elem_exec = NULL; 617 618 /* Size of Operation. */ 619 if (dev_priv->vbt.dsi.seq_version >= 3) 620 operation_size = *data++; 621 622 if (mipi_elem_exec) { 623 const u8 *next = data + operation_size; 624 625 data = mipi_elem_exec(intel_dsi, data); 626 627 /* Consistency check if we have size. */ 628 if (operation_size && data != next) { 629 drm_err(&dev_priv->drm, 630 "Inconsistent operation size\n"); 631 return; 632 } 633 } else if (operation_size) { 634 /* We have size, skip. */ 635 drm_dbg_kms(&dev_priv->drm, 636 "Unsupported MIPI operation byte %u\n", 637 operation_byte); 638 data += operation_size; 639 } else { 640 /* No size, can't skip without parsing. */ 641 drm_err(&dev_priv->drm, 642 "Unsupported MIPI operation byte %u\n", 643 operation_byte); 644 return; 645 } 646 } 647 } 648 649 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 650 enum mipi_seq seq_id) 651 { 652 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 653 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 654 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 655 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 656 657 intel_dsi_vbt_exec(intel_dsi, seq_id); 658 659 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 660 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 661 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 662 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 663 } 664 665 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 666 { 667 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 668 669 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 670 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) 671 return; 672 673 msleep(msec); 674 } 675 676 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 677 { 678 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 679 680 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); 681 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", 682 intel_dsi->pixel_overlap); 683 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); 684 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 685 drm_dbg_kms(&i915->drm, "Video mode format %s\n", 686 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ? 687 "non-burst with sync pulse" : 688 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ? 689 "non-burst with sync events" : 690 intel_dsi->video_mode_format == VIDEO_MODE_BURST ? 691 "burst" : "<unknown>"); 692 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", 693 intel_dsi->burst_mode_ratio); 694 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); 695 drm_dbg_kms(&i915->drm, "Eot %s\n", 696 enableddisabled(intel_dsi->eotp_pkt)); 697 drm_dbg_kms(&i915->drm, "Clockstop %s\n", 698 enableddisabled(!intel_dsi->clock_stop)); 699 drm_dbg_kms(&i915->drm, "Mode %s\n", 700 intel_dsi->operation_mode ? "command" : "video"); 701 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 702 drm_dbg_kms(&i915->drm, 703 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 704 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 705 drm_dbg_kms(&i915->drm, 706 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 707 else 708 drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); 709 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); 710 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); 711 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", 712 intel_dsi->lp_rx_timeout); 713 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", 714 intel_dsi->turn_arnd_val); 715 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); 716 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", 717 intel_dsi->hs_to_lp_count); 718 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 719 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 720 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", 721 intel_dsi->clk_lp_to_hs_count); 722 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", 723 intel_dsi->clk_hs_to_lp_count); 724 drm_dbg_kms(&i915->drm, "BTA %s\n", 725 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 726 } 727 728 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 729 { 730 struct drm_device *dev = intel_dsi->base.base.dev; 731 struct drm_i915_private *dev_priv = to_i915(dev); 732 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 733 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; 734 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; 735 u16 burst_mode_ratio; 736 enum port port; 737 738 drm_dbg_kms(&dev_priv->drm, "\n"); 739 740 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 741 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 742 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 743 intel_dsi->pixel_format = 744 pixel_format_from_register_bits( 745 mipi_config->videomode_color_format << 7); 746 747 intel_dsi->dual_link = mipi_config->dual_link; 748 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 749 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 750 intel_dsi->video_mode_format = mipi_config->video_transfer_mode; 751 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 752 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 753 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 754 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 755 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 756 intel_dsi->init_count = mipi_config->master_init_timer; 757 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 758 intel_dsi->video_frmt_cfg_bits = 759 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 760 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 761 762 /* Starting point, adjusted depending on dual link and burst mode */ 763 intel_dsi->pclk = mode->clock; 764 765 /* In dual link mode each port needs half of pixel clock */ 766 if (intel_dsi->dual_link) { 767 intel_dsi->pclk /= 2; 768 769 /* we can enable pixel_overlap if needed by panel. In this 770 * case we need to increase the pixelclock for extra pixels 771 */ 772 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 773 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 774 } 775 } 776 777 /* Burst Mode Ratio 778 * Target ddr frequency from VBT / non burst ddr freq 779 * multiply by 100 to preserve remainder 780 */ 781 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 782 if (mipi_config->target_burst_mode_freq) { 783 u32 bitrate = intel_dsi_bitrate(intel_dsi); 784 785 /* 786 * Sometimes the VBT contains a slightly lower clock, 787 * then the bitrate we have calculated, in this case 788 * just replace it with the calculated bitrate. 789 */ 790 if (mipi_config->target_burst_mode_freq < bitrate && 791 intel_fuzzy_clock_check( 792 mipi_config->target_burst_mode_freq, 793 bitrate)) 794 mipi_config->target_burst_mode_freq = bitrate; 795 796 if (mipi_config->target_burst_mode_freq < bitrate) { 797 drm_err(&dev_priv->drm, 798 "Burst mode freq is less than computed\n"); 799 return false; 800 } 801 802 burst_mode_ratio = DIV_ROUND_UP( 803 mipi_config->target_burst_mode_freq * 100, 804 bitrate); 805 806 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 807 } else { 808 drm_err(&dev_priv->drm, 809 "Burst mode target is not set\n"); 810 return false; 811 } 812 } else 813 burst_mode_ratio = 100; 814 815 intel_dsi->burst_mode_ratio = burst_mode_ratio; 816 817 /* delays in VBT are in unit of 100us, so need to convert 818 * here in ms 819 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 820 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 821 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 822 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 823 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 824 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 825 826 intel_dsi->i2c_bus_num = -1; 827 828 /* a regular driver would get the device in probe */ 829 for_each_dsi_port(port, intel_dsi->ports) { 830 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 831 } 832 833 return true; 834 } 835 836 /* 837 * On some BYT/CHT devs some sequences are incomplete and we need to manually 838 * control some GPIOs. We need to add a GPIO lookup table before we get these. 839 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 840 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 841 */ 842 static struct gpiod_lookup_table pmic_panel_gpio_table = { 843 /* Intel GFX is consumer */ 844 .dev_id = "0000:00:02.0", 845 .table = { 846 /* Panel EN/DISABLE */ 847 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 848 { } 849 }, 850 }; 851 852 static struct gpiod_lookup_table soc_panel_gpio_table = { 853 .dev_id = "0000:00:02.0", 854 .table = { 855 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 856 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 857 { } 858 }, 859 }; 860 861 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 862 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 863 "pwm0_grp", "pwm"), 864 }; 865 866 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 867 { 868 struct drm_device *dev = intel_dsi->base.base.dev; 869 struct drm_i915_private *dev_priv = to_i915(dev); 870 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 871 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 872 bool want_backlight_gpio = false; 873 bool want_panel_gpio = false; 874 struct pinctrl *pinctrl; 875 int ret; 876 877 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 878 mipi_config->pwm_blc == PPS_BLC_PMIC) { 879 gpiod_add_lookup_table(&pmic_panel_gpio_table); 880 want_panel_gpio = true; 881 } 882 883 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 884 gpiod_add_lookup_table(&soc_panel_gpio_table); 885 want_panel_gpio = true; 886 want_backlight_gpio = true; 887 888 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 889 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 890 ARRAY_SIZE(soc_pwm_pinctrl_map)); 891 if (ret) 892 drm_err(&dev_priv->drm, 893 "Failed to register pwm0 pinmux mapping\n"); 894 895 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 896 if (IS_ERR(pinctrl)) 897 drm_err(&dev_priv->drm, 898 "Failed to set pinmux to PWM\n"); 899 } 900 901 if (want_panel_gpio) { 902 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 903 if (IS_ERR(intel_dsi->gpio_panel)) { 904 drm_err(&dev_priv->drm, 905 "Failed to own gpio for panel control\n"); 906 intel_dsi->gpio_panel = NULL; 907 } 908 } 909 910 if (want_backlight_gpio) { 911 intel_dsi->gpio_backlight = 912 gpiod_get(dev->dev, "backlight", flags); 913 if (IS_ERR(intel_dsi->gpio_backlight)) { 914 drm_err(&dev_priv->drm, 915 "Failed to own gpio for backlight control\n"); 916 intel_dsi->gpio_backlight = NULL; 917 } 918 } 919 } 920 921 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 922 { 923 struct drm_device *dev = intel_dsi->base.base.dev; 924 struct drm_i915_private *dev_priv = to_i915(dev); 925 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 926 927 if (intel_dsi->gpio_panel) { 928 gpiod_put(intel_dsi->gpio_panel); 929 intel_dsi->gpio_panel = NULL; 930 } 931 932 if (intel_dsi->gpio_backlight) { 933 gpiod_put(intel_dsi->gpio_backlight); 934 intel_dsi->gpio_backlight = NULL; 935 } 936 937 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 938 mipi_config->pwm_blc == PPS_BLC_PMIC) 939 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 940 941 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 942 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 943 gpiod_remove_lookup_table(&soc_panel_gpio_table); 944 } 945 } 946