1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 * 5 */ 6 7 #include "gem/i915_gem_internal.h" 8 9 #include "i915_drv.h" 10 #include "i915_reg.h" 11 #include "intel_de.h" 12 #include "intel_display_types.h" 13 #include "intel_dsb.h" 14 15 struct i915_vma; 16 17 enum dsb_id { 18 INVALID_DSB = -1, 19 DSB1, 20 DSB2, 21 DSB3, 22 MAX_DSB_PER_PIPE 23 }; 24 25 struct intel_dsb { 26 enum dsb_id id; 27 28 u32 *cmd_buf; 29 struct i915_vma *vma; 30 struct intel_crtc *crtc; 31 32 /* 33 * maximum number of dwords the buffer will hold. 34 */ 35 unsigned int size; 36 37 /* 38 * free_pos will point the first free dword and 39 * help in calculating tail of command buffer. 40 */ 41 unsigned int free_pos; 42 43 /* 44 * ins_start_offset will help to store start dword of the dsb 45 * instuction and help in identifying the batch of auto-increment 46 * register. 47 */ 48 unsigned int ins_start_offset; 49 }; 50 51 /** 52 * DOC: DSB 53 * 54 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory 55 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA 56 * engine that can be programmed to download the DSB from memory. 57 * It allows driver to batch submit display HW programming. This helps to 58 * reduce loading time and CPU activity, thereby making the context switch 59 * faster. DSB Support added from Gen12 Intel graphics based platform. 60 * 61 * DSB's can access only the pipe, plane, and transcoder Data Island Packet 62 * registers. 63 * 64 * DSB HW can support only register writes (both indexed and direct MMIO 65 * writes). There are no registers reads possible with DSB HW engine. 66 */ 67 68 /* DSB opcodes. */ 69 #define DSB_OPCODE_SHIFT 24 70 #define DSB_OPCODE_NOOP 0x0 71 #define DSB_OPCODE_MMIO_WRITE 0x1 72 #define DSB_OPCODE_WAIT_USEC 0x2 73 #define DSB_OPCODE_WAIT_LINES 0x3 74 #define DSB_OPCODE_WAIT_VBLANKS 0x4 75 #define DSB_OPCODE_WAIT_DSL_IN 0x5 76 #define DSB_OPCODE_WAIT_DSL_OUT 0x6 77 #define DSB_OPCODE_INTERRUPT 0x7 78 #define DSB_OPCODE_INDEXED_WRITE 0x9 79 #define DSB_OPCODE_POLL 0xA 80 #define DSB_BYTE_EN 0xF 81 #define DSB_BYTE_EN_SHIFT 20 82 #define DSB_REG_VALUE_MASK 0xfffff 83 84 static bool assert_dsb_has_room(struct intel_dsb *dsb) 85 { 86 struct intel_crtc *crtc = dsb->crtc; 87 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 88 89 /* each instruction is 2 dwords */ 90 return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2, 91 "[CRTC:%d:%s] DSB %d buffer overflow\n", 92 crtc->base.base.id, crtc->base.name, dsb->id); 93 } 94 95 static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, 96 enum dsb_id id) 97 { 98 return intel_de_read(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY; 99 } 100 101 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) 102 { 103 u32 *buf = dsb->cmd_buf; 104 105 if (!assert_dsb_has_room(dsb)) 106 return; 107 108 /* Every instruction should be 8 byte aligned. */ 109 dsb->free_pos = ALIGN(dsb->free_pos, 2); 110 111 dsb->ins_start_offset = dsb->free_pos; 112 113 buf[dsb->free_pos++] = ldw; 114 buf[dsb->free_pos++] = udw; 115 } 116 117 static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, 118 u32 opcode, i915_reg_t reg) 119 { 120 const u32 *buf = dsb->cmd_buf; 121 u32 prev_opcode, prev_reg; 122 123 prev_opcode = buf[dsb->ins_start_offset + 1] >> DSB_OPCODE_SHIFT; 124 prev_reg = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK; 125 126 return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg); 127 } 128 129 static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg) 130 { 131 return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_MMIO_WRITE, reg); 132 } 133 134 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg) 135 { 136 return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_INDEXED_WRITE, reg); 137 } 138 139 /** 140 * intel_dsb_reg_write() - Emit register wriite to the DSB context 141 * @dsb: DSB context 142 * @reg: register address. 143 * @val: value. 144 * 145 * This function is used for writing register-value pair in command 146 * buffer of DSB. 147 */ 148 void intel_dsb_reg_write(struct intel_dsb *dsb, 149 i915_reg_t reg, u32 val) 150 { 151 /* 152 * For example the buffer will look like below for 3 dwords for auto 153 * increment register: 154 * +--------------------------------------------------------+ 155 * | size = 3 | offset &| value1 | value2 | value3 | zero | 156 * | | opcode | | | | | 157 * +--------------------------------------------------------+ 158 * + + + + + + + 159 * 0 4 8 12 16 20 24 160 * Byte 161 * 162 * As every instruction is 8 byte aligned the index of dsb instruction 163 * will start always from even number while dealing with u32 array. If 164 * we are writing odd no of dwords, Zeros will be added in the end for 165 * padding. 166 */ 167 if (!intel_dsb_prev_ins_is_mmio_write(dsb, reg) && 168 !intel_dsb_prev_ins_is_indexed_write(dsb, reg)) { 169 intel_dsb_emit(dsb, val, 170 (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | 171 (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) | 172 i915_mmio_reg_offset(reg)); 173 } else { 174 u32 *buf = dsb->cmd_buf; 175 176 if (!assert_dsb_has_room(dsb)) 177 return; 178 179 /* convert to indexed write? */ 180 if (intel_dsb_prev_ins_is_mmio_write(dsb, reg)) { 181 u32 prev_val = buf[dsb->ins_start_offset + 0]; 182 183 buf[dsb->ins_start_offset + 0] = 1; /* count */ 184 buf[dsb->ins_start_offset + 1] = 185 (DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT) | 186 i915_mmio_reg_offset(reg); 187 buf[dsb->ins_start_offset + 2] = prev_val; 188 189 dsb->free_pos++; 190 } 191 192 buf[dsb->free_pos++] = val; 193 /* Update the count */ 194 buf[dsb->ins_start_offset]++; 195 196 /* if number of data words is odd, then the last dword should be 0.*/ 197 if (dsb->free_pos & 0x1) 198 buf[dsb->free_pos] = 0; 199 } 200 } 201 202 static void intel_dsb_align_tail(struct intel_dsb *dsb) 203 { 204 u32 aligned_tail, tail; 205 206 tail = dsb->free_pos * 4; 207 aligned_tail = ALIGN(tail, CACHELINE_BYTES); 208 209 if (aligned_tail > tail) 210 memset(&dsb->cmd_buf[dsb->free_pos], 0, 211 aligned_tail - tail); 212 213 dsb->free_pos = aligned_tail / 4; 214 } 215 216 void intel_dsb_finish(struct intel_dsb *dsb) 217 { 218 intel_dsb_align_tail(dsb); 219 } 220 221 /** 222 * intel_dsb_commit() - Trigger workload execution of DSB. 223 * @dsb: DSB context 224 * @wait_for_vblank: wait for vblank before executing 225 * 226 * This function is used to do actual write to hardware using DSB. 227 */ 228 void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank) 229 { 230 struct intel_crtc *crtc = dsb->crtc; 231 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 232 enum pipe pipe = crtc->pipe; 233 u32 tail; 234 235 tail = dsb->free_pos * 4; 236 if (drm_WARN_ON(&dev_priv->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) 237 return; 238 239 if (is_dsb_busy(dev_priv, pipe, dsb->id)) { 240 drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n", 241 crtc->base.base.id, crtc->base.name, dsb->id); 242 return; 243 } 244 245 intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 246 (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) | 247 DSB_ENABLE); 248 intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), 249 i915_ggtt_offset(dsb->vma)); 250 intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), 251 i915_ggtt_offset(dsb->vma) + tail); 252 } 253 254 void intel_dsb_wait(struct intel_dsb *dsb) 255 { 256 struct intel_crtc *crtc = dsb->crtc; 257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 258 enum pipe pipe = crtc->pipe; 259 260 if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) 261 drm_err(&dev_priv->drm, 262 "[CRTC:%d:%s] DSB %d timed out waiting for idle\n", 263 crtc->base.base.id, crtc->base.name, dsb->id); 264 265 /* Attempt to reset it */ 266 dsb->free_pos = 0; 267 dsb->ins_start_offset = 0; 268 intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 0); 269 } 270 271 /** 272 * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer. 273 * @crtc: the CRTC 274 * @max_cmds: number of commands we need to fit into command buffer 275 * 276 * This function prepare the command buffer which is used to store dsb 277 * instructions with data. 278 * 279 * Returns: 280 * DSB context, NULL on failure 281 */ 282 struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc, 283 unsigned int max_cmds) 284 { 285 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 286 struct drm_i915_gem_object *obj; 287 intel_wakeref_t wakeref; 288 struct intel_dsb *dsb; 289 struct i915_vma *vma; 290 unsigned int size; 291 u32 *buf; 292 293 if (!HAS_DSB(i915)) 294 return NULL; 295 296 dsb = kzalloc(sizeof(*dsb), GFP_KERNEL); 297 if (!dsb) 298 goto out; 299 300 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 301 302 /* ~1 qword per instruction, full cachelines */ 303 size = ALIGN(max_cmds * 8, CACHELINE_BYTES); 304 305 obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size)); 306 if (IS_ERR(obj)) 307 goto out_put_rpm; 308 309 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); 310 if (IS_ERR(vma)) { 311 i915_gem_object_put(obj); 312 goto out_put_rpm; 313 } 314 315 buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC); 316 if (IS_ERR(buf)) { 317 i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); 318 goto out_put_rpm; 319 } 320 321 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 322 323 dsb->id = DSB1; 324 dsb->vma = vma; 325 dsb->crtc = crtc; 326 dsb->cmd_buf = buf; 327 dsb->size = size / 4; /* in dwords */ 328 dsb->free_pos = 0; 329 dsb->ins_start_offset = 0; 330 331 return dsb; 332 333 out_put_rpm: 334 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 335 kfree(dsb); 336 out: 337 drm_info_once(&i915->drm, 338 "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to MMIO for display HW programming\n", 339 crtc->base.base.id, crtc->base.name, DSB1); 340 341 return NULL; 342 } 343 344 /** 345 * intel_dsb_cleanup() - To cleanup DSB context. 346 * @dsb: DSB context 347 * 348 * This function cleanup the DSB context by unpinning and releasing 349 * the VMA object associated with it. 350 */ 351 void intel_dsb_cleanup(struct intel_dsb *dsb) 352 { 353 i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP); 354 kfree(dsb); 355 } 356