1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 * 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_display_types.h" 9 10 #define DSB_BUF_SIZE (2 * PAGE_SIZE) 11 12 /** 13 * DOC: DSB 14 * 15 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory 16 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA 17 * engine that can be programmed to download the DSB from memory. 18 * It allows driver to batch submit display HW programming. This helps to 19 * reduce loading time and CPU activity, thereby making the context switch 20 * faster. DSB Support added from Gen12 Intel graphics based platform. 21 * 22 * DSB's can access only the pipe, plane, and transcoder Data Island Packet 23 * registers. 24 * 25 * DSB HW can support only register writes (both indexed and direct MMIO 26 * writes). There are no registers reads possible with DSB HW engine. 27 */ 28 29 /* DSB opcodes. */ 30 #define DSB_OPCODE_SHIFT 24 31 #define DSB_OPCODE_MMIO_WRITE 0x1 32 #define DSB_OPCODE_INDEXED_WRITE 0x9 33 #define DSB_BYTE_EN 0xF 34 #define DSB_BYTE_EN_SHIFT 20 35 #define DSB_REG_VALUE_MASK 0xfffff 36 37 static inline bool is_dsb_busy(struct intel_dsb *dsb) 38 { 39 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); 40 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 41 enum pipe pipe = crtc->pipe; 42 43 return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id)); 44 } 45 46 static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb) 47 { 48 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); 49 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 50 enum pipe pipe = crtc->pipe; 51 u32 dsb_ctrl; 52 53 dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id)); 54 if (DSB_STATUS & dsb_ctrl) { 55 DRM_DEBUG_KMS("DSB engine is busy.\n"); 56 return false; 57 } 58 59 dsb_ctrl |= DSB_ENABLE; 60 I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl); 61 62 POSTING_READ(DSB_CTRL(pipe, dsb->id)); 63 return true; 64 } 65 66 static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb) 67 { 68 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); 69 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 70 enum pipe pipe = crtc->pipe; 71 u32 dsb_ctrl; 72 73 dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id)); 74 if (DSB_STATUS & dsb_ctrl) { 75 DRM_DEBUG_KMS("DSB engine is busy.\n"); 76 return false; 77 } 78 79 dsb_ctrl &= ~DSB_ENABLE; 80 I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl); 81 82 POSTING_READ(DSB_CTRL(pipe, dsb->id)); 83 return true; 84 } 85 86 /** 87 * intel_dsb_get() - Allocate DSB context and return a DSB instance. 88 * @crtc: intel_crtc structure to get pipe info. 89 * 90 * This function provides handle of a DSB instance, for the further DSB 91 * operations. 92 * 93 * Returns: address of Intel_dsb instance requested for. 94 * Failure: Returns the same DSB instance, but without a command buffer. 95 */ 96 97 struct intel_dsb * 98 intel_dsb_get(struct intel_crtc *crtc) 99 { 100 struct drm_device *dev = crtc->base.dev; 101 struct drm_i915_private *i915 = to_i915(dev); 102 struct intel_dsb *dsb = &crtc->dsb; 103 struct drm_i915_gem_object *obj; 104 struct i915_vma *vma; 105 intel_wakeref_t wakeref; 106 107 if (!HAS_DSB(i915)) 108 return dsb; 109 110 if (atomic_add_return(1, &dsb->refcount) != 1) 111 return dsb; 112 113 dsb->id = DSB1; 114 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 115 116 obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE); 117 if (IS_ERR(obj)) { 118 DRM_ERROR("Gem object creation failed\n"); 119 goto err; 120 } 121 122 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 123 if (IS_ERR(vma)) { 124 DRM_ERROR("Vma creation failed\n"); 125 i915_gem_object_put(obj); 126 atomic_dec(&dsb->refcount); 127 goto err; 128 } 129 130 dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); 131 if (IS_ERR(dsb->cmd_buf)) { 132 DRM_ERROR("Command buffer creation failed\n"); 133 i915_vma_unpin_and_release(&vma, 0); 134 dsb->cmd_buf = NULL; 135 atomic_dec(&dsb->refcount); 136 goto err; 137 } 138 dsb->vma = vma; 139 140 err: 141 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 142 return dsb; 143 } 144 145 /** 146 * intel_dsb_put() - To destroy DSB context. 147 * @dsb: intel_dsb structure. 148 * 149 * This function destroys the DSB context allocated by a dsb_get(), by 150 * unpinning and releasing the VMA object associated with it. 151 */ 152 153 void intel_dsb_put(struct intel_dsb *dsb) 154 { 155 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); 156 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 157 158 if (!HAS_DSB(i915)) 159 return; 160 161 if (WARN_ON(atomic_read(&dsb->refcount) == 0)) 162 return; 163 164 if (atomic_dec_and_test(&dsb->refcount)) { 165 i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP); 166 dsb->cmd_buf = NULL; 167 dsb->free_pos = 0; 168 dsb->ins_start_offset = 0; 169 } 170 } 171 172 /** 173 * intel_dsb_indexed_reg_write() -Write to the DSB context for auto 174 * increment register. 175 * @dsb: intel_dsb structure. 176 * @reg: register address. 177 * @val: value. 178 * 179 * This function is used for writing register-value pair in command 180 * buffer of DSB for auto-increment register. During command buffer overflow, 181 * a warning is thrown and rest all erroneous condition register programming 182 * is done through mmio write. 183 */ 184 185 void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, 186 u32 val) 187 { 188 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); 189 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 190 u32 *buf = dsb->cmd_buf; 191 u32 reg_val; 192 193 if (!buf) { 194 I915_WRITE(reg, val); 195 return; 196 } 197 198 if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) { 199 DRM_DEBUG_KMS("DSB buffer overflow\n"); 200 return; 201 } 202 203 /* 204 * For example the buffer will look like below for 3 dwords for auto 205 * increment register: 206 * +--------------------------------------------------------+ 207 * | size = 3 | offset &| value1 | value2 | value3 | zero | 208 * | | opcode | | | | | 209 * +--------------------------------------------------------+ 210 * + + + + + + + 211 * 0 4 8 12 16 20 24 212 * Byte 213 * 214 * As every instruction is 8 byte aligned the index of dsb instruction 215 * will start always from even number while dealing with u32 array. If 216 * we are writing odd no of dwords, Zeros will be added in the end for 217 * padding. 218 */ 219 reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK; 220 if (reg_val != i915_mmio_reg_offset(reg)) { 221 /* Every instruction should be 8 byte aligned. */ 222 dsb->free_pos = ALIGN(dsb->free_pos, 2); 223 224 dsb->ins_start_offset = dsb->free_pos; 225 226 /* Update the size. */ 227 buf[dsb->free_pos++] = 1; 228 229 /* Update the opcode and reg. */ 230 buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE << 231 DSB_OPCODE_SHIFT) | 232 i915_mmio_reg_offset(reg); 233 234 /* Update the value. */ 235 buf[dsb->free_pos++] = val; 236 } else { 237 /* Update the new value. */ 238 buf[dsb->free_pos++] = val; 239 240 /* Update the size. */ 241 buf[dsb->ins_start_offset]++; 242 } 243 244 /* if number of data words is odd, then the last dword should be 0.*/ 245 if (dsb->free_pos & 0x1) 246 buf[dsb->free_pos] = 0; 247 } 248 249 /** 250 * intel_dsb_reg_write() -Write to the DSB context for normal 251 * register. 252 * @dsb: intel_dsb structure. 253 * @reg: register address. 254 * @val: value. 255 * 256 * This function is used for writing register-value pair in command 257 * buffer of DSB. During command buffer overflow, a warning is thrown 258 * and rest all erroneous condition register programming is done 259 * through mmio write. 260 */ 261 void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) 262 { 263 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); 264 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 265 u32 *buf = dsb->cmd_buf; 266 267 if (!buf) { 268 I915_WRITE(reg, val); 269 return; 270 } 271 272 if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) { 273 DRM_DEBUG_KMS("DSB buffer overflow\n"); 274 return; 275 } 276 277 dsb->ins_start_offset = dsb->free_pos; 278 buf[dsb->free_pos++] = val; 279 buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | 280 (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) | 281 i915_mmio_reg_offset(reg); 282 } 283 284 /** 285 * intel_dsb_commit() - Trigger workload execution of DSB. 286 * @dsb: intel_dsb structure. 287 * 288 * This function is used to do actual write to hardware using DSB. 289 * On errors, fall back to MMIO. Also this function help to reset the context. 290 */ 291 void intel_dsb_commit(struct intel_dsb *dsb) 292 { 293 struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); 294 struct drm_device *dev = crtc->base.dev; 295 struct drm_i915_private *dev_priv = to_i915(dev); 296 enum pipe pipe = crtc->pipe; 297 u32 tail; 298 299 if (!dsb->free_pos) 300 return; 301 302 if (!intel_dsb_enable_engine(dsb)) 303 goto reset; 304 305 if (is_dsb_busy(dsb)) { 306 DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n"); 307 goto reset; 308 } 309 I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma)); 310 311 tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES); 312 if (tail > dsb->free_pos * 4) 313 memset(&dsb->cmd_buf[dsb->free_pos], 0, 314 (tail - dsb->free_pos * 4)); 315 316 if (is_dsb_busy(dsb)) { 317 DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n"); 318 goto reset; 319 } 320 DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n", 321 i915_ggtt_offset(dsb->vma), tail); 322 I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail); 323 if (wait_for(!is_dsb_busy(dsb), 1)) { 324 DRM_ERROR("Timed out waiting for DSB workload completion.\n"); 325 goto reset; 326 } 327 328 reset: 329 dsb->free_pos = 0; 330 dsb->ins_start_offset = 0; 331 intel_dsb_disable_engine(dsb); 332 } 333