1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 * 5 */ 6 7 #include "gem/i915_gem_internal.h" 8 9 #include "i915_drv.h" 10 #include "i915_reg.h" 11 #include "intel_de.h" 12 #include "intel_display_types.h" 13 #include "intel_dsb.h" 14 15 struct i915_vma; 16 17 enum dsb_id { 18 INVALID_DSB = -1, 19 DSB1, 20 DSB2, 21 DSB3, 22 MAX_DSB_PER_PIPE 23 }; 24 25 struct intel_dsb { 26 enum dsb_id id; 27 u32 *cmd_buf; 28 struct i915_vma *vma; 29 30 /* 31 * free_pos will point the first free entry position 32 * and help in calculating tail of command buffer. 33 */ 34 int free_pos; 35 36 /* 37 * ins_start_offset will help to store start address of the dsb 38 * instuction and help in identifying the batch of auto-increment 39 * register. 40 */ 41 u32 ins_start_offset; 42 }; 43 44 #define DSB_BUF_SIZE (2 * PAGE_SIZE) 45 46 /** 47 * DOC: DSB 48 * 49 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory 50 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA 51 * engine that can be programmed to download the DSB from memory. 52 * It allows driver to batch submit display HW programming. This helps to 53 * reduce loading time and CPU activity, thereby making the context switch 54 * faster. DSB Support added from Gen12 Intel graphics based platform. 55 * 56 * DSB's can access only the pipe, plane, and transcoder Data Island Packet 57 * registers. 58 * 59 * DSB HW can support only register writes (both indexed and direct MMIO 60 * writes). There are no registers reads possible with DSB HW engine. 61 */ 62 63 /* DSB opcodes. */ 64 #define DSB_OPCODE_SHIFT 24 65 #define DSB_OPCODE_MMIO_WRITE 0x1 66 #define DSB_OPCODE_INDEXED_WRITE 0x9 67 #define DSB_BYTE_EN 0xF 68 #define DSB_BYTE_EN_SHIFT 20 69 #define DSB_REG_VALUE_MASK 0xfffff 70 71 static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, 72 enum dsb_id id) 73 { 74 return DSB_STATUS & intel_de_read(i915, DSB_CTRL(pipe, id)); 75 } 76 77 static bool intel_dsb_enable_engine(struct drm_i915_private *i915, 78 enum pipe pipe, enum dsb_id id) 79 { 80 u32 dsb_ctrl; 81 82 dsb_ctrl = intel_de_read(i915, DSB_CTRL(pipe, id)); 83 if (DSB_STATUS & dsb_ctrl) { 84 drm_dbg_kms(&i915->drm, "DSB engine is busy.\n"); 85 return false; 86 } 87 88 dsb_ctrl |= DSB_ENABLE; 89 intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl); 90 91 intel_de_posting_read(i915, DSB_CTRL(pipe, id)); 92 return true; 93 } 94 95 static bool intel_dsb_disable_engine(struct drm_i915_private *i915, 96 enum pipe pipe, enum dsb_id id) 97 { 98 u32 dsb_ctrl; 99 100 dsb_ctrl = intel_de_read(i915, DSB_CTRL(pipe, id)); 101 if (DSB_STATUS & dsb_ctrl) { 102 drm_dbg_kms(&i915->drm, "DSB engine is busy.\n"); 103 return false; 104 } 105 106 dsb_ctrl &= ~DSB_ENABLE; 107 intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl); 108 109 intel_de_posting_read(i915, DSB_CTRL(pipe, id)); 110 return true; 111 } 112 113 /** 114 * intel_dsb_indexed_reg_write() -Write to the DSB context for auto 115 * increment register. 116 * @crtc_state: intel_crtc_state structure 117 * @reg: register address. 118 * @val: value. 119 * 120 * This function is used for writing register-value pair in command 121 * buffer of DSB for auto-increment register. During command buffer overflow, 122 * a warning is thrown and rest all erroneous condition register programming 123 * is done through mmio write. 124 */ 125 126 void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, 127 i915_reg_t reg, u32 val) 128 { 129 struct intel_dsb *dsb = crtc_state->dsb; 130 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 131 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 132 u32 *buf; 133 u32 reg_val; 134 135 if (!dsb) { 136 intel_de_write_fw(dev_priv, reg, val); 137 return; 138 } 139 buf = dsb->cmd_buf; 140 if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { 141 drm_dbg_kms(&dev_priv->drm, "DSB buffer overflow\n"); 142 return; 143 } 144 145 /* 146 * For example the buffer will look like below for 3 dwords for auto 147 * increment register: 148 * +--------------------------------------------------------+ 149 * | size = 3 | offset &| value1 | value2 | value3 | zero | 150 * | | opcode | | | | | 151 * +--------------------------------------------------------+ 152 * + + + + + + + 153 * 0 4 8 12 16 20 24 154 * Byte 155 * 156 * As every instruction is 8 byte aligned the index of dsb instruction 157 * will start always from even number while dealing with u32 array. If 158 * we are writing odd no of dwords, Zeros will be added in the end for 159 * padding. 160 */ 161 reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK; 162 if (reg_val != i915_mmio_reg_offset(reg)) { 163 /* Every instruction should be 8 byte aligned. */ 164 dsb->free_pos = ALIGN(dsb->free_pos, 2); 165 166 dsb->ins_start_offset = dsb->free_pos; 167 168 /* Update the size. */ 169 buf[dsb->free_pos++] = 1; 170 171 /* Update the opcode and reg. */ 172 buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE << 173 DSB_OPCODE_SHIFT) | 174 i915_mmio_reg_offset(reg); 175 176 /* Update the value. */ 177 buf[dsb->free_pos++] = val; 178 } else { 179 /* Update the new value. */ 180 buf[dsb->free_pos++] = val; 181 182 /* Update the size. */ 183 buf[dsb->ins_start_offset]++; 184 } 185 186 /* if number of data words is odd, then the last dword should be 0.*/ 187 if (dsb->free_pos & 0x1) 188 buf[dsb->free_pos] = 0; 189 } 190 191 /** 192 * intel_dsb_reg_write() -Write to the DSB context for normal 193 * register. 194 * @crtc_state: intel_crtc_state structure 195 * @reg: register address. 196 * @val: value. 197 * 198 * This function is used for writing register-value pair in command 199 * buffer of DSB. During command buffer overflow, a warning is thrown 200 * and rest all erroneous condition register programming is done 201 * through mmio write. 202 */ 203 void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, 204 i915_reg_t reg, u32 val) 205 { 206 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 207 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 208 struct intel_dsb *dsb; 209 u32 *buf; 210 211 dsb = crtc_state->dsb; 212 if (!dsb) { 213 intel_de_write_fw(dev_priv, reg, val); 214 return; 215 } 216 217 buf = dsb->cmd_buf; 218 if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { 219 drm_dbg_kms(&dev_priv->drm, "DSB buffer overflow\n"); 220 return; 221 } 222 223 dsb->ins_start_offset = dsb->free_pos; 224 buf[dsb->free_pos++] = val; 225 buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | 226 (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) | 227 i915_mmio_reg_offset(reg); 228 } 229 230 /** 231 * intel_dsb_commit() - Trigger workload execution of DSB. 232 * @crtc_state: intel_crtc_state structure 233 * 234 * This function is used to do actual write to hardware using DSB. 235 * On errors, fall back to MMIO. Also this function help to reset the context. 236 */ 237 void intel_dsb_commit(const struct intel_crtc_state *crtc_state) 238 { 239 struct intel_dsb *dsb = crtc_state->dsb; 240 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 241 struct drm_device *dev = crtc->base.dev; 242 struct drm_i915_private *dev_priv = to_i915(dev); 243 enum pipe pipe = crtc->pipe; 244 u32 tail; 245 246 if (!(dsb && dsb->free_pos)) 247 return; 248 249 if (!intel_dsb_enable_engine(dev_priv, pipe, dsb->id)) 250 goto reset; 251 252 if (is_dsb_busy(dev_priv, pipe, dsb->id)) { 253 drm_err(&dev_priv->drm, 254 "HEAD_PTR write failed - dsb engine is busy.\n"); 255 goto reset; 256 } 257 intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), 258 i915_ggtt_offset(dsb->vma)); 259 260 tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES); 261 if (tail > dsb->free_pos * 4) 262 memset(&dsb->cmd_buf[dsb->free_pos], 0, 263 (tail - dsb->free_pos * 4)); 264 265 if (is_dsb_busy(dev_priv, pipe, dsb->id)) { 266 drm_err(&dev_priv->drm, 267 "TAIL_PTR write failed - dsb engine is busy.\n"); 268 goto reset; 269 } 270 drm_dbg_kms(&dev_priv->drm, 271 "DSB execution started - head 0x%x, tail 0x%x\n", 272 i915_ggtt_offset(dsb->vma), tail); 273 intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), 274 i915_ggtt_offset(dsb->vma) + tail); 275 if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) { 276 drm_err(&dev_priv->drm, 277 "Timed out waiting for DSB workload completion.\n"); 278 goto reset; 279 } 280 281 reset: 282 dsb->free_pos = 0; 283 dsb->ins_start_offset = 0; 284 intel_dsb_disable_engine(dev_priv, pipe, dsb->id); 285 } 286 287 /** 288 * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer. 289 * @crtc_state: intel_crtc_state structure to prepare associated dsb instance. 290 * 291 * This function prepare the command buffer which is used to store dsb 292 * instructions with data. 293 */ 294 void intel_dsb_prepare(struct intel_crtc_state *crtc_state) 295 { 296 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 297 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 298 struct intel_dsb *dsb; 299 struct drm_i915_gem_object *obj; 300 struct i915_vma *vma; 301 u32 *buf; 302 intel_wakeref_t wakeref; 303 304 if (!HAS_DSB(i915)) 305 return; 306 307 dsb = kmalloc(sizeof(*dsb), GFP_KERNEL); 308 if (!dsb) { 309 drm_err(&i915->drm, "DSB object creation failed\n"); 310 return; 311 } 312 313 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 314 315 obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE); 316 if (IS_ERR(obj)) { 317 kfree(dsb); 318 goto out; 319 } 320 321 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); 322 if (IS_ERR(vma)) { 323 i915_gem_object_put(obj); 324 kfree(dsb); 325 goto out; 326 } 327 328 buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC); 329 if (IS_ERR(buf)) { 330 i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); 331 kfree(dsb); 332 goto out; 333 } 334 335 dsb->id = DSB1; 336 dsb->vma = vma; 337 dsb->cmd_buf = buf; 338 dsb->free_pos = 0; 339 dsb->ins_start_offset = 0; 340 crtc_state->dsb = dsb; 341 out: 342 if (!crtc_state->dsb) 343 drm_info(&i915->drm, 344 "DSB queue setup failed, will fallback to MMIO for display HW programming\n"); 345 346 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 347 } 348 349 /** 350 * intel_dsb_cleanup() - To cleanup DSB context. 351 * @crtc_state: intel_crtc_state structure to cleanup associated dsb instance. 352 * 353 * This function cleanup the DSB context by unpinning and releasing 354 * the VMA object associated with it. 355 */ 356 void intel_dsb_cleanup(struct intel_crtc_state *crtc_state) 357 { 358 if (!crtc_state->dsb) 359 return; 360 361 i915_vma_unpin_and_release(&crtc_state->dsb->vma, I915_VMA_RELEASE_MAP); 362 kfree(crtc_state->dsb); 363 crtc_state->dsb = NULL; 364 } 365