1a1b63119SJosé Roberto de Souza // SPDX-License-Identifier: MIT 2a1b63119SJosé Roberto de Souza /* 3a1b63119SJosé Roberto de Souza * Copyright © 2021 Intel Corporation 4a1b63119SJosé Roberto de Souza */ 5a1b63119SJosé Roberto de Souza 6a1b63119SJosé Roberto de Souza #include "i915_drv.h" 7a1b63119SJosé Roberto de Souza #include "intel_atomic.h" 8a1b63119SJosé Roberto de Souza #include "intel_de.h" 9a1b63119SJosé Roberto de Souza #include "intel_display_types.h" 10a1b63119SJosé Roberto de Souza #include "intel_drrs.h" 11a1b63119SJosé Roberto de Souza #include "intel_panel.h" 12a1b63119SJosé Roberto de Souza 13a1b63119SJosé Roberto de Souza /** 14a1b63119SJosé Roberto de Souza * DOC: Display Refresh Rate Switching (DRRS) 15a1b63119SJosé Roberto de Souza * 16a1b63119SJosé Roberto de Souza * Display Refresh Rate Switching (DRRS) is a power conservation feature 17a1b63119SJosé Roberto de Souza * which enables swtching between low and high refresh rates, 18a1b63119SJosé Roberto de Souza * dynamically, based on the usage scenario. This feature is applicable 19a1b63119SJosé Roberto de Souza * for internal panels. 20a1b63119SJosé Roberto de Souza * 21a1b63119SJosé Roberto de Souza * Indication that the panel supports DRRS is given by the panel EDID, which 22a1b63119SJosé Roberto de Souza * would list multiple refresh rates for one resolution. 23a1b63119SJosé Roberto de Souza * 24a1b63119SJosé Roberto de Souza * DRRS is of 2 types - static and seamless. 25a1b63119SJosé Roberto de Souza * Static DRRS involves changing refresh rate (RR) by doing a full modeset 26a1b63119SJosé Roberto de Souza * (may appear as a blink on screen) and is used in dock-undock scenario. 27a1b63119SJosé Roberto de Souza * Seamless DRRS involves changing RR without any visual effect to the user 28a1b63119SJosé Roberto de Souza * and can be used during normal system usage. This is done by programming 29a1b63119SJosé Roberto de Souza * certain registers. 30a1b63119SJosé Roberto de Souza * 31a1b63119SJosé Roberto de Souza * Support for static/seamless DRRS may be indicated in the VBT based on 32a1b63119SJosé Roberto de Souza * inputs from the panel spec. 33a1b63119SJosé Roberto de Souza * 34a1b63119SJosé Roberto de Souza * DRRS saves power by switching to low RR based on usage scenarios. 35a1b63119SJosé Roberto de Souza * 36a1b63119SJosé Roberto de Souza * The implementation is based on frontbuffer tracking implementation. When 37a1b63119SJosé Roberto de Souza * there is a disturbance on the screen triggered by user activity or a periodic 38a1b63119SJosé Roberto de Souza * system activity, DRRS is disabled (RR is changed to high RR). When there is 39a1b63119SJosé Roberto de Souza * no movement on screen, after a timeout of 1 second, a switch to low RR is 40a1b63119SJosé Roberto de Souza * made. 41a1b63119SJosé Roberto de Souza * 423a3dd534SJosé Roberto de Souza * For integration with frontbuffer tracking code, intel_drrs_invalidate() 433a3dd534SJosé Roberto de Souza * and intel_drrs_flush() are called. 44a1b63119SJosé Roberto de Souza * 45a1b63119SJosé Roberto de Souza * DRRS can be further extended to support other internal panels and also 46a1b63119SJosé Roberto de Souza * the scenario of video playback wherein RR is set based on the rate 47a1b63119SJosé Roberto de Souza * requested by userspace. 48a1b63119SJosé Roberto de Souza */ 49a1b63119SJosé Roberto de Souza 50c3e27f43SVille Syrjälä static bool can_enable_drrs(struct intel_connector *connector, 51*f0a57798SVille Syrjälä const struct intel_crtc_state *pipe_config) 52a1b63119SJosé Roberto de Souza { 53a1b63119SJosé Roberto de Souza if (pipe_config->vrr.enable) 54c3e27f43SVille Syrjälä return false; 55a1b63119SJosé Roberto de Souza 56a1b63119SJosé Roberto de Souza /* 57a1b63119SJosé Roberto de Souza * DRRS and PSR can't be enable together, so giving preference to PSR 58a1b63119SJosé Roberto de Souza * as it allows more power-savings by complete shutting down display, 593a3dd534SJosé Roberto de Souza * so to guarantee this, intel_drrs_compute_config() must be called 60a1b63119SJosé Roberto de Souza * after intel_psr_compute_config(). 61a1b63119SJosé Roberto de Souza */ 62a1b63119SJosé Roberto de Souza if (pipe_config->has_psr) 63c3e27f43SVille Syrjälä return false; 64a1b63119SJosé Roberto de Souza 65*f0a57798SVille Syrjälä return intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 66c3e27f43SVille Syrjälä } 67c3e27f43SVille Syrjälä 68c3e27f43SVille Syrjälä void 69c3e27f43SVille Syrjälä intel_drrs_compute_config(struct intel_dp *intel_dp, 70c3e27f43SVille Syrjälä struct intel_crtc_state *pipe_config, 71c3e27f43SVille Syrjälä int output_bpp, bool constant_n) 72c3e27f43SVille Syrjälä { 73c3e27f43SVille Syrjälä struct intel_connector *connector = intel_dp->attached_connector; 741d06c820SVille Syrjälä struct drm_i915_private *i915 = to_i915(connector->base.dev); 7509270678SVille Syrjälä const struct drm_display_mode *downclock_mode = 7609270678SVille Syrjälä intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 77c3e27f43SVille Syrjälä int pixel_clock; 78c3e27f43SVille Syrjälä 79*f0a57798SVille Syrjälä if (!can_enable_drrs(connector, pipe_config)) { 801d06c820SVille Syrjälä if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 811d06c820SVille Syrjälä intel_zero_m_n(&pipe_config->dp_m2_n2); 82a1b63119SJosé Roberto de Souza return; 831d06c820SVille Syrjälä } 84a1b63119SJosé Roberto de Souza 851fa7bb12SVille Syrjälä if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) 861fa7bb12SVille Syrjälä pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay; 871fa7bb12SVille Syrjälä 88a1b63119SJosé Roberto de Souza pipe_config->has_drrs = true; 89a1b63119SJosé Roberto de Souza 9009270678SVille Syrjälä pixel_clock = downclock_mode->clock; 91a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 92a1b63119SJosé Roberto de Souza pixel_clock /= pipe_config->splitter.link_count; 93a1b63119SJosé Roberto de Souza 94a1b63119SJosé Roberto de Souza intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, 95a1b63119SJosé Roberto de Souza pipe_config->port_clock, &pipe_config->dp_m2_n2, 96a1b63119SJosé Roberto de Souza constant_n, pipe_config->fec_enable); 97a1b63119SJosé Roberto de Souza 98a1b63119SJosé Roberto de Souza /* FIXME: abstract this better */ 99a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 1005f721a5dSVille Syrjälä pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 101a1b63119SJosé Roberto de Souza } 102a1b63119SJosé Roberto de Souza 10314683babSVille Syrjälä static void 10414683babSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state, 1055a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 10614683babSVille Syrjälä { 10714683babSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 10814683babSVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 10914683babSVille Syrjälä enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 11014683babSVille Syrjälä u32 val, bit; 11114683babSVille Syrjälä 11214683babSVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 113dd7ae6b3SVille Syrjälä bit = PIPECONF_REFRESH_RATE_ALT_VLV; 11414683babSVille Syrjälä else 115dd7ae6b3SVille Syrjälä bit = PIPECONF_REFRESH_RATE_ALT_ILK; 11614683babSVille Syrjälä 11714683babSVille Syrjälä val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 11814683babSVille Syrjälä 1195a220c53SVille Syrjälä if (refresh_rate == DRRS_REFRESH_RATE_LOW) 12014683babSVille Syrjälä val |= bit; 12114683babSVille Syrjälä else 12214683babSVille Syrjälä val &= ~bit; 12314683babSVille Syrjälä 12414683babSVille Syrjälä intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 12514683babSVille Syrjälä } 12614683babSVille Syrjälä 12714683babSVille Syrjälä static void 12814683babSVille Syrjälä intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state, 1295a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 13014683babSVille Syrjälä { 1310adc41deSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1320adc41deSVille Syrjälä 1330adc41deSVille Syrjälä intel_cpu_transcoder_set_m1_n1(crtc, crtc_state->cpu_transcoder, 1345a220c53SVille Syrjälä refresh_rate == DRRS_REFRESH_RATE_LOW ? 135be0c94eeSVille Syrjälä &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n); 13614683babSVille Syrjälä } 13714683babSVille Syrjälä 1383a3dd534SJosé Roberto de Souza static void intel_drrs_set_state(struct drm_i915_private *dev_priv, 139a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state, 1405a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 141a1b63119SJosé Roberto de Souza { 142a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp = dev_priv->drrs.dp; 143a1b63119SJosé Roberto de Souza struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 144a1b63119SJosé Roberto de Souza 145c7c4dfb6SJosé Roberto de Souza if (!intel_dp) { 146a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); 147a1b63119SJosé Roberto de Souza return; 148a1b63119SJosé Roberto de Souza } 149a1b63119SJosé Roberto de Souza 150a1b63119SJosé Roberto de Souza if (!crtc) { 151a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 152a1b63119SJosé Roberto de Souza "DRRS: intel_crtc not initialized\n"); 153a1b63119SJosé Roberto de Souza return; 154a1b63119SJosé Roberto de Souza } 155a1b63119SJosé Roberto de Souza 156c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) { 157a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); 158a1b63119SJosé Roberto de Souza return; 159a1b63119SJosé Roberto de Souza } 160a1b63119SJosé Roberto de Souza 1615a220c53SVille Syrjälä if (refresh_rate == dev_priv->drrs.refresh_rate) 162a1b63119SJosé Roberto de Souza return; 163a1b63119SJosé Roberto de Souza 164a1b63119SJosé Roberto de Souza if (!crtc_state->hw.active) { 165a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 166a1b63119SJosé Roberto de Souza "eDP encoder disabled. CRTC not Active\n"); 167a1b63119SJosé Roberto de Souza return; 168a1b63119SJosé Roberto de Souza } 169a1b63119SJosé Roberto de Souza 17014683babSVille Syrjälä if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) 1715a220c53SVille Syrjälä intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_rate); 17214683babSVille Syrjälä else if (DISPLAY_VER(dev_priv) > 6) 1735a220c53SVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_rate); 174a1b63119SJosé Roberto de Souza 1755a220c53SVille Syrjälä dev_priv->drrs.refresh_rate = refresh_rate; 176a1b63119SJosé Roberto de Souza 1775a220c53SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %s\n", 1785a220c53SVille Syrjälä refresh_rate == DRRS_REFRESH_RATE_LOW ? "low" : "high"); 179a1b63119SJosé Roberto de Souza } 180a1b63119SJosé Roberto de Souza 181a1b63119SJosé Roberto de Souza static void 1823a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(struct intel_dp *intel_dp) 183a1b63119SJosé Roberto de Souza { 184a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 185a1b63119SJosé Roberto de Souza 186a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits = 0; 187a1b63119SJosé Roberto de Souza dev_priv->drrs.dp = intel_dp; 188a1b63119SJosé Roberto de Souza } 189a1b63119SJosé Roberto de Souza 190a1b63119SJosé Roberto de Souza /** 1913a3dd534SJosé Roberto de Souza * intel_drrs_enable - init drrs struct if supported 192a1b63119SJosé Roberto de Souza * @intel_dp: DP struct 193a1b63119SJosé Roberto de Souza * @crtc_state: A pointer to the active crtc state. 194a1b63119SJosé Roberto de Souza * 195a1b63119SJosé Roberto de Souza * Initializes frontbuffer_bits and drrs.dp 196a1b63119SJosé Roberto de Souza */ 1973a3dd534SJosé Roberto de Souza void intel_drrs_enable(struct intel_dp *intel_dp, 198a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 199a1b63119SJosé Roberto de Souza { 200a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 201a1b63119SJosé Roberto de Souza 202a1b63119SJosé Roberto de Souza if (!crtc_state->has_drrs) 203a1b63119SJosé Roberto de Souza return; 204a1b63119SJosé Roberto de Souza 205a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n"); 206a1b63119SJosé Roberto de Souza 207a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 208a1b63119SJosé Roberto de Souza 209a1b63119SJosé Roberto de Souza if (dev_priv->drrs.dp) { 210a1b63119SJosé Roberto de Souza drm_warn(&dev_priv->drm, "DRRS already enabled\n"); 211a1b63119SJosé Roberto de Souza goto unlock; 212a1b63119SJosé Roberto de Souza } 213a1b63119SJosé Roberto de Souza 2143a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(intel_dp); 215a1b63119SJosé Roberto de Souza 216a1b63119SJosé Roberto de Souza unlock: 217a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 218a1b63119SJosé Roberto de Souza } 219a1b63119SJosé Roberto de Souza 220a1b63119SJosé Roberto de Souza static void 2213a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(struct intel_dp *intel_dp, 222a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 223a1b63119SJosé Roberto de Souza { 224a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 225a1b63119SJosé Roberto de Souza 2265a220c53SVille Syrjälä intel_drrs_set_state(dev_priv, crtc_state, DRRS_REFRESH_RATE_HIGH); 227a1b63119SJosé Roberto de Souza dev_priv->drrs.dp = NULL; 228a1b63119SJosé Roberto de Souza } 229a1b63119SJosé Roberto de Souza 230a1b63119SJosé Roberto de Souza /** 2313a3dd534SJosé Roberto de Souza * intel_drrs_disable - Disable DRRS 232a1b63119SJosé Roberto de Souza * @intel_dp: DP struct 233a1b63119SJosé Roberto de Souza * @old_crtc_state: Pointer to old crtc_state. 234a1b63119SJosé Roberto de Souza * 235a1b63119SJosé Roberto de Souza */ 2363a3dd534SJosé Roberto de Souza void intel_drrs_disable(struct intel_dp *intel_dp, 237a1b63119SJosé Roberto de Souza const struct intel_crtc_state *old_crtc_state) 238a1b63119SJosé Roberto de Souza { 239a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 240a1b63119SJosé Roberto de Souza 241a1b63119SJosé Roberto de Souza if (!old_crtc_state->has_drrs) 242a1b63119SJosé Roberto de Souza return; 243a1b63119SJosé Roberto de Souza 244a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 245a1b63119SJosé Roberto de Souza if (!dev_priv->drrs.dp) { 246a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 247a1b63119SJosé Roberto de Souza return; 248a1b63119SJosé Roberto de Souza } 249a1b63119SJosé Roberto de Souza 2503a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(intel_dp, old_crtc_state); 251a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 252a1b63119SJosé Roberto de Souza 253a1b63119SJosé Roberto de Souza cancel_delayed_work_sync(&dev_priv->drrs.work); 254a1b63119SJosé Roberto de Souza } 255a1b63119SJosé Roberto de Souza 256a1b63119SJosé Roberto de Souza /** 2573a3dd534SJosé Roberto de Souza * intel_drrs_update - Update DRRS state 258a1b63119SJosé Roberto de Souza * @intel_dp: Intel DP 259a1b63119SJosé Roberto de Souza * @crtc_state: new CRTC state 260a1b63119SJosé Roberto de Souza * 261a1b63119SJosé Roberto de Souza * This function will update DRRS states, disabling or enabling DRRS when 2623a3dd534SJosé Roberto de Souza * executing fastsets. For full modeset, intel_drrs_disable() and 2633a3dd534SJosé Roberto de Souza * intel_drrs_enable() should be called instead. 264a1b63119SJosé Roberto de Souza */ 265a1b63119SJosé Roberto de Souza void 2663a3dd534SJosé Roberto de Souza intel_drrs_update(struct intel_dp *intel_dp, 267a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 268a1b63119SJosé Roberto de Souza { 269a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 270a1b63119SJosé Roberto de Souza 271c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) 272a1b63119SJosé Roberto de Souza return; 273a1b63119SJosé Roberto de Souza 274a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 275a1b63119SJosé Roberto de Souza 276a1b63119SJosé Roberto de Souza /* New state matches current one? */ 277a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs == !!dev_priv->drrs.dp) 278a1b63119SJosé Roberto de Souza goto unlock; 279a1b63119SJosé Roberto de Souza 280a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs) 2813a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(intel_dp); 282a1b63119SJosé Roberto de Souza else 2833a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(intel_dp, crtc_state); 284a1b63119SJosé Roberto de Souza 285a1b63119SJosé Roberto de Souza unlock: 286a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 287a1b63119SJosé Roberto de Souza } 288a1b63119SJosé Roberto de Souza 2893a3dd534SJosé Roberto de Souza static void intel_drrs_downclock_work(struct work_struct *work) 290a1b63119SJosé Roberto de Souza { 291a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = 292a1b63119SJosé Roberto de Souza container_of(work, typeof(*dev_priv), drrs.work.work); 293a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp; 294a1b63119SJosé Roberto de Souza 295a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 296a1b63119SJosé Roberto de Souza 297a1b63119SJosé Roberto de Souza intel_dp = dev_priv->drrs.dp; 298a1b63119SJosé Roberto de Souza 299a1b63119SJosé Roberto de Souza if (!intel_dp) 300a1b63119SJosé Roberto de Souza goto unlock; 301a1b63119SJosé Roberto de Souza 302a1b63119SJosé Roberto de Souza /* 303a1b63119SJosé Roberto de Souza * The delayed work can race with an invalidate hence we need to 304a1b63119SJosé Roberto de Souza * recheck. 305a1b63119SJosé Roberto de Souza */ 306a1b63119SJosé Roberto de Souza 3075a220c53SVille Syrjälä if (!dev_priv->drrs.busy_frontbuffer_bits) { 3085a220c53SVille Syrjälä struct intel_crtc *crtc = 3095a220c53SVille Syrjälä to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); 310a1b63119SJosé Roberto de Souza 3115a220c53SVille Syrjälä intel_drrs_set_state(dev_priv, crtc->config, 3125a220c53SVille Syrjälä DRRS_REFRESH_RATE_LOW); 3135a220c53SVille Syrjälä } 314a1b63119SJosé Roberto de Souza 315a1b63119SJosé Roberto de Souza unlock: 316a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 317a1b63119SJosé Roberto de Souza } 318a1b63119SJosé Roberto de Souza 3196bd58b70SJosé Roberto de Souza static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, 3206bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits, 3216bd58b70SJosé Roberto de Souza bool invalidate) 322a1b63119SJosé Roberto de Souza { 323a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp; 324a1b63119SJosé Roberto de Souza struct drm_crtc *crtc; 325a1b63119SJosé Roberto de Souza enum pipe pipe; 326a1b63119SJosé Roberto de Souza 327c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) 328a1b63119SJosé Roberto de Souza return; 329a1b63119SJosé Roberto de Souza 330a1b63119SJosé Roberto de Souza cancel_delayed_work(&dev_priv->drrs.work); 331a1b63119SJosé Roberto de Souza 332a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 333a1b63119SJosé Roberto de Souza 334a1b63119SJosé Roberto de Souza intel_dp = dev_priv->drrs.dp; 335a1b63119SJosé Roberto de Souza if (!intel_dp) { 336a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 337a1b63119SJosé Roberto de Souza return; 338a1b63119SJosé Roberto de Souza } 339a1b63119SJosé Roberto de Souza 340a1b63119SJosé Roberto de Souza crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 341a1b63119SJosé Roberto de Souza pipe = to_intel_crtc(crtc)->pipe; 342a1b63119SJosé Roberto de Souza 343a1b63119SJosé Roberto de Souza frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 3446bd58b70SJosé Roberto de Souza if (invalidate) 345a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 3466bd58b70SJosé Roberto de Souza else 3476bd58b70SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 348a1b63119SJosé Roberto de Souza 3496bd58b70SJosé Roberto de Souza /* flush/invalidate means busy screen hence upclock */ 350c7c4dfb6SJosé Roberto de Souza if (frontbuffer_bits) 3513a3dd534SJosé Roberto de Souza intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config, 3525a220c53SVille Syrjälä DRRS_REFRESH_RATE_HIGH); 353a1b63119SJosé Roberto de Souza 3546bd58b70SJosé Roberto de Souza /* 3556bd58b70SJosé Roberto de Souza * flush also means no more activity hence schedule downclock, if all 3566bd58b70SJosé Roberto de Souza * other fbs are quiescent too 3576bd58b70SJosé Roberto de Souza */ 3586bd58b70SJosé Roberto de Souza if (!invalidate && !dev_priv->drrs.busy_frontbuffer_bits) 3596bd58b70SJosé Roberto de Souza schedule_delayed_work(&dev_priv->drrs.work, 3606bd58b70SJosé Roberto de Souza msecs_to_jiffies(1000)); 361a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 362a1b63119SJosé Roberto de Souza } 363a1b63119SJosé Roberto de Souza 364a1b63119SJosé Roberto de Souza /** 3656bd58b70SJosé Roberto de Souza * intel_drrs_invalidate - Disable Idleness DRRS 3666bd58b70SJosé Roberto de Souza * @dev_priv: i915 device 3676bd58b70SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 3686bd58b70SJosé Roberto de Souza * 3696bd58b70SJosé Roberto de Souza * This function gets called everytime rendering on the given planes start. 3706bd58b70SJosé Roberto de Souza * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 3716bd58b70SJosé Roberto de Souza * 3726bd58b70SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 3736bd58b70SJosé Roberto de Souza */ 3746bd58b70SJosé Roberto de Souza void intel_drrs_invalidate(struct drm_i915_private *dev_priv, 3756bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits) 3766bd58b70SJosé Roberto de Souza { 3776bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true); 3786bd58b70SJosé Roberto de Souza } 3796bd58b70SJosé Roberto de Souza 3806bd58b70SJosé Roberto de Souza /** 3813a3dd534SJosé Roberto de Souza * intel_drrs_flush - Restart Idleness DRRS 382a1b63119SJosé Roberto de Souza * @dev_priv: i915 device 383a1b63119SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 384a1b63119SJosé Roberto de Souza * 385a1b63119SJosé Roberto de Souza * This function gets called every time rendering on the given planes has 386a1b63119SJosé Roberto de Souza * completed or flip on a crtc is completed. So DRRS should be upclocked 387a1b63119SJosé Roberto de Souza * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 388a1b63119SJosé Roberto de Souza * if no other planes are dirty. 389a1b63119SJosé Roberto de Souza * 390a1b63119SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 391a1b63119SJosé Roberto de Souza */ 3923a3dd534SJosé Roberto de Souza void intel_drrs_flush(struct drm_i915_private *dev_priv, 393a1b63119SJosé Roberto de Souza unsigned int frontbuffer_bits) 394a1b63119SJosé Roberto de Souza { 3956bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 396a1b63119SJosé Roberto de Souza } 397a1b63119SJosé Roberto de Souza 3980f3692b5SJosé Roberto de Souza void intel_drrs_page_flip(struct intel_atomic_state *state, 3990f3692b5SJosé Roberto de Souza struct intel_crtc *crtc) 4000f3692b5SJosé Roberto de Souza { 4010f3692b5SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(state->base.dev); 4020f3692b5SJosé Roberto de Souza unsigned int frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); 4030f3692b5SJosé Roberto de Souza 4040f3692b5SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 4050f3692b5SJosé Roberto de Souza } 4060f3692b5SJosé Roberto de Souza 407a1b63119SJosé Roberto de Souza /** 4083a3dd534SJosé Roberto de Souza * intel_drrs_init - Init basic DRRS work and mutex. 409a1b63119SJosé Roberto de Souza * @connector: eDP connector 410a1b63119SJosé Roberto de Souza * @fixed_mode: preferred mode of panel 411a1b63119SJosé Roberto de Souza * 412a1b63119SJosé Roberto de Souza * This function is called only once at driver load to initialize basic 413a1b63119SJosé Roberto de Souza * DRRS stuff. 414a1b63119SJosé Roberto de Souza * 415a1b63119SJosé Roberto de Souza * Returns: 416a1b63119SJosé Roberto de Souza * Downclock mode if panel supports it, else return NULL. 417a1b63119SJosé Roberto de Souza * DRRS support is determined by the presence of downclock mode (apart 418a1b63119SJosé Roberto de Souza * from VBT setting). 419a1b63119SJosé Roberto de Souza */ 420a1b63119SJosé Roberto de Souza struct drm_display_mode * 4213a3dd534SJosé Roberto de Souza intel_drrs_init(struct intel_connector *connector, 422faf6e8fcSVille Syrjälä const struct drm_display_mode *fixed_mode) 423a1b63119SJosé Roberto de Souza { 424a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 425f0d4ce59SVille Syrjälä struct intel_encoder *encoder = connector->encoder; 426a1b63119SJosé Roberto de Souza struct drm_display_mode *downclock_mode = NULL; 427a1b63119SJosé Roberto de Souza 4283a3dd534SJosé Roberto de Souza INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_drrs_downclock_work); 429a1b63119SJosé Roberto de Souza mutex_init(&dev_priv->drrs.mutex); 430a1b63119SJosé Roberto de Souza 431a1b63119SJosé Roberto de Souza if (DISPLAY_VER(dev_priv) <= 6) { 432a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4335f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on platform\n", 4345f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 435a1b63119SJosé Roberto de Souza return NULL; 436a1b63119SJosé Roberto de Souza } 437a1b63119SJosé Roberto de Souza 438f0d4ce59SVille Syrjälä if ((DISPLAY_VER(dev_priv) < 8 && !HAS_GMCH(dev_priv)) && 439f0d4ce59SVille Syrjälä encoder->port != PORT_A) { 440f0d4ce59SVille Syrjälä drm_dbg_kms(&dev_priv->drm, 4415f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on [ENCODER:%d:%s]\n", 4425f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name, 4435f6a9beaSVille Syrjälä encoder->base.base.id, encoder->base.name); 444f0d4ce59SVille Syrjälä return NULL; 445f0d4ce59SVille Syrjälä } 446f0d4ce59SVille Syrjälä 4478e9c9848SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) { 4485f6a9beaSVille Syrjälä drm_dbg_kms(&dev_priv->drm, 4495f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported according to VBT\n", 4505f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 451a1b63119SJosé Roberto de Souza return NULL; 452a1b63119SJosé Roberto de Souza } 453a1b63119SJosé Roberto de Souza 454a1b63119SJosé Roberto de Souza downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 455a1b63119SJosé Roberto de Souza if (!downclock_mode) { 456a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4575f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported due to lack of downclock mode\n", 4585f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 459a1b63119SJosé Roberto de Souza return NULL; 460a1b63119SJosé Roberto de Souza } 461a1b63119SJosé Roberto de Souza 4625a220c53SVille Syrjälä dev_priv->drrs.refresh_rate = DRRS_REFRESH_RATE_HIGH; 463a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4645f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] seamless DRRS supported\n", 4655f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 4665f6a9beaSVille Syrjälä 467a1b63119SJosé Roberto de Souza return downclock_mode; 468a1b63119SJosé Roberto de Souza } 469