1a1b63119SJosé Roberto de Souza // SPDX-License-Identifier: MIT 2a1b63119SJosé Roberto de Souza /* 3a1b63119SJosé Roberto de Souza * Copyright © 2021 Intel Corporation 4a1b63119SJosé Roberto de Souza */ 5a1b63119SJosé Roberto de Souza 6a1b63119SJosé Roberto de Souza #include "i915_drv.h" 7a1b63119SJosé Roberto de Souza #include "intel_atomic.h" 8a1b63119SJosé Roberto de Souza #include "intel_de.h" 9a1b63119SJosé Roberto de Souza #include "intel_display_types.h" 10a1b63119SJosé Roberto de Souza #include "intel_drrs.h" 11a1b63119SJosé Roberto de Souza #include "intel_panel.h" 12a1b63119SJosé Roberto de Souza 13a1b63119SJosé Roberto de Souza /** 14a1b63119SJosé Roberto de Souza * DOC: Display Refresh Rate Switching (DRRS) 15a1b63119SJosé Roberto de Souza * 16a1b63119SJosé Roberto de Souza * Display Refresh Rate Switching (DRRS) is a power conservation feature 17a1b63119SJosé Roberto de Souza * which enables swtching between low and high refresh rates, 18a1b63119SJosé Roberto de Souza * dynamically, based on the usage scenario. This feature is applicable 19a1b63119SJosé Roberto de Souza * for internal panels. 20a1b63119SJosé Roberto de Souza * 21a1b63119SJosé Roberto de Souza * Indication that the panel supports DRRS is given by the panel EDID, which 22a1b63119SJosé Roberto de Souza * would list multiple refresh rates for one resolution. 23a1b63119SJosé Roberto de Souza * 24a1b63119SJosé Roberto de Souza * DRRS is of 2 types - static and seamless. 25a1b63119SJosé Roberto de Souza * Static DRRS involves changing refresh rate (RR) by doing a full modeset 26a1b63119SJosé Roberto de Souza * (may appear as a blink on screen) and is used in dock-undock scenario. 27a1b63119SJosé Roberto de Souza * Seamless DRRS involves changing RR without any visual effect to the user 28a1b63119SJosé Roberto de Souza * and can be used during normal system usage. This is done by programming 29a1b63119SJosé Roberto de Souza * certain registers. 30a1b63119SJosé Roberto de Souza * 31a1b63119SJosé Roberto de Souza * Support for static/seamless DRRS may be indicated in the VBT based on 32a1b63119SJosé Roberto de Souza * inputs from the panel spec. 33a1b63119SJosé Roberto de Souza * 34a1b63119SJosé Roberto de Souza * DRRS saves power by switching to low RR based on usage scenarios. 35a1b63119SJosé Roberto de Souza * 36a1b63119SJosé Roberto de Souza * The implementation is based on frontbuffer tracking implementation. When 37a1b63119SJosé Roberto de Souza * there is a disturbance on the screen triggered by user activity or a periodic 38a1b63119SJosé Roberto de Souza * system activity, DRRS is disabled (RR is changed to high RR). When there is 39a1b63119SJosé Roberto de Souza * no movement on screen, after a timeout of 1 second, a switch to low RR is 40a1b63119SJosé Roberto de Souza * made. 41a1b63119SJosé Roberto de Souza * 423a3dd534SJosé Roberto de Souza * For integration with frontbuffer tracking code, intel_drrs_invalidate() 433a3dd534SJosé Roberto de Souza * and intel_drrs_flush() are called. 44a1b63119SJosé Roberto de Souza * 45a1b63119SJosé Roberto de Souza * DRRS can be further extended to support other internal panels and also 46a1b63119SJosé Roberto de Souza * the scenario of video playback wherein RR is set based on the rate 47a1b63119SJosé Roberto de Souza * requested by userspace. 48a1b63119SJosé Roberto de Souza */ 49a1b63119SJosé Roberto de Souza 50*c3e27f43SVille Syrjälä static bool can_enable_drrs(struct intel_connector *connector, 51*c3e27f43SVille Syrjälä const struct intel_crtc_state *pipe_config) 52a1b63119SJosé Roberto de Souza { 53*c3e27f43SVille Syrjälä const struct drm_i915_private *i915 = to_i915(connector->base.dev); 54a1b63119SJosé Roberto de Souza 55a1b63119SJosé Roberto de Souza if (pipe_config->vrr.enable) 56*c3e27f43SVille Syrjälä return false; 57a1b63119SJosé Roberto de Souza 58a1b63119SJosé Roberto de Souza /* 59a1b63119SJosé Roberto de Souza * DRRS and PSR can't be enable together, so giving preference to PSR 60a1b63119SJosé Roberto de Souza * as it allows more power-savings by complete shutting down display, 613a3dd534SJosé Roberto de Souza * so to guarantee this, intel_drrs_compute_config() must be called 62a1b63119SJosé Roberto de Souza * after intel_psr_compute_config(). 63a1b63119SJosé Roberto de Souza */ 64a1b63119SJosé Roberto de Souza if (pipe_config->has_psr) 65*c3e27f43SVille Syrjälä return false; 66a1b63119SJosé Roberto de Souza 67*c3e27f43SVille Syrjälä return connector->panel.downclock_mode && 68*c3e27f43SVille Syrjälä i915->drrs.type == SEAMLESS_DRRS_SUPPORT; 69*c3e27f43SVille Syrjälä } 70*c3e27f43SVille Syrjälä 71*c3e27f43SVille Syrjälä void 72*c3e27f43SVille Syrjälä intel_drrs_compute_config(struct intel_dp *intel_dp, 73*c3e27f43SVille Syrjälä struct intel_crtc_state *pipe_config, 74*c3e27f43SVille Syrjälä int output_bpp, bool constant_n) 75*c3e27f43SVille Syrjälä { 76*c3e27f43SVille Syrjälä struct intel_connector *connector = intel_dp->attached_connector; 77*c3e27f43SVille Syrjälä int pixel_clock; 78*c3e27f43SVille Syrjälä 79*c3e27f43SVille Syrjälä if (!can_enable_drrs(connector, pipe_config)) 80a1b63119SJosé Roberto de Souza return; 81a1b63119SJosé Roberto de Souza 82a1b63119SJosé Roberto de Souza pipe_config->has_drrs = true; 83a1b63119SJosé Roberto de Souza 84*c3e27f43SVille Syrjälä pixel_clock = connector->panel.downclock_mode->clock; 85a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 86a1b63119SJosé Roberto de Souza pixel_clock /= pipe_config->splitter.link_count; 87a1b63119SJosé Roberto de Souza 88a1b63119SJosé Roberto de Souza intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, 89a1b63119SJosé Roberto de Souza pipe_config->port_clock, &pipe_config->dp_m2_n2, 90a1b63119SJosé Roberto de Souza constant_n, pipe_config->fec_enable); 91a1b63119SJosé Roberto de Souza 92a1b63119SJosé Roberto de Souza /* FIXME: abstract this better */ 93a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 945f721a5dSVille Syrjälä pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 95a1b63119SJosé Roberto de Souza } 96a1b63119SJosé Roberto de Souza 9714683babSVille Syrjälä static void 9814683babSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state, 9914683babSVille Syrjälä enum drrs_refresh_rate_type refresh_type) 10014683babSVille Syrjälä { 10114683babSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 10214683babSVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 10314683babSVille Syrjälä enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 10414683babSVille Syrjälä u32 val, bit; 10514683babSVille Syrjälä 10614683babSVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 10714683babSVille Syrjälä bit = PIPECONF_EDP_RR_MODE_SWITCH_VLV; 10814683babSVille Syrjälä else 10914683babSVille Syrjälä bit = PIPECONF_EDP_RR_MODE_SWITCH; 11014683babSVille Syrjälä 11114683babSVille Syrjälä val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 11214683babSVille Syrjälä 11314683babSVille Syrjälä if (refresh_type == DRRS_LOW_RR) 11414683babSVille Syrjälä val |= bit; 11514683babSVille Syrjälä else 11614683babSVille Syrjälä val &= ~bit; 11714683babSVille Syrjälä 11814683babSVille Syrjälä intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 11914683babSVille Syrjälä } 12014683babSVille Syrjälä 12114683babSVille Syrjälä static void 12214683babSVille Syrjälä intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state, 12314683babSVille Syrjälä enum drrs_refresh_rate_type refresh_type) 12414683babSVille Syrjälä { 1250adc41deSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1260adc41deSVille Syrjälä 1270adc41deSVille Syrjälä intel_cpu_transcoder_set_m1_n1(crtc, crtc_state->cpu_transcoder, 1280adc41deSVille Syrjälä refresh_type == DRRS_LOW_RR ? 129be0c94eeSVille Syrjälä &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n); 13014683babSVille Syrjälä } 13114683babSVille Syrjälä 1323a3dd534SJosé Roberto de Souza static void intel_drrs_set_state(struct drm_i915_private *dev_priv, 133a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state, 134c7c4dfb6SJosé Roberto de Souza enum drrs_refresh_rate_type refresh_type) 135a1b63119SJosé Roberto de Souza { 136a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp = dev_priv->drrs.dp; 137a1b63119SJosé Roberto de Souza struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 138c7c4dfb6SJosé Roberto de Souza struct drm_display_mode *mode; 139a1b63119SJosé Roberto de Souza 140c7c4dfb6SJosé Roberto de Souza if (!intel_dp) { 141a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); 142a1b63119SJosé Roberto de Souza return; 143a1b63119SJosé Roberto de Souza } 144a1b63119SJosé Roberto de Souza 145a1b63119SJosé Roberto de Souza if (!crtc) { 146a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 147a1b63119SJosé Roberto de Souza "DRRS: intel_crtc not initialized\n"); 148a1b63119SJosé Roberto de Souza return; 149a1b63119SJosé Roberto de Souza } 150a1b63119SJosé Roberto de Souza 151a1b63119SJosé Roberto de Souza if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { 152a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); 153a1b63119SJosé Roberto de Souza return; 154a1b63119SJosé Roberto de Souza } 155a1b63119SJosé Roberto de Souza 156c7c4dfb6SJosé Roberto de Souza if (refresh_type == dev_priv->drrs.refresh_rate_type) 157a1b63119SJosé Roberto de Souza return; 158a1b63119SJosé Roberto de Souza 159a1b63119SJosé Roberto de Souza if (!crtc_state->hw.active) { 160a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 161a1b63119SJosé Roberto de Souza "eDP encoder disabled. CRTC not Active\n"); 162a1b63119SJosé Roberto de Souza return; 163a1b63119SJosé Roberto de Souza } 164a1b63119SJosé Roberto de Souza 16514683babSVille Syrjälä if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) 16614683babSVille Syrjälä intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type); 16714683babSVille Syrjälä else if (DISPLAY_VER(dev_priv) > 6) 16814683babSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type); 169a1b63119SJosé Roberto de Souza 170c7c4dfb6SJosé Roberto de Souza dev_priv->drrs.refresh_rate_type = refresh_type; 171a1b63119SJosé Roberto de Souza 172c7c4dfb6SJosé Roberto de Souza if (refresh_type == DRRS_LOW_RR) 173c7c4dfb6SJosé Roberto de Souza mode = intel_dp->attached_connector->panel.downclock_mode; 174c7c4dfb6SJosé Roberto de Souza else 175c7c4dfb6SJosé Roberto de Souza mode = intel_dp->attached_connector->panel.fixed_mode; 176a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n", 177c7c4dfb6SJosé Roberto de Souza drm_mode_vrefresh(mode)); 178a1b63119SJosé Roberto de Souza } 179a1b63119SJosé Roberto de Souza 180a1b63119SJosé Roberto de Souza static void 1813a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(struct intel_dp *intel_dp) 182a1b63119SJosé Roberto de Souza { 183a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 184a1b63119SJosé Roberto de Souza 185a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits = 0; 186a1b63119SJosé Roberto de Souza dev_priv->drrs.dp = intel_dp; 187a1b63119SJosé Roberto de Souza } 188a1b63119SJosé Roberto de Souza 189a1b63119SJosé Roberto de Souza /** 1903a3dd534SJosé Roberto de Souza * intel_drrs_enable - init drrs struct if supported 191a1b63119SJosé Roberto de Souza * @intel_dp: DP struct 192a1b63119SJosé Roberto de Souza * @crtc_state: A pointer to the active crtc state. 193a1b63119SJosé Roberto de Souza * 194a1b63119SJosé Roberto de Souza * Initializes frontbuffer_bits and drrs.dp 195a1b63119SJosé Roberto de Souza */ 1963a3dd534SJosé Roberto de Souza void intel_drrs_enable(struct intel_dp *intel_dp, 197a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 198a1b63119SJosé Roberto de Souza { 199a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 200a1b63119SJosé Roberto de Souza 201a1b63119SJosé Roberto de Souza if (!crtc_state->has_drrs) 202a1b63119SJosé Roberto de Souza return; 203a1b63119SJosé Roberto de Souza 204a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n"); 205a1b63119SJosé Roberto de Souza 206a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 207a1b63119SJosé Roberto de Souza 208a1b63119SJosé Roberto de Souza if (dev_priv->drrs.dp) { 209a1b63119SJosé Roberto de Souza drm_warn(&dev_priv->drm, "DRRS already enabled\n"); 210a1b63119SJosé Roberto de Souza goto unlock; 211a1b63119SJosé Roberto de Souza } 212a1b63119SJosé Roberto de Souza 2133a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(intel_dp); 214a1b63119SJosé Roberto de Souza 215a1b63119SJosé Roberto de Souza unlock: 216a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 217a1b63119SJosé Roberto de Souza } 218a1b63119SJosé Roberto de Souza 219a1b63119SJosé Roberto de Souza static void 2203a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(struct intel_dp *intel_dp, 221a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 222a1b63119SJosé Roberto de Souza { 223a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 224a1b63119SJosé Roberto de Souza 225c7c4dfb6SJosé Roberto de Souza intel_drrs_set_state(dev_priv, crtc_state, DRRS_HIGH_RR); 226a1b63119SJosé Roberto de Souza dev_priv->drrs.dp = NULL; 227a1b63119SJosé Roberto de Souza } 228a1b63119SJosé Roberto de Souza 229a1b63119SJosé Roberto de Souza /** 2303a3dd534SJosé Roberto de Souza * intel_drrs_disable - Disable DRRS 231a1b63119SJosé Roberto de Souza * @intel_dp: DP struct 232a1b63119SJosé Roberto de Souza * @old_crtc_state: Pointer to old crtc_state. 233a1b63119SJosé Roberto de Souza * 234a1b63119SJosé Roberto de Souza */ 2353a3dd534SJosé Roberto de Souza void intel_drrs_disable(struct intel_dp *intel_dp, 236a1b63119SJosé Roberto de Souza const struct intel_crtc_state *old_crtc_state) 237a1b63119SJosé Roberto de Souza { 238a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 239a1b63119SJosé Roberto de Souza 240a1b63119SJosé Roberto de Souza if (!old_crtc_state->has_drrs) 241a1b63119SJosé Roberto de Souza return; 242a1b63119SJosé Roberto de Souza 243a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 244a1b63119SJosé Roberto de Souza if (!dev_priv->drrs.dp) { 245a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 246a1b63119SJosé Roberto de Souza return; 247a1b63119SJosé Roberto de Souza } 248a1b63119SJosé Roberto de Souza 2493a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(intel_dp, old_crtc_state); 250a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 251a1b63119SJosé Roberto de Souza 252a1b63119SJosé Roberto de Souza cancel_delayed_work_sync(&dev_priv->drrs.work); 253a1b63119SJosé Roberto de Souza } 254a1b63119SJosé Roberto de Souza 255a1b63119SJosé Roberto de Souza /** 2563a3dd534SJosé Roberto de Souza * intel_drrs_update - Update DRRS state 257a1b63119SJosé Roberto de Souza * @intel_dp: Intel DP 258a1b63119SJosé Roberto de Souza * @crtc_state: new CRTC state 259a1b63119SJosé Roberto de Souza * 260a1b63119SJosé Roberto de Souza * This function will update DRRS states, disabling or enabling DRRS when 2613a3dd534SJosé Roberto de Souza * executing fastsets. For full modeset, intel_drrs_disable() and 2623a3dd534SJosé Roberto de Souza * intel_drrs_enable() should be called instead. 263a1b63119SJosé Roberto de Souza */ 264a1b63119SJosé Roberto de Souza void 2653a3dd534SJosé Roberto de Souza intel_drrs_update(struct intel_dp *intel_dp, 266a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 267a1b63119SJosé Roberto de Souza { 268a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 269a1b63119SJosé Roberto de Souza 270a1b63119SJosé Roberto de Souza if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) 271a1b63119SJosé Roberto de Souza return; 272a1b63119SJosé Roberto de Souza 273a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 274a1b63119SJosé Roberto de Souza 275a1b63119SJosé Roberto de Souza /* New state matches current one? */ 276a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs == !!dev_priv->drrs.dp) 277a1b63119SJosé Roberto de Souza goto unlock; 278a1b63119SJosé Roberto de Souza 279a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs) 2803a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(intel_dp); 281a1b63119SJosé Roberto de Souza else 2823a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(intel_dp, crtc_state); 283a1b63119SJosé Roberto de Souza 284a1b63119SJosé Roberto de Souza unlock: 285a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 286a1b63119SJosé Roberto de Souza } 287a1b63119SJosé Roberto de Souza 2883a3dd534SJosé Roberto de Souza static void intel_drrs_downclock_work(struct work_struct *work) 289a1b63119SJosé Roberto de Souza { 290a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = 291a1b63119SJosé Roberto de Souza container_of(work, typeof(*dev_priv), drrs.work.work); 292a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp; 293c7c4dfb6SJosé Roberto de Souza struct drm_crtc *crtc; 294a1b63119SJosé Roberto de Souza 295a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 296a1b63119SJosé Roberto de Souza 297a1b63119SJosé Roberto de Souza intel_dp = dev_priv->drrs.dp; 298a1b63119SJosé Roberto de Souza 299a1b63119SJosé Roberto de Souza if (!intel_dp) 300a1b63119SJosé Roberto de Souza goto unlock; 301a1b63119SJosé Roberto de Souza 302a1b63119SJosé Roberto de Souza /* 303a1b63119SJosé Roberto de Souza * The delayed work can race with an invalidate hence we need to 304a1b63119SJosé Roberto de Souza * recheck. 305a1b63119SJosé Roberto de Souza */ 306a1b63119SJosé Roberto de Souza 307a1b63119SJosé Roberto de Souza if (dev_priv->drrs.busy_frontbuffer_bits) 308a1b63119SJosé Roberto de Souza goto unlock; 309a1b63119SJosé Roberto de Souza 310c7c4dfb6SJosé Roberto de Souza crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 311c7c4dfb6SJosé Roberto de Souza intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config, DRRS_LOW_RR); 312a1b63119SJosé Roberto de Souza 313a1b63119SJosé Roberto de Souza unlock: 314a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 315a1b63119SJosé Roberto de Souza } 316a1b63119SJosé Roberto de Souza 3176bd58b70SJosé Roberto de Souza static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, 3186bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits, 3196bd58b70SJosé Roberto de Souza bool invalidate) 320a1b63119SJosé Roberto de Souza { 321a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp; 322a1b63119SJosé Roberto de Souza struct drm_crtc *crtc; 323a1b63119SJosé Roberto de Souza enum pipe pipe; 324a1b63119SJosé Roberto de Souza 325a1b63119SJosé Roberto de Souza if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 326a1b63119SJosé Roberto de Souza return; 327a1b63119SJosé Roberto de Souza 328a1b63119SJosé Roberto de Souza cancel_delayed_work(&dev_priv->drrs.work); 329a1b63119SJosé Roberto de Souza 330a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 331a1b63119SJosé Roberto de Souza 332a1b63119SJosé Roberto de Souza intel_dp = dev_priv->drrs.dp; 333a1b63119SJosé Roberto de Souza if (!intel_dp) { 334a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 335a1b63119SJosé Roberto de Souza return; 336a1b63119SJosé Roberto de Souza } 337a1b63119SJosé Roberto de Souza 338a1b63119SJosé Roberto de Souza crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 339a1b63119SJosé Roberto de Souza pipe = to_intel_crtc(crtc)->pipe; 340a1b63119SJosé Roberto de Souza 341a1b63119SJosé Roberto de Souza frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 3426bd58b70SJosé Roberto de Souza if (invalidate) 343a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 3446bd58b70SJosé Roberto de Souza else 3456bd58b70SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 346a1b63119SJosé Roberto de Souza 3476bd58b70SJosé Roberto de Souza /* flush/invalidate means busy screen hence upclock */ 348c7c4dfb6SJosé Roberto de Souza if (frontbuffer_bits) 3493a3dd534SJosé Roberto de Souza intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config, 350c7c4dfb6SJosé Roberto de Souza DRRS_HIGH_RR); 351a1b63119SJosé Roberto de Souza 3526bd58b70SJosé Roberto de Souza /* 3536bd58b70SJosé Roberto de Souza * flush also means no more activity hence schedule downclock, if all 3546bd58b70SJosé Roberto de Souza * other fbs are quiescent too 3556bd58b70SJosé Roberto de Souza */ 3566bd58b70SJosé Roberto de Souza if (!invalidate && !dev_priv->drrs.busy_frontbuffer_bits) 3576bd58b70SJosé Roberto de Souza schedule_delayed_work(&dev_priv->drrs.work, 3586bd58b70SJosé Roberto de Souza msecs_to_jiffies(1000)); 359a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 360a1b63119SJosé Roberto de Souza } 361a1b63119SJosé Roberto de Souza 362a1b63119SJosé Roberto de Souza /** 3636bd58b70SJosé Roberto de Souza * intel_drrs_invalidate - Disable Idleness DRRS 3646bd58b70SJosé Roberto de Souza * @dev_priv: i915 device 3656bd58b70SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 3666bd58b70SJosé Roberto de Souza * 3676bd58b70SJosé Roberto de Souza * This function gets called everytime rendering on the given planes start. 3686bd58b70SJosé Roberto de Souza * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 3696bd58b70SJosé Roberto de Souza * 3706bd58b70SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 3716bd58b70SJosé Roberto de Souza */ 3726bd58b70SJosé Roberto de Souza void intel_drrs_invalidate(struct drm_i915_private *dev_priv, 3736bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits) 3746bd58b70SJosé Roberto de Souza { 3756bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true); 3766bd58b70SJosé Roberto de Souza } 3776bd58b70SJosé Roberto de Souza 3786bd58b70SJosé Roberto de Souza /** 3793a3dd534SJosé Roberto de Souza * intel_drrs_flush - Restart Idleness DRRS 380a1b63119SJosé Roberto de Souza * @dev_priv: i915 device 381a1b63119SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 382a1b63119SJosé Roberto de Souza * 383a1b63119SJosé Roberto de Souza * This function gets called every time rendering on the given planes has 384a1b63119SJosé Roberto de Souza * completed or flip on a crtc is completed. So DRRS should be upclocked 385a1b63119SJosé Roberto de Souza * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 386a1b63119SJosé Roberto de Souza * if no other planes are dirty. 387a1b63119SJosé Roberto de Souza * 388a1b63119SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 389a1b63119SJosé Roberto de Souza */ 3903a3dd534SJosé Roberto de Souza void intel_drrs_flush(struct drm_i915_private *dev_priv, 391a1b63119SJosé Roberto de Souza unsigned int frontbuffer_bits) 392a1b63119SJosé Roberto de Souza { 3936bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 394a1b63119SJosé Roberto de Souza } 395a1b63119SJosé Roberto de Souza 3960f3692b5SJosé Roberto de Souza void intel_drrs_page_flip(struct intel_atomic_state *state, 3970f3692b5SJosé Roberto de Souza struct intel_crtc *crtc) 3980f3692b5SJosé Roberto de Souza { 3990f3692b5SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(state->base.dev); 4000f3692b5SJosé Roberto de Souza unsigned int frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); 4010f3692b5SJosé Roberto de Souza 4020f3692b5SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 4030f3692b5SJosé Roberto de Souza } 4040f3692b5SJosé Roberto de Souza 405a1b63119SJosé Roberto de Souza /** 4063a3dd534SJosé Roberto de Souza * intel_drrs_init - Init basic DRRS work and mutex. 407a1b63119SJosé Roberto de Souza * @connector: eDP connector 408a1b63119SJosé Roberto de Souza * @fixed_mode: preferred mode of panel 409a1b63119SJosé Roberto de Souza * 410a1b63119SJosé Roberto de Souza * This function is called only once at driver load to initialize basic 411a1b63119SJosé Roberto de Souza * DRRS stuff. 412a1b63119SJosé Roberto de Souza * 413a1b63119SJosé Roberto de Souza * Returns: 414a1b63119SJosé Roberto de Souza * Downclock mode if panel supports it, else return NULL. 415a1b63119SJosé Roberto de Souza * DRRS support is determined by the presence of downclock mode (apart 416a1b63119SJosé Roberto de Souza * from VBT setting). 417a1b63119SJosé Roberto de Souza */ 418a1b63119SJosé Roberto de Souza struct drm_display_mode * 4193a3dd534SJosé Roberto de Souza intel_drrs_init(struct intel_connector *connector, 420a1b63119SJosé Roberto de Souza struct drm_display_mode *fixed_mode) 421a1b63119SJosé Roberto de Souza { 422a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 423f0d4ce59SVille Syrjälä struct intel_encoder *encoder = connector->encoder; 424a1b63119SJosé Roberto de Souza struct drm_display_mode *downclock_mode = NULL; 425a1b63119SJosé Roberto de Souza 4263a3dd534SJosé Roberto de Souza INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_drrs_downclock_work); 427a1b63119SJosé Roberto de Souza mutex_init(&dev_priv->drrs.mutex); 428a1b63119SJosé Roberto de Souza 429a1b63119SJosé Roberto de Souza if (DISPLAY_VER(dev_priv) <= 6) { 430a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 431a1b63119SJosé Roberto de Souza "DRRS supported for Gen7 and above\n"); 432a1b63119SJosé Roberto de Souza return NULL; 433a1b63119SJosé Roberto de Souza } 434a1b63119SJosé Roberto de Souza 435f0d4ce59SVille Syrjälä if ((DISPLAY_VER(dev_priv) < 8 && !HAS_GMCH(dev_priv)) && 436f0d4ce59SVille Syrjälä encoder->port != PORT_A) { 437f0d4ce59SVille Syrjälä drm_dbg_kms(&dev_priv->drm, 438f0d4ce59SVille Syrjälä "DRRS only supported on eDP port A\n"); 439f0d4ce59SVille Syrjälä return NULL; 440f0d4ce59SVille Syrjälä } 441f0d4ce59SVille Syrjälä 442a1b63119SJosé Roberto de Souza if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 443a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n"); 444a1b63119SJosé Roberto de Souza return NULL; 445a1b63119SJosé Roberto de Souza } 446a1b63119SJosé Roberto de Souza 447a1b63119SJosé Roberto de Souza downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 448a1b63119SJosé Roberto de Souza if (!downclock_mode) { 449a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 450a1b63119SJosé Roberto de Souza "Downclock mode is not found. DRRS not supported\n"); 451a1b63119SJosé Roberto de Souza return NULL; 452a1b63119SJosé Roberto de Souza } 453a1b63119SJosé Roberto de Souza 454a1b63119SJosé Roberto de Souza dev_priv->drrs.type = dev_priv->vbt.drrs_type; 455a1b63119SJosé Roberto de Souza 456a1b63119SJosé Roberto de Souza dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; 457a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 458a1b63119SJosé Roberto de Souza "seamless DRRS supported for eDP panel.\n"); 459a1b63119SJosé Roberto de Souza return downclock_mode; 460a1b63119SJosé Roberto de Souza } 461